Packaging structure and packaged device

Abstract

A packaging structure and a packaged device. The packaging structure comprises: a dielectric layer; a first redistribution layer located in the dielectric layer; a second redistribution layer located on the first redistribution layer, the first redistribution layer being electrically connected to the second redistribution layer, and the top of the second redistribution layer protruding beyond the dielectric layer; a chip located on the dielectric layer; and a bond wire connecting the chip and the second redistribution layer. The thickness of the packaging structure is small.

Description

Packaging structure, packaging devices

[0001] This application claims priority to Chinese Patent Application No. 202411183523.4, filed on August 26, 2024, entitled "Packaging Structure, Packaging Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and more particularly to a packaging structure and a packaging device. Background Technology

[0003] Recently, the demand for portable devices in the electronics market has increased rapidly, thus creating a growing demand for miniaturization and weight reduction of electronic components installed in electronic products. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a packaging structure is provided, comprising:

[0005] Dielectric layer;

[0006] The first wiring layer is located in the dielectric layer;

[0007] A second wiring layer is located on top of the first wiring layer. The first wiring layer and the second wiring layer are electrically connected. The top of the second wiring layer protrudes from the dielectric layer.

[0008] The chip is located on the dielectric layer;

[0009] Leads connect the chip to the second rewiring layer.

[0010] In some embodiments, the second redistribution layer includes:

[0011] The main body is located within the dielectric layer;

[0012] An extension portion is located on the main body portion and extends to the top surface of the dielectric layer.

[0013] In some embodiments, the thickness of the main body portion is greater than the thickness of the extension portion in the vertical direction.

[0014] In some embodiments, in the horizontal direction, there is an angle between the top surface of the extension and the top surface of the dielectric layer.

[0015] In some embodiments, the second redistribution layer further includes:

[0016] A metal layer is conformally disposed on the extension;

[0017] The thickness of the metal layer is less than the thickness of the extension.

[0018] In some embodiments, the lead is connected to the metal layer, and the angle between the metal layer and the lead is greater than the angle between the top surface of the metal layer and the top surface of the dielectric layer.

[0019] In some embodiments, the first redistribution layer includes:

[0020] A lower conductive pattern is located at the bottom of the dielectric layer, and the lower conductive pattern extends horizontally in the dielectric layer;

[0021] The intermediate conductive pattern is located in the middle of the dielectric layer and is connected to the lower conductive pattern;

[0022] The upper conductive pattern is located on the upper part of the dielectric layer and is connected to the middle conductive pattern.

[0023] In some embodiments, the material of the main body portion is different from the material of the upper conductive pattern, and the hardness of the main body portion is greater than the hardness of the upper conductive pattern.

[0024] In some embodiments, the intermediate conductive pattern includes:

[0025] The vertical section connects to the lower conductive pattern;

[0026] The horizontal portion connects to the vertical portion and extends horizontally within the dielectric layer;

[0027] In the vertical direction, the thickness of the vertical part is greater than the thickness of the horizontal part.

[0028] In some embodiments, the width of the vertical portion is smaller than the width of the main body portion in the horizontal direction.

[0029] In some embodiments, the sidewall of the vertical portion has a first slope, and the top surface of the extension has a second slope, wherein the absolute value of the first slope is greater than the absolute value of the second slope.

[0030] In some embodiments, the main body portion is connected to the upper conductive pattern, and the thickness of the main body portion is greater than the thickness of the horizontal portion.

[0031] In some embodiments, the second redistribution layer is located on both sides of the chip, and the distance between the second redistribution layer on both sides and the chip is different.

[0032] In some embodiments, the second redistribution layer further includes:

[0033] A recessed portion extends from the extension portion into the main body portion;

[0034] A gold ball is located in the recessed portion, and the lead wire is connected to the gold ball;

[0035] The height of the gold ball is greater than the depth of the recess.

[0036] In some embodiments, the chip includes:

[0037] The first chip is located on the dielectric layer.

[0038] The second chip is offsetly disposed on the first chip;

[0039] The third chip is offsetly disposed on the second chip;

[0040] The fourth chip is offsetly disposed on the third chip;

[0041] The second chip and the third chip have the same offset direction, while the fourth chip has the opposite offset direction to the third chip.

[0042] In some embodiments, the first chip and the second chip are connected by the leads, the first chip is connected to the second redistribution layer by the leads, the fourth chip and the third chip are connected by the leads, and the third chip is connected to the second redistribution layer by the leads.

[0043] In some embodiments, the length of the lead from the second chip to the first chip is equal to the length of the lead from the fourth chip to the third chip.

[0044] In some embodiments, the first distance from the second redistribution layer to the first chip is greater than the second distance from the second redistribution layer to the third chip.

[0045] According to a second aspect of the present disclosure, a packaging structure is provided, comprising:

[0046] Dielectric layer;

[0047] The first wiring layer is located in the dielectric layer;

[0048] A second wiring layer is located on top of the first wiring layer. The first wiring layer and the second wiring layer are electrically connected. The top of the second wiring layer protrudes from the dielectric layer.

[0049] The chip is located on the dielectric layer;

[0050] Leads connect the chip to the second wiring layer;

[0051] The dielectric layer includes:

[0052] The first dielectric layer is located on the fourth dielectric layer;

[0053] The second dielectric layer is located on the first dielectric layer;

[0054] A third dielectric layer is located on top of the second dielectric layer. The thickness of the third dielectric layer is equal to the thickness of the first dielectric layer. The thickness of the fourth dielectric layer is less than the thickness of the first dielectric layer. The thickness of the first dielectric layer is equal to the thickness of the second dielectric layer.

[0055] According to a third aspect of the present disclosure, a packaging device is provided, comprising:

[0056] substrate;

[0057] The packaging structure is mounted on the substrate.

[0058] In summary, this disclosure provides a packaging structure and packaging device. A first and second wiring layer are formed in a dielectric layer, with the top of the second wiring layer protruding beyond the dielectric layer. A chip is then placed on the dielectric layer, and the second wiring layer and the chip are connected by leads. Because the overall thickness of the dielectric layer is relatively small, and the top of the second wiring layer is on the outside of the dielectric layer, the leads can directly connect to the second wiring layer, thereby achieving miniaturization of the packaging structure. Attached Figure Description

[0059] Figure 1 is a schematic diagram illustrating a packaging structure according to an exemplary embodiment;

[0060] Figure 2 is a schematic diagram of a dielectric layer according to an exemplary embodiment;

[0061] Figure 3 is a schematic diagram of an intermediate conductive pattern according to an exemplary embodiment;

[0062] Figure 4 is a schematic diagram of a second rewiring layer according to an exemplary embodiment;

[0063] Figure 5 is a schematic diagram of a chip stack according to an exemplary embodiment;

[0064] Figure 6 is a schematic diagram illustrating another packaging structure according to an exemplary embodiment;

[0065] Figure 7 is another schematic diagram of a second rewiring layer according to an exemplary embodiment;

[0066] Figure 8 is an enlarged view of the dashed box in Figure 7 according to an exemplary embodiment;

[0067] Figure 9 is a schematic diagram illustrating the extension and vertical portion according to an exemplary embodiment;

[0068] Figure 10 is another schematic diagram of a second rewiring layer according to an exemplary embodiment;

[0069] Figure 11 is another schematic diagram of a second rewiring layer according to an exemplary embodiment;

[0070] Figure 12 is a schematic diagram of a packaged device according to an exemplary embodiment. Detailed Implementation

[0071] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0072] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0073] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0074] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0075] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0076] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0077] With the trend towards miniaturization in packaged products, the thickness of the substrate has a significant impact on the size of the package structure. Substrates are typically formed by stacking multiple layers of organic materials. To ensure the strength of the substrate, more organic material layers need to be stacked, resulting in a thicker substrate and consequently a thicker package structure, which is not conducive to achieving miniaturized products.

[0078] This disclosure proposes a packaging structure that uses a redistribution substrate as a support substrate. Since the redistribution substrate is formed through multiple deposition processes, the thickness of each film layer can be precisely controlled, thereby controlling the thickness of the redistribution layer and reducing the thickness of the redistribution substrate.

[0079] As shown in Figure 1, this embodiment of the present disclosure proposes a packaging structure 100, which may include a dielectric layer 110, a first redistribution layer 120, a second redistribution layer 130, a chip 140, leads 150, a molding compound layer 160, and external terminals 170. The first redistribution layer 120 is located within the dielectric layer 110. The second redistribution layer 130 is located on the first redistribution layer 120, and the top of the second redistribution layer 130 protrudes beyond the dielectric layer 110. The dielectric layer 110, the first redistribution layer 120, and the second redistribution layer 130 may be redistribution substrates. The chip 140 is located on the front side of the dielectric layer 110 and is connected to the second redistribution layer 130 via leads 150. The molding compound layer 160 covers the chip 140 and the leads 150. The external terminals 170 are located on the back side of the dielectric layer 110 and are connected to the first redistribution layer 120, thereby enabling external signal transmission. In this embodiment, the lead 140 is directly soldered onto the second wiring layer 130, that is, the second wiring layer 130 is used as a pad. Therefore, there is no need to set up additional pads. Since the thickness of the first wiring layer 120 and the second wiring layer 130 is relatively small, the overall thickness of the dielectric layer 110 can be reduced, thereby reducing the size of the package structure 100.

[0080] As shown in Figure 2, the dielectric layer 110 may include a first dielectric layer 111, a second dielectric layer 112, a third dielectric layer 113, and a fourth dielectric layer 114 stacked in a vertical direction. The first dielectric layer 111 is located on the fourth dielectric layer 114, the second dielectric layer 112 is located on the first dielectric layer 111, and the third dielectric layer 113 is located on the second dielectric layer 112. When forming the dielectric layer 110, the first dielectric layer 111, the second dielectric layer 112, and the third dielectric layer 113 can be formed on a temporary substrate first, and then the temporary substrate can be removed, thereby forming the fourth dielectric layer 114 on the first dielectric layer 111. In this embodiment, the materials of the first dielectric layer 111 to the fourth dielectric layer 114 can be the same. The material of the first dielectric layer 111 can be an insulating material, such as a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), or an insulating material in which these resins are impregnated in a core material (e.g., inorganic filler and / or glass fiber (glass fiber, glass cloth, glass fabric)). The first dielectric layer 111 may also include a photosensitive resin such as a photoimageable dielectric (PID) resin.

[0081] As shown in Figure 2, the thickness of the first dielectric layer 111 is approximately the same as the thickness of the second dielectric layer 112, the thickness of the second dielectric layer 112 is approximately the same as the thickness of the third dielectric layer 113, and the thickness of the first dielectric layer 111 is greater than the thickness of the fourth dielectric layer 114. Since redistribution layers need to be formed in the first dielectric layer 111, the second dielectric layer 112, and the third dielectric layer 113, but not in the fourth dielectric layer 114, the thickness of the first dielectric layer 111 to the third dielectric layer 113 is relatively large. Simultaneously, since the external terminal 170 is formed after the fourth dielectric layer 114, the thickness of the fourth dielectric layer 114 is smaller, which also reduces the etching time of the fourth dielectric layer 114. In this embodiment, the thickness of the fourth dielectric layer 114 can be reduced, thereby reducing the overall thickness of the dielectric layer 110, shrinking the size of the external terminal 170, and thus improving the thickness of the package structure 100. The thickness of the first dielectric layer 111 can be 9-10 μm, and the thickness of the fourth dielectric layer 114 can be 4-5 μm. The thickness of the fourth dielectric layer 114 can be half the thickness of the first dielectric layer 111. If the thickness of the fourth dielectric layer 114 is close to the thickness of the first dielectric layer 111, the size of the external terminal 170 will also increase accordingly, thus increasing the overall thickness of the dielectric layer 110. If the thickness of the fourth dielectric layer 114 is too small, for example, 1-2 μm, the fourth dielectric layer 114 cannot protect the first redistribution layer 120, and it is also not conducive to the placement of the external terminal 170.

[0082] As shown in Figures 2-3, a first redistribution layer 120 is present in the dielectric layer 110. The first redistribution layer 120 may include a lower conductive pattern 121, an intermediate conductive pattern 122, and an upper conductive pattern 123. The lower conductive pattern 121 is located on the fourth dielectric layer 114. When forming the lower conductive pattern 121, the lower conductive pattern 121 is first formed on a temporary substrate, and then the first dielectric layer 111 is formed, thereby covering the lower conductive pattern 121. The lower conductive pattern 121 may extend horizontally on the fourth dielectric layer 114. An intermediate conductive pattern 122 is present on the lower conductive pattern 111, and the intermediate conductive pattern 122 may include a vertical portion 1221 and a horizontal portion 1222. The vertical portion 1221 may be located in the first dielectric layer 111, thereby being electrically connected to the lower conductive pattern 121. The horizontal portion 1222 is located on the first dielectric layer 111 and extends horizontally on the first dielectric layer 111. Meanwhile, in the vertical direction (Y direction), the thickness of the vertical portion 1221 is greater than the thickness of the horizontal portion 1222. In this embodiment, an intermediate conductive pattern 122 is formed after the first dielectric layer 111, thereby allowing the vertical portion 1221 to be formed in the first dielectric layer 111 and the horizontal portion 1222 to be formed on the first dielectric layer 111. In this embodiment, the sidewalls of the vertical portion 1221 are inclined. By increasing the thickness of the vertical portion 1221, the upper width of the vertical portion 1221 can be increased, which is beneficial for metal filling and thus increases the contact area with the horizontal portion 1222, improving signal transmission performance. In some embodiments, the first redistribution layer 120 may include a ground pattern, a power pattern, a signal pattern, etc. The signal pattern may include various signals (such as data signals) other than the ground pattern and power-related power patterns.

[0083] As shown in Figure 2, after forming the intermediate conductive pattern 122, a second dielectric layer 112 is first formed on the first dielectric layer 111, and then an upper conductive pattern 123 is formed in the second dielectric layer 112. The upper conductive pattern 123 is electrically connected to the intermediate conductive pattern 122. The structure of the upper conductive pattern 123 can be the same as that of the intermediate conductive pattern 122. Part of the upper conductive pattern 123 is located in the second dielectric layer 112, and part of the upper conductive pattern 123 is located on the second dielectric layer 112. After forming the upper conductive pattern 123, a third dielectric layer 113 is formed on the second dielectric layer 122. The third dielectric layer 113 can cover the horizontal portion of the upper conductive pattern 123. It should be noted that a seed barrier layer is also formed between the lower conductive pattern 121, the intermediate conductive pattern 122, and the upper conductive pattern 123 and the dielectric layer 110. The seed barrier layer can be titanium or tantalum.

[0084] As shown in Figures 2 and 4, after forming the third dielectric layer 113, a second redistribution layer 130 can also be formed within the third dielectric layer 113. The top of the second redistribution layer 130 protrudes beyond the top surface of the third dielectric layer 113, meaning that in the vertical direction, the top of the second redistribution layer 130 is located outside the third dielectric layer 113. Since the top of the second redistribution layer 130 is located outside the third dielectric layer 113, i.e., outside the dielectric layer 110, the second redistribution layer 130 can be used as a pad, eliminating the need to additionally form pads on the third dielectric layer 113.

[0085] As shown in Figures 2 and 4, the second redistribution layer 130 may include a main body 131 and an extension 132. The main body 131 may be located in the third dielectric layer 113, and the extension 132 may be located on the main body 131 and extend into the third dielectric layer 113, i.e., the extension 132 is located on the third dielectric layer 113. The extension 132 may be the top of the second redistribution layer 130. In the vertical direction, the thickness of the extension 132 is less than the thickness of the main body 131. Since wiring is required on the second redistribution layer 130, the top of the second redistribution layer 130 needs to be lower than the chip 140, thus forming a thinner extension 132. Of course, the second redistribution layer 130 may also include a metal layer 133, which is located on the extension 132 and conformally disposed on the extension 132. Conformal growth can be understood as the metal layer 133 continuing the growth of the top surface of the extension 132. For example, if the top surface of the extension 132 is horizontal, then the top surface of the metal layer 133 is also horizontal; conversely, if the top surface of the extension 132 is inclined, then the top surface of the metal layer 133 is also inclined. A lead 140 can be connected to the metal layer 133. It should be noted that there is a seed barrier layer between the main body 131 and the dielectric layer 110, and similarly, there is a seed barrier layer between the extension 132 and the dielectric layer 110.

[0086] As shown in Figures 2 and 4, the metal layer 133 is located only on the top surface of the extension 132, meaning that the metal layer 133 is not on the sidewall of the extension 132. Since there are a large number of second wiring layers 130 on the dielectric layer 110, and these second wiring layers 130 are arranged regularly, and since the metal layer 133 is located only on the top surface of the extension 132, the spacing between adjacent second wiring layers 130 can be appropriately reduced, thereby increasing the number of second wiring layers 130 and providing better signal transmission for the chip.

[0087] As shown in Figures 2 and 4, the main body 131 and the extension 132 are made of the same material, while the extension 132 and the metal layer 133 are made of different materials. Since the lead 150 is connected to the metal layer 133, the metal layer 133 and the lead 150 are made of the same material. Simultaneously, the main body 131 is electrically connected to the upper conductive pattern 123, but the main body 131 and the upper conductive pattern 123 are made of different materials. The hardness of both the main body 131 and the extension 132 can be greater than the hardness of the upper conductive pattern 123. After connecting the lead 150 to the metal layer 133, the endpoint of the lead 150 needs to be cut off with a chopping tool. The chopping tool applies force to the main body 131; therefore, the main body 131 and the extension 132 require higher hardness to prevent deformation of the main body 131. In this embodiment, the material of the main body 131 can be nickel or titanium, the material of the upper conductive pattern 123 can be copper or aluminum, and the material of the metal layer 133 can be gold.

[0088] As shown in Figures 1 and 5, a chip 140 is disposed on the front side of the dielectric layer 110, and the chip 140 is connected to the second redistribution layer 130 via leads 150. The number of chips 140 can be multiple, for example, two, four, eight, or more. Chips 140 can be logic chips or memory chips. Logic chips can include, for example, central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), encryption processors, microprocessors, microcontrollers, analog-to-digital converters, application-specific integrated circuits (ASICs), etc. Memory chips can include, for example, volatile memory devices (such as dynamic random access memory (DRAM) or static RAM (SRAM)) or non-volatile memory devices (such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or flash memory). In this embodiment, four chips 140 are disposed, namely, first chip 141 to fourth chip 144. First chip 141 to fourth chip 144 are stacked sequentially. The first chip 141 is located on the third dielectric layer 113. The second chip 142 is offset from the first chip 142, the third chip 143 is offset from the second chip 142, and the fourth chip 144 is offset from the third chip 143. The offset directions of the second chip 142 and the third chip 143 are the same, for example, offset to the right in Figure 5. The offset direction of the fourth chip 141 is opposite to the offset direction of the third chip 143, for example, offset to the left in Figure 5. The first chip 141 and the second chip 142 are connected by a lead 150. The first chip 141 is connected to the second redistribution layer 130 by a lead 150. The fourth chip 144 is connected to the third chip 143 by a lead 150, and the third chip 143 is connected to the second redistribution layer 130 by a lead 150. Since the first chip 141 to the fourth chip 144 are chips of the same specification, such as DRAM chips of the same model, the length of the lead 150 from the second chip 142 to the first chip 141 is the same as the length of the lead 150 from the fourth chip 144 to the third chip 143. The distance from the first chip 141 to the third dielectric layer 113 can be the thickness of the first chip 141, and the distance from the third chip 143 to the third dielectric layer 113 can be the sum of the thicknesses of the first chip 141 to the third chip 143. Therefore, the first chip 141 is lower than the third chip 143. Consequently, the length of the lead 150 from the first chip 141 to the second redistribution layer 130 is less than the length of the lead 150 from the third chip 143 to the second redistribution layer 130. As a result, there will be a time difference in signal transmission on the first chip 141 and the third chip 143, leading to inconsistent signal transmission.In this embodiment, the first distance d1 from the second wiring layer 130 on the left to the first chip 141 is greater than the second distance d2 from the second wiring layer 130 on the right to the third chip 143, thereby reducing the length difference of the leads 150 on the left and right sides, and thus reducing the signal transmission time difference. In this embodiment, the second distance d2 from the second wiring layer 130 on the right to the third chip 143 can be 240-250 μm, and the first distance d1 from the second wiring layer 130 on the left to the first chip 141 can be 300-350 μm. That is, the difference between the first distance d1 and the second distance d2 is basically equal to the sum of the thicknesses of the second chip 142 and the third chip 143.

[0089] As shown in Figure 5, after the lead 150 is completed, a molding compound 160 can be formed on the third dielectric layer 113. The molding compound 160 covers the first chip 141 to the fourth chip 144, and also covers the lead 150. The molding compound 160 can protect the chip 140. The molding compound 160 may include an insulating material. Examples of insulating materials may include thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or prepregs including inorganic fillers and / or glass fibers, Ajinomoto composite film (ABF), FR-4, bismaleimide triazine (BT), epoxy molding compound (EMC), etc.

[0090] As shown in Figures 2 and 5, after forming the molding compound 160, a temporary substrate is disposed on the surface of the molding compound 160. This temporary substrate is then flipped, allowing a fourth dielectric layer 114 to be formed on the first dielectric layer 111. A portion of the fourth dielectric layer 114 is then etched, thereby forming an external terminal 170 within the fourth dielectric layer 114. The external terminal 170 can be electrically connected to the lower conductive pattern 121, thereby enabling signal transmission. The external terminal 170 can be a solder ball or a bump.

[0091] As shown in Figure 1, in this embodiment, when forming the second wiring layer 130, the chip 140 is connected to the second wiring layer 130 via leads 150, instead of using solder balls to fix the chip 140 to the second wiring layer 130. When using solder balls to fix the chip 140, during molding, the molding material needs to enter between the chip 140 and the dielectric layer 110. As the density of solder balls increases and the size of solder balls decreases, it becomes difficult for the molding material to enter between the chip 140 and the dielectric layer 110, and gaps are easily formed in the molding layer 160, leading to a decrease in the performance of the molding layer 160. Furthermore, solder balls have a certain height; using solder balls to fix the chip 140 increases the overall height of the package structure 100. In this embodiment, the chip 140 is bonded to the dielectric layer 110, and then the chip and the second wiring layer 130 are connected via leads 150. The molding layer 160 can completely cover the chip 140, while also reducing the overall height of the package structure 100. At the same time, the overall thickness of the dielectric layer 110 is reduced, thereby reducing the overall thickness of the packaging structure.

[0092] As shown in Figure 1, in this embodiment of the present disclosure, the top of the second wiring layer 130 is outside the dielectric layer 110, and the lead 150 can be directly connected to the second wiring layer 130. If the top of the second wiring layer 130 is inside the dielectric layer 110, that is, the second wiring layer 130 is lower than the dielectric layer 110, the portion of the dielectric layer 110 protruding from the second wiring layer 130 may affect the bonding process of the lead 150. Simultaneously, when the lead 150 is wired onto the second wiring layer 130, the length of the lead 150 will also be extended. During the subsequent molding process, the molding compound needs to be filled into the dielectric layer 110, which will cause the lead 150 to wobble, reducing its stability. In this embodiment of the present disclosure, the top of the second wiring layer 130 is outside the dielectric layer 110, and the second wiring layer 130 will not obstruct the wire bonding process. Since the present embodiment can also reduce the length of the lead 150, the second rewiring layer 130 will also slow down the flow rate of the molding compound, reduce the impact on the lead 150, and improve the stability of the lead 150.

[0093] As shown in Figure 2, in this embodiment, the first dielectric layer 111, the second dielectric layer 112, and the third dielectric layer 113 are formed through multiple deposition processes. The deposition process can improve the precision of the first dielectric layer 111 to the third dielectric layer 113, reduce the thickness of the first dielectric layer 111 to the third dielectric layer 113, and thus reduce the thickness of the dielectric layer 110, thereby reducing the thickness of the encapsulation structure 100. This embodiment does not use an organic substrate. Organic substrates require multiple organic sub-substrates to be stacked, and then conductive lines are formed by drilling. This results in a relatively large thickness of the organic substrate, which is not conducive to reducing the thickness of the encapsulation structure 100.

[0094] As shown in Figure 6, this embodiment of the present disclosure proposes another packaging structure 100. The difference between this packaging structure 100 and that in Figure 1 is that the structure of the second redistribution layer 130 in Figure 6 is different from that in Figure 1. The structures of the dielectric layer 110, the first redistribution layer 120, the chip 140, the lead 150, the molding layer 160, and the external terminal 170 in Figure 6 can be referred to the above description. Here, the structure of the second redistribution layer 130 is described in detail.

[0095] As shown in Figures 7 and 8, the second redistribution layer 130 includes a main body 131, an extension 132, and a metal layer 133. The main body 131 is located in the third dielectric layer 113, and the extension 132 is located on the main body 131 and extends onto the third dielectric layer 113. The top surface of the extension 132 is inclined, and the metal layer 133 is conformally formed on the extension 132, thus the top surface of the metal layer 132 is also inclined. As can be seen from Figure 8, in the vertical direction, the end of the extension 132 near the chip 140 has a larger thickness, and the end of the extension 132 away from the chip 140 has a smaller thickness. The maximum thickness of the extension 132 is less than the thickness of the main body 131. The maximum thickness of the extension 132 is much smaller than the thickness of the chip 140. In this embodiment, the maximum thickness of the extension 132 is approximately 1 / 10 of the thickness of the chip 140. If the maximum thickness of the extension 132 is too large, it will be detrimental to the bonding process of the lead 150. As shown in Figure 8, the top surface 1331 of the metal layer 133 is inclined, meaning it is inclined relative to the surface of the third dielectric layer 113. Therefore, the angle between the top surface 1331 and the third dielectric layer 113 can be angle b. The end of the lead 150 is on the top surface 1331, so there is an angle α between the lead 150 and the top surface 1331. This angle can be understood as the angle between the tangent of the lead 150 and the top surface 1331. In this embodiment, angle α can be greater than angle b, meaning the top surface 1331 is relatively flat, and thus the top surface of the extension 132 is relatively flat. Consequently, the thickness of the extension 132 near the chip 140 is smaller, which is beneficial for wire bonding. During wire bonding, to ensure the lead 150 has good curvature and stability, the range of angle α should be relatively large; therefore, angle α can be greater than angle b. Simultaneously, when the end of the lead 150 is led onto the metal layer 133, a wedge is used to press the lead 150 together. Since the bottom of the wedge is arc-shaped, by setting a gentle top surface 1331, the cut surface of the bottom of the wedge is basically parallel to the top surface 1331. When the wedge is pressing and cutting, the lead 150 is subjected to overall pressure, improving the uniformity and stability of the lead pressing and forming, thereby improving the stability of the lead 150. In this embodiment, the angle b can be between 8-10°, for example, 9°, and the angle a can be between 15-20°, for example, 16° or 17°.

[0096] As shown in Figures 7 and 8, in this embodiment of the present disclosure, the thickness of the end of the extension 132 near the chip 140 is greater than the thickness of the end of the extension 132 away from the chip 140, which is beneficial to the bonding process of the lead 150. If the thickness of the end of the extension 132 near the chip 140 is less than the thickness of the end of the extension 132 away from the chip 140, the angle α between the lead 150 and the top surface 1331 becomes larger, and the bottom surface of the cutter cannot be well matched to the lead 150, which is detrimental to the bonding process of the lead 150 and makes it difficult to form a stable lead 150.

[0097] As shown in Figures 7 and 8, in this embodiment of the present disclosure, by forming an inclined extension 132 and then an inclined metal layer 133, the stability of the lead 150 can be improved during the pressing process of the lead 150.

[0098] As shown in Figure 9, (a) is a simplified schematic diagram of the extension 132, and (b) is a simplified schematic diagram of the vertical portion 221. The top surface 1321 of the extension 132 is inclined, and the sidewall 1221a of the vertical portion 1221 is also inclined. The top surface 1321 of the extension 132 can facilitate the stability of the lead 150, and the sidewall 1221a of the vertical portion 1221 can facilitate metal filling. Simultaneously, the sidewall 1221a of the extension 1221 has a first slope, and the top surface 1321 of the extension 132 has a second slope, the absolute value of which is greater than the absolute value of the second slope. The angle of the first slope is less than 90°. If the absolute value of the first slope is less than the absolute value of the second slope, i.e., the angle of the second slope is larger, the top surface 1321 becomes steep, which is detrimental to the formation process of the lead 150.

[0099] As shown in FIG10, this embodiment of the present disclosure also proposes another second redistribution layer 130, in which no metal layer is shown. The second redistribution layer 130 includes a main body 131 and an extension 132. The extension 132 is located on the main body 131. The extension 132 has an inclined surface. In the vertical direction, the end of the extension 132 near the chip 140 has a greater thickness, and the end of the extension 132 away from the chip 140 has a smaller thickness. The centerline S2 of the extension 132 deviates from the centerline S1 of the main body 131, and the centerline S2 of the extension 132 is closer to the chip 140, that is, the centerline S2 of the extension 132 is offset towards the chip 140. As can be seen from FIG10, the distance from the right end of the extension 132 to the main body 131 is greater than the distance from the left end of the extension 132 to the main body 131. Since the thicker end of the extension 132 is closer to the chip 140, it is beneficial to the lead bonding process of the chip 140, and improves the stability and uniformity of the leads.

[0100] As shown in Figure 11, this embodiment of the present disclosure also proposes another second redistribution layer 130. This second redistribution layer 130 may include a main body 131, an extension 132, and a recess 134. Since an opening is formed in the third dielectric layer 113, during electroplating, metal material grows simultaneously on the inner wall of the opening and the top surface of the third dielectric layer 113, and because the opening has a certain depth, the electroplating solution inside the opening is not updated in a timely manner during electroplating, and metal ions cannot be deposited inside the opening in a timely manner. Therefore, the metal layer growth rate inside the opening is slow, and thus the recess 134 is formed in the extension 132 and the main body 131. That is, the recess 134 is located in the extension 132 and the main body 131, extending from the extension 132 into the main body 131. The main body 131 is still located in the third dielectric layer 113, and the extension 132 is located on the top surface of the third dielectric layer 113, that is, the extension 132 protrudes from the third dielectric layer 113. The presence of the recess 134 hinders the wiring process. Therefore, in this embodiment, a gold ball 135 is formed within the recess 134, allowing the gold ball 135 to be considered part of the second redistribution layer 130, meaning the second redistribution layer 130 includes the gold ball 135. The gold ball 135 can contact the sidewalls and bottom surface of the recess 134. The gold ball 135 is located within the recess 134, with a gap between it and the sidewalls. In some embodiments, the bottom of the gold ball 135 can deform, eliminating the gap between it and the sidewalls, thus increasing the contact area. Simultaneously, the top surface of the gold ball 135 is higher than the top surface of the extension 132, meaning the height of the gold ball 135 is greater than the depth of the recess 134. Because the gold ball 135 is taller, the lead wire 150 can be directly pressed onto the gold ball 135. Since both are made of the same material, the bonding strength is high, which is beneficial for the wire bonding process. Simultaneously, pressing the lead wire 150 onto the gold ball 135 also increases the bonding strength between the gold ball 135 and the recess 134. In some embodiments, the height of the gold ball 135 can be 2µm greater than the depth of the recess 134. For example, the height of the gold ball 135 is 8-10µm, and the depth of the recess 134 is 6-8µm.

[0101] As shown in Figure 1, this embodiment of the present disclosure also proposes a packaging structure 100, which may include a dielectric layer 110, a first redistribution layer 120, a second redistribution layer 130, a chip 140, and leads 150. The first redistribution layer 120 is located within the dielectric layer 110, and the second redistribution layer 130 is located on the first redistribution layer 130. The first redistribution layer 120 and the second redistribution layer 130 are electrically connected, and the top of the second redistribution layer 130 protrudes beyond the dielectric layer 110. The chip 140 is located on the dielectric layer 110, and the leads 150 connect the chip 140 and the second redistribution layer 130. The dielectric layer 110 may include a first dielectric layer 111 to a fourth dielectric layer 114. The first dielectric layer 111 is located on the fourth dielectric layer 114, the second dielectric layer 112 is located on the first dielectric layer 111, and the third dielectric layer 113 is located on the second dielectric layer 112. The first dielectric layer 111 to the third dielectric layer 113 have the same thickness, and the fourth dielectric layer 114 has a thickness less than that of the first dielectric layer 111. In this packaging structure 100, the dielectric layer 110 can have a smaller thickness, thereby allowing the packaging structure 100 to have a smaller package volume.

[0102] As shown in Figure 12, this disclosure provides an encapsulation device 10, which may include a substrate 200 and an encapsulation structure 100. The substrate 200 is, for example, a PCB, a flexible substrate, or a strip substrate, and the encapsulation structure 100 may refer to the above-described structure. This encapsulation structure 10 can be applied to electronic devices. These electronic devices may include one or more of the following: for example, smartphones, tablet PCs, mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, personal digital assistants (PDAs), portable multimedia players (PMPs), MPEG-1 audio layer 3 (MP3) players, mobile medical devices, cameras, home appliances, medical devices, Internet of Things (IoT) devices, and wearable devices. Wearable devices may be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices may be, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted devices (HMDs).

[0103] In summary, the embodiments of this disclosure propose a packaging structure and packaging device that supports the chip using a thinner redistribution substrate, thereby reducing the thickness of the packaging structure. Furthermore, since the top of the second redistribution layer protrudes from the dielectric layer, it facilitates direct connection of leads to the second redistribution layer, thus facilitating the lead formation process.

[0104] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A packaging structure (100), comprising: Dielectric layer (110); The first redistribution layer (120) is located in the dielectric layer; The second wiring layer (130) is located on the first wiring layer, the first wiring layer is electrically connected to the second wiring layer, and the top of the second wiring layer protrudes from the dielectric layer. Chip (140) is located on the dielectric layer; Lead (150) connects the chip and the second rewiring layer.

2. The packaging structure according to claim 1, wherein, The second redistribution layer includes: The main body is located within the dielectric layer; An extension portion is located on the main body portion and extends to the top surface of the dielectric layer.

3. The packaging structure according to claim 2, wherein, In the vertical direction, the thickness of the main body is greater than the thickness of the extension.

4. The packaging structure according to claim 2 or 3, wherein, In the horizontal direction, there is an angle between the top surface of the extension and the top surface of the dielectric layer.

5. The packaging structure according to claim 4, wherein, The thickness of the extension near the chip is greater than the thickness of the extension away from the chip.

6. The packaging structure according to claim 4, wherein, The center line of the extension is offset from the center line of the main body, and the center line of the extension is offset toward the chip.

7. The packaging structure according to any one of claims 2-6, wherein, The second redistribution layer also includes: A metal layer is conformally disposed on the extension; The thickness of the metal layer is less than the thickness of the extension.

8. The packaging structure according to claim 7, wherein, The lead is connected to the metal layer, and the angle between the metal layer and the lead is greater than the angle between the top surface of the metal layer and the top surface of the dielectric layer.

9. The packaging structure according to any one of claims 1-3, wherein, The first redistribution layer includes: A lower conductive pattern is located at the bottom of the dielectric layer, and the lower conductive pattern extends horizontally in the dielectric layer; The intermediate conductive pattern is located in the middle of the dielectric layer and is connected to the lower conductive pattern; The upper conductive pattern is located on the upper part of the dielectric layer and is connected to the middle conductive pattern.

10. The packaging structure according to claim 9, wherein, The material of the main body is different from the material of the upper conductive pattern, and the hardness of the main body is greater than that of the upper conductive pattern.

11. The packaging structure according to claim 9, wherein, The intermediate conductive pattern includes: The vertical part connects to the lower conductive pattern; The horizontal portion connects to the vertical portion and extends horizontally within the dielectric layer; In the vertical direction, the thickness of the vertical part is greater than the thickness of the horizontal part. In the horizontal direction, the width of the vertical part is smaller than the width of the main body part.

12. The packaging structure according to claim 11, wherein, The sidewall of the vertical part has a first slope, and the top surface of the extension has a second slope, wherein the absolute value of the first slope is greater than the absolute value of the second slope.

13. The packaging structure according to claim 11, wherein, The main body is connected to the upper conductive pattern, and the thickness of the main body is greater than the thickness of the horizontal part.

14. The packaging structure according to any one of claims 1-3, wherein, The second redistribution layer is located on both sides of the chip, and the distance between the second redistribution layer on both sides and the chip is different.

15. The packaging structure according to claim 2, wherein, The second redistribution layer also includes: A recessed portion extends from the extension portion into the main body portion; A gold ball is located in the recessed portion, and the lead wire is connected to the gold ball; The height of the gold ball is greater than the depth of the recess.

16. The packaging structure according to any one of claims 1-3, wherein, The chip includes: The first chip is located on the dielectric layer. The second chip is offsetly disposed on the first chip; The third chip is offsetly disposed on the second chip; The fourth chip is offsetly disposed on the third chip; The second chip and the third chip have the same offset direction, while the fourth chip has the opposite offset direction to the third chip.

17. The packaging structure according to claim 16, wherein, The first chip and the second chip are connected by the leads. The first chip is connected to the second redistribution layer by the leads. The fourth chip and the third chip are connected by the leads. The third chip is connected to the second redistribution layer by the leads.

18. The packaging structure according to claim 17, wherein, The length of the lead from the second chip to the first chip is equal to the length of the lead from the fourth chip to the third chip.

19. The packaging structure according to claim 17, wherein, The first distance from the second redistribution layer to the first chip is greater than the second distance from the second redistribution layer to the third chip.

20. A packaging structure, comprising: Dielectric layer (110); The first redistribution layer (120) is located in the dielectric layer; The second wiring layer (130) is located on the first wiring layer, the first wiring layer is electrically connected to the second wiring layer, and the top of the second wiring layer protrudes from the dielectric layer. Chip (140) is located on the dielectric layer; Lead (150) connects the chip and the second rewiring layer; The dielectric layer (110) includes: The first dielectric layer (111) is located on the fourth dielectric layer (114); The second dielectric layer (112) is located on the first dielectric layer; The third dielectric layer (113) is located on the second dielectric layer. The thickness of the third dielectric layer is equal to the thickness of the first dielectric layer. The thickness of the fourth dielectric layer is less than the thickness of the first dielectric layer. The thickness of the first dielectric layer is equal to the thickness of the second dielectric layer.

21. A packaged device (10), comprising: substrate(200); The packaging structure (100) according to any one of claims 1-19, wherein the packaging structure is disposed on the substrate.

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