Three-dimensional stacked optoelectronic chip packaging structure and manufacturing method

Abstract

The present invention provides a three-dimensional stacked optoelectronic chip packaging structure and a manufacturing method. 3D stacked packaging of an optical chip and an electrical chip can effectively reduce the packaging area. In addition, the optical chip and the electrical chip are interconnected and led out by means of redistribution layers and conductive pillars, which can effectively shorten the transmission path of the optical chip and the electrical chip. Compared with 2D optoelectronic integrated packaging, the transmission path can be shortened by 20 times, and has low insertion loss and RC delay.

Description

A three-dimensional stacked optoelectronic chip packaging structure and fabrication method Technical Field

[0001] This invention belongs to the field of chip packaging and relates to a three-dimensional stacked optoelectronic chip packaging structure and its fabrication method. Background Technology

[0002] By 2022, global internet traffic is projected to reach nearly 400 EB per month, and the demand for data center interconnect bandwidth will continue to grow exponentially. It is predicted that by 2030, with the continued increase in data center energy consumption, global data center power consumption will exceed 3 PWh, and may even reach 8 PWh. To meet the demands of internet traffic, data center node bandwidth needs to reach 10 Tb / s. To mitigate the trend of increasing data center energy consumption, it is essential to find ways to reduce the power consumption of systems and devices. The number of I / O pins per package roughly doubles every 6 years, and total I / O bandwidth doubles every 3 to 4 years.

[0003] Light possesses advantages such as low signal attenuation, low power consumption, high bandwidth, and CMOS compatibility. These factors directly impact I / O bandwidth and power consumption. The introduction of silicon photonics technology aims to increase I / O bandwidth and minimize power consumption. The packaging of optical integrated circuits (PICs) and electrical integrated circuits (EICs) is crucial; improper integration of light and electricity can negate all the potential advantages of silicon photonics.

[0004] Most existing optoelectronic integrated semiconductor packaging structures directly bond optical and electrical integrated chips to a substrate for 2D packaging, using wire bonding or flip-chip bonding for electrical connection. Theoretically, this packaging is excellent; however, in practice, it is not. Silicon photonics process nodes are relatively backward compared to electrical chip processes. The most advanced processes developed for monolithic integration are 45nm and 32nm, which are significantly inferior in performance compared to electrical chip processes of 10nm and below. The performance of existing optoelectronic integrated packaging structures is insufficient to meet the demands of high-density integrated packaging. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a three-dimensional stacked optoelectronic chip packaging structure and manufacturing method to solve the problem of high-density integration and packaging of optical chips and electrical chips in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a three-dimensional stacked optoelectronic chip packaging structure, comprising the following steps:

[0007] A substrate is provided, a first redistribution layer is formed on the substrate, and conductive pillars are formed on the first redistribution layer, the conductive pillars being electrically connected to the first redistribution layer;

[0008] An optical chip is provided, the optical chip including a first side and a second side disposed opposite to each other, the first side of the optical chip is provided with optical chip solder joints and optical signal ports, and the second side of the optical chip is bonded to the first redistribution layer;

[0009] An encapsulation layer is formed on the first redistribution layer to cover the conductive pillars and the optical chip, and the encapsulation layer exposes the conductive pillars and the solder joints of the optical chip.

[0010] A second redistribution layer is formed on the encapsulation layer, and the second redistribution layer is electrically connected to the conductive pillar and the optical chip solder joint;

[0011] An electrical chip is provided, the electrical chip including a first side and a second side disposed opposite to each other, the second side of the electrical chip being provided with electrical chip solder joints, the second side of the electrical chip being bonded to a second redistribution layer, the electrical chip solder joints being electrically connected to the second redistribution layer, wherein, in the vertical projection, the electrical chip does not cover the optical signal port;

[0012] An opening is formed in the second redistribution layer to expose the optical signal port, and an optical bridging structure is formed on the second redistribution layer to cover the opening and correspond to the optical signal port.

[0013] Optionally, the optical chip is bonded to the first redistribution layer via a wafer bonding film.

[0014] Optionally, the electrical chip is bonded to the second redistribution layer via flip-chip bonding.

[0015] Optionally, the method for forming the opening in the second redistribution layer includes laser drilling or dry etching.

[0016] Optionally, after forming the optical bridging structure on the second redistribution layer, the step of removing the substrate is further included.

[0017] Optionally, a separation layer is further formed between the substrate and the first redistribution layer, wherein the substrate is removed based on the separation layer.

[0018] Optionally, the conductive pillar may comprise a copper pillar.

[0019] Optionally, the substrate may include a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, or a ceramic substrate.

[0020] The present invention also provides a three-dimensional stacked optoelectronic chip packaging structure, comprising:

[0021] First redistribution layer;

[0022] A conductive post is located above the first redistribution layer and is electrically connected to the first redistribution layer.

[0023] An optical chip is located above the first redistribution layer, and optical chip solder joints and optical signal ports are provided on the side of the optical chip away from the first redistribution layer.

[0024] The second redistribution layer is located above the conductive pillar and the optical chip, and the second redistribution layer is electrically connected to the solder joints of the conductive pillar and the optical chip.

[0025] An encapsulation layer is located between the first redistribution layer and the second redistribution layer, and covers the conductive pillars and the exposed surface of the optical chip;

[0026] An electrical chip is located above the second redistribution layer and is electrically connected to the second redistribution layer, wherein, in its vertical projection, the electrical chip does not cover the optical signal port;

[0027] An opening is provided, penetrating the second rewiring layer to expose the optical signal port;

[0028] An optical bridging structure is located above the second redistribution layer, the optical bridging structure covering the opening to correspond to the optical signal port.

[0029] Optionally, a wafer bonding film is disposed between the optical chip and the first redistribution layer, and the optical chip is bonded and fixed to the first redistribution layer by the wafer bonding film.

[0030] As described above, in the three-dimensional stacked optoelectronic chip packaging structure and manufacturing method of the present invention, the optical chip and electrical chip are 3D stacked and packaged, which can effectively reduce the packaging area; and the optical chip and electrical chip are interconnected and led out through the redistribution layer and conductive pillars, which can effectively shorten the transmission path of the optical chip and electrical chip. Compared with 2D optoelectronic integrated packaging, the transmission path can be shortened by 20 times, and it has low insertion loss and RC delay. Attached Figure Description

[0031] Figure 1 shows a process flow diagram of the fabrication method of the three-dimensional stacked optoelectronic chip packaging structure in an embodiment of the present invention.

[0032] Figure 2 shows a schematic diagram of a substrate provided in an embodiment of the present invention, on which a separation layer is formed.

[0033] Figure 3 shows a schematic diagram of the formation of the first redistribution layer in an embodiment of the present invention.

[0034] Figure 4 shows a schematic diagram of the formation of conductive pillars in an embodiment of the present invention.

[0035] Figure 5 shows a schematic diagram of an optical chip provided in an embodiment of the present invention, wherein the optical chip is bonded to a first rewiring layer.

[0036] Figure 6 shows a schematic diagram of the formation of the encapsulation layer in an embodiment of the present invention.

[0037] Figure 7 shows a schematic diagram of the thinned encapsulation layer in an embodiment of the present invention.

[0038] Figure 8 shows a schematic diagram of the formation of the second redistribution layer in an embodiment of the present invention.

[0039] Figure 9 shows a schematic diagram of an electrical chip provided in an embodiment of the present invention, wherein the electrical chip is bonded to a second redistribution layer.

[0040] Figure 10 shows a schematic diagram of the opening formed in an embodiment of the present invention.

[0041] Figure 11 shows a schematic diagram of the optical bridging structure formed in an embodiment of the present invention.

[0042] Figure 12 shows a schematic diagram of substrate removal in an embodiment of the present invention.

[0043] Component Labeling Explanation: 1. Substrate; 2. Separator Layer; 3. First Redistribution Layer; 4. Conductive Pillar; 5. Optical Chip 500; Optical Chip Solder Joint; 501. Optical Signal Port; 502. Protective Layer; 6. Wafer Bonding Film; 7. Encapsulation Layer; 8. Second Redistribution Layer; 9. Electrical Chip 900; Electrical Chip Solder Joint; 10. Bottom Filler Layer; 11. Opening; 12. Optical Bridging Structure S1~S6 Steps Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] Please refer to Figures 1 to 12. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the figures only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] This embodiment provides a method for fabricating a three-dimensional stacked optoelectronic chip packaging structure, as shown in Figure 1, including the following steps:

[0047] S1: Provide a substrate, form a first redistribution layer on the substrate, form conductive pillars on the first redistribution layer, and electrically connect the conductive pillars to the first redistribution layer;

[0048] S2: Provide an optical chip, the optical chip including a first side and a second side disposed opposite to each other, the first side of the optical chip is provided with optical chip solder joints and optical signal ports, and the second side of the optical chip is bonded to the first redistribution layer;

[0049] S3: An encapsulation layer is formed on the first redistribution layer to cover the conductive pillars and the optical chip, the encapsulation layer exposing the conductive pillars and the optical chip solder joints;

[0050] S4: A second redistribution layer is formed on the encapsulation layer, and the second redistribution layer is electrically connected to the conductive pillar and the optical chip solder joint;

[0051] S5: Provide an electrical chip, the electrical chip including a first side and a second side disposed opposite to each other, the second side of the electrical chip being provided with electrical chip solder joints, the second side of the electrical chip being bonded to the second redistribution layer, the electrical chip solder joints being electrically connected to the second redistribution layer, wherein, in the vertical projection, the electrical chip does not cover the optical signal port.

[0052] S6: An opening is formed in the second redistribution layer, the opening exposing an optical signal port, and an optical bridging structure is formed on the second redistribution layer, the optical bridging structure covering the opening to correspond to the optical signal port.

[0053] The fabrication method of the three-dimensional stacked optoelectronic chip packaging structure of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0054] First, please refer to Figures 2 to 4 and perform step S1: Provide a substrate 1, form a first redistribution layer 3 on the substrate 1, form conductive pillars 4 on the first redistribution layer 3, and electrically connect the conductive pillars 4 to the first redistribution layer 3.

[0055] As an example, the substrate 1 may include a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, a ceramic substrate, etc., and the substrate 1 provides support for subsequent processes; specifically, in this embodiment, the substrate 1 is a glass substrate.

[0056] As an example, before forming the first redistribution layer 3, the step of forming a separation layer 2 on the surface of the substrate 1 is also included. The separation layer 2 includes, but is not limited to, tape and polymer layers. For example, the separation layer 2 can be a photothermal conversion layer, so that the separation layer 2 can be heated by means of a laser to remove the substrate 1, thereby improving the ease of operation.

[0057] As an example, the first redistribution layer 3 is formed above the separation layer 2. The first redistribution layer 3 may be a damascus redistribution layer, an organic redistribution layer, or a combination of both. That is, the material of the dielectric layer may include silicon oxide, silicon nitride, or polyimide (PI), etc., and the material of the metal wiring may include copper, aluminum, etc. The material, number of layers, layout, and preparation method of the first redistribution layer 3 can be selected as needed, and no excessive restrictions are imposed here.

[0058] As an example, the method of forming the conductive pillar 4 on the first redistribution layer 3 includes bonding, electroplating, etc. The conductive pillar 4 is made of copper, and the bottom end of the conductive pillar 4 is electrically connected to the metal wiring in the first redistribution layer 3.

[0059] As an example, the conductive post 4 occupies a portion of the space above the first redistribution layer 3, and space is reserved above the first redistribution layer 3 for subsequent bonding of the optical chip 5.

[0060] Next, referring to Figure 5, step S2 is performed: an optical chip 5 is provided, the optical chip 5 includes a first side and a second side arranged opposite to each other, the first side of the optical chip 5 is provided with an optical chip solder joint 500 and an optical signal port 501, and the second side of the optical chip 5 is bonded to the first redistribution layer 3.

[0061] As an example, the first side of the optical chip 5 faces upward and the second side of the optical chip 5 faces downward. The second side of the optical chip 5 is bonded to the first redistribution layer 3 by a die attach film (DAF).

[0062] As an example, the optical chip solder joint 500 is a copper bump, and the first side of the optical chip 5 is also provided with a protective layer 502. The protective layer 502 covers the sidewall of the optical chip solder joint 500 and covers the optical signal port 501, protecting the optical signal port 501 from contamination by subsequent processes. In this embodiment, the material of the protective layer 502 is polyimide.

[0063] Next, referring to Figures 6 and 7, step S3 is performed: an encapsulation layer 7 is formed on the first redistribution layer 3 to cover the conductive pillar 4 and the optical chip 5, and the encapsulation layer 7 exposes the conductive pillar 4 and the optical chip solder joint 500.

[0064] As an example, the method of forming the encapsulation layer 7 may include molding, vacuum lamination and spin coating, etc. The material of the encapsulation layer 7 may be commonly used epoxy resin. No excessive restrictions are placed here on the material and preparation method of the encapsulation layer 7.

[0065] As an example, a grinding method is used to thin the encapsulation layer 7 to expose the conductive pillar 4 and the optical chip solder joint 500, such as chemical mechanical polishing (CMP), to obtain a smoother surface, which is beneficial for subsequent processes.

[0066] Next, referring to Figure 8, step S4 is performed: a second redistribution layer 8 is formed on the encapsulation layer 7, and the second redistribution layer 8 is electrically connected to the conductive pillar 4 and the optical chip solder joint 500.

[0067] As an example, the second redistribution layer 8 may be a damascus redistribution layer, an organic redistribution layer, or a combination of both. That is, the material of the dielectric layer may include silicon oxide, silicon nitride, or polyimide (PI), and the material of the metal wiring may include copper, aluminum, etc. The material, number of layers, layout, and preparation method of the second redistribution layer 8 may be selected as needed, and no excessive restrictions are imposed here.

[0068] As an example, in the second rewiring layer 8, no metal wiring is formed in the dielectric layer located directly above the optical signal port 501, which facilitates the subsequent opening of the optical port.

[0069] As an example, the second redistribution layer 8 has protruding metal pillars (copper pillars) on the side away from the encapsulation layer 7, which facilitates subsequent bonding with the electrical chip 9.

[0070] Next, referring to Figure 9, step S5 is performed: an electrical chip 9 is provided, the electrical chip 9 includes a first side and a second side disposed opposite to each other, the second side of the electrical chip 9 is provided with an electrical chip solder joint 900, the second side of the electrical chip 9 is bonded to the second redistribution layer 8, the electrical chip solder joint 900 is electrically connected to the second redistribution layer 8, wherein, in the vertical projection, the electrical chip 9 does not cover the optical signal port 501.

[0071] As an example, the electrical chip 9 is bonded to the second redistribution layer 8 by flip-chip bonding (FC Bond).

[0072] As an example, a bottom filler layer 10 with filling gaps can also be formed between the electrical chip 9 and the second redistribution layer 8 to improve the bonding strength and avoid the influence of moisture, gas, etc. The material of the bottom filler layer 10 can be selected as needed, and it can be an insulating material. There are no excessive restrictions here.

[0073] Next, referring to Figures 10 and 11, step S6 is performed: an opening 11 is formed in the second redistribution layer 8, the opening 11 exposing the optical signal port 501, and an optical bridging structure 12 is formed on the second redistribution layer 8, the optical bridging structure 12 covering the opening 11 to correspond to the optical signal port 501.

[0074] As an example, the opening 11 can be formed by laser drilling or dry etching, and the opening 11 penetrates the protective layer 502 located above the optical signal port 501.

[0075] As an example, the optical bridging structure 12 can be an optical fiber, an optical waveguide, a microlens, or any other suitable optical bridge device. The optical bridging structure 12 can be disposed on the second redistribution layer 8 by adhesion, bonding, or any other suitable method. The optical chip 5 exchanges optical signals with the external environment through the optical signal port 501 and the optical bridging structure 12.

[0076] As an example, the optical bridging structure 12 extends to the side of the packaging structure, which can increase modular combination capabilities.

[0077] As an example, as shown in FIG12, the step of removing the substrate 1 is also included, wherein the substrate 1 is removed based on the separation layer 2.

[0078] Thus, a three-dimensional stacked optoelectronic chip packaging structure is obtained. Referring to Figure 12, the packaging structure includes a first redistribution layer 3, conductive pillars 4, an optical chip 5, a second redistribution layer 8, a packaging layer 7, an electrical chip 9, an opening 11, and an optical bridging structure 12. The conductive pillars 4 are located above the first redistribution layer 3 and electrically connected to it. The optical chip 5 is located above the first redistribution layer 3, and optical chip solder joints 500 and optical signal ports 501 are provided on the side of the optical chip 5 away from the first redistribution layer 3. The second redistribution layer 8 is located above the conductive pillars 4 and the optical chip 5, and the second redistribution layer 8 is connected to the conductive pillars 4 and the optical chip 5. The optical chip solder joint 500 is electrically connected; the encapsulation layer 7 is located between the first redistribution layer 3 and the second redistribution layer 8, and covers the conductive pillar 4 and the exposed surface of the optical chip 5; the electrical chip 9 is located above the second redistribution layer 8, and the electrical chip 9 is electrically connected to the second redistribution layer 8, wherein, in the vertical projection, the electrical chip 9 does not cover the optical signal port 501; the opening 11 penetrates the second redistribution layer 8 to expose the optical signal port 501; the optical bridging structure 12 is located above the second redistribution layer 8, and the optical bridging structure 12 covers the opening 11 to correspond to the optical signal port 501.

[0079] As an example, the first redistribution layer 3 may be a damascus redistribution layer, an organic redistribution layer, or a stacked combination of both. That is, the material of the dielectric layer may include silicon oxide, silicon nitride, or polyimide (PI), etc., and the material of the metal wiring may include copper, aluminum, etc.

[0080] As an example, the conductive post 4 is made of copper, and the bottom end of the conductive post 4 is electrically connected to the metal wiring in the first rewiring layer 3.

[0081] As an example, a wafer bonding film 6 is provided between the optical chip 5 and the first redistribution layer 3, and the optical chip 5 is bonded to the first redistribution layer 3 through the wafer bonding film 6.

[0082] As an example, the optical chip solder joint 500 is a copper bump. A protective layer 502 is also provided on the side of the optical chip 5 away from the first redistribution layer 3. The protective layer 502 covers the sidewall of the optical chip solder joint 500 and covers the optical signal port 501. In this embodiment, the protective layer 502 is made of polyimide. The opening 11 extends through the protective layer 502 located above the optical signal port 501.

[0083] As an example, the encapsulation layer 7 is made of commonly used epoxy resin.

[0084] As an example, the second redistribution layer 8 may be a damascus redistribution layer, an organic redistribution layer, or a combination of both. That is, the material of the dielectric layer may include silicon oxide, silicon nitride, or polyimide (PI), and the material of the metal wiring may include copper, aluminum, etc.

[0085] As an example, the electrical chip 9 is provided with an electrical chip solder joint 900 on the side facing the second redistribution layer 8. The electrical chip 9 is bonded to the second redistribution layer 8 by a flip chip bonding method, wherein the electrical chip solder joint 900 is electrically connected to the second redistribution layer 8.

[0086] As an example, a bottom filler layer 10 is provided between the electrical chip 9 and the second rewiring layer 8 to fill the gap, so as to improve the bonding strength and avoid the influence of moisture, gas, etc.

[0087] As an example, the optical bridging structure 12 can be an optical fiber, an optical waveguide, a microlens, or any other suitable optical bridge device. The optical bridging structure 12 can be disposed on the second redistribution layer 8 by adhesion, bonding, or any other suitable method. The optical chip 5 exchanges optical signals with the external environment through the optical signal port 501 and the optical bridging structure 12.

[0088] As an example, the optical bridging structure 12 extends to the side of the packaging structure, which can increase modular combination capabilities.

[0089] In summary, the 3D stacked optoelectronic chip packaging structure and fabrication method of the present invention, in which the optical chip and electrical chip are 3D stacked and packaged, can effectively reduce the packaging area. Furthermore, the optical chip and electrical chip are interconnected through a redistribution layer and conductive pillars, which can effectively shorten the transmission path of the optical chip and electrical chip. Compared with 2D optoelectronic integrated packaging, the transmission path can be shortened by 20 times, and it has low insertion loss and RC delay. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0090] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a three-dimensional stacked optoelectronic chip packaging structure, characterized in that, Includes the following steps: A substrate is provided, a first redistribution layer is formed on the substrate, and conductive pillars are formed on the first redistribution layer, the conductive pillars being electrically connected to the first redistribution layer; An optical chip is provided, the optical chip including a first side and a second side disposed opposite to each other, the first side of the optical chip is provided with optical chip solder joints and optical signal ports, and the second side of the optical chip is bonded to the first redistribution layer; An encapsulation layer is formed on the first redistribution layer to cover the conductive pillars and the optical chip, and the encapsulation layer exposes the conductive pillars and the solder joints of the optical chip. A second redistribution layer is formed on the encapsulation layer, and the second redistribution layer is electrically connected to the conductive pillar and the optical chip solder joint; An electrical chip is provided, the electrical chip including a first side and a second side disposed opposite to each other, the second side of the electrical chip being provided with electrical chip solder joints, the second side of the electrical chip being bonded to a second redistribution layer, the electrical chip solder joints being electrically connected to the second redistribution layer, wherein, in the vertical projection, the electrical chip does not cover the optical signal port; An opening is formed in the second redistribution layer to expose the optical signal port, and an optical bridging structure is formed on the second redistribution layer to cover the opening and correspond to the optical signal port.

2. The method for fabricating a three-dimensional stacked optoelectronic chip packaging structure according to claim 1, characterized in that: The optical chip is bonded to the first rewiring layer via a wafer bonding film.

3. The method for fabricating a three-dimensional stacked optoelectronic chip packaging structure according to claim 1, characterized in that: The electrical chip is bonded to the second redistribution layer via flip-chip bonding.

4. The method for fabricating a three-dimensional stacked optoelectronic chip packaging structure according to claim 1, characterized in that: The method for forming the opening in the second redistribution layer includes laser drilling or dry etching.

5. The method for fabricating a three-dimensional stacked optoelectronic chip packaging structure according to claim 1, characterized in that: After forming the optical bridging structure on the second redistribution layer, the method further includes the step of removing the substrate.

6. The method for fabricating a three-dimensional stacked optoelectronic chip packaging structure according to claim 5, characterized in that: A separation layer is also formed between the substrate and the first redistribution layer, wherein the substrate is removed based on the separation layer.

7. The method for fabricating a three-dimensional stacked optoelectronic chip packaging structure according to claim 1, characterized in that: The conductive pillars include copper pillars.

8. The method for fabricating a three-dimensional stacked optoelectronic chip packaging structure according to claim 1, characterized in that: The substrate includes a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, or a ceramic substrate.

9. A three-dimensional stacked optoelectronic chip packaging structure, characterized in that, include: First redistribution layer; A conductive post is located above the first redistribution layer and is electrically connected to the first redistribution layer. An optical chip is located above the first redistribution layer, and optical chip solder joints and optical signal ports are provided on the side of the optical chip away from the first redistribution layer. The second redistribution layer is located above the conductive pillar and the optical chip, and the second redistribution layer is electrically connected to the solder joints of the conductive pillar and the optical chip. An encapsulation layer is located between the first redistribution layer and the second redistribution layer, and covers the conductive pillars and the exposed surface of the optical chip; An electrical chip is located above the second redistribution layer and is electrically connected to the second redistribution layer, wherein, in its vertical projection, the electrical chip does not cover the optical signal port; An opening is provided, penetrating the second rewiring layer to expose the optical signal port; An optical bridging structure, located above the second redistribution layer, covers the opening to correspond to the optical signal port.

10. The three-dimensional stacked optoelectronic chip packaging structure according to claim 9, characterized in that: A wafer bonding film is disposed between the optical chip and the first redistribution layer, and the optical chip is bonded and fixed to the first redistribution layer by the wafer bonding film.

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