Display substrate

Abstract

A display substrate. The display substrate is provided with a plurality of sub-pixels (SP) arranged in a plurality of rows and a plurality of columns, and comprises a base substrate (10), a plurality of data lines (Da), and a plurality of first data line leads (DL1); the base substrate (10) comprises a display area (AA) and a non-display area (NA); the plurality of sub-pixels (SP) are arranged in the display area (AA); the plurality of data lines (Da) are arranged on the base substrate (10) and located at least in the display area (AA), extend in a first direction (R1) and are configured to provide data signals to the plurality of sub-pixels (SP); the plurality of first data line leads (DL1) are arranged on the base substrate (10) and extend from the display area (AA) to the non-display area (NA) in the first direction (R1); at least some of the plurality of data lines (Da) are respectively electrically connected to the plurality of first data line leads (DL1) to acquire data signals from the non-display area (NA); at least one of the plurality of first data line leads (DL1) comprises a first lead portion (DL11) and a second lead portion (DL12); the first lead portion (DL11) is located in a first conductive layer (M1); the second lead portion (DL12) is located in a second conductive layer (M2); and the first lead portion (DL11) and the second lead portion (DL12) are electrically connected by means of vias.

Description

Display substrate

[0001] This application claims priority to Chinese Patent Application No. 202411216350.1, filed on August 30, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of this disclosure relate to a display substrate. Background Technology

[0003] Organic light-emitting diode (OLED) display devices have a series of advantages such as self-illumination, high contrast, high definition, wide viewing angle, low power consumption, fast response speed, and low manufacturing cost. As a result, they have become one of the key development directions for next-generation display devices and have therefore received increasing attention. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display substrate having a plurality of sub-pixels arranged in multiple rows and columns, and including a substrate, a plurality of data lines, and a plurality of first data line leads; the substrate includes a display area and a non-display area, wherein the plurality of sub-pixels are disposed in the display area, the plurality of data lines are disposed on the substrate and at least located in the display area, extending along a first direction and configured to provide data signals to the plurality of sub-pixels, the plurality of first data line leads are disposed on the substrate and extend along the first direction from the display area to the non-display area, wherein at least a portion of the plurality of data lines is electrically connected to the plurality of first data line leads to obtain data signals from the non-display area, at least one of the plurality of first data line leads includes a first lead portion and a second lead portion, the first lead portion is located in a first conductive layer, the second lead portion is located in a second conductive layer, and the first lead portion and the second lead portion are electrically connected through a via.

[0005] For example, in a display substrate provided in at least one embodiment of this disclosure, one or two first data line leads are provided between two adjacent data lines in a direction parallel to the substrate.

[0006] For example, in a display substrate provided in at least one embodiment of this disclosure, the second conductive layer is located on the side of the first conductive layer away from the substrate, and the plurality of data lines are located in the second conductive layer.

[0007] For example, in a display substrate provided in at least one embodiment of this disclosure, a first insulating layer is provided between the second conductive layer and the first conductive layer, and the via includes a first via and a second via penetrating the first insulating layer, and the two ends of the first lead portion are respectively connected to the second lead portion through the first via and the second via.

[0008] For example, in a display substrate provided in at least one embodiment of this disclosure, for a first data line lead and a data line disposed adjacent to each other, the first insulating layer further has a third via that overlaps with the data line in a direction perpendicular to the substrate, wherein in the first direction, the third via is located between the first via and the second via.

[0009] For example, in a display substrate provided in at least one embodiment of this disclosure, two data lines and two first data line leads are disposed between two adjacent columns of sub-pixels, wherein the two data lines are located between the two first data line leads, or the two first data line leads are located between the two data lines.

[0010] For example, in at least one embodiment of the display substrate provided in this disclosure, the two data lines are arranged symmetrically, and the third vias corresponding to the two data lines are arranged symmetrically; the two first data line leads are arranged symmetrically, and the first vias and second vias corresponding to the two first data line leads are arranged symmetrically.

[0011] For example, in a display substrate provided in at least one embodiment of this disclosure, two data lines and two first data line leads are provided between two adjacent columns of sub-pixels, and the two first data line leads are located between the two data lines; in the first direction, the first vias and second vias corresponding to the two first data line leads are arranged alternately at intervals.

[0012] For example, at least one embodiment of the present disclosure provides a display substrate that further includes: a second data line lead located in the first conductive layer and extending along a second direction, the second direction being different from the first direction, wherein at least one of the two first data line leads is connected to the second data line lead via a first adapter wire, the first adapter wire being located in the first conductive layer and at least partially overlapping the at least one first data line lead in a direction perpendicular to the substrate.

[0013] For example, in a display substrate provided in at least one embodiment of this disclosure, the second lead portion of the two first data line leads respectively includes a bent portion that bends toward each other.

[0014] For example, in a display substrate provided in at least one embodiment of this disclosure, two data lines and two first data line leads are provided between two adjacent columns of sub-pixels, and the two first data line leads are located between the two data lines; in the first direction, the first vias and second vias corresponding to the two first data line leads are located on the same straight line.

[0015] For example, in at least one embodiment of the display substrate provided in this disclosure, two data lines are disposed between two adjacent columns of sub-pixels in a direction parallel to the substrate, and a first data line lead is disposed between the two data lines. The display substrate further includes: a second data line lead located in the first conductive layer and extending along a second direction, the second direction being different from the first direction. The first data line lead is connected to the second data line lead through a second adapter wire located in the first conductive layer. In a direction perpendicular to the substrate, the second adapter wire at least partially overlaps with one of the two data lines.

[0016] For example, in at least one embodiment of the display substrate provided in this disclosure, two data lines are disposed between two adjacent columns of sub-pixels in a direction parallel to the substrate, and two first data line leads are disposed between the two data lines; or, two first data line leads are disposed between two adjacent columns of sub-pixels, and two data lines are disposed between the two first data line leads. The display substrate further includes: a plurality of second data line leads located in the first conductive layer and extending along a second direction, the second direction being different from the first direction; a first data line among the two data lines is connected to a first second data line lead among the plurality of second data line leads, and the first second data line lead is connected to a first first data line lead spaced at least one sub-pixel apart from the first data line; a second data line among the two data lines is connected to a second second data line lead among the plurality of second data line leads, and the second second data line lead is connected to a second first data line lead spaced at least one sub-pixel apart from the second data line.

[0017] For example, in a display substrate provided in at least one embodiment of this disclosure, the first data line of the two data lines is connected to the first second data line lead of the plurality of second data line leads via a third adapter wire, and the first data line and the third adapter wire at least partially overlap in a direction perpendicular to the substrate; the second data line of the two data lines is connected to the second second data line lead of the plurality of second data line leads via a fourth adapter wire, and the second data line and the fourth adapter wire at least partially overlap in a direction perpendicular to the substrate.

[0018] For example, in a display substrate provided in at least one embodiment of this disclosure, the first data line of the two data lines is connected to the first second data line lead of the plurality of second data line leads via a third adapter wire, and in a direction perpendicular to the substrate, the third adapter wire and the first data line lead adjacent to the first data line at least partially overlap; the second data line of the two data lines is connected to the second second data line lead of the plurality of second data line leads via a fourth adapter wire, and in a direction perpendicular to the substrate, the fourth adapter wire and the first data line lead adjacent to the second data line at least partially overlap.

[0019] For example, in a display substrate provided in at least one embodiment of this disclosure, the first second data line lead is connected to a first first data line lead spaced at least one sub-pixel apart from the first data line via a fifth adapter wire. In a direction perpendicular to the substrate, the fifth adapter wire and the data line adjacent to the first first data line lead at least partially overlap. The second second data line lead is connected to a second first data line lead spaced at least one sub-pixel apart from the second data line via a sixth adapter wire. In a direction perpendicular to the substrate, the sixth adapter wire and the data line adjacent to the second first data line lead at least partially overlap.

[0020] For example, in a display substrate provided in at least one embodiment of this disclosure, the first second data line lead is directly connected to a first first data line lead spaced at least one sub-pixel apart from the first data line through a fourth via; the second second data line lead is directly connected to a second first data line lead spaced at least one sub-pixel apart from the second data line through a fifth via.

[0021] For example, in a display substrate provided in at least one embodiment of this disclosure, the first data line, the first second data line lead, and the first first data line lead form a first data line mesh, and the second data line, the second second data line lead, and the second first data line lead form a second data line mesh, with the second data line mesh located outside the first data line mesh.

[0022] For example, in a display substrate provided in at least one embodiment of this disclosure, two first data line leads located between the two data lines include disconnected portions that are disconnected from the first data line network and the second data line network. The display substrate also includes a first power line, and the disconnected portions are connected to the first power line.

[0023] For example, in at least one embodiment of the display substrate provided in this disclosure, the location of the break overlaps with the first conductive layer or the second conductive layer in a direction perpendicular to the substrate.

[0024] For example, in a display substrate provided in at least one embodiment of this disclosure, each of the plurality of sub-pixels includes a light-emitting device and a pixel driving circuit for driving the light-emitting device. The light-emitting device includes a first electrode connected to the pixel driving circuit, a second electrode spaced apart from the first electrode, and a light-emitting layer between the first electrode and the second electrode. The second electrode is electrically connected to the first power line.

[0025] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel driving circuit includes a transistor, the transistor includes a gate and a source / drain, the source / drain is electrically connected to the first electrode through a connecting electrode, the source / drain is located in the first conductive layer, and the connecting electrode is located in the second conductive layer.

[0026] For example, in at least one embodiment of the present disclosure, in a display substrate, two data lines are provided between adjacent first column sub-pixels and second column sub-pixels in a direction parallel to the substrate, a reset voltage line is provided between the two data lines, and two first data line leads are provided between adjacent second column sub-pixels and third column sub-pixels.

[0027] For example, in a display substrate provided in at least one embodiment of this disclosure, the data line adjacent to the second column of sub-pixels and the first data line lead are electrically connected through a first second data line lead, and the data line adjacent to the first column of sub-pixels and the first data line lead adjacent to the third column of sub-pixels are electrically connected through a second second data line lead.

[0028] For example, in a display substrate provided in at least one embodiment of this disclosure, two second power lines are further provided in adjacent second and third column sub-pixels, and the two first data line leads are located between the two second power lines. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0030] Figure 1 is a plan view of a display substrate provided in at least one embodiment of the present disclosure;

[0031] Figure 2 is a schematic diagram of the planar arrangement of some traces in a display substrate provided in at least one embodiment of the present disclosure;

[0032] Figure 3 is a schematic diagram of the cross-section of the trace in Figure 2 along line aa;

[0033] Figure 4 is a schematic diagram of another planar arrangement of some traces in a display substrate provided in at least one embodiment of the present disclosure;

[0034] Figures 5A and 5B are schematic diagrams showing the overlap between some of the traces in Figures 2 and 4 and the first electrode, respectively.

[0035] Figure 6 is another planar arrangement of some traces in a display substrate provided in at least one embodiment of the present disclosure;

[0036] Figure 7 is a schematic diagram of the planar arrangement of a display substrate provided in at least one embodiment of the present disclosure;

[0037] Figures 8-11 are schematic diagrams of various planar arrangements of some traces in a display substrate provided in at least one embodiment of the present disclosure;

[0038] Figure 12 is a schematic diagram of the planar arrangement of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure, where the first data line lead adopts a 2-in-1 design;

[0039] Figure 13 is a schematic diagram of another planar arrangement of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure, where the first data line lead adopts a 2-in-1 design;

[0040] Figures 14 and 15 are schematic diagrams of the planar arrangement of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure, where the first data line lead adopts a 1-to-1 design.

[0041] Figure 16 is an enlarged view of the area within the dashed box in Figure 14;

[0042] Figure 17 is a planar schematic diagram showing the overlap between some of the traces in Figure 16 and the first electrode;

[0043] Figure 18 is a schematic diagram of the connection between data lines, first data line leads and second data line leads in a display substrate provided in at least one embodiment of the present disclosure;

[0044] Figure 19 is a schematic diagram of the connection between the first data line lead and the second data line lead in a display substrate provided in at least one embodiment of the present disclosure;

[0045] Figure 20 is a planar schematic diagram showing the overlap between some of the traces in Figure 19 and the first electrode;

[0046] Figure 21A is a schematic diagram of the connection between data lines and second data line leads in a display substrate provided in at least one embodiment of the present disclosure;

[0047] Figure 21B is another schematic diagram of the connection between data lines and second data line leads in a display substrate provided in at least one embodiment of the present disclosure;

[0048] Figure 22 is another schematic diagram of the connection between the first data line lead and the second data line lead in a display substrate provided in at least one embodiment of the present disclosure;

[0049] Figures 23 and 24 are schematic diagrams of another planar arrangement of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure, under the 1-to-1 design.

[0050] Figure 25 is a schematic diagram of another planar arrangement of the first data line lead and the data line in the display substrate provided in at least one embodiment of the present disclosure;

[0051] Figures 26 and 27 are schematic diagrams of another planar arrangement of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure, under the 1-to-1 design.

[0052] Figure 28 is a planar schematic diagram showing the overlap between some of the traces in Figure 27 and the first electrode;

[0053] Figure 29 is a partial cross-sectional schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0054] Figure 30 is a circuit diagram of a pixel driving circuit of a display substrate provided in at least one embodiment of the present disclosure;

[0055] Figure 31 is a timing diagram of the pixel driving circuit in Figure 30;

[0056] Figure 32 is a schematic diagram showing that data lines and first data line leads are bonded in a non-display area in a display substrate provided by at least one embodiment of the present disclosure;

[0057] Figure 33 is another schematic diagram showing the binding of data lines and first data line leads in a non-display area of ​​a display substrate provided in at least one embodiment of the present disclosure; and

[0058] Figures 34 and 35 are schematic diagrams of the arrangement of the first data line lead in a display substrate provided by at least one embodiment of the present disclosure in another plane under the 1-to-1 design. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0060] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0061] With the increasing demand for narrow bezels in display devices, such as mobile phones, a series of design solutions dedicated to reducing bezel size have emerged. FIP (Fanout In Pixel) technology is an excellent method for narrowing bezels. In FIP technology, by fanning out lines within the display area, the space occupied by the fanout at the bottom corner of the display device can be effectively reduced, thus achieving the goal of narrowing the bezel.

[0062] In display substrates, the wire layout based on FIP technology is a crucial factor that determines the display effect, manufacturing difficulty, and yield of the display substrate. Therefore, how to optimize the wire layout is a topic that those skilled in the art are constantly researching.

[0063] This disclosure provides at least one embodiment of a display substrate having multiple sub-pixels arranged in multiple rows and columns, and including a substrate, multiple data lines, and multiple first data line leads. The substrate includes a display area and a non-display area, wherein the multiple sub-pixels are disposed in the display area, the multiple data lines are disposed on the substrate and located in the display area, extending along a first direction and configured to provide data signals to the multiple sub-pixels, and the multiple first data line leads are disposed on the substrate and extend along the first direction from the display area to the non-display area. At least a portion of the multiple data lines is electrically connected to the multiple first data line leads to obtain data signals from the non-display area. At least one of the multiple first data line leads includes a first lead portion and a second lead portion, the first lead portion being located in a first conductive layer, the second lead portion being located in a second conductive layer, and the first lead portion and the second lead portion being electrically connected through a via.

[0064] In the embodiments of this disclosure, a first conductive layer and a second conductive layer are used for wiring the first data line lead, and the first data line lead is designed with a jumper design in the first and second conductive layers. On the one hand, compared with single conductive layer wiring, the above design can prevent electrostatic discharge (ESD) during the manufacturing process and improve the manufacturing yield of the display substrate. On the other hand, using double metal layer wiring can reduce manufacturing costs and wiring difficulty compared with more layers of wiring, and can simultaneously achieve narrow bezels and thinness of the display substrate.

[0065] The display substrate provided in this disclosure will be described below through several specific embodiments.

[0066] This disclosure provides a display substrate in at least one embodiment. FIG1 shows a planar schematic diagram of the display substrate, FIG2 shows a planar schematic diagram of the arrangement of some traces in the display substrate, and FIG3 shows a cross-sectional schematic diagram of the traces in FIG2 along line aa. As shown in FIG1-FIG3, the display substrate has multiple sub-pixels SP arranged in multiple rows and columns, and includes a substrate 10, multiple data lines Da, and multiple first data line leads DL1, etc.

[0067] As shown in Figures 1-3, the substrate 10 includes a display area AA and a non-display area NA. Multiple sub-pixels SP are disposed in the display area AA for display. Multiple data lines Da are disposed on the substrate 10 and at least located in the display area AA, extending, for example, into the non-display area NA in some embodiments. The multiple data lines Da extend along a first direction R1, and are electrically connected, for example, to the multiple sub-pixels SP, configured to provide data signals to the multiple sub-pixels SP. Multiple first data line leads DL1 are disposed on the substrate 10 and extend along the first direction R1 from the display area AA to the non-display area NA, for example, extending into the non-display area NA below the display area AA, so as to be bonded in that area and connected to an integrated circuit IC (not shown in the figures). At least portions of the multiple data lines Da are respectively electrically connected to at least one of the multiple first data line leads DL1 to obtain data signals from the non-display area NA.

[0068] For example, in some embodiments, a portion of multiple data lines Da is electrically connected to a first data line lead DL1 to obtain data signals from a non-display area NA, while another portion of the multiple data lines Da extends directly to the non-display area NA to obtain data signals from the non-display area NA. In this case, the multiple first data line leads DL1 can be used to plan the location where a portion of the aforementioned multiple data lines Da extends to the non-display area NA, thereby facilitating the bonding of the multiple data lines Da and the multiple first data line leads DL1 used for transmitting data signals in the non-display area NA, for example, making the bonding positions more concentrated to achieve a narrow bezel.

[0069] As shown in Figures 2 and 3, at least one of the multiple first data line leads DL1 (e.g., multiple first data line leads DL1, e.g., all first data line leads DL1) includes a first lead portion DL11 and a second lead portion DL12. The first lead portion DL11 is located in the first conductive layer M1, and the second lead portion DL12 is located in the second conductive layer M2. The first lead portion DL11 and the second lead portion DL12 are electrically connected through vias (e.g., the first via V1 and the second via V2, which will be described in detail later).

[0070] Therefore, the first data line lead DL1 adopts a jumper design in the first conductive layer M1 and the second conductive layer M2, which can prevent adverse phenomena such as electrostatic discharge (ESD) during the manufacturing process and improve the manufacturing yield of the display substrate.

[0071] For example, in some embodiments, at least one first data line lead DL1 is provided between two adjacent data lines Da in a direction parallel to the substrate 10. For example, one or two first data line leads DL1 are provided. Figure 2 shows two first data line leads DL1 provided between two adjacent data lines Da as an example. The case where one first data line lead DL1 is provided between two adjacent data lines Da will be described in detail later.

[0072] For example, in some embodiments, as shown in FIG3, the second conductive layer M2 is located on the side of the first conductive layer M1 away from the substrate 10, and multiple data lines Da are located on the second conductive layer M2. For example, in other embodiments, the first conductive layer M1 may be located on the side of the second conductive layer M2 away from the substrate 10.

[0073] For example, in some embodiments, as shown in FIG3, a first insulating layer 11 is provided between the second conductive layer M2 and the first conductive layer M1 to insulate the conductive patterns in the second conductive layer M2 and the first conductive layer M1. Vias for connecting the first lead portion DL11 and the second lead portion DL12 include a first via V1 and a second via V2 penetrating the first insulating layer 11. The two ends of the first lead portion DL11 are connected to the second lead portion DL12 through the first via V1 and the second via V2, respectively, thereby realizing a jumper design.

[0074] For example, in FIG3, a film layer X is disposed on the substrate 10. The film layer X may include a stack of multiple conductive layers and multiple insulating layers, which will be described in detail below with reference to FIG29.

[0075] For example, in some embodiments, as shown in FIG2, for an adjacent first data line lead DL1 and a data line Da, the first insulating layer 11 further has a third via V3 overlapping the data line Da in a direction perpendicular to the substrate 10, for electrical connection of the data line Da, such as for connecting the data line Da to the pixel driving circuit of the sub-pixel SP (described in detail below), or for connecting the data line Da to the first data line lead DL1 or the second data line lead DL2 (described in detail below); in the first direction R1, the third via V3 is located between the first via V1 and the second via V2, thereby the third via V3 is staggered from the first via V1 and the second via V2, and the distance between adjacent first data line leads DL1 and data line Da can be arranged closer to save wiring layout space.

[0076] For example, in some embodiments, two data lines Da and two first data line leads DL1 are provided between two adjacent columns of sub-pixels SP. For example, as shown in FIG2, the two first data line leads DL1 are located between the two data lines Da; or, as shown in FIG4, the two data lines Da are located between the two first data line leads DL1; or, the two first data line leads DL1 and the two data lines Da are arranged sequentially or alternately, for example, it can be first data lead DL1, one data line Da, first data lead DL1, one data line Da, or one data line Da, first data lead DL1, one data line Da, first data lead DL1.

[0077] Therefore, the technical solutions in Figures 2 and 4 adopt a design where each column of sub-pixels SP corresponds to one data line Da and one first data line lead DL1, hereinafter referred to as a 1-in-1 design. Compared to the design where each two columns of sub-pixels SP correspond to two data lines Da and one first data line lead DL1, hereinafter referred to as a 2-in-1 design, the 1-in-1 design has more first data line leads DL1, which facilitates wiring connections, shortens the total length of the first data line lead DL1 and the second data line lead DL2, reduces the resistance and overlapping capacitance of the data line leads, reduces data signal loss, and reduces data line load. In addition, the 1-in-1 design can increase, for example, the density of the first power line VSS connection wire (the part DL0 mentioned later, which will be introduced later), to better reduce the voltage drop of the first power line VSS and reduce screen power consumption. In addition, the 1-in-1 design can also connect data signals through multiple first data line leads DL1 located in the middle of the display area AA, so as to reduce the width of the Fanout connection below the display area AA and reduce the binding space of the data line Da and the first data line lead DL1 used to bind and transmit data signals in the non-display area NA below the display area AA, thereby realizing a narrow bezel design (which will be described in detail later).

[0078] For example, in some embodiments, as shown in Figures 2 and 4, the two data lines Da between two adjacent columns of sub-pixels SP are symmetrically arranged, and the third vias V3 corresponding to the two data lines Da are symmetrically arranged; for example, the two first data line leads DL1 between two adjacent columns of sub-pixels SP are symmetrically arranged, and the first vias V1 and the second vias V2 corresponding to the two first data line leads DL1 are also symmetrically arranged.

[0079] For example, in the design of Figure 2, after the first electrode 1041 (e.g., the anode of the light-emitting device EM of the sub-pixel SP, which will be described in detail later) is fabricated on the side of the second conductive layer M2 away from the substrate 10, as shown in Figure 5A, the first electrode 1041 may overlap with the first via V1 and the second via V2 corresponding to the first data line lead DL1; in the design of Figure 4, after the first electrode 1041 is fabricated on the side of the second conductive layer M2 away from the substrate 10, as shown in Figure 5B, the first electrode 1041 can avoid the first via V1 and the second via V2 corresponding to the first data line lead DL1, thereby improving the flatness of the first electrode 1041.

[0080] For example, in some embodiments, the two first data line leads DL1 can also be arranged in other ways, such as an asymmetrical arrangement. For example, as shown in Figure 6, when the two first data line leads DL1 are located between the two data lines Da, the two first data line leads DL1 are arranged in a straight line along the first direction R1, and the first vias V1 and second vias V2 corresponding to the two first data line leads DL1 can be arranged alternately, or staggered. For example, in the first direction, from top to bottom, the first vias V1 corresponding to the left first data line lead DL1, the first vias V1 corresponding to the right first data line lead DL1, the second vias V2 corresponding to the left first data line lead DL1, and the second vias V2 corresponding to the right first data line lead DL1 are arranged sequentially. At this time, the first vias V1 and second vias V2 corresponding to the two first data line leads DL1 are asymmetrical, which can reduce the lateral arrangement space occupied by the first vias V1 and second vias V2, making the arrangement of the two first data line leads DL1 more compact.

[0081] For example, in some embodiments, as shown in FIG7, the display substrate may further include a second data line lead DL2, which is located in the first conductive layer M1 and extends along a second direction R2. The second direction R2 is different from the first direction R1; for example, the second direction R2 is perpendicular to the first direction R1. For example, the second data line lead DL2 can be used to connect a data line Da and a first data line lead DL1 that are a certain distance apart in the second direction R2.

[0082] For example, as shown in Figure 7, at least one of the two first data line leads DL1 between two adjacent columns of sub-pixels SP is connected to the second data line lead DL2 through a first adapter line Z1. The first adapter line Z1 can be located in the first conductive layer M1, and in the direction perpendicular to the substrate 10, the first adapter line Z1 and at least one first data line lead DL1 overlap at least partially, so that the first adapter line Z1 is blocked, thereby avoiding defects such as screen-off mura (a defective phenomenon of displaying strip-shaped traces when the display substrate is in a screen-off state) from appearing on the display substrate.

[0083] For example, as shown in Figure 7, the first adapter line Z1 is straight. In the embodiment of Figure 7, it connects the first data line lead DL1 and the second data line lead DL2 along the first direction R1, that is, along the vertical direction in the figure. This can shorten the length of the adapter line and reduce the overlap capacitance of the adapter line. When both first data line leads DL1 are connected to the second data line lead DL2 through the first adapter line Z1, the first adapter line Z1 and the second data line lead DL2 are basically symmetrical. Therefore, when the first electrode 1041 is fabricated on the second conductor layer M2, the flatness of the first electrode 1041 can be optimized. In addition, the first adapter line Z1 and the first data line lead DL1 overlap at least partially, so that the first data line lead DL1 can block the first adapter line Z1, thereby reducing screen-off mura. Furthermore, the wiring layout of the embodiment of Figure 7 is less modified than the wiring layout of the 2-in-1 design.

[0084] For example, in some embodiments, as shown in FIG8, the second lead portions DL12 of the two first data line leads DL1 between two adjacent columns of sub-pixels SP may each include a bent portion B that bends inward toward each other. Compared to the embodiment of FIG6, the two first data line leads DL1 are recessed inward toward each other, which can further save lateral space. This saved lateral space can be used to widen, for example, the width of the second power line VDD (described in detail later), to reduce the voltage drop of the second power line VDD. For example, the situation shown in the embodiment of FIG8 can also be applied to the connection relationship of FIG7.

[0085] For example, in some embodiments, as shown in Figures 9-11, in the first direction R1, the first via V1 and the second via V2 corresponding to the two first data line leads DL1 between two adjacent columns of sub-pixels SP can be located on the same straight line. This can further reduce the lateral space occupied by the two first data line leads DL1 and the first via V1 and the second via V2. For example, the embodiments in Figures 9-11 employ different jumper arrangement methods.

[0086] For example, in the embodiment of FIG9, as shown in FIG9, in the first direction R1, the first vias V1 and the second via V2 corresponding to the two first data line leads DL1 are located on a straight line extending along the first direction R1. In the direction from top to bottom, the first vias V1 and the second via V2 corresponding to the left first data line lead DL1 and the first vias V1 and the second via V2 corresponding to the right first data line lead DL1 are arranged sequentially. Compared with the embodiments of FIG6 and FIG8, in the embodiment of FIG9, the arrangement of the first vias V1 and the second via V2 is more neat and symmetrical, which can improve the flatness of the first electrode 1041 subsequently formed above the second conductive layer M2. In addition, the first lead portions DL11 of the two first data line leads DL1 are also located on the same straight line, making the lateral arrangement space of the first lead portions DL11 smaller, which is suitable for situations where there are many traces in the first conductive layer M1, so as to facilitate the arrangement of traces in the first conductive layer M1.

[0087] For example, in the embodiment of FIG10, as shown in FIG10, in the first direction R1, the first via V1 and the second via V2 corresponding to the two first data line leads DL1 are located on a straight line extending along the first direction R1. In the direction from top to bottom, the first via V1 corresponding to the left first data line lead DL1, the first via V1 corresponding to the right first data line lead DL1, the second via V2 corresponding to the left first data line lead DL1 and the second via V2 corresponding to the right first data line lead DL1 are arranged sequentially. At this time, both the first lead portion DL11 and the second lead portion DL12 have bent portions. Compared with the embodiment of FIG9, the second lead portion DL12 in the second conductive layer M2 has fewer protruding portions on the left and right, saving the arrangement space of the second conductive layer M2, which is suitable for situations where there are many traces in the second conductive layer M2.

[0088] For example, in the embodiment of FIG11, as shown in FIG11, in the first direction R1, the first via V1 and the second via V2 corresponding to the two first data line leads DL1 are located on a straight line extending along the first direction R1. In the direction from top to bottom, the first via V1 corresponding to the left first data line lead DL1, the first via V1 and the second via V2 corresponding to the right first data line lead DL1, and the second via V2 corresponding to the left first data line lead DL1 are arranged sequentially. Compared with the embodiments of FIG9 and FIG10, in the first conductive layer M1, the first lead portion DL11 only protrudes to the left, and in the second conductive layer M2, the second lead portion DL12 only protrudes to the right, which is suitable for the case of multiple sub-pixel SPs not being symmetrically designed.

[0089] For example, in the above embodiments, the positions of the first data line lead DL1 and the data line Da can be interchanged, and the arrangement of adjacent first data line leads DL1 and their vias can also be interchanged. The embodiments of this disclosure will not be described in detail here.

[0090] In the above embodiments of this disclosure, the first data line lead DL1 adopts a double conductive layer arrangement and a jumper design, which can avoid adverse phenomena such as electrostatic discharge during the manufacturing process of the display substrate, improve the manufacturing yield of the display substrate, and save costs. In addition, the above-mentioned 1-in-1 design can shorten the total length of the data line lead, reduce the resistance and overlapping capacitance of the data line lead, reduce data signal loss, reduce load, narrow the bezel, and reduce costs.

[0091] For example, in some embodiments, the display substrate may also adopt a 2-in-1 design. For example, FIG12 shows a schematic diagram of the planar arrangement of the first data line lead in a display substrate provided in at least one embodiment of the present disclosure using a 2-in-1 design. As shown in FIG12, in a direction parallel to the substrate 10, two data lines Da are arranged between two adjacent columns of sub-pixels SP, and a first data line lead DL1 is arranged between the two data lines Da. In this case, two data lines Da and one first data line lead DL1 are arranged for every two columns of sub-pixels SP. The data lines Da and the first data line lead DL1 extend along the first direction R1.

[0092] For example, as shown in FIG12, the display substrate may further include a second data line lead DL2, which is located in the first conductive layer M1 and extends along a second direction R2. The second direction R2 is different from the first direction R1; for example, the second direction R2 is perpendicular to the first direction R1. For example, the second data line lead DL2 can be used to connect a data line Da and the first data line lead DL1, which are a certain distance apart in the second direction R2. For example, the first data line lead DL1 is connected to the second data line lead DL2 through a second adapter Z2, which is located in the first conductive layer M1. In a direction perpendicular to the substrate 10, the second adapter Z2 at least partially overlaps with one of the two data lines Da (the data line Da on the right in FIG12) so that the second adapter Z2 is shielded.

[0093] For example, as shown in Figure 12, a break DS can be designed in the first data line lead DL1 or the second data line lead DL2 to disconnect the part of the first data line lead DL1 or the second data line lead DL2 used to connect different data lines Da, or to disconnect the part connected to the data line Da and the part connected to the first power line VSS, so as to prevent signal crosstalk.

[0094] For example, in some embodiments, the second data line lead DL2 is located in the first conductive layer M1, and the break DS of the second data line lead DL2 can overlap with the conductive pattern in the second conductive layer M2 so as to be shielded by the conductive pattern in the second conductive layer M2, for example, in FIG12, it is shielded by the second power line VDD in the second conductive layer M2; for example, the first data line lead DL1 is located in the second conductive layer M2, and the break in the first data line lead DL1 (not shown in FIG12) can overlap with the conductive pattern in the first conductive layer M1 so as to be shielded by the conductive pattern in the first conductive layer M1. Shielding the break can prevent defects such as light leakage from occurring on the display substrate.

[0095] For example, in the above embodiment, a vertically extending first data line lead DL1 is inserted between every two columns of sub-pixels SP. The first data line lead DL1 is connected to a horizontally extending second data line lead DL2 via a second adapter line Z2. The second adapter line Z2 at least partially overlaps with the data line Da, thereby being shielded by the data line Da, which can prevent defects such as screen-off mura from occurring on the display substrate. At the same time, the second adapter line Z2 can also avoid the source and drain electrodes SD and other structures of the transistors (described in detail later) of the pixel driving circuit of the sub-pixel SP, as shown in FIG12. For example, the second data line lead DL2 can overlap with signal lines in other conductive layers other than the first conductive layer M1, so as to be shielded / blocked by signal lines in other conductive layers other than the first conductive layer M1, such as reset voltage lines or scan signal lines, to prevent defects such as screen-off mura.

[0096] For example, in some embodiments, a portion of the longitudinally extending first data line lead DL1 and the laterally extending second data line lead DL2 is used to transmit data signals, i.e., connected to the data line Da, while the other portion can be used to connect to the first power line VSS to transmit a first power signal, thereby reducing the voltage drop of the first power line VSS. In this case, the portion used to transmit the data signal and the portion used to transmit the first power signal are disconnected through a break (e.g., break DS and breaks DS1, DS2, etc. mentioned below) to prevent signal crosstalk.

[0097] For example, in some embodiments, as shown in FIG13, there can be two adapter wires ZS for connecting the first data line lead DL1 and the second data line lead DL2, and the two adapter wires ZS can be arranged symmetrically. When this part of the first data line lead DL1 and the second data line lead DL2 is used to connect the first power line VSS, this design can increase the access points of the first power line VSS, further reduce the voltage drop, reduce the overall power consumption, and optimize the flatness of the subsequently formed first electrode 1041.

[0098] For example, Figure 14 is a schematic diagram of the planar arrangement of the first data line leads in a display substrate provided by at least one embodiment of the present disclosure using a 1-in-1 design. As shown in Figure 14, in the 1-in-1 design, two first data line leads DL1 are arranged between two adjacent columns of sub-pixels SP in a direction parallel to the substrate 10, and two data lines Da are arranged between two adjacent columns of sub-pixels SP, with the two first data line leads DL1 arranged between the two data lines Da; or, in some other embodiments, the positions of data lines Da and first data line leads DL1 can be interchanged, with two data lines Da arranged between the two first data line leads DL1. The following description uses the case shown in Figure 14, where two first data line leads DL1 are arranged between the two data lines Da, as an example.

[0099] For example, as shown in Figure 14, the display substrate may further include multiple second data line leads DL2, which are located in the first conductive layer M1 and extend along the second direction R2. The first data line Da1 of the two data lines Da is connected to the first second data line lead 1DL2 of the multiple second data line leads DL2, and the first second data line lead 1DL2 is connected to the first first data line lead 1DL1 spaced at least one sub-pixel SP (two sub-pixels SP in the figure) from the first data line Da1; the second data line Da2 of the two data lines Da is connected to the second second data line lead 2DL2 of the multiple second data line leads DL2, and the second second data line lead 2DL2 is connected to the second first data line lead 2DL1 spaced at least one sub-pixel SP (two sub-pixels SP in the figure) from the second data line Da2.

[0100] For example, in the embodiment of FIG14, the first data line Da1 of the two data lines Da is connected to the first second data line lead 1DL2 of the plurality of second data line leads DL2 via a third adapter Z3. In the direction perpendicular to the substrate 10, the first data line Da1 and the third adapter Z3 at least partially overlap, for example, almost completely overlap, so that the third adapter Z3 is blocked. The second data line Da2 of the two data lines Da is connected to the second second data line lead 2DL2 of the plurality of second data line leads DL2 via a fourth adapter Z4. In the direction perpendicular to the substrate 10, the second data line Da and the third adapter Z3 at least partially overlap, for example, almost completely overlap, so that the fourth adapter Z4 is blocked. For example, both the third adapter Z3 and the fourth adapter Z4 are located in the first conductive layer M1. Blocking the third adapter Z3 and the fourth adapter Z4 can prevent defects such as screen-off mura from occurring on the display substrate.

[0101] For example, in the embodiment of FIG14, the first second data line lead 1DL2 is connected to the first first data line lead 1DL1, which is spaced at least one sub-pixel SP (two sub-pixels SP apart in the figure), via a fifth adapter Z5. In the direction perpendicular to the substrate 10, the fifth adapter Z5 and the data line Da adjacent to the first first data line lead 1DL1 (on the left) at least partially overlap, so that the fifth adapter Z5 is at least partially blocked. The second second data line lead DL2 is connected to the second first data line lead 2DL1, which is spaced at least one sub-pixel SP (two sub-pixels SP apart in the figure), via a sixth adapter Z6. In the direction perpendicular to the substrate 10, the sixth adapter Z6 and the data line Da adjacent to the second first data line lead 2DL1 (on the right) at least partially overlap, so that the sixth adapter Z6 is at least partially blocked. For example, the fifth adapter line Z5 and the sixth adapter line Z6 are both located in the first conductive layer M1. The shielding of the fifth adapter line Z5 and the sixth adapter line Z6 can prevent defects such as screen-off mura from occurring on the display substrate.

[0102] For example, in the embodiment of FIG14, the display substrate further includes a first power line VSS, a first data line lead DL1, and a portion of the second data line lead DL2 DL0 for connecting the first power line VSS. At this time, the portion of DL0 is disconnected from the portion of the first data line lead DL1 and the second data line lead DL2 used for transmitting data signals through the break DS / DS1. The portion of DL0 can reduce the voltage drop of the first power line VSS, thereby improving the display uniformity of the display substrate.

[0103] For example, Figure 16 shows an enlarged schematic diagram of the area within the dashed box in Figure 14. As shown in Figure 16, the first data line lead DL1 and the second data line lead DL2 are connected by an adapter line Z0. The two adapter lines Z0 are arranged symmetrically, and the data line Da bypasses the position of the adapter hole. Thus, as shown in Figure 17, after the first electrode 1041 of the light-emitting device EM is subsequently formed, the data line leads, adapter lines, adapter holes, etc. below the first electrode 1041 are all symmetrically designed, which can improve the flatness of the first electrode 1041.

[0104] For example, in Figure 14, in order to highlight the connection relationship between data line Da, first data line lead DL1 and second data line lead DL2, Figure 14 emphasizes (lines used to transmit data signals) / de-emphasizes (lines used to transmit the first power signal) the connection relationship of these lines to clearly show these connection relationships. The clean circuit layout diagram without the emphasized connection relationship is shown in Figure 15. Please refer to Figure 15 for details.

[0105] For example, as shown in Figure 14, the first data line Da1, the first second data line lead 1DL2, and the first first data line lead 1DL1 form a first data line mesh G1. The second data line Da2, the second second data line lead 2DL2, and the second first data line lead 2DL1 form a second data line mesh G2. The second data line mesh G2 is located around the first data line mesh G1; for example, the second data line mesh G2 surrounds the first data line mesh G1. For example, the first data line mesh G1 and the second data line mesh G2 extend to the lower non-display area NA of the display substrate near the center (shown on the right side in the figure) to bond in the non-display area NA. For example, the display substrate may also include more data lines located around the second data line mesh G2, these data lines are wound layer by layer and extend to the lower non-display area NA of the display substrate near the center (shown on the right side in the figure) to bond in the non-display area NA.

[0106] In the embodiments of this disclosure, the above-described winding method can reduce the binding width of the traces used for transmitting data signals below the display area AA, or the Fanout access width, so as to save the space occupied by binding in the non-display area NA.

[0107] For example, as shown in Figure 14, the two first data line leads DL1 located between the two data lines Da include a disconnected portion DL0 that is disconnected from the first data line network G1 and the second data line network G2. The disconnection point, i.e., the break, is shown as the dashed circle DS1. For example, the disconnected portion DL0 is connected to the first power line VSS to reduce the voltage drop of the first power line VSS. For example, in the direction perpendicular to the substrate 10, the disconnection point overlaps with the first conductive layer M1 or the second conductive layer M2, that is, overlaps with the conductive pattern in the first conductive layer M1 or the second conductive layer M2, or overlaps with the structure in other conductive layers, so that the break is blocked to prevent adverse phenomena such as light leakage.

[0108] For example, in some examples, when the break DS1 of the first data line lead DL1 is located in the first lead portion DL11, since the first lead portion DL11 is located in the first conductive layer M1, the break DS1 can overlap with the second conductive layer M2, that is, be blocked by the conductive pattern in the second conductive layer M2; or, when the break DS1 is located in the second lead portion DL12, the second lead portion DL12 is located in the second conductive layer M2, and the break DS1 can overlap with the first conductive layer M1, that is, be blocked by the conductive pattern in the first conductive layer M1.

[0109] For example, in the embodiments of Figures 14-17, the first data line lead DL1 extends along the first direction R1 without any bends to maximize the use of the layout space; as shown in Figure 17, the adapter line Z0 bypasses the source and drain electrodes SD of the transistor on both sides, and each adapter line is located in the first conductive layer M1 and can be shielded by traces in other conductive layers; compared with the FIP 2-in-1 design, the 1-in-1 design can shorten the total length of the data line leads (including the first data line lead DL1 and the second data line lead DL2), reduce lead resistance and overlapping capacitance, reduce data signal loss, and reduce data signal load; in addition, the 1-in-1 design can increase, for example, the density of the first power line VSS connection line (e.g., part of DL0), thereby better controlling the voltage drop of the first power line VSS and reducing screen power consumption; furthermore, the 1-in-1 design can also reduce the bonding width of the traces used for transmitting data signals below the display area AA, saving the space occupied by bonding in the non-display area NA.

[0110] For example, Figure 32 shows a schematic diagram of data line Da and first data line lead DL1 being bound in the non-display area NA in a 2-in-1 design. As shown in Figure 32, a box represents two sub-pixels P, and two sub-pixels P are respectively set with two data lines Da and one first data line lead DL1. Figure 32 shows a total of 16 data lines Da and 8 first data line leads DL1 corresponding to 16 sub-pixels P, totaling 24 signal lines. That is, 24 signal lines require the space corresponding to 16 sub-pixels P to be connected to the binding area below, and the vertical part SL of the connection occupies a certain space. Figure 33 shows a schematic diagram of data line Da and first data line lead DL1 being bound in the non-display area NA in a 1-to-1 design. A box represents two sub-pixels P, and two data lines Da and two first data line leads DL1 are set for each sub-pixel P. Figure 32 shows a total of 12 data lines Da and 12 first data line leads DL1 corresponding to 12 sub-pixels P, totaling 24 signal lines. That is, 24 signal lines require the space corresponding to 12 sub-pixels P to access the binding area below. The vertical space occupied by the connecting part SL is relatively smaller, thus saving the space occupied by binding in the non-display area NA.

[0111] For example, in some other embodiments, the data line Da, the first data line lead DL1, and the second data line lead DL2 can also use different connection methods. For example, as shown in FIG18, the data line Da can also be connected to the second data line lead DL2 through the first data line lead DL1. In this case, the data line Da is first connected to the first data line lead DL1 through adapter Z21, and then connected to the second data line lead DL2 through adapter Z22. For example, as shown in FIG18, the adapter Z21 and adapter Z22 used for two adjacent data lines Da can be arranged symmetrically.

[0112] For example, as shown in Figure 18, the second data line lead DL2 also has a break DS to separate the part of the second data line lead DL2 used for transmitting data signals and the part used for transmitting the first power signal. For example, the second data line lead DL2 is located in the first conductive layer M1, and the break DS in the second data line lead DL2 overlaps at least partially with the conductive pattern in the second conductive layer M2 so as to be blocked by the conductive pattern in the second conductive layer M2, for example, blocked by the second power line VDD in the second conductive layer M2, thereby preventing defects such as light leakage from the display substrate.

[0113] For example, Figure 19 is a schematic diagram of the connection between the first data line lead and the second data line lead in a display substrate provided in at least one embodiment of the present disclosure; as shown in Figure 19, in some other embodiments, two first data line leads DL1 are provided between two adjacent columns of sub-pixels SP, and two data lines Da are provided between the two first data line leads DL1. For example, the data line Da extends in a straight line along the first direction R1, and the first data line lead DL1 has a bent portion at the position of the third via V3 of the data line Da to avoid the third via V3. The first data line lead DL1 is electrically connected to the second data line lead DL2 through the adapter hole V0 and the adapter wire Z23.

[0114] For example, compared with the embodiment of Figure 14, the first data line lead DL1 and the data line Da in the embodiment of Figure 19 are interchanged, and the two data lines Da are placed between the two first data line leads DL1, thereby reducing the impact of data signal transitions on surrounding signal lines; as shown in Figure 20, after the first electrode 1041 is provided on the second conductive layer M2, the first electrode 1041 can avoid the adapter hole V0 and the third via V3, thereby improving the flatness of the first electrode 1041.

[0115] For example, in embodiments of this disclosure, the data line Da can be connected to the second data line lead DL2 in different ways. Figures 21A and 21B show schematic diagrams of different connection scenarios for the data line Da and the second data line lead. As shown in Figure 21A, the data line Da is electrically connected to the second data line lead DL2 through a third via V3 and an adapter wire Z24. The adapter wire Z24 is located in the first conductive layer M1 and at least partially overlaps with the data line Da and the first data line lead DL1. Thus, the adapter wire Z24 can be shielded by the data line Da and the first data line lead DL1 to prevent defects such as screen muta.

[0116] For example, as shown in Figure 21B, data line Da is first connected to the adjacent first data line lead DL1 through the third via V3 and the adapter Z25. The first data line lead DL1 is then connected to the second data line lead DL2 through the via V31 and the adapter Z26. For example, both adapter Z25 and adapter Z26 are located on the first conductive layer M1, and adapter Z25 and adapter Z26 at least partially overlap with the first data line lead DL1, so that adapter Z25 and adapter Z26 can be shielded by the first data line lead DL1 to prevent defects such as screen muta.

[0117] Compared to the embodiment in Figure 21A, the embodiment in Figure 21B allows the first data line lead DL1 and data line Da to share a common adapter cable, saving layout space. Furthermore, the design of multiple breaks DS2 allows for the disconnection of transmission networks transmitting different signals, such as separating the portion used for transmitting data signals from the portion used for transmitting the first power signal. The adapter patterns of the two portions are not significantly different, which helps improve the uniformity of the film layer. Compared to the embodiment in Figure 21B, the adapter path for data line Da is shorter, eliminating the need to borrow a section of the first data line lead DL1, thus avoiding waste of adjacent first data line leads DL1. This also reduces data signal loading and overlap capacitance, thereby increasing the density of the portion used for transmitting the first power signal.

[0118] For example, in some other embodiments, as shown in FIG22, the second data line lead DL2 can be directly connected to the first data line lead DL1 through the adapter hole V4. Compared with the embodiments in FIG19, the adapter wire is no longer used for electrical connection. At this time, it is no longer necessary to set vias in the first insulation layer 11. This can reduce the length of the adapter path, eliminate the need to design a special wiring layout to cover the adapter wire and the break, and simplify the arrangement of the break and the adapter line.

[0119] For example, if it is necessary to connect the second data line lead DL2 to the vertical first data line lead DL1, the adapter cable can be replaced with an adapter hole, referring to the adapter hole V36 in Figure 35. The first conductive layer M1 and the second conductive layer M2 are retained, as is the hole layer, i.e., the layer with the via, i.e., the first insulating layer 11, thus saving space for the adapter cable. Alternatively, if it is necessary for both the first data line lead DL1 and the second data line lead DL2 to be continuously connected, the hole layer can be removed, i.e., the adapter hole is not provided, retaining only the first conductive layer M1 and the second conductive layer M2. The conductive pattern of the second conductive layer M2 is shown in the portion indicated by the dashed circle 1 in Figure 35. For example, if it is necessary to set the break position of the first data line lead DL1, the via layer can be removed, that is, no adapter hole is set, and only the conductive pattern of the first conductive layer M1 is retained, as shown in the portion indicated by the dashed circle 3 in Figure 35. Similarly, if it is necessary to set the break position of the second data line lead DL2, the via layer can be removed, that is, no adapter hole is set, and only the conductive pattern of the second conductive layer M2 is retained, as shown in the portion indicated by the dashed circle 2 in Figure 35. This reduces the length of the adapter path, eliminates the need for specially designed wiring layouts to cover the adapter wires and breaks, and simplifies the arrangement of breaks and adapter lines.

[0120] For example, the connection methods of Figures 21A, 21B, and 22 can be used in the wiring layout provided in any embodiment of this disclosure.

[0121] For example, Figure 23 is a schematic diagram of another planar arrangement of the first data line leads in the display substrate provided by at least one embodiment of the present disclosure under the 1-in-1 design. In some embodiments, as shown in Figure 23, two first data line leads DL1 are arranged between two adjacent columns of sub-pixels SP, and two data lines Da are arranged between the two first data line leads DL1. For example, the first data line Da1 of two data lines Da is connected to the first second data line lead 1DL2 of multiple second data line leads DL2 via a third adapter Z3. In the direction perpendicular to the substrate 10, the third adapter Z3 and the first data line lead DL1 adjacent to the first data line Da1 at least partially overlap, for example, also at least partially overlap with the first data line Da1, so that the third adapter Z3 is blocked. The second data line Da2 of two data lines Da is connected to the second second data line lead 2DL2 of multiple second data line leads DL2 via a fourth adapter Z4. In the direction perpendicular to the substrate 10, the fourth adapter Z4 and the first data line lead DL1 adjacent to the second data line Da at least partially overlap, for example, also at least partially overlap with the second data line Da2, so that the fourth adapter Z4 is blocked.

[0122] For example, as shown in Figure 23, the first second data line lead 1DL2 is directly connected to the first first data line lead 1DL1, which is spaced at least one sub-pixel SP (shown as two sub-pixels SP in the figure), through the fourth via V4; the second second data line lead DL2 is directly connected to the second first data line lead 2DL1, which is spaced at least one sub-pixel SP (shown as two sub-pixels SP in the figure), through the fifth via V5. This saves on the design and arrangement of adapter cables.

[0123] For example, as shown in FIG23, the first data line lead 1DL1 and the second data line lead DL2 also have a portion DL0 for connecting a first power signal. This portion DL0 is disconnected from the portion of the first data line lead 1DL1 and the second data line lead DL2 used for connecting the data signal via a break DS3. For example, in the embodiment of FIG23, in the portion DL0 of the first data line lead 1DL1 and the second data line lead DL2 used for connecting the first power signal, the first data line lead 1DL1 and the second data line lead DL2 are electrically connected via a via V41.

[0124] For example, in the embodiment of FIG. 23, the first data line Da1, the first second data line lead 1DL2, and the first first data line lead 1DL1 form a first data net G1, and the second data line Da2, the second second data line lead 2DL2, and the second first data line lead 2DL1 form a second data net G2. The second data net G2 is located around the first data net G1, for example, the second data net G2 surrounds the first data net G1. For example, the first data net G1 and the second data net G2 may extend to the lower non-display area NA of the display substrate near the center (shown as the right side in the figure) to be bonded in the non-display area NA. For example, the display substrate may also include more data nets located around the second data net G2, these data nets being wound layer by layer and extending to the lower non-display area NA of the display substrate near the center (e.g., shown as the right side in the figure) to be bonded in the non-display area NA.

[0125] For example, in Figure 23, in order to highlight the connection relationship between data line Da, first data line lead DL1 and second data line lead DL2, the connection of these traces is highlighted in Figure 23 to clearly show these connection relationships. The clean circuit layout without highlighting the connection relationships is shown in Figure 24. Please refer to Figure 24 for details.

[0126] For example, in other embodiments, the display data line Da and the first data line lead DL1 may also be arranged in other ways. For example, FIG25 is a schematic diagram of another planar arrangement of the first data line lead and data line in a display substrate provided in at least one embodiment of the present disclosure. As shown in FIG25, in the direction parallel to the substrate 10, two data lines Da are arranged between adjacent first column sub-pixels SP1 and second column sub-pixels SP2, and a reset voltage line Vint (described in detail later) is arranged between the two data lines Da. Two first data line leads DL1 are arranged between adjacent second column sub-pixels SP2 and third column sub-pixels SP3.

[0127] For example, Figure 26 is a schematic diagram of another planar arrangement of the first data line lead in the display substrate provided by at least one embodiment of the present disclosure using a 1-to-1 design. Figure 26 shows the connection relationship between the data line Da, the first data line lead DL1 and the second data line lead DL2. As shown in Figure 26, the data line Da1 (the first data line Da1 on the left side of the second sub-pixel SP2) adjacent to the second column sub-pixel SP2 and the first data line lead DL1 (the first first data line lead DL1 on the right side of the second column sub-pixel SP2) are electrically connected through the first second data line lead DL2. For example, the first data line Da1 is electrically connected to the first second data line lead 1DL2 via a seventh adapter Z7, where the seventh adapter Z7 at least partially overlaps with data line Da1 to shield the seventh adapter Z7. Alternatively, the first second data line lead 1DL2 is electrically connected to the first first data line lead 1DL1 via an eighth adapter Z8, where the eighth adapter Z8 at least partially overlaps with the first first data line lead 1DL1 to shield the eighth adapter Z8. Or, in other embodiments, the first second data line lead 1DL2 may also be directly electrically connected to the first data line lead DL1 via a via; or, the first data line Da1 may also be directly electrically connected to the first second data line lead 1DL2 via a via.

[0128] For example, as shown in Figure 26, the data line Da2 adjacent to the first column sub-pixel SP (the second data line Da2 to the right of the second column sub-pixel SP2) and the first data line lead DL1 adjacent to the third column sub-pixel SP (the second first data line lead 2DL1 to the left of the third column sub-pixel SP) are electrically connected through the second data line lead 2DL2. For example, the data line Da2 is electrically connected to the second data line lead 2DL2 through the ninth adapter Z9, for example, the ninth adapter Z9 and the second data line Da2 at least partially overlap, so that the ninth adapter Z9 is blocked; for example, the second data line lead 2DL2 is electrically connected to the first data line lead DL1 through the tenth adapter Z10, for example, the tenth adapter Z10 and the second data line lead 2DL2 at least partially overlap, so that the tenth adapter Z10 is blocked. Alternatively, in other embodiments, the second data line lead 2DL2 can also be electrically connected to the second data line lead 2DL1 directly through a via; or, the data line Da2 can also be electrically connected to the second data line lead 2DL2 directly through a via.

[0129] For example, as shown in Figure 26, the first data line lead DL1 has a break DS1. Figure 26 shows an example of the first data line lead DL1 having a break DS1. The break DS1 disconnects the portion of the first data line lead DL1 used for transmitting data signals from the portion used for transmitting first power signals. For example, the disconnected portion of the first data line lead DL1 is the first lead portion DL11. Since the first lead portion DL11 is located in the first conductive layer M1, the break DS1 can overlap with the second conductive layer M2, that is, it is blocked by the conductive pattern in the second conductive layer M2; or, the disconnected portion of the first data line lead DL1 is the second lead portion DL12. The second lead portion DL12 is located in the second conductive layer M2. In this case, the break DS1 can overlap with the first conductive layer M1, that is, it is blocked by the conductive pattern in the first conductive layer M1.

[0130] For example, as shown in Figure 26, two second power lines VDD are also provided in the adjacent second column sub-pixels SP and third column sub-pixels SP. That is, the second column sub-pixels SP corresponds to one second power line VDD, and the third column sub-pixels SP corresponds to one second power line VDD. For example, the two first data line leads DL1 can be located between the two second power lines VDD.

[0131] For example, in Figure 26, in order to highlight the connection relationship between data line Da, first data line lead DL1 and second data line lead DL2, the connection of these traces is highlighted in Figure 26 to clearly show these connection relationships. The clean circuit layout without highlighting the connection relationships is shown in Figure 27. Please refer to Figure 27 for details.

[0132] For example, Figure 28 shows a planar schematic diagram of a first electrode 1041 disposed on the second conductive layer M2 in the embodiments of Figures 26 and 27. As shown in Figure 28, the first electrode 1041 can avoid the third via V3 of the data line Da, thereby improving the flatness of the first electrode 1041.

[0133] For example, in the embodiments of Figures 26 and 27, compared to the embodiments of Figures 23 and 24, the positions of the two first data line leads DL1 and the reset voltage line Vint are interchanged. The reset voltage line Vint is located between the two data lines Da, and the two first data line leads DL1 are located between the two second power lines VDD. As a result, the transition path between the display data line Da, the first data line leads DL1 and the second data line leads DL2 is short, the break is easy to design, and it is easy to be shielded by other conductive layers. The third via V3 and other vias can avoid the first electrode 1041 to improve the flatness of the first electrode 1041.

[0134] For example, Figure 34 is a schematic diagram of another planar arrangement of the first data line leads in a display substrate provided by at least one embodiment of the present disclosure using a 1-to-1 design. In some embodiments, as shown in Figure 34, two first data line leads DL1 are arranged between two adjacent columns of sub-pixels SP, and two data lines Da are arranged between the two first data line leads DL1. For example, the first data line Da1 of the two data lines Da is connected to the first first data line lead 1DL1 and the first second data line lead 1DL2 through an adapter hole V35, an adapter wire Z35, and an adapter hole V36. In this case, the first data line Da1 is connected to the first first data line lead 1DL1 adjacent to it and located in the same sub-pixel SP.

[0135] For example, in a direction perpendicular to the substrate 10, the adapter Z35 and the first data line lead 1DL1 at least partially overlap, so that the adapter Z35 is blocked.

[0136] For example, as shown in Figure 34, in the portion DL0 of the first data line lead DL1 and the second data line lead DL2 used for transmitting the first power signal, the two first data line leads DL1 are respectively connected to the second data line lead DL2 through two adapter holes V34 to form a transmission network for the first power signal.

[0137] For example, in Figure 34, in order to highlight the connection relationship between data line Da, first data line lead DL1 and second data line lead DL2, the connection of these traces is highlighted in Figure 34 to clearly show these connection relationships. The clean circuit layout without highlighting the connection relationships is shown in Figure 35. Please refer to Figure 35 for details.

[0138] For example, Figure 29 shows a partial cross-sectional schematic diagram of the display substrate. As shown in Figure 29, each of the multiple sub-pixels SP includes a light-emitting device EM and a pixel driving circuit for driving the light-emitting device EM. The light-emitting device EM includes a first electrode 1041 connected to the pixel driving circuit, a second electrode 1043 spaced apart from the first electrode 1041, and a light-emitting layer 1042 between the first electrode 1041 and the second electrode 1043. For example, the first electrode 1041 is the anode of the light-emitting device EM and is used to receive a second power signal provided by the second power line VDD, for example, the second power signal is a high-level signal. For example, the second electrode 1043 is the cathode of the light-emitting device EM, electrically connected to the first power line VSS, and is used to receive a first power signal, for example, the first power signal is a low-level signal.

[0139] For example, as shown in Figure 29, the pixel driving circuit includes a transistor T and a storage capacitor C. The transistor T includes an active layer 1021, a gate 1022, a first source-drain 1023, and a second source-drain 1024. The first source-drain 1023 is electrically connected to the first electrode 1041 through a connecting electrode CEL. The first source-drain 1023 and the second source-drain 1024 are located in the first conductive layer M1, which can also be called the SD1 conductive layer. The connecting electrode CEL is located in the second conductive layer M2, which can also be called the SD2 conductive layer.

[0140] For example, as shown in Figure 29, the display substrate may also include more conductive layers, such as a third conductive layer M3 and a fourth conductive layer M4. The fourth conductive layer M4 is disposed on the side of the third conductive layer M3 away from the substrate 10, and the first conductive layer M1 is disposed on the side of the fourth conductive layer M4 away from the substrate 10. For example, the storage capacitor C includes a first capacitor electrode C1 and a second capacitor electrode C2. For example, the first capacitor electrode C1 and the first gate 1022 are disposed on the third conductive layer M3, which may also be called the Gate 1 conductive layer, and the second capacitor electrode C2 is disposed on the fourth conductive layer M4, which may also be called the Gate 2 conductive layer.

[0141] For example, as shown in FIG29, the display substrate may further include at least one barrier layer 1012 and at least one buffer layer 1013 disposed on the substrate 10. FIG29 shows a barrier layer 1012 and a buffer layer 1013 as an example. The barrier layer 1012 and the buffer layer 1013 can prevent impurities in the substrate 10 from entering the multiple functional layers on the display substrate, thereby providing a protective function. For example, the barrier layer 1012 and the buffer layer 1013 may be one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0142] For example, as shown in FIG29, the display substrate may further include a first gate insulating layer GI1 disposed on the side of the active layer 1021 away from the substrate 11, a second gate insulating layer GI2 disposed on the side of the gate electrode 1022 and the first capacitor electrode C1 away from the substrate 11, and an interlayer insulating layer IDL disposed on the side of the second capacitor electrode C2 away from the substrate 11. For example, the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer IDL may be one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0143] For example, as shown in FIG29, a first insulating layer 11 is disposed on the side of the first source-drain electrode 1023 and the second source-drain electrode 1024 away from the substrate 11. The first insulating layer 11 can serve as a planarization layer to planarize the pixel driving circuit, thereby forming a relatively flat surface to facilitate the placement of the light-emitting device EM. For example, the display substrate may also include a second insulating layer 12 disposed on the side of the connecting electrode CEL away from the substrate 10. The second insulating layer 12 can also serve as a planarization layer to further planarize the pixel driving circuit and the connecting electrode CEL.

[0144] For example, the display substrate may further include a pixel defining layer PDL disposed on the side of the first electrode 1041 away from the substrate 10. The pixel defining layer PDL has a plurality of sub-pixel openings OP to expose the first electrode 1041 of a plurality of sub-pixels SP and to define the light-emitting areas of the plurality of sub-pixels SP. For example, the display substrate may further include a spacer layer PS disposed on the side of the pixel defining layer PDL away from the substrate 10. The spacer layer PS has a plurality of spacers to serve as support and isolation.

[0145] For example, the first insulating layer 11, the second insulating layer, and the spacer layer PS can be made of organic insulating materials such as resin and polyimide. The pixel defining layer PDL can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride; or, in other embodiments, the pixel defining layer PDL can also be made of organic insulating materials such as resin and polyimide.

[0146] For example, as shown in Figure 29, the display substrate may further include an encapsulation layer EN disposed on the side of the light-emitting device EM away from the substrate 10. The encapsulation layer EN may be a composite encapsulation layer, comprising a stack of an inorganic encapsulation layer EN1 and an organic encapsulation layer EN2. The inorganic encapsulation layer EN1 may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The organic encapsulation layer EN2 may be made of organic insulating materials such as resin or polyimide.

[0147] For example, in embodiments of this disclosure, the substrate 10 can be a rigid substrate such as glass or quartz, or a flexible substrate such as polyimide or resin. The active layer 1021 of each transistor can be a semiconductor layer of various forms, such as an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide semiconductor layer. For example, the polycrystalline silicon can be high-temperature polycrystalline silicon or low-temperature polycrystalline silicon, and the oxide semiconductor can be indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), or gallium zinc oxide (GZO), etc.

[0148] For example, the gate 1022 of each transistor can be made of metal materials or alloy materials such as copper (Cu), aluminum (Al), and titanium (Ti), and can be formed as a single-layer metal layer structure or a multi-layer metal layer structure, such as a titanium / aluminum / titanium multi-layer metal layer structure. The source / drain electrodes 1023 / 1024 of each transistor can be made of metal materials or alloy materials such as copper (Cu), aluminum (Al), and titanium (Ti), and can be formed as a single-layer metal layer structure or a multi-layer metal layer structure, such as a titanium / aluminum / titanium multi-layer metal layer structure.

[0149] For example, the first electrode 1041 can be made of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and gallium zinc oxide (GZO), while the second electrode 1043 can be made of metals such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag). The embodiments of this disclosure do not specifically limit the materials used in each structure.

[0150] For example, the pixel driving circuit in the embodiments of this disclosure can be various forms of pixel driving circuits such as 3T1C (i.e., including 3 transistors and 1 storage capacitor), 7T1C (i.e., including 7 transistors and 1 storage capacitor), 8T1C (i.e., including 8 transistors and 1 storage capacitor), or 8T2C (i.e., including 8 transistors and 2 storage capacitors). Figure 30 is a schematic diagram of the equivalent circuit of the 8T1C pixel driving circuit provided in at least one embodiment of this disclosure. The connection relationship and function of the transistors and signal lines in the pixel driving circuit will be explained below using the 8T1C pixel driving circuit as an example.

[0151] For example, as shown in Figure 30, the pixel driving circuit may include eight transistors (first transistor T1 to eighth transistor T8), one storage capacitor C, and multiple signal lines (e.g., data line Da, first scan signal line Gate, second scan signal line GateN, reset control signal line Reset, first reset voltage line INIT1, second reset voltage line INIT2, second power supply line VDD, first power supply line VSS, and light emission control signal line Em, etc.).

[0152] For example, the gate of the first transistor T1 is connected to the reset control signal line Reset, the first terminal of the first transistor T1 is connected to the second reset voltage line INIT2, and the second terminal of the first transistor T1 is connected to the fifth node N5.

[0153] For example, the gate of the second transistor T2 is connected to the first scan signal line Gate, the first terminal of the second transistor T2 is connected to the fifth node N5, and the second terminal of the second transistor T2 is connected to the third node N3.

[0154] For example, the gate of the third transistor T3 is connected to the first node N1, the first terminal of the third transistor T3 is connected to the second node N2, and the second terminal of the third transistor T3 is connected to the third node N3.

[0155] For example, the gate of the fourth transistor T4 is connected to the first scan signal line Gate, the first terminal of the fourth transistor T4 is connected to the data line Da, and the second terminal of the fourth transistor T4 is connected to the second node N2.

[0156] For example, the gate of the fifth transistor T5 is connected to the light-emitting control signal line Em, the first terminal of the fifth transistor T5 is connected to the second power supply line VDD, and the second terminal of the fifth transistor T5 is connected to the second node N2.

[0157] For example, the gate of the sixth transistor T6 is connected to the light-emitting control signal line Em, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4 (i.e., the first electrode 1041 of the light-emitting device EM).

[0158] For example, the gate of the seventh transistor T7 is connected to the first scan signal line Gate or the reset control signal line Reset, the first terminal of the seventh transistor T7 is connected to the first reset voltage line INIT1, and the second terminal of the seventh transistor T7 is connected to the fourth node N4.

[0159] For example, the gate of the eighth transistor T8 is connected to the second scan signal line GateN, the first terminal of the eighth transistor T8 is connected to the fifth node N5, and the second terminal of the eighth transistor T8 is connected to the first node N1.

[0160] For example, the first capacitor electrode C1 of the storage capacitor C is connected to the second power line VDD, and the second capacitor electrode C2 of the storage capacitor C is connected to the first node N1.

[0161] For example, the first transistor T1 to the seventh transistor T7 can be N-type thin-film transistors, and the eighth transistor T8 can be a P-type thin-film transistor; or, the first transistor T1 to the seventh transistor T7 can be P-type thin-film transistors, and the eighth transistor T8 can be an N-type thin-film transistor.

[0162] For example, transistors T1 through T7 can be low-temperature polysilicon (LTPS) thin-film transistors. Transistor (TFT), the eighth transistor T8 can be an indium gallium zinc oxide (IGZO) thin film transistor.

[0163] In the above embodiments, indium gallium zinc oxide (IGN) thin-film transistors (LTVs) generate less leakage current compared to low-temperature polycrystalline silicon (LTPS) thin-film transistors (LTPS). Therefore, setting the eighth transistor T8 as an IGNV can significantly reduce leakage current, thereby improving the low-frequency, low-brightness flicker problem of the display panel. Furthermore, the first transistor T1 and the second transistor T2 do not need to be IGNVs. Since the size of LTPS is generally smaller than that of IGNVs, the pixel driving circuit of this embodiment occupies less space, which is beneficial for improving the resolution of the display panel.

[0164] The pixel driving circuit provided in this embodiment combines the good switching characteristics of LTPS-TFT and the low leakage current characteristics of Oxide-TFT, enabling low-frequency driving (1Hz to 60Hz) and significantly reducing the power consumption of the display screen.

[0165] In some embodiments, the second electrode 1043 of the light-emitting device EM is connected to the first power line VSS. The signal of the first power line VSS is a continuously supplied low-level signal, and the signal of the second power line VDD is a continuously supplied high-level signal. The signal of the first scan signal line Gate is the scan signal in the pixel driving circuit of this display row, and the signal of the reset control signal line Reset is the scan signal in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line Gate is Gate(n), and the reset control signal line Reset is Gate(n-1). The signal of the reset control signal line Reset of this display row and the signal of the first scan signal line Gate in the pixel driving circuit of the previous display row can be the same signal to reduce the signal lines of the display panel and achieve a narrow bezel of the display panel.

[0166] For example, Figure 31 is a timing diagram of the pixel driving circuit in Figure 30. As shown in Figure 31, in some embodiments, the operation of the pixel driving circuit can be divided into the following stages.

[0167] In the first stage, t1, called the reset stage, the signals of the first scan signal line Gate, the reset control signal line Reset, the second scan signal line GateN, and the light emission control signal line Em are all high-level signals, while the signal of the reset control signal line Reset is low-level. The high-level signal of the light emission control signal line Em turns off the fifth transistor T5 and the sixth transistor T6. The high-level signal of the second scan signal line GateN turns on the eighth transistor T8. The low-level signal of the reset control signal line Reset turns on the first transistor T1. Therefore, the voltage of the first node N1 is reset to the second reset voltage Vinit2 provided by the second reset voltage line INIT2. Then, the voltage of the reset control signal line Reset goes high, and the first transistor T1 turns off. Since the fifth transistor T5 and the sixth transistor T6 are off, the light-emitting device EL does not emit light in this stage.

[0168] In the second stage, t2, known as the data writing stage, the first scan signal line Gate is at a low level. Transistors T4, T2, and T7 are turned on, and data line Da outputs a data voltage. The voltage at node N4 is reset to the first reset voltage Vinit1 provided by the first reset voltage line INIT1, completing initialization. During this stage, since node N1 is low, transistor T3 is turned on. The turn-on of transistors T4 and T2 allows the data voltage output from data line Da to be supplied to node N1 via the turned-on transistors T4, N2, T3, N3, T2, N5, and T8. The sum of the data voltage output from data line Da and the threshold voltage of transistor T3 is then charged into the storage capacitor C. The light-emitting control signal line Em is at a high level, and transistors T5 and T6 are turned off, ensuring that the light-emitting device EM does not emit light.

[0169] The third stage, t3, is called the light-emitting stage. During this stage, the first scan signal line (Gate) and the reset control signal line (Reset) are both high-level signals, while the light-emitting control signal line (EM) and the second scan signal line (GateN) are both low-level signals. The high-level signal on the reset control signal line (Reset) turns off the seventh transistor (T7), and the low-level signal on the light-emitting control signal line (Em) turns on the fifth transistor (T5) and the sixth transistor (T6). The power supply voltage output from the second power supply line (VDD) provides a driving voltage to the first electrode (i.e., the fourth node N4) of the light-emitting device (EM) through the turned-on fifth transistor (T5), third transistor (T3), and sixth transistor (T6), driving the EM to emit light.

[0170] For example, in the embodiments of Figures 25 and 26, the reset voltage line Vint can be the first reset voltage line INIT1 and / or the second reset voltage line INIT2 described above, in order to achieve the corresponding functions.

[0171] The following points also need to be explained:

[0172] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0173] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0174] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0175] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A display substrate having a plurality of sub-pixels arranged in multiple rows and columns, and comprising: A substrate includes a display area and a non-display area, wherein the plurality of sub-pixels are disposed in the display area. Multiple data lines, disposed on the substrate and at least located in the display area, extend along a first direction and are configured to provide data signals to the plurality of sub-pixels. Multiple first data line leads are disposed on the substrate and extend from the display area to the non-display area along the first direction. At least a portion of each of the plurality of data lines is electrically connected to the plurality of first data line leads to obtain data signals from the non-display area. At least one of the plurality of first data line leads includes a first lead portion and a second lead portion, the first lead portion being located in a first conductive layer and the second lead portion being located in a second conductive layer, and the first lead portion and the second lead portion being electrically connected through a via.

2. The display substrate according to claim 1, wherein, In a direction parallel to the substrate, one or two first data line leads are provided between two adjacent data lines.

3. The display substrate according to claim 1 or 2, wherein, The second conductive layer is located on the side of the first conductive layer away from the substrate, and the plurality of data lines are located on the second conductive layer.

4. The display substrate according to any one of claims 1-3, wherein, A first insulating layer is provided between the second conductive layer and the first conductive layer. The via includes a first via and a second via penetrating the first insulating layer. The two ends of the first lead portion are respectively connected to the second lead portion through the first via and the second via.

5. The display substrate according to claim 4, wherein, For a first data line lead and a data line arranged adjacent to each other, the first insulating layer also has a third via that overlaps with the data line in a direction perpendicular to the substrate. In the first direction, the third via is located between the first via and the second via.

6. The display substrate according to claim 5, wherein, Two data lines and two first data line leaders are set between two adjacent columns of sub-pixels. The two data lines are located between the leads of the two first data lines, or, The two first data line leads are located between the two data lines.

7. The display substrate according to claim 6, wherein, The two data lines are arranged symmetrically, and the corresponding third vias of the two data lines are arranged symmetrically. The two first data line leads are arranged symmetrically, and the first vias and second vias corresponding to the two first data line leads are arranged symmetrically.

8. The display substrate according to claim 4, wherein, Two data lines and two first data line leads are provided between two adjacent columns of sub-pixels, and the two first data line leads are located between the two data lines. In the first direction, the first vias and second vias corresponding to the two first data line leads are arranged alternately at intervals.

9. The display substrate according to claim 6 or 8, further comprising: The second data line lead is located in the first conductive layer and extends along a second direction, which is different from the first direction. Wherein, at least one of the two first data line leads is connected to the second data line lead through a first adapter wire, the first adapter wire being located in the first conductive layer and at least partially overlapping the at least one first data line lead in a direction perpendicular to the substrate.

10. The display substrate according to claim 8, wherein, The second lead portion of each of the two first data lines includes a bent portion that bends toward each other.

11. The display substrate according to claim 4, wherein, Two data lines and two first data line leads are provided between two adjacent columns of sub-pixels, and the two first data line leads are located between the two data lines. In the first direction, the first via and the second via corresponding to the two first data line leads are located on the same straight line.

12. The display substrate according to any one of claims 1-3, wherein, In a direction parallel to the substrate, two data lines are provided between two adjacent columns of sub-pixels, and a first data line lead is provided between the two data lines. The display substrate further includes: a second data line lead, located in the first conductive layer, extending along a second direction, wherein the second direction is different from the first direction. The first data line lead is connected to the second data line lead via a second adapter wire located in the first conductive layer. In a direction perpendicular to the substrate, the second adapter wire at least partially overlaps with one of the two data lines.

13. The display substrate according to any one of claims 1-3, wherein, In a direction parallel to the substrate, two data lines are provided between two adjacent columns of sub-pixels, and two first data line leads are provided between the two data lines; alternatively, two first data line leads are provided between two adjacent columns of sub-pixels, and two data lines are provided between the two first data line leads. The display substrate further includes: a plurality of second data line leads located in the first conductive layer and extending along a second direction, wherein the second direction is different from the first direction. The first of the two data lines is connected to the first of the multiple second data line leads, and the first second data line lead is connected to the first first data line lead that is spaced at least one sub-pixel apart from the first data line. The second data line of the two data lines is connected to the second second data line lead of the plurality of second data line leads, and the second second data line lead is connected to the second first data line lead that is spaced at least one sub-pixel apart from the second data line.

14. The display substrate according to claim 13, wherein, The first of the two data lines is connected to the first of the multiple second data line leads via a third adapter cable. In a direction perpendicular to the substrate, the first data line and the third adapter cable at least partially overlap. The second of the two data lines is connected to the second of the multiple second data line leads via a fourth adapter cable. In a direction perpendicular to the substrate, the second data line and the fourth adapter cable at least partially overlap.

15. The display substrate according to claim 13, wherein, The first of the two data lines is connected to the first of the multiple second data line leads via a third adapter cable. In a direction perpendicular to the substrate, the third adapter cable and the first data line lead adjacent to the first data line at least partially overlap. The second of the two data lines is connected to the second of the multiple second data line leads via a fourth adapter cable. In a direction perpendicular to the substrate, the fourth adapter cable and the first data line lead adjacent to the second data line overlap at least partially.

16. The display substrate according to any one of claims 13-15, wherein, The first second data line lead is connected to the first first data line lead spaced at least one sub-pixel apart from the first data line via a fifth adapter wire. In a direction perpendicular to the substrate, the fifth adapter wire and the data line adjacent to the first first data line lead at least partially overlap. The second data line lead is connected to the second data line lead, which is spaced at least one sub-pixel apart from the second data line, via a sixth adapter. In a direction perpendicular to the substrate, the sixth adapter line and the data line adjacent to the second data line lead at least partially overlap.

17. The display substrate according to any one of claims 13-15, wherein, The first second data line lead is directly connected to the first first data line lead that is spaced at least one sub-pixel apart from the first data line through the fourth via; The second data line lead is directly connected to the second data line lead, which is spaced at least one sub-pixel apart from the second data line, through the fifth via.

18. The display substrate according to any one of claims 13-17, wherein, The first data line, the first second data line lead, and the first first data line lead form a first data line network. The second data line, the second second data line lead, and the second first data line lead form a second data line mesh. The second data net is located outside the first data net.

19. The display substrate according to claim 18, wherein, The two first data line leads located between the two data lines include disconnected portions that are disconnected from the first data line network and the second data line network. The display substrate also includes a first power line, and the disconnected portion is connected to the first power line.

20. The display substrate according to claim 19, wherein, In a direction perpendicular to the substrate, the break point overlaps with either the first conductive layer or the second conductive layer.

21. The display substrate according to claim 19 or 20, wherein, Each of the plurality of sub-pixels includes a light-emitting device and a pixel driving circuit for driving the light-emitting device. The light-emitting device includes a first electrode connected to the pixel driving circuit, a second electrode spaced apart from the first electrode, and a light-emitting layer between the first electrode and the second electrode. The second electrode is electrically connected to the first power line.

22. The display substrate according to claim 21, wherein, The pixel driving circuit includes a transistor, which includes a gate and a source / drain. The source / drain is electrically connected to the first electrode via a connection electrode. The source and drain electrodes are located in the first conductive layer, and the connection electrodes are located in the second conductive layer.

23. The display substrate according to any one of claims 1-3, wherein, In a direction parallel to the substrate, two data lines are provided between adjacent first column sub-pixels and second column sub-pixels, a reset voltage line is provided between the two data lines, and two first data line leads are provided between adjacent second column sub-pixels and third column sub-pixels.

24. The display substrate according to claim 23, wherein, The data line adjacent to the second column of sub-pixels and the first data line lead are electrically connected through the first second data line lead, and the data line adjacent to the first column of sub-pixels and the first data line lead adjacent to the third column of sub-pixels are electrically connected through the second second data line lead.

25. The display substrate according to claim 24, wherein, Two second power lines are also provided in the adjacent second and third column sub-pixels, and the two first data line leads are located between the two second power lines.

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