Semiconductor device

Abstract

Provided is a semiconductor device comprising a transistor having a large on-current. The semiconductor device comprises a vertical transistor. A lower electrode of the vertical transistor has a laminated structure of: a first conductive layer having high electrical conductivity; a second conductive layer containing zirconium, titanium, or tin; and a third conductive layer containing an oxide that includes indium and a metallic element. An insulating layer is provided on the third conductive layer. The insulating layer and the third conductive layer are provided with an opening reaching the second conductive layer. A semiconductor layer contains indium oxide, and has a region that is in contact with the upper surface of the second conductive layer and a region that is in contact with the side surface of the opening in the third conductive layer.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0005] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a low-power central processing unit (CPU) that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor.

[0006] Examples of oxide semiconductors that can be used in the active layer of a transistor include indium oxide and indium gallium zinc oxide. Non-Patent Document 1 discloses the use of indium oxide in thin film transistors. Non-Patent Document 2 discloses a thin film transistor that uses hydrogenated polycrystalline indium oxide formed by low-temperature solid phase crystallization as the active layer.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Dhananjay and C. W. Chu, Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process. Appl. Phys. Lett. 91, 132111 (2007). Y. Magari et al. , "High-mobility hydrogenated polycrystalline In 2 O 3 (In 2 O 3 : H) thin-film transistors", Nature Communications, 13, 1078 (2022) Takashi Koida, "High-mobility transparent conductive film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] An object of one embodiment of the present invention is to provide a semiconductor device, a memory device, or a display device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a semiconductor device, a memory device, or a display device including a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device, a memory device, or a display device with high operating speed.An object of one embodiment of the present invention is to provide a semiconductor device or a memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device, a memory device, or a display device with low power consumption.An object of one embodiment of the present invention is to provide a manufacturing method of the semiconductor device, the memory device, or the display device.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One embodiment of the present invention includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, and a second insulating layer, in which the second conductive layer is in contact with a top surface of the first conductive layer, the third conductive layer is in contact with a top surface of the second conductive layer, the first insulating layer is located over the third conductive layer, and the fourth conductive layer is located over the first insulating layer, and the third conductive layer, the fourth conductive layer, and the first insulating layer have openings at positions overlapping with the second conductive layer, and the semiconductor layer is in contact with a top surface of the second conductive layer. a region in contact with the semiconductor layer, a region in contact with a side surface of the third conductive layer in the opening, and a region in contact with the fourth conductive layer; the second insulating layer is located on the semiconductor layer; the fifth conductive layer is located on the second insulating layer; the fifth conductive layer has a region inside the opening that faces the semiconductor layer with the second insulating layer sandwiched therebetween; the semiconductor layer contains indium oxide; the second conductive layer contains zirconium, titanium, or tin; and the third conductive layer has an oxide containing indium and a metal element.

[0012] Alternatively, one embodiment of the present invention includes a semiconductor layer, a protective layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, and a second insulating layer, in which the second conductive layer is in contact with a top surface of the first conductive layer, the third conductive layer is in contact with a top surface of the second conductive layer, the first insulating layer is located over the third conductive layer, and the fourth conductive layer is located over the first insulating layer, and the third conductive layer, the fourth conductive layer, and the first insulating layer have openings at positions overlapping with the second conductive layer, and the semiconductor layer has a region located inside the opening and a region located over the fourth conductive layer, and the semiconductor layer has a region in contact with a top surface of the second conductive layer, a region in contact with a side surface of the third conductive layer in the opening, and a region in contact with the fourth conductive layer, the fifth conductive layer is located on the second insulating layer and has a region in the opening that faces the semiconductor layer with the second insulating layer sandwiched therebetween; the fifth conductive layer is located on the second insulating layer and has a region in the opening that faces the semiconductor layer with the second insulating layer sandwiched therebetween; the semiconductor layer comprises indium oxide; the second conductive layer comprises zirconium, titanium, or tin; the third conductive layer comprises an oxide containing indium and a metal element; and the oxygen permeability in the protective layer is lower than the oxygen permeability in the semiconductor layer.

[0013] Alternatively, in the above embodiment, the protective layer may include an oxide semiconductor or an insulator.

[0014] Alternatively, in the above aspect, the oxide semiconductor may include indium and an element M, and the element M may be one or more elements selected from zinc, aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0015] Alternatively, in the above embodiment, the oxide semiconductor may contain indium, gallium, and zinc.

[0016] Alternatively, in the above aspect, the insulator may include silicon nitride.

[0017] Alternatively, one embodiment of the present invention includes a semiconductor layer, a protective layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, and a second insulating layer, in which the second conductive layer is in contact with a top surface of the first conductive layer, the third conductive layer is in contact with a top surface of the second conductive layer, the first insulating layer is located over the third conductive layer, the fourth conductive layer is located over the first insulating layer, and the third conductive layer, the fourth conductive layer, and the first insulating layer overlap with the second conductive layer. the semiconductor layer has a region located inside the opening and a region located on the fourth conductive layer, the semiconductor layer has a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the third conductive layer in the opening, and a region in contact with the fourth conductive layer; the protective layer has a region located on the semiconductor layer and a region inside the opening that faces the fourth conductive layer with the semiconductor layer sandwiched therebetween; and the height of the lower end of the protective layer from a reference plane is the second insulating layer has a region located on the protective layer and a region in contact with a side surface of the semiconductor layer inside the opening; the fifth conductive layer is located on the second insulating layer and has a region facing the semiconductor layer inside the opening with the second insulating layer sandwiched therebetween; the semiconductor layer contains indium oxide; the second conductive layer contains zirconium, titanium, or tin; the third conductive layer contains an oxide containing indium and a metal element; the protective layer contains indium and an element M, wherein the element M is one or more elements selected from zinc, aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0018] Alternatively, in the above embodiment, the first insulating layer may include an oxide layer, the second insulating layer may include a layer containing silicon oxide, and the oxygen concentration of the layer containing silicon oxide may be higher than the oxygen concentration of the oxide layer.

[0019] Alternatively, in the above aspect, the oxygen concentration in the region of the semiconductor layer that is in contact with the protective layer may be lower than the oxygen concentration in the region of the semiconductor layer that is in contact with the second insulating layer.

[0020] Alternatively, in the above embodiment, the metal element may be tin or zinc.

[0021] Alternatively, in the above aspect, the electrical conductivity of the first conductive layer may be higher than the electrical conductivity of the second conductive layer.

[0022] According to one embodiment of the present invention, a semiconductor device, a memory device, or a display device including a transistor with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device, a memory device, or a display device including a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device, a memory device, or a display device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device or a memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device, a memory device, or a display device with low power consumption can be provided. According to one embodiment of the present invention, a manufacturing method of the semiconductor device, the memory device, or the display device can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0024] FIGS. 1A and 1B are perspective views showing a configuration example of a semiconductor device. FIGS. 2A and 2B are plan views showing a configuration example of a semiconductor device. FIGS. 3A and 3B are plan views showing a configuration example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing a configuration example of a semiconductor device. FIG. 5 is a cross-sectional view showing a configuration example of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views showing a configuration example of a semiconductor device. FIG. 8 is a cross-sectional view showing a configuration example of a semiconductor device. FIGS. 9A and 9B are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 10A and 10B are perspective views showing a configuration example of a semiconductor device. FIG. 11 is a perspective view showing a configuration example of a semiconductor device. FIG. 12 is a plan view showing a configuration example of a semiconductor device. FIGS. 13A and 13B are cross-sectional views showing an example of a semiconductor device. FIGS. 14A, 14B, and 14C are cross-sectional views showing an example of a semiconductor device. FIG. 15A is a plan view showing a configuration example of a semiconductor device. FIG. 15B is a cross-sectional view showing an example of a semiconductor device. 16A and 16B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 17A and 17B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 18A and 18B are cross-sectional views showing a structural example of a semiconductor device. FIG. 19A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 19B and 19C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 20A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 20B and 20C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 21A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 21B and 21C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 22A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 22B and 22C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 23A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 23B and 23C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 24A is a plan view showing an example of a method for manufacturing a semiconductor device. 24B and 24C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device, Fig. 25A, Fig. 25B, and Fig. 25C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device, and Fig. 26A is a plan view illustrating an example of a method for manufacturing a semiconductor device.26B and 26C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 27A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 27B and 27C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 28A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 28B and 28C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 29A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 29B and 29C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 30A and 30B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 30C is a cross-sectional view illustrating an indium oxide film. FIG. 31A is a plan view illustrating a structural example of a memory device. FIGS. 31B and 31C are cross-sectional views illustrating a structural example of a memory device. FIGS. 32A1 and 32A2 are plan views illustrating a structural example of a memory device. FIGS. 32B and 32C are cross-sectional views illustrating a structural example of a memory device. FIG. 33 is a cross-sectional view illustrating a structural example of a memory device. FIG. 34 is a block diagram showing a configuration example of a semiconductor device. FIGS. 35A, 35B, 35C, 35D, 35E, 35F, 35G, and 35H are diagrams showing circuit configuration examples of memory cells. FIGS. 36A and 36B are perspective views showing a configuration example of a semiconductor device. FIG. 37 is a block diagram explaining a CPU. FIGS. 38A and 38B are perspective views showing a configuration example of a semiconductor device. FIGS. 39A and 39B are perspective views showing a configuration example of a semiconductor device. FIG. 40A is an equivalent circuit diagram of a logic circuit. FIG. 40B is a circuit symbol for the logic circuit. FIG. 40C is a timing chart showing the operation of the logic circuit. FIG. 41 is a cross-sectional view showing a configuration example of a semiconductor device. FIGS. 42A and 42D are equivalent circuit diagrams of logic circuits. FIGS. 42B, 42C, 42E, and 42F are circuit symbols for logic circuits. FIG. 43A is an equivalent circuit diagram of a DFF circuit. Fig. 43B is a circuit symbol for a DFF circuit. Fig. 44A is a diagram explaining an example of the configuration of a shift register circuit. Fig. 44B is a timing chart showing the operation of the shift register circuit. Figs. 45A and 45B are diagrams showing an example of electronic components. Figs. 46A, 46B, and 46C are diagrams showing an example of a mainframe computer. Fig. 46D is a diagram showing an example of space equipment.FIG. 46E is a diagram illustrating an example of a storage system applicable to a data center.

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0027] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0028] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes, stacking order, or arrangement order. Furthermore, even if a term is not accompanied by an ordinal number in this specification, ordinal numbers may be accompanied in the claims to avoid confusion between components. Furthermore, even if a term is accompanied by an ordinal number in this specification, ordinal numbers may be accompanied by a different ordinal number in the claims. Furthermore, even if a term is accompanied by an ordinal number in this specification, ordinal numbers may be omitted in the claims.

[0029] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0030] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0031] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0032] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0033] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ (also called) may be formed.

[0034] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0035] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0036] In this specification and the like, the term "content" refers to the ratio of a component contained in a film. For example, when an oxide semiconductor layer contains a metal element X, a metal element Y, and a metal element Z, the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is expressed as A. Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +BＺ ) can be shown as

[0037] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0038] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, in this specification, due to formatting restrictions, numbers may be expressed by adding a minus sign (-) before them instead of adding a bar above them. Individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0039] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0040] In this specification and the like, the opening also includes, for example, a groove, a slit, and the like.

[0041] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0042] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0043] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0044] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0045] Unless otherwise specified, in this specification, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0046] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0047] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0048] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0049] Embodiment 1 In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention includes a vertical transistor. In addition, in one embodiment of the present invention, a semiconductor layer included in the vertical transistor can contain indium oxide.

[0050] In this specification, a vertical transistor refers to a transistor in which the source electrode and the drain electrode are provided at different heights. For example, a transistor in which the bottom surfaces of the source electrode and the drain electrode are provided at different heights can be called a vertical transistor. Here, of the source electrode and the drain electrode, the electrode with a lower height from a reference plane such as the top surface of the substrate or the top surface of the insulating base layer is called the lower electrode, and the electrode with a higher height is called the upper electrode. An interlayer insulating layer is provided between the lower electrode and the upper electrode. In a vertical transistor, the channel length direction has a component in the height direction (vertical direction). Note that a vertical transistor is also called a VFET (Vertical Field Effect Transistor), a vertical channel transistor, a vertical channel transistor, etc.

[0051] 1A and 1B are perspective views showing a configuration example of a semiconductor device including a transistor 200 A. Fig. 1B is a partially cutaway view of Fig. 1A.

[0052] 1A and 1B, the X direction, Y direction, and Z direction are indicated by arrows. Note that although the same X, Y, and Z symbols are used in both Fig. 1A and Fig. 1B, the directions do not necessarily have to match between them. Furthermore, although the X direction, Y direction, and Z direction are also indicated by arrows in the drawings shown below, the directions do not necessarily have to match between the drawings.

[0053] 2A, 2B, 3A, and 3B are plan views showing configuration examples of a semiconductor device including a transistor 200A. 2B, 3A, and 3B are views in which some elements are omitted from FIG. 2A. Note that some elements are omitted from plan views such as FIG. 2A for clarity. Some elements may also be omitted from subsequent plan views.

[0054] Fig. 4A is a cross-sectional view taken along dashed lines A1-A2 in Fig. 2A to Fig. 3B. Fig. 4B is a cross-sectional view taken along dashed lines A3-A4 in Fig. 2A to Fig. 3B. Fig. 5 is a cross-sectional view taken along dashed lines A5-A6 in Fig. 4A. Fig. 5 is also referred to as a plan view.

[0055] 1A to 5 includes an insulating layer 210 over a substrate (not shown), a transistor 200A over the insulating layer 210, and an insulating layer 280 over the insulating layer 210. The insulating layer 210 functions as a base insulating layer or an interlayer insulating layer. The insulating layer 280 functions as an interlayer insulating layer.

[0056] [Transistor 200A] The transistor 200A includes a conductive layer 220a on the insulating layer 210, a conductive layer 220b on the conductive layer 220a, a conductive layer 220c on the conductive layer 220b, a conductive layer 240 on the insulating layer 280, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. The insulating layer 280 is located on the insulating layer 210 and the conductive layer 220c. The conductive layer 220b can be in contact with the top surface of the conductive layer 220a. The conductive layer 220c can be in contact with the top surface of the conductive layer 220b. Note that the insulating layer 280 can also be considered part of the components of the transistor 200A. The insulating layer 210 can also be considered part of the components of the transistor 200A.

[0057] In Fig. 2B, the conductive layer 260 is omitted from Fig. 2A. In Fig. 3A, the semiconductor layer 230 is further omitted from Fig. 2B. In Fig. 3B, the conductive layer 240 is further omitted from Fig. 3A.

[0058] 4A and 4B show an example in which the conductive layer 240 has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1. Also, FIGS. 4A to 5 show an example in which the conductive layer 260 has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1.

[0059] The semiconductor layer 230 includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor. Here, a transistor including an oxide semiconductor is referred to as an OS transistor. Note that in this specification and the like, a semiconductor layer including an oxide semiconductor can be alternatively referred to as an oxide semiconductor layer. Furthermore, since the semiconductor layer 230 includes a metal oxide, the semiconductor layer 230 can be alternatively referred to as a metal oxide layer. In the semiconductor device of one embodiment of the present invention, indium oxide can be used as the semiconductor layer 230, for example.

[0060] When the semiconductor layer 230 is a metal oxide layer, the higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide layer, the higher the field-effect mobility of the transistor. Therefore, by using indium oxide for the semiconductor layer 230, the transistor 200A can have a large on-state current and high frequency characteristics. Therefore, a semiconductor device with high operating speed can be realized. Details of indium oxide will be described in Embodiment 2.

[0061] Furthermore, when the semiconductor layer 230 is a metal oxide layer, the semiconductor layer 230 is preferably a film having crystallinity (i.e., having crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains. In particular, when an indium oxide film is used as the semiconductor layer 230, a polycrystalline film is preferable, and a single-crystal film is more preferable. A single-crystal film does not have crystal grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at crystal grain boundaries. Using a single-crystal film can suppress carrier scattering at crystal grain boundaries. Therefore, the transistor 200A can exhibit high field-effect mobility. Furthermore, variations in the electrical characteristics of the transistor 200A due to the crystal grain boundaries can be suppressed.

[0062] At least part of the conductive layer 220a, at least part of the conductive layer 220b, and at least part of the conductive layer 220c function as one of a source electrode and a drain electrode of the transistor 200A. At least part of the conductive layer 240 functions as the other of the source electrode and the drain electrode of the transistor 200A. At least part of the conductive layer 260 functions as a gate electrode of the transistor 200A. At least part of the insulating layer 250 functions as a gate insulating layer of the transistor 200A. The semiconductor layer 230 has a channel formation region of the transistor 200A.

[0063] As described above, in the transistor 200A, the source electrode and the drain electrode are provided at different heights. Therefore, the transistor 200A is a vertical transistor. Here, the height of the conductive layer 240 from, for example, the top surface of the insulating layer 210 is higher than the height of the conductive layers 220a, 220b, and 220c from, for example, the top surface of the insulating layer 210. Therefore, the conductive layers 220a, 220b, and 220c are referred to as the lower electrode of the transistor 200A, and the conductive layer 240 is referred to as the upper electrode of the transistor 200A.

[0064] The conductive layer 220c, the insulating layer 280, and the conductive layer 240 have an opening 290 at a position overlapping with the conductive layer 220b. Specifically, the conductive layer 220c, the insulating layer 280, and the conductive layer 240 have the opening 290 reaching the conductive layer 220b.

[0065] The openings 290 include an opening in the conductive layer 220c, an opening in the insulating layer 280, and an opening in the conductive layer 240. The shape and size of the openings 290 in a plan view may differ depending on the layer. When the shape of the openings 290 in a plan view is circular, the openings in each layer may or may not be concentric.

[0066] Each of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 is provided so that at least a portion thereof is located inside the opening 290. Furthermore, the portions of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 that are located inside the opening 290 are provided to reflect the shape of the opening 290.

[0067] The semiconductor layer 230 is provided so as to cover the bottom and sidewalls of the opening 290. The semiconductor layer 230 has a recess that reflects the shape of the opening 290. The semiconductor layer 230 has a region in contact with the top surface of the conductive layer 220b, a region in contact with the side surface of the conductive layer 220c in the opening 290, and a region in contact with the conductive layer 240. The semiconductor layer 230 can have a region in contact with the top surface of the conductive layer 240 and a region in contact with the side surface of the opening 290. The semiconductor layer 230 is provided along the side surface of the insulating layer 280 in the opening 290, and can have, for example, a region in contact with the side surface of the insulating layer 280 in the opening 290.

[0068] In this specification and the like, the sidewall of an opening refers to the side surface within the opening of the layer in which the opening is formed.

[0069] A region of the semiconductor layer 230 in contact with the conductive layer 220b, a region of the semiconductor layer 230 in contact with the conductive layer 220c, and a region near these regions function as one of a source region and a drain region. A region of the semiconductor layer 230 in contact with the conductive layer 240 and a region near the conductive layer 240 function as the other of the source region and the drain region. In the semiconductor layer 230, a region between the source region and the drain region functions as a channel formation region of the transistor 200A. For example, a region of the semiconductor layer 230 provided along a side surface of the opening 290 of the insulating layer 280 functions as a channel formation region of the transistor 200A. For example, a region of the semiconductor layer 230 in contact with a side surface of the opening 290 of the insulating layer 280 and a region near the side surface function as a channel formation region of the transistor 200A.

[0070] Here, the conductive layer 220b, whose upper surface is in contact with the semiconductor layer 230, contains a metal element that generates carriers when supplied to the semiconductor layer 230. This reduces the resistance of the region of the semiconductor layer 230 that is in contact with the conductive layer 220b and the region nearby. This reduced-resistance region is referred to as region 230n. By including region 230n in the semiconductor layer 230, the contact resistance between the lower electrode of the transistor 200A and the semiconductor layer 230 can be reduced. This increases the on-current of the transistor 200A, resulting in a semiconductor device with high operating speed. Note that regions other than region 230n of the semiconductor layer 230 are not shown in FIG. 3A .

[0071] When, for example, zirconium, titanium, or tin is used as the conductive layer 220b, these metal elements can be supplied to the semiconductor layer 230 as impurity elements, and some of the elements contained in the semiconductor layer 230 can be replaced with the impurity elements. For example, when indium oxide, specifically crystalline indium oxide, is used as the semiconductor layer 230, some of the indium in the crystal can be replaced with the impurity elements. Since the above-mentioned impurity elements can become ions with a valence different from that of indium ions, for example, by replacing indium contained in the semiconductor layer 230 with the above-mentioned impurity elements, a shallow donor level is easily formed. In other words, a donor level is easily formed so that the difference between the energy of the conduction band minimum (CBM) and the donor level is small. Therefore, a transistor with high field-effect mobility can be realized.

[0072] The concentration of the metal element contained in the semiconductor layer 230 can be measured by, for example, inductively coupled plasma mass spectrometry (ICP-MS), XPS, SIMS, time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES), energy dispersive X-ray spectroscopy (EDX), inductively coupled plasma optical emission spectroscopy (ICP-AES), or the like. The evaluation can be performed using plasma-atomic emission spectroscopy or the like.

[0073] Here, for example, the boundary between region 230n and conductive layer 220b may not be clearly visible in an electron microscope image, such as a scanning transmission electron microscope (STEM) image. In this case, the boundary between region 230n and conductive layer 220b can be defined based on the content of the metal element. Specifically, a region where the content of the metal element is less than a predetermined value can be defined as region 230n, and a region where the content is equal to or greater than the predetermined value can be defined as conductive layer 220b. For example, a region where the content of the metal element measured using EDX is less than 3 atomic% can be defined as region 230n, and a region where the content is 3 atomic% or greater can be defined as conductive layer 220b. Here, the content of the metal element in a predetermined region refers to the ratio of the number of atoms of the metal element to the sum of the number of atoms of all metal elements contained in the predetermined region.

[0074] The conductive layer 220a is made of a material having higher electrical conductivity than the conductive layer 220b. This allows the electrical resistance of one of the source and drain electrodes of the transistor 200A to be lower than when the conductive layer 220a is not provided. Therefore, the on-state current of the transistor 200A can be increased, thereby realizing a semiconductor device with high operating speed.

[0075] The conductive layer 220a can be made of a conductive material containing, for example, tungsten, copper, aluminum, or molybdenum as a main component. Alternatively, the conductive layer 220a can be made of, for example, ruthenium, titanium nitride, tantalum nitride, or the like. Furthermore, increasing the thickness of the conductive layer 220a is preferable because it can reduce the electrical resistance of the conductive layer 220a. For example, it is preferable that the thickness of the conductive layer 220a be thicker than the thickness of the conductive layer 220b. In other words, the thickness of the conductive layer 220b can be thinner than the thickness of the conductive layer 220a. This can improve the productivity of the semiconductor device.

[0076] Furthermore, when the conductive layer 220a and the conductive layer 220b are made of the above-described materials, the contact resistance between the conductive layer 220b and the semiconductor layer 230 can be made lower than the contact resistance between the conductive layer 220a and the semiconductor layer 230. Therefore, the contact resistance between the lower electrode of the transistor 200A and the semiconductor layer 230 can be made lower than when the lower electrode does not have the conductive layer 220b. Therefore, the on-state current of the transistor 200A can be increased, and a semiconductor device with high operating speed can be realized.

[0077] The semiconductor layer 230 has a region in contact with the side surface of the conductive layer 220c as described above, in addition to the top surface of the conductive layer 220b. Therefore, the contact area between the lower electrode of the transistor 200A and the semiconductor layer 230 can be made larger than when the lower electrode does not have the conductive layer 220c. This can reduce the contact resistance between the lower electrode and the semiconductor layer 230. As a result, the on-state current of the transistor 200A can be increased, and a semiconductor device with high operating speed can be realized.

[0078] Here, it is preferable to increase the thickness of the conductive layer 220c, because this increases the contact area between the lower electrode of the transistor 200A and the semiconductor layer 230. For example, it is preferable to make the thickness of the conductive layer 220c thicker than the thickness of the conductive layer 220b. In other words, the thickness of the conductive layer 220b can be made thinner than the thickness of the conductive layer 220c. This can improve the productivity of the semiconductor device.

[0079] The conductive layer 220c is preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220c. In addition, the contact resistance between the conductive layer 220c and the semiconductor layer 230 can be made lower than the contact resistance between the conductive layer 220a and the semiconductor layer 230, for example.

[0080] By using a conductive material containing oxygen for the conductive layer 220c, the conductive layer 220c can maintain its conductivity even when it absorbs oxygen. Examples of the conductive material include a conductor containing an element contained in the semiconductor layer 230. The conductive layer 220c includes, for example, an oxide containing indium and a metal element. For example, indium tin oxide (In—Sn oxide, also referred to as ITO), indium tin oxide containing silicon oxide (also referred to as ITSO), indium zinc oxide (In—Zn oxide), or the like is preferably used for the conductive layer 220c.

[0081] The thickness of the conductive layer 220a is, for example, preferably 10 nm to 100 nm, more preferably 10 nm to 80 nm, more preferably 20 nm to 60 nm, and even more preferably 30 nm to 50 nm. The thickness of the conductive layer 220b is, for example, preferably 1 nm to less than 50 nm, more preferably 3 nm to 30 nm, and even more preferably 5 nm to 20 nm. The thickness of the conductive layer 220c is, for example, preferably 10 nm to 100 nm, more preferably 10 nm to 70 nm, and even more preferably 15 nm to 50 nm.

[0082] At least a portion of the insulating layer 250 is located on the semiconductor layer 230. The insulating layer 250 is provided so as to cover the semiconductor layer 230. The insulating layer 250 is provided on the insulating layer 280 so as to cover the top surface and side surfaces of the semiconductor layer 230 and the side surfaces of the conductive layer 240. The insulating layer 250 also has a recess that reflects the shape of the recess that the semiconductor layer 230 has.

[0083] The conductive layer 260 is provided so as to fill at least a part of a recessed portion of the insulating layer 250. The conductive layer 260 has a region inside the opening 290 that faces the semiconductor layer 230 with the insulating layer 250 sandwiched therebetween. In other words, the semiconductor layer 230 has a region inside the opening 290 that faces the conductive layer 260 with the insulating layer 250 sandwiched therebetween. At least a part of the region of the semiconductor layer 230 functions as a channel formation region of the transistor 200A.

[0084] As described above, the transistor 200A is a vertical transistor. In the transistor 200A, a current, for example, a drain current, flows vertically in the semiconductor layer 230. That is, a channel is formed along the side surface of the opening 290 in the insulating layer 280. As a result, the transistor 200A can occupy a smaller area than a planar transistor in which a channel formation region, a source region, and a drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.

[0085] 1A to 4B show a configuration in which the side edge of the conductive layer 240 and the side edge of the semiconductor layer 230 are aligned or substantially aligned outside the opening 290. The conductive layer 240 and the semiconductor layer 230 can be fabricated by processing using the same mask. This is preferable because it reduces the number of masks required to fabricate a semiconductor device. Note that the present invention is not limited to this. For example, a structure may be adopted in which any one of the side edge of the semiconductor layer 230, the side edge of the conductive layer 240_1, and the side edge of the conductive layer 240_2 is located inside or outside the other in the X direction or Y direction.

[0086] 2A , the transistor 200A is provided at the intersection of a conductive layer 260 extending in the X direction and a conductive layer 240 extending in the Y direction. As shown in FIG. 2A , the diameter of the opening 290 can be made smaller than both the width of the short side of the conductive layer 240 and the width of the short side of the conductive layer 260. In this way, the transistor 200A can be said to have a structure that allows for high integration and miniaturization.

[0087] As shown in FIG. 5 , by forming the opening 290 so that it has a circular shape in a plan view, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side surface of the conductive layer 260 provided at the center of the opening 290 faces the side surface of the semiconductor layer 230 via the insulating layer 250. That is, in a plan view, the entire periphery of the semiconductor layer 230 becomes a channel formation region. In this case, for example, the channel width of the transistor 200A is determined by the outer periphery length of the semiconductor layer 230 shown in FIG. 5 . That is, the channel width of the transistor 200A can be determined by the width of the opening 290 (or the diameter if the opening 290 is circular in a plan view). In FIGS. 4A and 5 , the width D of the opening 290 is shown, and in FIG. 5 , the channel width W of the transistor 200A is shown.

[0088] Furthermore, by arranging the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 concentrically, the distance between the conductive layer 260 and the semiconductor layer 230 becomes approximately uniform, so that a gate electric field can be applied to the semiconductor layer 230 approximately uniformly.

[0089] Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current. Meanwhile, the area occupied by the transistor 200A, for example, the area of ​​the transistor 200A in a plan view, is roughly determined by the width of the opening 290. Reducing the width D of the opening 290 reduces the area occupied by the transistor 200A, thereby enabling a semiconductor device to be highly integrated.

[0090] The width D of the opening 290 may vary in the depth direction. Here, the shortest distance between two side surfaces of the opening 290 in the conductive layer 240 in a cross-sectional view is used as the width D. In other words, the minimum width of the opening 290 in the conductive layer 240 is used as the width D of the opening 290. Alternatively, the width of the opening 290 at the highest position in the conductive layer 240, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D of the opening 290 in the conductive layer 240 is used to determine the width D of the opening 290, but the method for determining the width D is not particularly limited. For example, the shortest distance between two side surfaces of the opening 290 in the insulating layer 280 can be used as the width D. Alternatively, the width of the opening 290 at the highest position, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these positions in the insulating layer 280, or the average value of these three widths may be used as the width D of the opening 290. Similarly, the width D of the opening 290 may be determined using the width of the opening 290 in the conductive layer 220c.

[0091] The width D of the opening 290 is set by the film thickness of each of the semiconductor layer 230, insulating layer 250, and conductive layer 260 provided inside the opening 290. The width D of the opening 290 is, for example, preferably 5 nm to 120 nm, more preferably 5 nm to 100 nm, more preferably 10 nm to 60 nm, more preferably 20 nm to 50 nm, more preferably 20 nm to 40 nm, and even more preferably 20 nm to 30 nm. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D × π".

[0092] 4A and 5, when the film thickness of the semiconductor layer 230 is defined as thickness Tsc, the channel width W can also be calculated as, for example, "(D-Tsc) x π". Here, the width D can be defined as the outer diameter of the semiconductor layer 230. Furthermore, "D-Tsc" can be defined as the arithmetic mean of the outer diameter and the inner diameter of the semiconductor layer 230 in the cross section shown in FIG.

[0093] In this embodiment, an example is shown in which the opening 290 is circular in plan view. By using a circular shape, the processing accuracy during the formation of the opening can be improved, and openings of minute sizes can be formed. However, the present invention is not limited to this. In plan view, the opening 290 can be, for example, a circle or a substantially circular shape such as an ellipse, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygonal shape with rounded corners. Note that the circle is not limited to a perfect circle. Furthermore, the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees).

[0094] The channel length of the transistor 200A is the distance between the source region and the drain region. In other words, the channel length of the transistor 200A is determined by the thickness of the insulating layer 280 on the conductive layer 220c. Therefore, the channel length of the transistor 200A does not affect the area occupied by the transistor 200A, for example, the area of ​​the transistor 200A in a planar view. In FIG. 4A , the channel length L of the transistor 200A is indicated by a dashed double-headed arrow. Note that the channel length L can be considered to be the distance between the edge of the region where the semiconductor layer 230 and the conductive layer 220c contact each other and the edge of the region where the semiconductor layer 230 and the conductive layer 240 contact each other in a cross-sectional view. In this case, the channel length L corresponds to the length of the side of the opening 290 in the insulating layer 280 in a cross-sectional view.

[0095] The channel length of the transistor 200A can be, for example, 500 nm or less, 300 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and can be 0.1 nm or more, 1 nm or more, or 5 nm or more. Typically, the channel length can be 1 nm or more and 300 nm or less, preferably 5 nm or more and 100 nm or less. This can improve productivity and yield in the formation of the insulating layer 280, the formation of the opening 290 in the insulating layer 280, and the like. Furthermore, the on-state current of the transistor 200A can be increased, thereby improving frequency characteristics.

[0096] The channel length L of the transistor 200A is preferably at least shorter than the channel width W of the transistor 200A. The channel length L of the transistor 200A is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200A. With such a structure, a transistor with good electrical characteristics and high reliability can be realized.

[0097] Since the insulating layer 210 functions as an interlayer insulating layer, it is preferable to use a material with a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer insulating layer, the parasitic capacitance generated between wirings can be reduced.

[0098] The insulating layer 210 preferably has a barrier property against hydrogen. When the insulating layer 210 provided below the semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200A to the semiconductor layer 230 can be suppressed.

[0099] The insulating layer 210 preferably has a function of capturing or fixing hydrogen. When the insulating layer 210 has the function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 230 can be diffused into the insulating layer 210 through the conductive layer 220b, the conductive layer 220a, and the like, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0100] The concentration of impurities such as hydrogen or water in the insulating layer 210 is preferably reduced, which can prevent impurities such as hydrogen or water from entering the channel formation region of the semiconductor layer 230.

[0101] 4A shows an example in which the insulating layer 210 has a single-layer structure. The insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable that the first insulating layer has a barrier property against hydrogen, and the second insulating layer has a function of capturing or fixing hydrogen. Specifically, it is preferable to use silicon nitride as the first insulating layer and aluminum oxide, hafnium oxide, hafnium zirconium oxide, or hafnium silicate as the second insulating layer.

[0102] Since the insulating layer 280 functions as an interlayer insulating layer, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer insulating layer, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0103] By using silicon oxide, which has a small thermal expansion coefficient, for the insulating layer 280 provided before the formation of the semiconductor layer 230, it is possible to promote the crystal growth of indium oxide formed by atomic layer deposition (ALD) inside the opening of the insulating layer 280.

[0104] The concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. This can prevent impurities such as hydrogen or water from entering the channel formation region of the semiconductor layer 230.

[0105] The conductive layer 240 shown in FIGS. 1A to 4B has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240_2 and a material having higher conductivity than the conductive layer 240_2 for the conductive layer 240_1. The conductive layer 240_1 can be made of a material that can be used for the conductive layer 220a. The conductive layer 240_2 can be made of a material that can be used for the conductive layer 220c. By using an oxide conductor for the conductive layer 240_2 that is mainly in contact with the semiconductor layer 230, the contact resistance with the semiconductor layer 230 can be reduced. Furthermore, by using a material having higher conductivity than an oxide conductor for the layer that constitutes the conductive layer 240, the conductivity of the conductive layer 240 can be increased.

[0106] The conductive layer 240_1 may be made of a material that generates carriers when supplied to the semiconductor layer 230. Specifically, the conductive layer 240_1 may be made of a material that can be used for the conductive layer 220b. This allows the resistance of a region of the semiconductor layer 230 that is in contact with the conductive layer 240_1 and a region in the vicinity thereof to be reduced, similar to the region 230n.

[0107] Note that a conductive material containing oxygen can be used for the conductive layer 240_1, and a material having higher conductivity than the conductive layer 240_1 can be used for the conductive layer 240_2. In this case, an oxide conductor is used for the layer of the conductive layer 240 that is closest to the channel formation region of the semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200A can be increased. Alternatively, a conductive material containing oxygen can be used for the conductive layer 240_1, and a material that generates carriers when supplied to the semiconductor layer 230 can be used for the conductive layer 240_2. This can increase the area of ​​a low-resistance region in the semiconductor layer 230.

[0108] The insulating layer 250 preferably has a function of supplying oxygen to the semiconductor layer 230. The insulating layer 250 preferably has a region containing oxygen that is desorbed by heating (hereinafter, sometimes referred to as excess oxygen), for example. When the insulating layer having the region containing excess oxygen is in contact with the semiconductor layer 230, oxygen can be supplied to the semiconductor layer 230. The oxygen supplied to the semiconductor layer 230 repairs oxygen vacancies, and the amount of oxygen vacancies in the semiconductor layer 230 can be reduced. Examples of insulating materials that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies. Examples of insulating layers that easily form a region containing excess oxygen include a silicon oxide film, a silicon oxynitride film, and a silicon oxide film having vacancies.

[0109] The insulating layer 250 preferably has a function of capturing or fixing oxygen (also referred to as gettering). As described above, an indium oxide film is a film through which oxygen easily moves. Therefore, when the insulating layer 250 has the function of capturing or fixing oxygen, excess oxygen in the semiconductor layer 230 can diffuse into the insulating layer 250 and the oxygen can be captured or fixed. Therefore, the OS transistor can suppress positive drift degradation in a +GBT stress test caused by excess oxygen. Examples of insulating materials having a function of capturing or fixing oxygen include aluminum oxide, hafnium oxide, hafnium zirconium oxide, and oxides containing hafnium and silicon (hafnium silicate). Examples of insulating layers having a function of capturing or fixing oxygen include an aluminum oxide film, a hafnium oxide film, a hafnium zirconium oxide film, and a hafnium silicate film.

[0110] Note that an aluminum oxide film, a hafnium oxide film, a hafnium zirconium oxide film, and a hafnium silicate film have the function of capturing or fixing hydrogen. As described above, an indium oxide film is a film through which hydrogen easily moves. Therefore, when the insulating layer 250 has the function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 230 can be diffused into the insulating layer 250 and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region) can be reduced.

[0111] FIG. 4A shows an example in which the insulating layer 250 has a single layer structure. The insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 using two or more types of films, the insulating layer 250 can be given multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting excess oxygen from the semiconductor layer 230, a function of extracting hydrogen from the semiconductor layer 230, and a function of suppressing diffusion of hydrogen into the semiconductor layer 230. Details of the case in which the insulating layer 250 has a stacked structure will be described later.

[0112] 1A to 4B has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, titanium nitride is preferably used for the conductive layer 260_1 and tungsten is preferably used for the conductive layer 260_2. Alternatively, tantalum nitride is preferably used for the conductive layer 260_1 and copper is preferably used for the conductive layer 260_2. Such a structure can increase the conductivity of the conductive layer 260.

[0113] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0114] 1A to 5. The following describes examples of the configuration of the transistor 200A that differ from those in FIGS. 1A to 5. The following mainly describes configurations that differ from those in FIGS. 1A to 5, and omits descriptions of similar configurations as appropriate.

[0115] 6A is a diagram showing an example in which the transistor 200A shown in FIG. 4A does not have the conductive layer 220c. The semiconductor device shown in FIG. 6A can be manufactured using fewer steps than the semiconductor device shown in FIG. 4A. On the other hand, the semiconductor device shown in FIG. 4A can have a larger contact area between the bottom electrode of the transistor 200A and the semiconductor layer 230 than the semiconductor device shown in FIG. 6A, and therefore can have a smaller contact resistance between the bottom electrode and the semiconductor layer 230.

[0116] 6A , the channel length L of the transistor 200A is indicated by a dashed double-headed arrow. Note that in the transistor 200A shown in FIG. 6A , the channel length L can be considered to be the distance between the top end of the region 230n and the end of the region where the semiconductor layer 230 and the conductive layer 240 contact each other. In the transistor 200A shown in FIG. 6A , the channel length L can be made shorter than the length of the side surface of the opening 290 of the insulating layer 280 in a cross-sectional view by the thickness of the region 230n.

[0117] 6B is a diagram showing an example in which the transistor 200A shown in FIG. 4A does not include the conductive layer 220a. The semiconductor device shown in FIG. 6B can be manufactured using fewer steps than the semiconductor device shown in FIG. 4A. On the other hand, the conductive layer 220a shown in FIG. 4A has higher electrical conductivity than the conductive layer 220b, as described above. Therefore, the transistor 200A shown in FIG. 4A can have lower electrical resistance of one of the source electrode and the drain electrode than the transistor 200A shown in FIG. 6B.

[0118] FIG. 7A is a diagram showing an example in which the conductive layer 220b shown in FIG. 4A has a recess that overlaps the opening 290. The recess in the conductive layer 220b increases the contact area between the semiconductor layer 230 and the conductive layer 220b compared to when the recess is not present. This increases the volume of the low-resistance region 230n. This increases the on-current of the transistor 200A. On the other hand, when the conductive layer 220b is formed without a recess, the thickness of the conductive layer 220b can be made thinner than when the conductive layer 220b is formed with a recess, while preventing the opening 290 from reaching the conductive layer 220a.

[0119] 4A has a three-layer structure including a layer 240_3, a conductive layer 240_1 on the layer 240_3, and a conductive layer 240_2 on the conductive layer 240_1. That is, in the example shown in FIG. 7B, the layer 240_3 is provided between the insulating layer 280 and the conductive layer 240_1.

[0120] 7B , the conductive layer 240_1 can be formed using a material that can be used for the conductive layer 220a. The conductive layer 240_2 can be formed using a material that can be used for the conductive layer 220c. The layer 240_3 can be formed using a material that can be used for the conductive layer 220b. That is, the layer 240_3 can be formed using a material that generates carriers when supplied to the semiconductor layer 230. Note that the material that can be used for the layer 240_3 is not limited to the material that can be used for the conductive layer 220b, and can be formed using a material that can be used for the layer 220d, which will be described later.

[0121] As a result, the resistance of the region of the semiconductor layer 230 in contact with the layer 240_3 and the region in the vicinity thereof can be reduced. The region with reduced resistance is referred to as a region 230na. For the region 230na, the description of the region 230n can be referred to.

[0122] The stacking order of the conductive layer 240_1, the conductive layer 240_2, and the layer 240_3 is not limited to the configuration shown in FIG. 7B . For example, a three-layer structure including the conductive layer 240_1, the layer 240_3 on the conductive layer 240_1, and the conductive layer 240_2 on the layer 240_3 may be used. The uppermost layer of the conductive layer 240 may be the layer 240_3. In this case, the lowermost layer of the conductive layer 240 may be the conductive layer 240_1 or the conductive layer 240_2.

[0123] 8 illustrates an example in which the lower electrode of the transistor 200A includes a conductive layer 220a, a layer 220d on the conductive layer 220a, and a conductive layer 220c on the layer 220d and on the conductive layer 220a. The conductive layer 220c shown in FIG. 8 has a region in contact with the conductive layer 220a and a region in contact with the layer 220d. The side edges of the layer 220d are located inside (closer to the opening 290) than the side edges of the conductive layer 220a and the conductive layer 220c. The side edges of the layer 220d are covered by the conductive layer 220c.

[0124] The layer 220d can be made of a material that can be used for the conductive layer 220b. However, the layer 220d can be made of a material other than a conductive material. That is, the layer 220d is not limited to a conductive layer. For example, yttria-stabilized zirconia (YSZ) can be used as the layer 220d.

[0125] In FIG. 8 , the current flowing from the region 230n of the semiconductor layer 230 toward the bottom electrode of the transistor 200A is indicated as current I. By configuring the bottom electrode of the transistor 200A as shown in FIG. 8 , the current I can flow without passing through the layer 220d. As described above, the electrical conductivity of the layer 220d is lower than that of the conductive layer 220a. Therefore, by providing a region in which the conductive layer 220c is in contact with the conductive layer 220a, the electrical resistance of the bottom electrode of the transistor 200A can be reduced. This increases the on-state current of the transistor 200A, thereby achieving a semiconductor device with high operating speed. Meanwhile, when the bottom electrode of the transistor 200A has the configuration shown in FIG. 4A , the number of manufacturing steps for the semiconductor device can be reduced compared to when the bottom electrode has the configuration shown in FIG. 8 . Note that while FIG. 8 illustrates an example in which the current I flows from the region 230n toward the conductive layer 220a, the current I may also flow from the conductive layer 220a toward the region 230n.

[0126] 9A and 9B are diagrams showing an example in which an oxide layer 229 is provided between the conductive layer 240_2 shown in FIG. 4B and the semiconductor layer 230. Fig. 9A shows an example in which the side edges of the oxide layer 229 coincide or substantially coincide with the side edges of the conductive layer 240. In the example shown in Fig. 9A, an opening 290 is also provided in the oxide layer 229. Fig. 9B shows an example in which the side edges of the conductive layer 240 do not overlap with the oxide layer 229.

[0127] The oxide layer 229 has crystal grains. By forming the semiconductor layer 230 so as to be in contact with the oxide layer 229, the semiconductor layer 230 can have crystal grains. The oxide layer 229 functions as a nucleus or a seed when the semiconductor layer 230 grows crystals. In this specification and the like, the oxide layer 229 can be referred to as a crystal nucleus or a seed crystal. Furthermore, since the oxide layer 229 has crystal grains, the oxide layer 229 can be referred to as a crystal portion. Here, by thinning the thickness of the oxide layer 229 as described above, the crystal growth of the semiconductor layer 230 can be promoted.

[0128] Indium oxide crystals have a cubic crystal structure (bixbyite type). When indium oxide is used for the semiconductor layer 230, the oxide layer 229 preferably has, for example, a hexagonal or trigonal crystal structure. In this case, when the oxide layer 229 has crystal grains whose crystal orientation with respect to the surface or the surface on which the oxide layer 229 is formed is <001>, the semiconductor layer 230 can be formed having crystal grains whose crystal orientation is <111>. When the crystal grains of the oxide layer 229 have a <001> crystal orientation with respect to the surface or the surface on which the oxide layer 229 is formed, the c-axis of the crystal grains is perpendicular or approximately perpendicular to the surface or the surface on which the oxide layer 229 is formed. Note that a crystal with a hexagonal or trigonal crystal structure can sometimes be referred to as a crystal with a layered structure. Therefore, the above structure can be regarded as a structure in which the semiconductor layer 230 having crystals with a cubic crystal structure is formed on the oxide layer 229 having crystals with a layered structure. That is, it can be considered as a layered structure produced by using a heteroepitaxial growth technique or a technique similar to heteroepitaxial growth. As a hexagonal or trigonal crystal, for example, a wurtzite structure, YbFe ２ O ４Type structure, Yb ２ Fe ３ O ７ There are various types of structures, including modified structures.

[0129] In this specification, the crystal orientation of a crystal grain refers to the orientation relative to the surface or surface of the film containing the crystal grain. For example, a crystal grain with a <100> crystal orientation is said to be a crystal grain whose (100) plane is parallel to the surface or surface of the film containing the crystal grain.

[0130] Specifically, the oxide layer 229 can be made of zinc oxide, In—Ga oxide, gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), In—Al—Zn oxide, In—Ga—Zn oxide, or In—Sn—Zn oxide. It is preferable to use In—Ga—Zn oxide as the oxide layer 229. In this case, the oxide layer 229 contains indium, gallium, zinc, and oxygen. Specifically, the oxide layer 229 preferably has a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition thereabout. Metal oxides with these compositions are suitable for the oxide layer 229 because they easily form a layered structure. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio.

[0131] In—Ga—Zn oxide, In—Sn—Zn oxide, and the like tend to have a c-axis aligned crystalline (CAAC) structure. The CAAC structure has fewer crystal grain boundaries in the a-b plane than a polycrystalline structure. When an oxide having a CAAC structure is used for the oxide layer 229, the c-axis of the crystal nuclei is perpendicular or approximately perpendicular to the surface of the oxide layer 229 or the surface on which it is formed. In other words, by using an oxide that tends to have a CAAC structure for the oxide layer 229, it is possible to improve the controllability of the crystal orientation of the crystal nuclei.

[0132] [Transistor 200B] An example of the configuration of a semiconductor device including transistor 200B will be described below. The configuration applicable to transistor 200A described above can also be applied to transistor 200B. The description of transistor 200A described above can also be applied to transistor 200B. Note that the following mainly describes configurations that are different from transistor 200A, and descriptions of similar configurations will be omitted as appropriate.

[0133] 10A, 10B, and 11 are perspective views showing an example of the configuration of a semiconductor device having a transistor 200B. Fig. 10B is a cutaway view of Fig. 10A. Fig. 11 is a view in which the insulating layer 250 and the conductive layer 260 are omitted from Fig. 10B.

[0134] 12 is a plan view illustrating a configuration example of a semiconductor device including a transistor 200B. Note that the conductive layer 260 and the like are not illustrated in FIG.

[0135] Fig. 13A is a cross-sectional view taken along dashed dotted lines A1-A2 and A3-A4 in Fig. 12.

[0136] 10A to 13B includes a protective layer 231. The protective layer 231 has a region located on the semiconductor layer 230 and a region facing the conductive layer 240 with the semiconductor layer 230 sandwiched therebetween inside the opening 290. The protective layer 231 is provided so as to cover an upper surface of the semiconductor layer 230 overlapping with the conductive layer 240 and a side surface of the conductive layer 240 located inside the opening 290.

[0137] In the transistor 200B, the semiconductor layer 230 has a region located between the conductive layer 240 and the protective layer 231. The protective layer 231 can be provided to be in contact with the semiconductor layer 230.

[0138] In the transistor 200B, the insulating layer 250 has a region located on the protective layer 231 and a region in contact with the side surface of the semiconductor layer 230 inside the opening 290. The insulating layer 250 is provided so as to cover the protective layer 231. At least a portion of the insulating layer 250 is located on the semiconductor layer 230. The insulating layer 250 is provided so as to cover the semiconductor layer 230. The insulating layer 250 is provided on the insulating layer 280 so as to cover the top surface and side surface of the semiconductor layer 230 and the side surface of the conductive layer 240. The insulating layer 250 also has a recess that reflects the shape of the recess of the semiconductor layer 230. Inside the opening 290, the insulating layer 250 has, for example, a region in contact with the semiconductor layer 230 and a region in contact with the protective layer 231.

[0139] When a metal oxide such as indium oxide is used for the semiconductor layer 230, it is preferable to supply oxygen to the channel formation region. As a result, for example, oxygen reacts with excess hydrogen contained in the semiconductor layer 230 to form water molecules (H ２ O) can be released. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. Ｏ ) is present, Vo can be compensated. As a result, a highly reliable semiconductor device can be realized. On the other hand, when oxygen is supplied to the conductive layer 240, the conductive layer 240 is oxidized, and the electrical conductivity of the conductive layer 240 may decrease. For example, when tungsten, copper, or aluminum is used for the conductive layer 240_1, the conductive layer 240_1 may be oxidized, and the electrical conductivity of the conductive layer 240_1 may decrease. In particular, when the side surface of the conductive layer 240_1 is oxidized, the contact resistance between the conductive layer 240_1 and the semiconductor layer 230 may increase. As a result, the channel length of the transistor may be the distance between the end of the region where the semiconductor layer 230 and the conductive layer 220c are in contact and the end of the region where the semiconductor layer 230 and the conductive layer 240_2 are in contact in a cross-sectional view. Therefore, the channel length of the transistor may be longer by the thickness of the conductive layer 240_1 compared to when the side surface of the conductive layer 240_1 is not oxidized.

[0140] Therefore, a film having a barrier property against oxygen is used as the protective layer 231. Specifically, a film having a lower oxygen permeability than the semiconductor layer 230 is used as the protective layer 231. Then, after the protective layer 231 is formed, a process for supplying oxygen to the semiconductor layer 230 is performed. This makes it possible to supply oxygen to the channel formation region of the transistor 200B while suppressing oxidation of the conductive layer 240. As a result, a highly reliable semiconductor device can be realized.

[0141] 13A, 13B, and the like, a region in the semiconductor layer 230 to which oxygen is supplied by the above-described treatment is shown as a region 230i. The region 230i includes a region of the semiconductor layer 230 in contact with the insulating layer 250. At least a part of the region 230i functions as a channel formation region of the transistor 200B.

[0142] The oxygen concentration in the region 230i is higher than the oxygen concentration in the region of the semiconductor layer 230 that is covered with the protective layer 231. In other words, the oxygen concentration in the region of the semiconductor layer 230 that is covered with the protective layer 231 is lower than the oxygen concentration in the region 230i. Specifically, the oxygen concentration in the region of the semiconductor layer 230 that is in contact with the protective layer 231 is lower than the oxygen concentration in the region 230i. For example, the oxygen deficiency (V Ｏ The concentration of excess oxygen in the region of the semiconductor layer 230 in contact with the protective layer 231 can be made lower than the concentration of excess oxygen in the region 230i.

[0143] Here, the height of the bottom end 232 of the protective layer 231 from the reference plane is set to be higher than the height of the top surface of the conductive layer 220c from the reference plane. This prevents the entire channel formation region of the transistor 200B from being covered with the protective layer 231, preventing oxygen from being supplied to the channel formation region. Furthermore, the closer the height of the bottom end 232 from the reference plane to the height of the bottom surface of the conductive layer 240 from the reference plane, the easier it is to supply oxygen to the channel formation region of the transistor 200B, which is preferable. FIGS. 13A and 13B show an example in which the height of the bottom end 232 from the reference plane is equal to or approximately equal to the height of the bottom surface of the conductive layer 240 from the reference plane. Note that the height of the bottom end 232 from the reference plane may be lower than the height of the bottom surface of the conductive layer 240 from the reference plane. In this case, oxidation of the conductive layer 240, specifically, oxidation of the conductive layer 240_1, is more easily suppressed.

[0144] The protective layer 231 can be formed, for example, by depositing a semiconductor film that will become the semiconductor layer 230, followed by depositing a protective film that will become the protective layer 231 using a method with low coverage, and then removing a portion of the film outside the opening 290 using an etching method or the like. The protective film that will become the protective layer 231 is preferably deposited using a method with lower coverage than the method used to deposit the semiconductor film that will become the semiconductor layer 230. For example, it is preferable to deposit the semiconductor film that will become the semiconductor layer 230 using an ALD method, and then deposit the protective film that will become the protective layer 231 using a sputtering method. This prevents the height of the lower end 232 from the reference plane from being equal to or lower than the height of the upper surface of the conductive layer 220c from the reference plane. Furthermore, increasing the aspect ratio of the opening 290 is preferable because it makes it easier to form the protective layer 231.

[0145] On the other hand, by depositing the semiconductor film that becomes the semiconductor layer 230 using a method that has higher coverage than the method used to deposit the protective film that becomes the protective layer 231, the semiconductor layer 230 can be formed to cover the opening 290 with good coverage, even if the aspect ratio of the opening 290 is high. For example, the semiconductor layer 230 can be formed to have a region in contact with the top surface of the conductive layer 220b, a region in contact with the side surface of the conductive layer 220c in the opening 290, a region in contact with the side surface of the insulating layer 280 in the opening 290, and a region in contact with the side surface of the conductive layer 240 in the opening 290. Furthermore, it is possible to prevent discontinuities from occurring in the semiconductor layer 230.

[0146] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0147] 12 to 13B , for example, a conductive film that will become the conductive layer 240 is first formed on the insulating layer 280, and then an opening 290 is formed in the conductive film, etc. Subsequently, a semiconductor film that will become the semiconductor layer 230 and a protective film that will become the protective layer 231 are formed in this order, and then the protective film that will become the protective layer 231, the semiconductor film that will become the semiconductor layer 230, and the conductive film that will become the conductive layer 240 are processed using the same mask, thereby forming the protective layer 231, the semiconductor layer 230, and the conductive layer 240.

[0148] The treatment for supplying oxygen to the semiconductor layer 230 can be carried out, for example, after the insulating layer 250 is formed and before the conductive layer 260 is formed. By carrying out the treatment after the insulating layer 250 is formed, it is possible to suppress outward diffusion of oxygen once supplied to the semiconductor layer 230 compared to when the treatment is carried out before the insulating layer 250 is formed. This reduces the hydrogen concentration in the semiconductor layer 230 and oxygen deficiency (V Ｏ ) can be effectively compensated for. Therefore, a highly reliable semiconductor device can be realized.

[0149] For example, ion implantation or plasma treatment can be used as a treatment for supplying oxygen to the semiconductor layer 230. For the plasma treatment, an apparatus that converts oxygen gas into plasma by high-frequency power can be suitably used. Examples of apparatus that convert gas into plasma by high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The ion implantation or plasma treatment is preferably performed in an atmosphere containing oxygen. For example, the atmosphere may contain oxygen, nitrous oxide (N ２ O), nitrogen dioxide (NO ２ An atmosphere containing one or more of oxygen, carbon monoxide, and carbon dioxide can be suitably used. The amount of oxygen supplied can be adjusted, for example, by adjusting the power and processing time in the plasma treatment. Oxygen can also be supplied by irradiating high-frequency electromagnetic waves in an oxygen-containing atmosphere to generate oxygen plasma. For example, oxygen can be supplied by performing microwave treatment in an oxygen-containing atmosphere.

[0150] In this specification, microwaves refer to electromagnetic waves with a frequency of 300 MHz or more and 300 GHz or less. A typical example of microwaves is electromagnetic waves with a frequency of 2.45 GHz. Microwave processing refers to processing using a device with a power source that generates high-density plasma using microwaves. Microwave processing can also be called microwave-excited high-density plasma processing. Details of microwave processing will be described later.

[0151] The protective layer 231 can include an oxide semiconductor. Therefore, the protective layer 231 can be an oxide semiconductor layer. In this case, the protective layer 231 can include, for example, indium and the element M. As a result, when indium oxide is used as the semiconductor layer 230, the oxygen permeability of the protective layer 231 can be made lower than the oxygen permeability of the semiconductor layer 230.

[0152] The element M is one or more elements selected from zinc, aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. It is particularly preferable that the element M is one or more elements selected from zinc, aluminum, gallium, yttrium, and tin. Furthermore, the protective layer 231 may contain, for example, indium, zinc, and an element M other than zinc.

[0153] For the protective layer 231, a metal oxide containing indium, gallium, and zinc (In—Ga—Zn oxide, also referred to as IGZO) can be used. Alternatively, an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)) can be used. Alternatively, an oxide containing indium, gallium, tin, and zinc can be used. Alternatively, an oxide containing indium, aluminum, and zinc (also referred to as IAZO) can be used. Alternatively, an oxide containing indium, aluminum, gallium, and zinc (also referred to as IAGZO) can be used.

[0154] Alternatively, the protective layer 231 can have an insulator, specifically an insulator having a barrier property against oxygen. Therefore, the protective layer 231 can be an insulating layer. Examples of insulators having a barrier property against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0155] 14A, 14B, and 14C are enlarged views of region P shown in Fig. 13A. Figures 14A, 14B, and 14C show the lower end portion 232 of the protective layer 231 and the region nearby. Figures 14A, 14B, and 14C show parts of the insulating layer 280, the conductive layer 240_1, the conductive layer 240_2, the semiconductor layer 230, the protective layer 231, the insulating layer 250, the conductive layer 260_1, and the conductive layer 260_2, respectively.

[0156] 14A, 14B, and 14C show an example in which the insulating layer 250 located between the semiconductor layer 230 and the conductive layer 260 has a stacked structure. The stacked structures of the insulating layer 250 differ from one another in FIGS. 14A, 14B, and 14C.

[0157] 14A shows an example in which the insulating layer 250 has a three-layer structure of an insulating layer 250_1, an insulating layer 250_2, and an insulating layer 250_3, which are arranged in this order from the semiconductor layer 230 side. In this case, the insulating layer 250_1 has a region in contact with the region 230i of the semiconductor layer 230 and a region in contact with the protective layer 231.

[0158] The insulating layer 250_1 can be formed using any of the above-described materials applicable to the insulating layer 250. For example, when the insulating layer 250_1 includes an insulating layer having a function of capturing or fixing oxygen, an excess amount of oxygen in the semiconductor layer 230 can be reduced. In addition, an insulating layer having a function of capturing or fixing oxygen may also have a function of capturing or fixing hydrogen, which may reduce the hydrogen concentration in the semiconductor layer 230. Therefore, a highly reliable transistor can be realized.

[0159] Furthermore, a high-k material with a high dielectric constant can be used for the insulating layer 250_1. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulating layer 250_1 makes it possible to reduce the gate voltage applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0160] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium for the insulating layer 250_1, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Aluminum oxide having an amorphous structure is preferably used because an amorphous film can be formed relatively easily using an ALD method. Aluminum oxide has a function of capturing or fixing oxygen and hydrogen, and therefore can be suitably used for the insulating layer 250_1. Alternatively, hafnium oxide has a high function of capturing or fixing oxygen and hydrogen, and therefore can be suitably used for the insulating layer 250_1.

[0161] For example, the insulating layer 250_2 preferably includes a material with a low dielectric constant, such as silicon oxide or silicon oxynitride.

[0162] The insulating layer 250_3 preferably has a barrier property against hydrogen. With such a structure, diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Furthermore, the insulating layer 250_3 preferably has a barrier property against oxygen. The insulating layer 250_3 is provided between the region 230i and the conductive layer 260. With such a structure, diffusion of oxygen contained in the region 230i into the conductive layer 260 can be suppressed. This can suppress, for example, the formation of oxygen vacancies in the region 230i. Furthermore, for example, diffusion of oxygen contained in the insulating layer 250_2 into the conductive layer 260 and oxidation of the conductive layer 260 can be suppressed. The insulating layer 250_3 is preferably at least less permeable to oxygen than the insulating layer 250_2. Furthermore, the insulating layer 250_3 preferably has a function of suppressing diffusion of hydrogen. This can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250_3.

[0163] Here, when a layer that does not contain oxygen as a main component is used as part of the insulating layer 250, it is preferable to perform treatment to supply oxygen to the semiconductor layer 230 before forming the layer. For example, when silicon nitride is used as the insulating layer 250_3, it is preferable to perform the above-described treatment before forming the insulating layer 250_3. It is preferable to perform the above-described treatment, for example, after forming the insulating layer 250_2 and before forming the insulating layer 250_3. As a result, for example, oxidation of the insulating layer 250_3 can be suppressed, which can prevent a decrease in the barrier property against hydrogen. Therefore, a highly reliable semiconductor device can be realized.

[0164] 14B , a structure in which an insulating layer 250_4 is provided between the insulating layer 250_2 and the insulating layer 250_3 may be used. The insulating layer 250_4 can be formed using an insulating material that can be used for the insulating layer 250_1. For example, by providing the insulating layer 250_4 having a function of capturing or fixing hydrogen between the insulating layer 250_2 and the insulating layer 250_3, hydrogen contained in the insulating layer 250_2 or the like can be captured or fixed.

[0165] The treatment for supplying oxygen to the semiconductor layer 230 is preferably performed, for example, after the formation of the insulating layer 250_2 and before the formation of the insulating layer 250_4, because oxygen can be easily supplied to the semiconductor layer 230. Note that the treatment for supplying oxygen to the semiconductor layer 230 may be performed after the formation of the insulating layer 250_4 and before the formation of the insulating layer 250_3.

[0166] Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. With such a structure, hydrogen in the semiconductor layer 230 can be diffused to the insulating layer 250_1 or the insulating layer 250_4 and captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0167] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value) can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0168] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. It is preferable that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0169] Typically, the thicknesses of the insulating layer 250_1, the insulating layer 250_2, the insulating layer 250_4, and the insulating layer 250_3 are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have favorable electrical characteristics even when miniaturized or highly integrated.

[0170] 14C , the insulating layer 250 may have a four-layer structure without the insulating layer 250_3. For example, an insulating layer having a function of capturing or fixing oxygen may be used as the insulating layer 250_1, an insulating layer containing a material with a low dielectric constant may be used as the insulating layer 250_2, and an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 250_4. Specifically, the insulating layer 250 may have a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the semiconductor layer 230 side.

[0171] The insulating layer 250 can have a three-layer structure in which a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. The thicknesses of the hafnium oxide film, the silicon oxide film, and the silicon nitride film are set to 2 nm, 2 nm, and 1 nm, respectively. This structure allows excess oxygen in the semiconductor layer 230 to be discharged to the insulating layer 250, thereby reducing the amount of excess oxygen in the semiconductor layer 230. Furthermore, hydrogen in the semiconductor layer 230 can be captured or fixed. Therefore, the electrical characteristics and reliability of the transistor 200A can be improved.

[0172] In order to thin the insulating layers 250_1 to 250_4 as described above, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method. In addition, in order to form the insulating layers 250_1 to 250_4 inside the opening 290 with good coverage, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method.

[0173] It is preferable to use the ALD process two or more times in forming the insulating layer 250 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, for example, it is possible to increase productivity by successively forming two or more types of insulating films using the ALD process.

[0174] Although the insulating layer 250 has been described above as having a three-layer structure or a four-layer structure, the present invention is not limited to this. The insulating layer 250 can have a structure including at least one of the insulating layers 250_1 to 250_4. By forming the insulating layer 250 using one, two, or three of the insulating layers 250_1 to 250_4, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0175] The configuration of the insulating layer 250 shown in FIGS. 14A to 14C can also be applied to the transistor 200A.

[0176] 10A to 13B of the transistor 200B will be described below. Note that the description will be focused on the differences from the configurations of the transistor 200B shown in FIGS. 10A to 13B, and descriptions of the similar configurations will be omitted as appropriate.

[0177] Fig. 15A is a plan view showing a configuration example of a semiconductor device including a transistor 200B. Fig. 15B is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 15A. Note that Fig. 13A can be referred to for a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 15A.

[0178] 15A and 15B show an example in which, outside the opening 290, the side edge of the protective layer 231 is located inside (on the opening 290 side) relative to the side edge of the semiconductor layer 230. In the example shown in FIGS. 15A and 15B , the side edge of the semiconductor layer 230 and the side edge of the conductive layer 240 do not overlap with the protective layer 231. Note that the side edge of the protective layer 231 may be located outside (on the opposite side from the opening 290) relative to the side edge of the conductive layer 240 and the side edge of the semiconductor layer 230. In this case, the protective layer 231 can be configured to cover the side surface of the conductive layer 240 and the side surface of the semiconductor layer 230.

[0179] The protective layer 231 shown in Figures 15A and 15B can be formed by forming a conductive layer 240 and a semiconductor layer 230, then depositing a protective film that will become the protective layer 231, and removing a portion of the region of the film that is located outside the opening 290.

[0180] 16A is a diagram showing an example in which a protective layer 231a is provided inside the opening 290 shown in Fig. 13A so as to be in contact with the upper surface of the semiconductor layer 230. Fig. 16A shows an example in which the protective layer 231a is in contact with a region 230n of the semiconductor layer 230.

[0181] 13A , protective layer 231a may be formed by depositing a protective film that becomes protective layer 231. Therefore, protective layer 231a has the same material as protective layer 231. Therefore, protective layer 231a has the same barrier properties against oxygen as protective layer 231.

[0182] As described above, the transistor 200B shown in FIG. 16A can suppress oxidation of the low-resistance region 230n compared to the transistor 200B shown in FIG. 13A. This can sometimes suppress the resistance of the region 230n from increasing. Meanwhile, the transistor 200B shown in FIG. 13A can increase the aspect ratio of the opening 290, for example, the width of the opening 290, compared to the transistor 200B shown in FIG. 16A. This reduces the area occupied by the transistor 200B, enabling a highly integrated semiconductor device.

[0183] 16B is a diagram showing an example in which the insulating layer 280 shown in FIG. 13A has a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2. In this case, it is preferable to use a material with a low dielectric constant for the insulating layer 280_2. Furthermore, using oxygen barrier insulating layers for the insulating layers 280_1 and 280_3 is preferable because it can prevent the conductive layers 220a, 220b, and 240 from being oxidized. Specifically, using an oxygen barrier insulating layer for the insulating layer 280_1 can prevent the side surfaces of the conductive layers 220a and 220b from being oxidized. Furthermore, using an oxygen barrier insulating layer for the insulating layer 280_3 can prevent the lower surface of the conductive layer 240_1 from being oxidized. As a result, the conductive layers 220a, 220b, 240_1, and the like can be prevented from increasing in resistance.

[0184] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２O, NO, and NO ２ The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0185] For example, it is preferable to use silicon nitride or aluminum oxide for the insulating layer 280_1 and the insulating layer 280_3, and silicon oxide for the insulating layer 280_2. Here, when an oxide such as silicon oxide is used for the insulating layer 280_2, the insulating layer 280_2 can be referred to as an oxide layer. Note that each of the insulating layer 280_1 and the insulating layer 280_3 may have a stacked structure of two or more layers.

[0186] In one embodiment of the present invention, treatment for supplying oxygen to the semiconductor layer 230 is performed after forming at least part of the layers included in the insulating layer 250. For example, when the insulating layer 250 includes a layer containing silicon oxide (also referred to as a silicon oxide layer), treatment for supplying oxygen to the semiconductor layer 230 is performed after the silicon oxide layer is formed. Therefore, the oxygen concentration of the silicon oxide layer is higher than the oxygen concentration of the oxide layer. For example, when the insulating layer 250_2 shown in FIGS. 14A to 14C is a silicon oxide layer and the insulating layer 280_2 shown in FIG. 16B is an oxide layer, the oxygen concentration of the insulating layer 250_2 is higher than the oxygen concentration of the insulating layer 280_2.

[0187] 16B shows an example in which the height from the reference plane of the lower end 232 of the protective layer 231 is lower than the height from the reference plane of the lower surface of the conductive layer 240. With such a configuration, it is easy to suppress oxidation not only of the lower surface of the conductive layer 240_1 but also of the side surface of the opening 290 of the conductive layer 240_1, for example.

[0188] 16B shows an example in which the height of the lower end 232 from the reference plane is the same as or approximately the same as the height of the lower surface of the insulating layer 280_3 from the reference plane. Note that the height of the lower end 232 from the reference plane may be higher than the height of the lower surface of the insulating layer 280_3 from the reference plane and lower than the height of the lower surface of the conductive layer 240 from the reference plane. Alternatively, the height of the lower end 232 from the reference plane may be higher than the height of the lower surface of the insulating layer 280_2 from the reference plane and lower than the height of the lower surface of the insulating layer 280_3 from the reference plane.

[0189] The configuration of the insulating layer 280 shown in Fig. 16B can also be applied to a semiconductor device including the transistor 200 A. The configuration of the insulating layer 280 shown in Fig. 16B can also be applied to the insulating layer 280 shown in Fig. 15B and the insulating layer 280 shown in Fig. 16A.

[0190] 13A , the protective layer 231 has a different film thickness in a portion where the top surface of the semiconductor layer 230 is to be formed and a portion where the side surface of the semiconductor layer 230 is to be formed. Fig. 17B is an enlarged view of a region Q shown in Fig. 17A. Fig. 17B shows parts of the insulating layer 280, the conductive layer 240_1, the conductive layer 240_2, the semiconductor layer 230, the protective layer 231, the insulating layer 250, the conductive layer 260_1, and the conductive layer 260_2.

[0191] 17B, ​​the film thickness of the portion where the upper surface of the semiconductor layer 230 is to be formed is shown as film thickness T1, and the film thickness of the portion where the side surface of the semiconductor layer 230 is to be formed is shown as film thickness T2.

[0192] 17B also shows the width D of the opening 290. In the example shown in Fig. 17B, the shortest distance between two side surfaces of the opening 290 of the conductive layer 240 in a cross-sectional view is used as the width D. Furthermore, in Fig. 17B, the shortest distance between two side surfaces of the protective layer 231 inside the opening 290 in a cross-sectional view is shown as width Da.

[0193] In this specification and the like, the side surface of the protective layer 231 refers to the surface overlapping the opening 290 and the surface located inside the opening 290, excluding the upper and lower surfaces. The side surface of the protective layer 231 may have a curved surface.

[0194] In the examples shown in FIGS. 17A and 17B , the thickness T2 is thinner than the thickness T1. The ratio of the thickness T2 to the thickness T1, i.e., “T2 / T1,” may be, for example, less than 1, 0.8 or less, or 0.5 or less. The smaller the ratio of the thickness T2 to the thickness T1, i.e., the thinner the thickness T2 is compared to the thickness T1, the more likely it is that the width Da will be prevented from becoming too small relative to the width D. This prevents the conductive layer 260 from filling a portion of the interior of the opening 290, thereby preventing the formation of a cavity. On the other hand, if the thickness T2 is too thin compared to the thickness T1, the oxygen barrier properties of the protective layer 231 may be reduced. In other words, if the thickness T2 is too thin compared to the thickness T1, the oxygen permeability of the protective layer 231 may be higher than when the ratio of the thickness T2 to the thickness T1 is closer to 1. As a result, for example, within the opening 290, a region 230i may be formed in the region of the semiconductor layer 230 that contacts the protective layer 231 and in the vicinity thereof. In view of the above, it is preferable to control the ratio of the thickness T2 to the thickness T1.

[0195] The configuration of the protective layer 231 shown in FIGS. 17A and 17B can also be applied to the protective layer 231 shown in FIGS. 15A to 16B.

[0196] Fig. 18A shows an example in which the side surfaces of the opening 290 in the conductive layer 240 shown in Fig. 17A are tapered. Fig. 18B shows an example in which the side surfaces of the conductive layer 240, the insulating layer 280, and the conductive layer 220c shown in Fig. 17A are tapered.

[0197] By tapering the sidewalls of the opening 290, the coverage of the semiconductor layer 230, the insulating layer 250, etc. can be improved, and defects such as voids can be reduced. When the sidewalls of the opening 290 are tapered, for example, the taper angle (angle θ240) of the side surface of the conductive layer 240 inside the opening 290 and the taper angle (angle θ280) of the side surface of the insulating layer 280 inside the opening 290 are preferably 45 degrees or more and less than 90 degrees. Specifically, an angle of 80 degrees or more and less than 90 degrees is preferable, as this allows for miniaturization or high integration of the semiconductor device. Alternatively, an angle of 45 degrees or more and less than 80 degrees, or 50 degrees or more and less than 75 degrees is preferable, as this improves the coverage of the film formed inside the opening 290. Furthermore, a small angle θ240, for example, less than 80 degrees, allows for a larger width Da. This is preferable because it prevents the conductive layer 260 from filling a portion of the opening 290, thereby preventing the formation of a cavity.

[0198] Also, for example, it is preferable that angle θ240 is smaller than angle θ280. With such a configuration, the coverage of the semiconductor layer 230 and the like on the side surface of the conductive layer 240 inside the opening 290 is improved, and defects such as voids can be reduced. Furthermore, when the insulating layer 280 has a laminated structure, the inclination of the side surface of each layer inside the opening 290 may be different. Similarly, when the conductive layer 240 has a laminated structure, the inclination of the side surface of each layer inside the opening 290 may be different.

[0199] The configuration of the opening 290 shown in Fig. 18A and the configuration of the opening 290 shown in Fig. 18B can also be applied to a semiconductor device including the transistor 200 A. In addition, the configuration of the opening 290 shown in Fig. 18A and the configuration of the opening 290 shown in Fig. 18B can also be applied to the insulating layer 280 shown in Figs. 10A to 16B.

[0200] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0201] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 250, insulating layer 280, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layers included in the semiconductor device.

[0202] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer insulating layer can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0203] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0204] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0205] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of the semiconductor device. As the material capable of exhibiting ferroelectricity, an oxide containing one or both of hafnium and zirconium is preferably used. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, as the material capable of exhibiting ferroelectricity, a material obtained by adding an element J1 (here, the element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to a metal oxide containing one of hafnium and zirconium may be used.

[0206] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, if the amount of the Group 3 element added is too large, the crystallinity of the oxide may decrease, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0207] Furthermore, examples of materials that can have ferroelectricity include metal nitrides containing at least one of element M1 and element M2 and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0208] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Furthermore, examples of materials that can have ferroelectricity include lead titanate (PbTiO ＸPiezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0209] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0210] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described in embodiment 3 can have a layered structure made of a plurality of materials selected from the materials listed above. Incidentally, the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, etc., and therefore, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0211] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0212] The ferroelectric layer preferably contains crystals having an orthorhombic crystal structure, since this allows ferroelectricity to be exhibited. The crystal structure of the crystals contained in the ferroelectric layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure having an amorphous structure and a crystalline structure.

[0213] A metal oxide containing either or both of hafnium and zirconium is also an insulating material capable of capturing or fixing hydrogen. Therefore, by using a metal oxide containing either or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0214] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0215] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Examples of nitrides include aluminum nitride, aluminum titanium nitride, silicon nitride oxide, and silicon nitride. Examples of nitride oxides include silicon nitride oxide. Examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0216] An insulating layer such as a gate insulating layer that is in contact with or near an oxide semiconductor layer preferably has a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with or near an oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0217] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0218] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), hafnium silicate, etc. These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium.

[0219] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0220] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0221] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0222] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, and silicon nitride oxide.

[0223] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0224] [Conductive Layer] The conductive layers (conductive layer 220a, conductive layer 220c, conductive layer 240, conductive layer 260, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0225] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In—Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0226] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0227] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0228] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0229] 19A to 29C , an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that with regard to materials and formation methods of components, descriptions of parts that are similar to those described above may be omitted.

[0230] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed using a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0231] RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used for film formation using a conductive target. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used for forming films of compounds such as oxides, nitrides, and carbides by reactive sputtering.

[0232] CVD methods can be further classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0233] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0234] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0235] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs one or both of the following conditions: a high substrate temperature during film formation and / or an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without these conditions.

[0236] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0237] The CVD and ALD methods differ from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which have a faster film formation rate.

[0238] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0239] Furthermore, in the ALD method, a film of any composition can be formed by using multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0240] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0241] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0242] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0243] Unless otherwise specified, A in Fig. 19 to Fig. 29 shows a plan view. B in Fig. 19 to Fig. 29 shows a cross-sectional view taken along dashed line A1-A2 in Fig. 19 to Fig. 29. C in Fig. 19 to Fig. 29 shows a cross-sectional view taken along dashed line A3-A4 in Fig. 19 to Fig. 29.

[0244] Below, an example of a method for manufacturing a semiconductor device including the transistor 200B shown in FIGS. 12, 13A, and 13B will be described with reference to FIGS. 19A to 26C.

[0245] 19A to 19C , an insulating layer 210 is formed on a substrate (not shown), a conductive layer 220a is formed on the insulating layer 210, a conductive layer 220b is formed on the conductive layer 220a, and a conductive layer 220c is formed on the conductive layer 220b. For example, a conductive film to become the conductive layer 220a, a conductive film to become the conductive layer 220b, and a conductive film to become the conductive layer 220c are formed in this order on the insulating layer 210, and these conductive films are processed to form the conductive layers 220a, 220b, and 220c. Here, it is preferable to process the conductive film to become the conductive layer 220a, the conductive film to become the conductive layer 220b, and the conductive film to become the conductive layer 220c using the same mask, because this reduces the number of masks required to manufacture a semiconductor device.

[0246] The conductive film that becomes the conductive layer 220a can be, for example, a tungsten film. The conductive film that becomes the conductive layer 220b can be, for example, a zirconium film. The conductive film that becomes the conductive layer 220c can be, for example, an ITO film. The conductive film that becomes the conductive layer 220a, the conductive film that becomes the conductive layer 220b, and the conductive film that becomes the conductive layer 220c can each be formed by, for example, a CVD method, a sputtering method, or an ALD method.

[0247] Subsequently, the insulating layer 280 is formed over the conductive layer 220c and the insulating layer 210. The insulating layer 280 can be formed by, for example, a sputtering method, an ALD method, or a CVD method. Note that the insulating layer 280 can be formed by two types of film formation methods.

[0248] Note that after the insulating layer 280 is formed, planarization treatment is preferably performed to planarize the top surface of the insulating layer 280. As the planarization treatment, planarization treatment using chemical mechanical polishing (CMP) (also referred to as CMP treatment) is preferable. Alternatively, planarization treatment using etching (also referred to as etch-back treatment) may be performed. By performing the planarization treatment on the insulating layer 280, the surface on which the conductive layer 240 is to be formed can be flattened, and discontinuity of the conductive layer 240 can be suppressed. Note that the planarization treatment is not necessarily performed, and in that case, manufacturing costs can be reduced.

[0249] The insulating layer 280 can be formed using, for example, silicon oxide. Furthermore, as shown in FIG. 16B , for example, an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2 can be formed as the insulating layer 280. In this case, the insulating layer 280_1 and the insulating layer 280_3 can be formed using, for example, silicon nitride. Furthermore, the insulating layer 280_2 can be formed using, for example, silicon oxide. In this case, for example, the above-described planarization process can be performed after the insulating layer 280_2 is formed, and then the insulating layer 280_3 can be formed.

[0250] 19A to 19C, a conductive film 240f_1 to be the conductive layer 240_1 and a conductive film 240f_2 to be the conductive layer 240_2 are formed in this order over the insulating layer 280. In this way, a conductive film 240f to be the conductive layer 240 is formed.

[0251] The conductive film 240f_1 can be formed using, for example, a tungsten film. The conductive film 240f_2 can be formed using, for example, an ITO film. The conductive films 240f_1 and 240f_2 can each be formed using, for example, a sputtering method, a CVD method, or an ALD method.

[0252] 20A to 20C , an opening 290 is formed in the conductive film 240f_2, the conductive film 240f_1, the insulating layer 280, and the conductive layer 220c at a position overlapping with the conductive layer 220b. The opening 290 is formed to reach the conductive layer 220b. By forming the opening 290 in this manner, the top surface of the conductive layer 220b and the side surface of the conductive layer 220c are exposed.

[0253] To facilitate microfabrication and reduce the size of the transistor, when forming the opening 290, it is preferable to process and remove a portion of the conductive film 240f_2, a portion of the conductive film 240f_1, a portion of the insulating layer 280, and a portion of the conductive layer 220c using anisotropic etching. Dry etching is particularly preferable because it is suitable for microfabrication. The conductive film 240f_2, the conductive film 240f_1, the insulating layer 280, and the conductive layer 220c may be processed under different processing conditions. Depending on the materials and processing conditions of the conductive film 240f_2, the conductive film 240f_1, the insulating layer 280, and the conductive layer 220c, the slopes of the side surfaces of the conductive film 240f_2, the conductive film 240f_1, the insulating layer 280, and the conductive layer 220c in the opening 290 may differ from one another.

[0254] Subsequently, heat treatment is preferably performed at a temperature of, for example, 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower.

[0255] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above-described heat treatment, impurities such as hydrogen or water contained in the insulating layer 280 or the like can be reduced before the formation of the semiconductor layer 230.

[0256] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the insulating layer 280 and the like as much as possible.

[0257] 21A to 21C , a semiconductor film 230f to be the semiconductor layer 230 is formed so as to cover the opening 290. The semiconductor film 230f can be formed to have a region in contact with the top surface of the conductive layer 220b, a region in contact with the side surface of the conductive layer 220c in the opening 290, a region in contact with the side surface of the insulating layer 280 in the opening 290, a region in contact with the side surface of the conductive film 240f_1 in the opening 290, a region in contact with the side surface of the conductive film 240f_2 in the opening 290, and a region in contact with the top surface of the conductive film 240f_2. As the semiconductor film 230f, for example, an indium oxide film is preferably formed.

[0258] The semiconductor film 230f is preferably formed as a film with as uniform a thickness as possible along the sidewall of the opening 290. By forming the film using the ALD method, a thin film can be formed with good controllability. Therefore, it is preferable to form the semiconductor film 230f using the ALD method.

[0259] Furthermore, when the semiconductor film 230f has high crystallinity, diffusion of impurities in the semiconductor film 230f is suppressed, so that the electrical characteristics of the transistor are less likely to fluctuate, and reliability can be improved.

[0260] Next, a heat treatment is preferably performed at a temperature of 100° C. or higher and 650° C. or lower, more preferably 250° C. or higher and 600° C. or lower, and even more preferably 350° C. or higher and 550° C. or lower.

[0261] By performing heat treatment, the material contained in the conductive layer 220b is diffused into the semiconductor film 230f. Therefore, the material contained in the conductive layer 220b can be supplied to the semiconductor film 230f as an impurity element, and some of the elements contained in the semiconductor film 230f can be replaced with the impurity element. For example, when an indium oxide film, specifically a crystalline indium oxide film, is formed as the semiconductor film 230f, some of the indium in the crystal can be replaced with the impurity element. As a result, a region 230n containing the element contained in the conductive layer 220b is formed. For example, when an indium oxide film is formed as the semiconductor film 230f, the region 230n is formed by forming the conductive layer 220b so as to contain an element, such as zirconium, that can become an ion with a different valence from indium ions. The region 230n is formed to overlap with the conductive layer 220b.

[0262] Furthermore, the heat treatment can improve the crystallinity of the semiconductor layer 230. As a result, the on-state current, the S value, the field-effect mobility, the frequency characteristics, and the like of the transistor can be improved, and a semiconductor device with favorable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

[0263] The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0264] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the semiconductor film 230f and the like as much as possible. Note that highly purified gas can also be used for the heat treatment before this step and the heat treatment after this step.

[0265] Furthermore, the heat treatment using oxygen gas as described above can reduce impurities such as carbon, water, and hydrogen in the semiconductor film 230f. Reducing the impurities in the film in this manner can improve the crystallinity of the semiconductor film 230f, resulting in a denser, more compact structure. This increases the crystalline regions in the semiconductor film 230f, reducing in-plane variations in the crystalline regions in the semiconductor film 230f. This reduces in-plane variations in the electrical characteristics of the transistor.

[0266] Next, as shown in FIGS. 22A to 22C , a protective film 231f that will become the protective layer 231 is formed on the semiconductor film 230f. The protective film 231f is formed using a method that provides low coverage, specifically, a method that provides lower coverage than the method used to form the semiconductor film 230f. For example, when forming the semiconductor film 230f using the ALD method, it is preferable to form the protective film 231f using a sputtering method. This causes a step in the protective film 231f due to the step caused by the opening 290. Therefore, the protective film 231f can be formed so that the height of the lower end 232 of the protective film 231f from the reference plane is higher than the height of the upper surface of the conductive layer 220c from the reference plane. This prevents the entire region of the semiconductor film 230f that will become the channel formation region of the transistor 200B from being covered by the protective film 231f. Here, a high aspect ratio of the opening 290 is preferable because it makes it easier for a step to occur in the protective film 231f.

[0267] A film having a barrier property against oxygen is formed as the protective film 231f. The protective film 231f can be, for example, an oxide semiconductor film or an insulating film. When the protective film 231f is an oxide semiconductor film, the protective film 231f can be formed using, for example, IGZO. When the protective film 231f is an insulating film, the protective film 231f can be formed using, for example, silicon nitride.

[0268] Here, the protective film 231f may be formed inside the opening 290 so as to contact the upper surface of the semiconductor film 230f. In this case, the protective layer 231a is formed as shown in FIG. 16A . Even in this case, the protective film 231f is cut off due to the step caused by the opening 290. Therefore, the protective film 231f can be formed so that the height of the lower end 232 of the protective film 231f from the reference plane is higher than the height of the upper surface of the conductive layer 220c from the reference plane.

[0269] 23A to 23C , the protective film 231f, the semiconductor film 230f, the conductive film 240f_2, and the conductive film 240f_1 are processed. As a result, the protective layer 231, the semiconductor layer 230, the conductive layer 240f_2, and the conductive layer 240f_1 are formed, respectively. The protective film 231f, the semiconductor film 230f, the conductive film 240f_2, and the conductive film 240f_1 can be processed using the same mask. This is preferable because it reduces the number of masks required to manufacture a semiconductor device.

[0270] Furthermore, it is preferable to perform a cleaning treatment in order to remove impurities and the like that have adhered to the surface of the semiconductor layer 230 during the above processing. Examples of cleaning methods include wet cleaning using a cleaning solution or the like (which can also be called wet etching), plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate.

[0271] Wet cleaning may be performed using an aqueous solution prepared by diluting one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid with pure water or carbonated water. Wet cleaning may also be performed using pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0272] In this specification, an aqueous solution of hydrofluoric acid diluted with pure water or carbonated water may be referred to as diluted hydrofluoric acid, and an aqueous solution of ammonia water diluted with pure water may be referred to as diluted ammonia water. The concentration or temperature of the aqueous solution may be adjusted appropriately depending on the impurities to be removed, the configuration of the semiconductor device to be cleaned, and other factors. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0273] For ultrasonic cleaning, a frequency of 200 kHz or more is preferably used, and a frequency of 900 kHz or more is more preferably used. By using such a frequency, damage to the semiconductor layer 230 and the like can be reduced.

[0274] The cleaning process may be performed multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0275] 24A to 24C , an insulating layer 250 is formed to cover the conductive layer 240_1, the conductive layer 240_2, the semiconductor layer 230, and the protective layer 231. The insulating layer 250 can be formed to be in contact with the semiconductor layer 230.

[0276] The insulating layer 250 is formed inside the opening 290, which has a large aspect ratio. Therefore, it is preferable to use a film formation method with good coverage for forming the insulating layer 250, such as the ALD method.

[0277] After the insulating layer 250 is formed, a process for supplying oxygen to the semiconductor layer 230 is performed. As a result, a region 230i is formed in the semiconductor layer 230. As described above, by performing the process for supplying oxygen to the semiconductor layer 230 after the insulating layer 250 is formed, it is possible to suppress outward diffusion of oxygen once supplied to the semiconductor layer 230 compared to when the process is performed before the insulating layer 250 is formed. This reduces the hydrogen concentration in the semiconductor layer 230 and oxygen deficiency (V ＯTherefore, a highly reliable semiconductor device can be manufactured.

[0278] The region 230i is formed to include a region of the semiconductor layer 230 in contact with the insulating layer 250. As described above, at least a portion of the region 230i functions as a channel formation region of the transistor 200B. Here, the protective layer 231 has a barrier property against oxygen as described above. Therefore, the region 230i is not formed in at least a portion of the region of the semiconductor layer 230 that is covered with the protective layer 231. As described above, the oxygen concentration in the channel formation region of the transistor 200B is higher than the oxygen concentration in at least a portion of the region of the semiconductor layer 230 that is covered with the protective layer 231.

[0279] As described above, microwave treatment can be used as a treatment for supplying oxygen to the semiconductor layer 230. In this case, the microwave treatment is preferably performed under reduced pressure, and the pressure is preferably from 10 Pa to 1000 Pa, more preferably from 50 Pa to 700 Pa, and even more preferably from 100 Pa to 400 Pa. The treatment temperature is preferably from room temperature (25° C.) to 750° C., more preferably from 300° C. to 500° C., and can be from 400° C. to 450° C.

[0280] When performing microwave treatment, the substrate may be heated to a temperature preferably equal to or higher than room temperature (e.g., 25°C), 100°C, 200°C, 300°C, or 400°C, and 500°C or lower, or 450°C or lower.

[0281] The microwave treatment can be performed using, for example, oxygen gas and argon gas. For example, the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0282] By performing microwave treatment in an atmosphere containing oxygen, oxygen gas is turned into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by turning the oxygen gas into plasma can act on the semiconductor layer 230. By the action of plasma, microwaves, oxygen radicals, or the like, defects in which hydrogen has entered oxygen vacancies in the semiconductor layer 230 (hereinafter referred to as V Ｏ The V contained in the semiconductor layer 230 can be separated into oxygen vacancies and hydrogen, and the hydrogen impurities can be removed from the semiconductor layer 230. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the semiconductor layer 230, the oxygen vacancies in the semiconductor layer 230 can be further reduced.

[0283] Furthermore, by performing microwave treatment after forming the insulating layer 250, the film quality of the insulating layer 250 can be improved, and the diffusion of impurities such as hydrogen and water into the semiconductor layer 230 can be suppressed. This makes it possible to manufacture a highly reliable semiconductor device.

[0284] After the microwave treatment, a heat treatment may be performed successively without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0285] Oxygen supplied into the semiconductor layer 230 can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with an unpaired electron). Note that the oxygen injected into the semiconductor layer 230 is preferably in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0286] 25A to 25C are enlarged views of a region P shown in Fig. 24B and are cross-sectional views illustrating the formation of an insulating layer 250. Fig. 25A to 25C illustrate an example of forming an insulating layer 250 having an insulating layer 250_1, an insulating layer 250_2, and an insulating layer 250_3 as shown in Fig. 14A.

[0287] 25A , an insulating layer 250_1 and an insulating layer 250_2 are formed in this order. The insulating layer 250_1 can be formed to have a region in contact with the semiconductor layer 230 and a region in contact with the protective layer 231. The insulating layer 250_1 can be formed using, for example, aluminum oxide or hafnium oxide. The insulating layer 250_2 can be formed using, for example, silicon oxide.

[0288] Next, a process for supplying oxygen to the semiconductor layer 230, such as microwave treatment, is performed. FIG. 25B is a diagram illustrating this process, showing oxygen (O). As shown in FIG. 25B, oxygen is supplied to the semiconductor layer 230 through the insulating layer 250_2 and the insulating layer 250_1, and a region 230i is formed. On the other hand, since the protective layer 231 has a barrier property against oxygen as described above, oxygen is not supplied to the semiconductor layer 230 through the protective layer 231. That is, as shown in FIG. 25B, oxygen is blocked by the protective layer 231. As a result, oxygen is not supplied to at least a portion of the region of the semiconductor layer 230 covered by the protective layer 231. Note that at least a portion of the oxygen supplied to the insulating layer 250_2 by the above process may accumulate in the insulating layer 250.

[0289] By performing microwave treatment after the formation of the insulating layer 250_2, impurities such as hydrogen and water contained in the insulating layer 250_2 can be prevented from diffusing into the semiconductor layer 230. For example, when a silicon oxide film is formed as the insulating layer 250_2 by an ALD method, hydrogen may be contained in the precursor. In this case, hydrogen, water, and the like may be contained in the insulating layer 250_2. As described above, by performing microwave treatment after the formation of the insulating layer 250_2, impurities such as hydrogen and water can be effectively prevented from being mixed into the semiconductor layer 230. Therefore, a highly reliable semiconductor device can be manufactured.

[0290] After performing a process for supplying oxygen to the semiconductor layer 230, an insulating layer 250_3 is formed as shown in FIG. 25C . The insulating layer 250_3 can be formed using, for example, silicon nitride. In this case, the insulating layer 250_3 does not contain oxygen as a main component. Therefore, if a process for supplying oxygen to the semiconductor layer 230 is performed before the insulating layer 250_3 is formed, oxidation of the insulating layer 250_3 can be prevented. Therefore, for example, a decrease in the barrier property of the insulating layer 250_3 against hydrogen can be suppressed. Therefore, a highly reliable semiconductor device can be manufactured.

[0291] 26A to 26C , a conductive layer 260_1 is formed over the insulating layer 250, and a conductive layer 260_2 is formed over the conductive layer 260_1. The conductive layer 260_2 is preferably formed so as to fill the opening 290. Note that depending on the width of the opening 290, the thickness of the conductive layer 260_1, and the like, the conductive layer 260_2 may not be formed inside the opening 290. That is, the conductive layer 260_1 may be formed so as to fill the opening 290.

[0292] The conductive layer 260_1 is formed inside the opening 290 having a large aspect ratio. The conductive layer 260_2 can be formed inside the opening 290 having a large aspect ratio. For the above reasons, the conductive layer 260_1 and the conductive layer 260_2 are preferably formed by a film formation method with good coverage. For example, a CVD method, an ALD method, or the like is preferably used.

[0293] Through the above steps, a semiconductor device including the transistor 200B illustrated in FIGS. 12, 13A, and 13B can be manufactured.

[0294] The above-described example of a method for manufacturing a semiconductor device including the transistor 200B can also be referred to in manufacturing a semiconductor device including the transistor 200A. Specifically, by not forming the protective film 231f shown in FIGS. 22A to 22C, the above-described example of a method for manufacturing a semiconductor device can also be referred to in manufacturing a semiconductor device including the transistor 200A.

[0295] 9A , an oxide film to be the oxide layer 229 is formed over the conductive film 240f_2 in the steps illustrated in FIGS. 19A to 19C . Subsequently, an opening 290 is formed in the oxide film, and then the opening 290 is formed in the conductive film 240f_2, the conductive film 240f_1, the insulating layer 280, and the conductive layer 220c. After that, the steps illustrated in FIGS. 21A to 22C are performed, and then the oxide film is processed by the steps illustrated in FIGS. 23A to 23C . Through the above steps, the oxide layer 229 illustrated in FIG. 9A is formed. Here, the protective film 231f, the semiconductor film 230f, the oxide film, the conductive film 240f_2, and the conductive film 240f_1 can be processed using the same mask.

[0296] When forming the oxide layer 229 shown in FIG. 9B, the oxide film described above is formed in the steps shown in FIGS. 19A to 19C, and then the oxide film is processed to form the oxide layer 229.

[0297] 27A to 29C , an example of a method for manufacturing a semiconductor device including the transistor 200B shown in FIG. 15A and FIG. 15B will be described. Note that the description will mainly focus on steps different from those in FIG. 19A to FIG. 26C , and descriptions of similar components will be omitted as appropriate.

[0298] 19A to 21C are performed. Subsequently, the semiconductor film 230f, the conductive film 240f_2, and the conductive film 240f_1 are processed. As a result, the semiconductor layer 230, the conductive layer 240_2, and the conductive layer 240_1 are formed, as shown in FIGS. 27A to 27C. For the formation of the semiconductor layer 230, the conductive layer 240_2, and the conductive layer 240_1, refer to the description of FIGS. 23A to 23C.

[0299] 28A to 28C, a protective film 231f is formed on the semiconductor layer 230 and the insulating layer 280. For the formation of the protective film 231f, refer to the description of FIGS. 22A to 22C.

[0300] 29A to 29C, the protective film 231f is processed to form the protective layer 231. For the formation of the protective layer 231, the description of FIGS. 23A to 23C can be referred to.

[0301] 24A to 26C are then performed. Through the above steps, a semiconductor device including the transistor 200B shown in FIGS.

[0302] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0303] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0304] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0305] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0306] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 30A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 30B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0307] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 30B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 30A (see Non-Patent Document 3). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 30A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 30A.

[0308] 30A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0309] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0310] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0311] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0312] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 30A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0313] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0314] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 30B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei is finally achieved, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the transistor may no longer function. On the other hand, in indium oxide, as shown in FIG. 30A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei is finally achieved, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0315] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. The normally-off state can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to the state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of the transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0316] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0317] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0318] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Furthermore, hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0319] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0320] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0321] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0322] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0323] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0324] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can cause a decrease in field-effect mobility. These impurities can also inhibit the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and the like are elements that can be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0325] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0326] In addition, the indium oxide film in this specification and the like has a high film density. ２ O ３ The film densities of the films are shown in Table 1.

[0327]

[0328] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the condition of the base of the indium oxide film, Samples 1 to 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition of the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the formation of the indium oxide film, with Sample 1, Sample 4, and Sample 5 being no heat treatment (as-deposited), Sample 2 being baked at 350°C in a CDA atmosphere, Sample 3 being baked at 650°C in a CDA atmosphere, and Sample 6 being baked at 250°C in a vacuum atmosphere.

[0329] In Table 1, CDA stands for clean dry air. It is preferable that the atmosphere used in the heat treatment (condition 3) after the formation of the indium oxide film contains as little hydrogen, water, and the like as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower, as the atmosphere.

[0330] As shown in Table 1, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment causes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) to be removed from the film, resulting in a higher purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. ３ The theoretical film density of an indium oxide film is 7.18 g / cm ３ In this specification, the range of the film density of the indium oxide film is 6.70 g / cm ３ 7.18g / cm or more ３ Preferably, it is 6.90 g / cm or less. ３ 7.18g / cm or more ３ More preferably, it is 7.00 g / cm or less. ３ 7.18g / cm or more ３ The following is the result.

[0331] The film density can be evaluated by, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated by cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image.

[0332] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0333] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 30C, Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0334] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0335] Furthermore, as shown in FIG. 30C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the film and is released as water molecules. The oxygen and hydrogen diffuse in the indium oxide film by heat treatment. The temperature of the heat treatment is 200° C. or higher and 700° C. or lower, preferably 350° C. or higher and 650° C. or lower, and more preferably 400° C. or higher and 500° C. or lower.

[0336] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0337] Table 2 shows the results of single crystal indium oxide (here, In ２ O ３) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 2, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0338]

[0339] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0340] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L１ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the seed layer.

[0341] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0342] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0343] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0344] Here, a comparison is made among a transistor having a crystalline indium oxide film, a transistor having an IGZO (a compound oxide of In, Ga, and Zn) film, and a transistor having a silicon (Si) film. The comparison is shown in Table 3.

[0345]

[0346] In Table 3, transistors having a crystalline indium oxide film are intended for use in LSIs and are clearly indicated as crystalline IO (LSI). Hereinafter, this may be simply referred to as crystalline IO. Transistors having an IGZO film are intended for use in displays and are clearly indicated as IGZO (Display). Hereinafter, this may be simply referred to as IGZO. Transistors having a Si film are also clearly indicated as Si. In Table 3, ◎ represents +2 points, ○ represents +1 point, △ represents 0 points, and × represents −1 point, respectively. Total is the total value of the ◎, ○, △, and × points shown in Table 3. A higher score indicates better characteristics than a lower score.

[0347] In Table 3, the first comparison item is extremely small off-state current, with crystalline IO and IGZO being superior to Si. The second comparison item is on-state current (Ion) characteristics, with crystalline IO and Si being superior to IGZO. The third comparison item is reliability, with crystalline IO and Si being superior to IGZO. The fourth comparison item is miniaturization of channel length, with crystalline IO and IGZO being superior to Si. In the section on miniaturization of channel length, VFET represents a vertical transistor, UFET represents a transistor with a U-shape structure, and 3D structure represents a three-dimensional structure. The fifth comparison item is cutoff frequency, with the characteristics increasing in the order of crystalline IO, Si, and IGZO. The sixth comparison item is improvement in integration, with Si being superior to crystalline IO and IGZO. The seventh comparison item is threshold voltage controllability (Vth controllability), in which Si is superior to crystalline IO and IGZO. The eighth comparison item is radiation resistance, in which crystalline IO and IGZO are superior to Si. The ninth comparison item is 3D (multi-level) integrated structure, in which crystalline IO and IGZO are superior to Si. The tenth comparison item is the possibility of self-heating, in which crystalline IO and IGZO are superior to Si.

[0348] As shown in Table 3, the total score for crystalline IO (LSI) is 9 points, for IGZO (Display) is 4 points, and for Si is 3 points. As described above, the semiconductor device of one embodiment of the present invention, in particular the semiconductor device including a crystalline indium oxide film, has the potential to replace a semiconductor device using Si.

[0349] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0350] 31A to 33. The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0351] The configuration of a memory device having memory cells will be described with reference to Figures 31A to 32C. Figure 31A is a plan view of a memory device having memory cells 150. Figure 31B is a cross-sectional view taken along dashed line A1-A2 in Figure 31A. Figure 31C is a cross-sectional view taken along dashed line A3-A4 in Figure 31A.

[0352] 31A to 31C includes an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a memory cell 150 on the conductive layer 110, an insulating layer 180 on the conductive layer 110, and an insulating layer 280 on the insulating layer 180. The insulating layer 140 and the insulating layer 180 function as interlayer insulating layers. The conductive layer 110 functions as wiring.

[0353] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 200 over the capacitor 100 .

[0354] The capacitor 100 includes a conductive layer 115 over the conductive layer 110, an insulating layer 130 over the conductive layer 115, and a conductive layer 220a over the insulating layer 130. The conductive layer 220a functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. That is, the capacitor 100 constitutes a metal-insulator-metal (MIM) capacitor. Here, the conductive layer 220a can function as both the upper electrode of the capacitor 100 and one of the source and drain electrodes of the transistor 200. Note that the upper electrode of the capacitor 100 may include a conductive layer 220b. Alternatively, the upper electrode of the capacitor 100 may include a conductive layer 220c.

[0355] As shown in FIGS. 31B and 31C , an opening 190 is provided in the insulating layer 180, reaching the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190. The conductive layer 115 has a region in contact with the top surface of the conductive layer 110 in the opening 190 and a region in contact with the side surface of the insulating layer 180 in the opening 190. At least a portion of the insulating layer 130 is disposed in the opening 190. At least a portion of the conductive layer 220a is disposed in the opening 190. The conductive layer 220a is disposed so as to fill the opening 190. A capacitor 100 having such a configuration may be referred to as a trench capacitor or a trench capacitor. The films disposed in the opening 190 are preferably formed using an ALD method. This improves the film coverage. For example, the conductive layer 115 and the insulating layer 130 are preferably formed using an ALD method.

[0356] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across a dielectric not only on the bottom surface but also on the side surface of the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, it is possible to promote miniaturization or high integration of memory devices.

[0357] 31B and 31C show an example in which the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110 and the opening 190 is circular in plan view. With such a configuration, miniaturization or high integration of the memory device can be achieved.

[0358] The conductive layer 110 functions as wiring CAL, which will be described later, and can be provided in, for example, a strip shape. Note that the strip shape refers to a shape having an area extending in a certain direction (for example, the X direction, the Y direction, or the Z direction).

[0359] The conductive layer 110 can be formed as a single layer or a stacked layer using the conductive material described in [Conductive Layer] in Embodiment 1. For example, a conductive material with high conductivity such as tungsten can be used as the conductive layer 110. By using a conductive material with high conductivity, the conductivity of the conductive layer 110 can be improved, and the conductive layer 110 can function sufficiently as a wiring CAL.

[0360] The conductive layer 115 has a region with rounded corners in the recess of the conductive layer 110. This makes it possible to suppress electric field concentration in the insulating layer 130 near the region, compared to when the region has a corner (right angle or acute angle) in cross-sectional view, for example. Therefore, it is possible to suppress dielectric breakdown of the insulating layer 130 and provide a highly reliable memory device.

[0361] The conductive layer 115 is preferably formed of a single layer or a stacked layer of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. For example, titanium nitride, ITSO, or the like may be used. Alternatively, for example, a structure in which a titanium nitride film is stacked on a tungsten film may be used. Alternatively, for example, a structure in which a tungsten film is stacked on a first titanium nitride film and a second titanium nitride film is stacked on the tungsten film may be used. With such a structure, when an oxide is used for the insulating layer 130, the insulating layer 130 can suppress oxidation of the conductive layer 110. Furthermore, when an oxide is used for the insulating layer 180, the insulating layer 180 can suppress oxidation of the conductive layer 110.

[0362] The insulating layer 130 is provided so as to be in contact with the upper surface and side surfaces of the conductive layer 115. That is, the insulating layer 130 preferably has a structure that covers the end portion of the conductive layer 115. This can prevent a short circuit between the conductive layer 115 and the conductive layer 220a.

[0363] It is preferable to use a high-k material for the insulating layer 130. By using a high-k material for the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current and the capacitance of the capacitor 100 can be sufficiently ensured.

[0364] Furthermore, the insulating layer 130 is preferably formed by stacking insulating layers made of a high-k material, and preferably by using a layered structure of a high-k material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. Using a stack of insulating layers with a relatively high dielectric strength, such as aluminum oxide, improves the dielectric strength and suppresses electrostatic breakdown of the capacitor element 100.

[0365] Furthermore, a material that can have ferroelectricity may be used as the insulating layer 130. For details of the material that can have ferroelectricity, the description in Embodiment 1 can be referred to.

[0366] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor element (hereinafter, sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor element 100, the memory device described in this embodiment functions as a ferroelectric memory.

[0367] The conductive layer 220a is provided in contact with the upper surface of the insulating layer 130. The side edges of the conductive layer 220a can be structured so as to coincide or substantially coincide with the side edges of the insulating layer 130. By using this structure, the conductive layer 220a and the insulating layer 130 can be formed using the same mask, which can simplify the manufacturing process of the memory device. Note that the side edges of the conductive layer 220a may be structured so as to be located inside the side edges of the insulating layer 130 in either the X direction or the Y direction.

[0368] Since the insulating layer 180 functions as an interlayer insulating layer, it is preferable that the insulating layer 180 has a low relative dielectric constant. By using a material with a low relative dielectric constant as the interlayer insulating layer, the parasitic capacitance occurring between wirings can be reduced.

[0369] 31A to 31C illustrate an example in which the transistor 200 has a structure similar to that of the transistor 200A illustrated in FIGS. 2A, 4A, and 4B of Embodiment 1. Note that the transistor 200 may be the transistor 200A or the transistor 200B illustrated in FIGS. 6A and 6B.

[0370] As shown in FIGS. 31A to 31C , the transistor 200 is provided to overlap with the capacitor 100. The opening 290 where part of the transistor 200 is provided overlaps with the opening 190 where part of the capacitor 100 is provided. In particular, the conductive layer 220a functions as one of the source and drain electrodes of the transistor 200 and the upper electrode of the capacitor 100, as described above. Therefore, the transistor 200 and the capacitor 100 share part of their structures. This structure allows the transistor 200 and the capacitor 100 to be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, thereby enabling the memory cells 150 to be densely arranged and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated. FIGS. 31B and 31C show an example in which the width of the opening 190 is smaller than the width of the opening 290. The relationship between the width of the opening 190 and the width of the opening 290 is not particularly limited. From the viewpoint of miniaturization, it is preferable that the width of the opening 190 be equal to or smaller than the width of the opening 290 .

[0371] Furthermore, by providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of the electrical characteristics, can be suppressed.

[0372] 35A shows a circuit diagram of the memory device described in this embodiment. As shown in FIG. 35A, the configurations shown in FIGS. 31A to 31C function as memory cells. The memory cell 951 includes a transistor M1 and a capacitor CA. Here, the transistor M1 corresponds to the transistor 200, and the capacitor CA corresponds to the capacitor 100.

[0373] One of the source and drain of the transistor M1 is connected to one of a pair of electrodes of the capacitor CA. The other of the source and drain of the transistor M1 is connected to a wiring BIL. The gate of the transistor M1 is connected to a wiring WOL. The other of the pair of electrodes of the capacitor CA is connected to a wiring CAL.

[0374] Here, the wiring BIL corresponds to the conductive layer 240, the wiring WOL corresponds to the conductive layer 260, and the wiring CAL corresponds to the conductive layer 110. As shown in FIGS. 31A to 31C , it is preferable that the conductive layer 260 is provided extending in the X direction, and the conductive layer 240 is provided extending in the Y direction. With this configuration, the wiring BIL and the wiring WOL are provided intersecting each other. Also, in FIG. 31A , the wiring CAL (conductive layer 110) is provided parallel to the wiring WOL (conductive layer 260). However, the present invention is not limited to this. The wiring CAL may be provided parallel to the wiring BIL (conductive layer 240), for example.

[0375] The memory cells will be described in detail in a later embodiment.

[0376] The memory cell 150 may have a transistor instead of the capacitor element. In this case, the memory cell 150 has two transistors.

[0377] Fig. 32A1 and Fig. 32A2 are plan views of the memory device. Fig. 32B is a cross-sectional view taken along dashed dotted lines A1-A2 in Fig. 32A1 and Fig. 32A2. Fig. 32C is a cross-sectional view taken along dashed dotted lines A3-A4 in Fig. 32A1 and Fig. 32A2.

[0378] 32A1 to 32C includes a memory cell 150 over an insulating layer 210. The memory cell 150 includes a transistor 200[1] and a transistor 200[2] over the transistor 200[1]. Here, FIG. 32A1 shows a configuration example of the transistor 200[1]. Also, FIG. 32A2 shows a configuration example of the transistor 200[2].

[0379] 32A1 to 32C show an example in which the transistor 200[1] and the transistor 200[2] have the same structure as the transistor 200A shown in FIGS. 2A, 4A, and 4B of Embodiment 1. Note that the transistor 200A shown in FIG. 6A and subsequent figures may be used as the transistor 200[1] and the transistor 200[2], or the transistor 200B may be used. The structure of the transistor 200[1] may be different from the structure of the transistor 200[2].

[0380] 32A1 to 32C, the conductive layer 220a, the conductive layer 220b, the conductive layer 220c, the conductive layer 240, the semiconductor layer 230, and the insulating layer 250 of the transistor 200[1] are shown as the conductive layer 220a[1], the conductive layer 220b[1], the conductive layer 220c[1], the conductive layer 240[1], the semiconductor layer 230[1], and the insulating layer 250[1], respectively. In addition, the conductive layer 220a, the conductive layer 220b, the conductive layer 220c, the conductive layer 240, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 included in the transistor 200[2] are shown as the conductive layer 220a[2], the conductive layer 220b[2], the conductive layer 220c[2], the conductive layer 240[2], the semiconductor layer 230[2], the insulating layer 250[2], and the conductive layer 260[2], respectively.

[0381] The region 230n included in the semiconductor layer 230[1] and the region 230n included in the semiconductor layer 230[2] are shown as region 230n[1] and region 230n[2], respectively. The insulating layer 280 provided between the conductive layer 220c[1] and the conductive layer 240[1] and the insulating layer 280 provided between the conductive layer 220c[2] and the conductive layer 240[2] are shown as insulating layer 280[1] and insulating layer 280[2], respectively. The opening 290 provided in the conductive layer 220c[1], the insulating layer 280[1], and the conductive layer 240[1] is shown as opening 290[1]. Furthermore, an opening 290 provided in the conductive layer 220c[2], the insulating layer 280[2], and the conductive layer 240[2] is shown as an opening 290[2].

[0382] 32A1 to 32C , the transistor 200[1] includes a conductive layer 260_1[1] and a conductive layer 220a[2] over the conductive layer 260_1[1] as a gate electrode. The conductive layer 260[2] functioning as the gate electrode of the transistor 200[2] includes a conductive layer 260_1[2] and a conductive layer 260_2 over the conductive layer 260_1[2]. The description of the conductive layer 260_1 in Embodiment 1 can be referred to for the structures of the conductive layer 260_1[1] and the conductive layer 260_1[2]. The conductive layer 220b[2] may be included in the gate electrode of the transistor 200[1], and the conductive layer 220c[2] may be included in the gate electrode of the transistor 200[1]. The conductive layer 260_1[1] may be included in one of the source electrode and the drain electrode of the transistor 200[2]. Furthermore, the conductive layer 260_1[1] does not necessarily have to be provided between the insulating layer 250[1] and the conductive layer 220a[2].

[0383] In the memory cell 150 shown in Figures 32A1 to 32C, the capacitance generated between the conductive layer 240[1] and the conductive layer 260_1[1] can be used, so that data can be retained without forming a separate capacitor.

[0384] As shown in FIGS. 32A1 to 32B , the transistor 200[2] is provided to overlap with the transistor 200[1]. The opening 290[2] has a region overlapping with the opening 290[1]. In particular, the conductive layer 220a[2] functions as one of the source electrode and drain electrode of the transistor 200[2] and the gate electrode of the transistor 200[1]. Therefore, the transistors 200[2] and 200[1] share part of their structures. This structure allows the transistors 200[2] and 200[1] to be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, thereby enabling the memory cells 150 to be arranged at high density and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0385] 35E shows a circuit diagram of the memory device described in this embodiment. As shown in FIG. 35E, the configurations shown in FIGS. 32A1 to 32C function as memory cells. The memory cell 955 includes a transistor M2 and a transistor M3. Here, the transistor M2 corresponds to the transistor 200[2], and the transistor M3 corresponds to the transistor 200[1].

[0386] One of the source and drain of transistor M2 is connected to the gate of transistor M3. The other of the source and drain of transistor M1 is connected to wiring WBL. The gate of transistor M2 is connected to wiring WOL. One of the source and drain of transistor M3 is connected to wiring RBL. The other of the source and drain of transistor M3 is connected to wiring SL.

[0387] Here, the wiring WBL corresponds to the conductive layer 240 of the transistor 200[2], and the wiring WOL corresponds to the conductive layer 260. As shown in Figures 32A1 to 32C, it is preferable that the conductive layer 260 is provided to extend in the X direction, and the conductive layer 240 of the transistor 200[2] is provided to extend in the Y direction. With this configuration, the wiring WBL and the wiring WOL are provided to intersect with each other.

[0388] The memory cell 150 described in this embodiment can be used as a memory cell of a storage device. The transistor 200 is an OS transistor. Because the off-state current of the transistor 200 is small, the use of the transistor 200 in a storage device allows stored data to be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced. Furthermore, the high frequency characteristics of the transistor 200 enable high-speed reading and writing of data from and to the storage device.

[0389] A memory cell array can be configured by arranging the memory cells 150 in a three-dimensional matrix. By stacking layers (also called memory layers) each having a plurality of memory cells, the cells can be integrated and arranged without increasing the area occupied by the memory cell array. In other words, a 3D memory cell array can be configured.

[0390] FIG. 33 shows an example of a cross-sectional configuration of a memory device in which a memory layer is stacked on a layer in which a driver circuit including a sense amplifier is provided.

[0391] 33, a memory cell 150 is provided above a transistor 300. The transistor 300 is one of the transistors included in the sense amplifier. For the memory cell 150 shown in FIG. 33, the description of the memory cell 150 described above can be referred to.

[0392] 33, the bit lines can be shortened by providing a sense amplifier so as to overlap the memory cells 150. This reduces the bit line capacitance, enabling the memory device to be driven at high speed.

[0393] 33 can correspond to the semiconductor device 900 described in Embodiment 4. Specifically, the transistor 300 corresponds to a transistor included in a sense amplifier 927 in the semiconductor device 900. The memory cell 150 corresponds to a memory cell 950.

[0394] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel or n-channel transistor. The substrate 311 preferably contains a silicon-based semiconductor, specifically, single-crystal silicon.

[0395] Alternatively, the substrate 311 may be a structure in which a single-crystal oxide semiconductor film (typically, an indium oxide film) is provided on a stabilized zirconia substrate. The indium oxide film formed on the stabilized zirconia substrate has single crystallinity. By using a part of the indium oxide film as the semiconductor region 313, the field-effect mobility of the transistor 300 can be increased. Furthermore, the reliability of the transistor 300 can be improved.

[0396] Here, in the transistor 300 shown in FIG. 33 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0397] Between each structure, a wiring layer provided with an interlayer insulating layer, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer functioning as a plug or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0398] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer insulating layer over the transistor 300. A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as plugs or wirings.

[0399] The insulating layer functioning as an interlayer insulating layer may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0400] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in Fig. 33, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0401] The insulating layer 352, the insulating layer 354, and the like which function as interlayer insulating layers can be formed using the above-described insulating layer which can be used in a semiconductor device or a memory device.

[0402] Conductive layers functioning as plugs or wirings, such as the conductive layer 328, the conductive layer 330, and the conductive layer 356, can be formed using a conductive material applicable to the conductive layer 240. A high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity is preferably used, and tungsten is preferred. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

[0403] The conductive layer 240 of the transistor 200 is connected to the low-resistance region 314b through the conductive layer 384, the conductive layer 383c, the conductive layer 383b, the conductive layer 383a, the conductive layer 382, ​​the conductive layer 381, the conductive layer 371, the conductive layer 356, the conductive layer 330, and the conductive layer 328.

[0404] The insulating layer 372 is located over the conductive layer 356 and the insulating layer 354. The insulating layer 372 has an opening 391 that reaches the conductive layer 356, and the conductive layer 371 is provided to fill the opening 391. The conductive layer 381 is located over the conductive layer 371 and the insulating layer 372. The insulating layer 180 is located over the conductive layer 110, the conductive layer 381, and the insulating layer 372. The insulating layer 180 has an opening 392 that reaches the conductive layer 381, and the conductive layer 382 is provided to fill the opening 392. The conductive layer 383a is located over the conductive layer 382 and the insulating layer 180. The conductive layer 383b is located over the conductive layer 383a. The conductive layer 383c is located over the conductive layer 383b. Here, the conductive layers 383a, 383b, and 383c are collectively referred to as the conductive layer 383.

[0405] The insulating layer 280 is located over the conductive layer 220c, the conductive layer 383c, and the insulating layer 180. The conductive layer 383b, the conductive layer 383c, and the insulating layer 280 have an opening 394 that reaches the conductive layer 383a, and the conductive layer 384 is provided to fill the opening 394. The conductive layer 240 is located over the conductive layer 384 and the insulating layer 280.

[0406] The conductive layer 381 can be manufactured using the same material and in the same process as the conductive layer 110. The conductive layers 383a, 383b, and 383c can be manufactured using the same material and in the same process as the conductive layers 220a, 220b, and 220c, respectively.

[0407] By providing the openings 394 not only in the insulating layer 280 but also in the conductive layers 383c and 383b, the conductive layer 384 can be in contact with the conductive layer 383a. The electrical conductivity of the conductive layer 383a can be higher than that of the conductive layers 383b and 383c. As a result, the contact resistance between the conductive layer 383 and the conductive layer 384 can be lower than when the openings 394 are not provided in the conductive layer 383b, for example. Furthermore, by providing the openings 394 in the conductive layers 383c and 383b, the conductive layer 384 can be in contact with the side surfaces of the conductive layers 383b and 383c at the openings 394. This allows the contact area between the conductive layer 383 and the conductive layer 384 to be larger than when the openings 394 are not provided in the conductive layers 383b and 383c, for example. As a result, a semiconductor device with high operating speed can be realized.

[0408] 33, an insulating layer 283 is provided over the conductive layer 260 and the insulating layer 250. In addition, an insulating layer 285 is provided over the insulating layer 283.

[0409] The insulating layer 283 is preferably the barrier insulating layer against hydrogen described in Embodiment 1. This can suppress diffusion of hydrogen from above the transistor 200 to the semiconductor layer 230. The insulating layer 283 can be formed using, for example, silicon nitride.

[0410] The insulating layer 285 functions as an interlayer insulating layer. Therefore, the insulating layer 285 is preferably formed using the material with a low relative dielectric constant described in Embodiment 1. The insulating layer 285 can be formed using, for example, silicon oxide.

[0411] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0412] Embodiment 4 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0413] Fig. 34 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 34 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 34 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0414] The memory cell 950 can be any of the memory devices (memory cell 150 and the like) described in Embodiment 3.

[0415] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0416] In the semiconductor device 900, the circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. The signals BW, CE, GW, clock signal CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside.

[0417] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0418] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0419] The voltage generation circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the clock signal CLK to the voltage generation circuit 928. For example, when an H-level signal is given as the signal WAKE, the clock signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0420] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0421] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0422] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0423] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭis the high power supply potential used to drive the word line high, and V ＤＤ 34, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it may be set to a plurality of power domains. In this case, a power switch can be provided for each power domain.

[0424] 35A to 35H, examples of other memory cell configurations that can be applied to the memory cell 950 will be described.

[0425] 35A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). A memory cell 951 includes a transistor M1 and a capacitor CA.

[0426] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0427] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0428] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0429] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0430] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, a configuration in which one wiring BIL is provided in common for two or more memory cells may be used. Alternatively, for example, the configuration of the memory cell 952 shown in FIG. 35B may be used. The memory cell 952 is an example in which the memory cell 952 does not include the capacitor element CA and the wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0431] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0432] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, because the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0433] 35C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a memory device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0434] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0435] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0436] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0437] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0438] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 35D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0439] 35E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 35F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0440] Note that it is preferable to use an OS transistor for at least the transistor M2. In particular, it is preferable to use OS transistors for the transistors M2 and M3. By using an OS transistor as the transistor M2, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cells 953 to 956.

[0441] The memory cells 953 to 956 in which an OS transistor is used as the transistor M2 are one embodiment of NOSRAM.

[0442] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0443] 35G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitative element CC.

[0444] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0445] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0446] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0447] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0448] Note that at least the transistor M4 is preferably an OS transistor.

[0449] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0450] [OS-SRAM] FIG. 35H shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 35H is a memory cell of an SRAM capable of backing up data.

[0451] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0452] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0453] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0454] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0455] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0456] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0457] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0458] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0459] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. After that, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0460] Data is read by precharging the wirings BIL and BILB to a predetermined potential in advance, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. The potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. The potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1, respectively. Therefore, the potential held in the memory cell can be read from the potential of the wiring BIL or BILB.

[0461] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells or eliminates the need for refreshing the memory cells.

[0462] Note that Si transistors may be used as the transistors MS1 to MS4.

[0463] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 36A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 36B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0464] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0465] 37 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 37 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0466] The arithmetic device 960 shown in FIG. 37 has an ALU 962 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 969 and the cache interface 969i may also be provided on separate chips.

[0467] The cache 969 is connected to a main memory provided on a separate chip via a cache interface 969i. The cache interface 969i has a function of supplying part of the data held in the main memory to the cache 969. The cache interface 969i also has a function of outputting part of the data held in the cache 969 to the ALU 962, register 966, etc. via the bus interface 968.

[0468] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have a function of supplying data held in the memory array 920 to the cache 969. In this case, it is preferable that a drive circuit 910 be provided as part of the cache interface 969i.

[0469] It is also possible to use only the memory array 920 as a cache without providing the cache 969 .

[0470] The arithmetic device 960 shown in FIG. 37 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 37 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0471] An instruction input to the arithmetic unit 960 via the bus interface 968 is input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, the interrupt controller 964, the register controller 967, and the timing controller 965.

[0472] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals for controlling the operation of the ALU 962. Furthermore, the interrupt controller 964 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 967 generates an address for the register 966 and reads and writes data from and to the register 966 depending on the state of the arithmetic unit 960.

[0473] Furthermore, the timing controller 965 generates signals that control the timing of the operations of the ALU 962, the ALU controller 962c, the instruction decoder 963, the interrupt controller 964, and the register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0474] 37, the register controller 967 selects the holding operation of the register 966 in accordance with an instruction from the ALU 962. That is, it selects whether the memory cells of the register 966 will hold data using flip-flops or using capacitors. If holding data using flip-flops is selected, a power supply potential is supplied to the memory cells in the register 966. If holding data using capacitors is selected, the data is rewritten to the capacitors, and the supply of power supply potential to the memory cells in the register 966 can be stopped.

[0475] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 38A and 38B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 38B.

[0476] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0477] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also referred to as monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (Cu-Cu bonding, etc.) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0478] Here, the arithmetic unit 960 does not have a cache 969, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0479] When the cache 969 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0480] 38B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0481] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0482] When the memory array 920L1 is used as a cache, the driver 910L1 may function as part of the cache interface 969i, or may be configured to be connected to the cache interface 969i. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 969i, or may be configured to be connected thereto.

[0483] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0484] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0485] Also, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 39A shows a perspective view of a semiconductor device 970B.

[0486] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Figure 39A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0487] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0488] Also, multiple memory arrays may be stacked. Figure 39B shows a perspective view of a semiconductor device 970C.

[0489] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0490] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0491] Embodiment 5 In this embodiment, a structural example of a semiconductor device including a Si transistor and an OS transistor according to one embodiment of the present invention, specifically a CMOS circuit structure example, will be described.

[0492] Si transistors have higher field-effect mobility and faster operation speed than OS transistors. Furthermore, OS transistors have significantly lower off-state current than Si transistors. In particular, OS transistors that use indium oxide for the semiconductor layer in which a channel is formed have significantly lower off-state current and higher field-effect mobility comparable to that of Si transistors. By using an OS transistor and a Si transistor in combination, a CMOS circuit that consumes less power and operates at high speed can be realized.

[0493] In this embodiment, examples of circuits using Si transistors and OS transistors will be described, including a NOT circuit, a NOR circuit, and a NAND circuit, which are logic circuits. Also, examples of delay flip-flop (DFF) circuits and a shift register circuit using the DFF circuits will be described.

[0494] [NOT Circuit] Fig. 40A is a circuit diagram showing an example configuration of a NOT circuit (NOT). A NOT circuit is also called an inversion circuit, an inverter circuit, etc. Fig. 40B shows the circuit symbol for a NOT circuit. Fig. 40C is a timing chart explaining the operation of the NOT circuit.

[0495] The NOT circuit shown in FIG. 40A includes transistors Tr11 and Tr12. The transistor Tr11 is a Si transistor functioning as a p-type transistor, and the transistor Tr12 is an OS transistor functioning as an n-type transistor. A potential H (e.g., a high power supply potential VDD) is supplied to one of the source and the drain of the transistor Tr11. The other of the source and the drain of the transistor Tr11 is connected to one of the source and the drain of the transistor Tr12 and to a terminal Y. A potential L (e.g., a low power supply potential VSS) is supplied to the other of the source and the drain of the transistor Tr12. The gates of the transistors Tr11 and Tr12 are connected to a terminal A.

[0496] 40A, the terminal A functions as an input terminal, and the terminal Y functions as an output terminal. When a potential H is input to the terminal A of the NOT circuit, the terminal Y outputs a potential L, and when a potential L is input to the terminal A, the terminal Y outputs a potential H (see FIG. 40C).

[0497] 40C, the NOT circuit has a function of correcting an input signal distorted by wiring resistance, parasitic capacitance, noise, etc., to a signal that is distorted or has reduced distortion, and outputting the corrected signal. The NOT circuit also has a function of amplifying the voltage amplitude of the input signal, and the output of the NOT circuit is supplied to a load such as a capacitance element Cx and a transistor Trx.

[0498] An example of the structure of a NOT circuit will now be described with reference to Fig. 41. As shown in Fig. 41, a transistor Tr12 is provided above a transistor Tr11.

[0499] The transistor Tr11 is a modified example of the transistor 300 shown in Fig. 33 and has a so-called planar configuration. The same components of the transistor Tr11 as those of the transistor 300 shown in Fig. 33 are denoted by the same reference numerals. For details of the transistor Tr11, the description of the transistor 300 can be referred to.

[0500] 41 illustrates an example in which the transistor Tr12 has a configuration similar to that of the transistor 200A illustrated in FIGS. 2A, 4A, and 4B of Embodiment 1. Note that the transistor Tr12 may be the transistor 200A or the transistor 200B illustrated in FIGS. 6A and subsequent drawings.

[0501] 41 , an insulating layer 320 is provided on an insulating layer 315 that functions as a gate insulating layer for a transistor Tr11. A conductive layer 316 that functions as a gate electrode for the transistor Tr11 is provided so as to fill an opening provided in the insulating layer 320. An insulating layer 210 is provided on the conductive layer 316 and the insulating layer 320. A transistor Tr12 is provided on the insulating layer 210.

[0502] 41 , an insulating layer 283 is provided over the conductive layer 260 included in the transistor Tr12 and over the insulating layer 250. An insulating layer 285 is provided over the insulating layer 283, and a wiring layer 287 is provided over the insulating layer 285. An insulating layer 289 is provided over the wiring layer 287, and conductive layers 248a, 248b, 248c, and 248d functioning as wirings are provided so as to fill openings in the insulating layer 289.

[0503] The insulating layer 289 functions as an interlayer insulating layer. Therefore, the insulating layer 289 is preferably formed using the material with a low relative dielectric constant described in Embodiment 1. The insulating layer 289 can be formed using the material that can be used for the insulating layer 285.

[0504] The conductive layer 248a is connected to the low-resistance region 314a via the conductive layer 448a, the conductive layer 421c, the conductive layer 421b, the conductive layer 421a, and the conductive layer 331a. The conductive layer 248b is connected to the conductive layer 220a, the conductive layer 220b, and the conductive layer 220c via the conductive layer 448b. The conductive layer 248c is connected to the conductive layer 240 via the conductive layer 448c. The conductive layer 248d is connected to the conductive layer 316 via the conductive layer 448d, the conductive layer 422c, the conductive layer 422b, the conductive layer 422a, and the conductive layer 331c, and is connected to the conductive layer 260 via the conductive layer 448e.

[0505] The insulating layer 315, the insulating layer 320, and the insulating layer 210 each have an opening that reaches the low-resistance region 314a and an opening that reaches the low-resistance region 314b. A conductive layer 331a is provided to fill the opening that reaches the low-resistance region 314a, and a conductive layer 331b is provided to fill the opening that reaches the low-resistance region 314b. The insulating layer 210 also has an opening that reaches the conductive layer 316, and a conductive layer 331c is provided to fill the opening.

[0506] The conductive layer 220a is located over the conductive layer 331b and the insulating layer 210. The conductive layer 421a is located over the conductive layer 331a and the insulating layer 210. The conductive layer 422a is located over the conductive layer 331c and the insulating layer 210.

[0507] The conductive layer 421b is located over the conductive layer 421a. The conductive layer 422b is located over the conductive layer 422a. The conductive layer 421c is located over the conductive layer 421b. The conductive layer 422c is located over the conductive layer 422b. The conductive layers 421a and 422a can be formed using the same material and in the same process as the conductive layer 220a. The conductive layers 421b and 422b can be formed using the same material and in the same process as the conductive layer 220b. The conductive layers 421c and 422c can be formed using the same material and in the same process as the conductive layer 220c.

[0508] The conductive layer 421b, the conductive layer 421c, the insulating layer 280, the insulating layer 250, the insulating layer 283, and the insulating layer 285 have openings that reach the conductive layer 421a, and a conductive layer 448a is provided to fill the openings. The conductive layer 220b, the conductive layer 220c, the insulating layer 280, the insulating layer 250, the insulating layer 283, and the insulating layer 285 have openings that reach the conductive layer 220a, and a conductive layer 448b is provided to fill the openings. The conductive layer 240_2, the semiconductor layer 230, the insulating layer 250, the insulating layer 283, and the insulating layer 285 have openings that reach the conductive layer 240_1, and a conductive layer 448c is provided to fill the openings. The conductive layer 422b, the conductive layer 422c, the insulating layer 280, the insulating layer 250, the insulating layer 283, and the insulating layer 285 have openings that reach the conductive layer 422a, and a conductive layer 448d is provided to fill the openings. The insulating layer 283 and the insulating layer 285 have openings that reach the conductive layer 260_2, and a conductive layer 448e is provided to fill the openings.

[0509] A conductive layer 248a is provided over the conductive layer 448a and the insulating layer 285. A conductive layer 248b is provided over the conductive layer 448b and the insulating layer 285. A conductive layer 248c is provided over the conductive layer 448c and the insulating layer 285. A conductive layer 248d is provided over the conductive layer 448d, the conductive layer 448e, and the insulating layer 285.

[0510] A potential H is supplied to the conductive layer 248a. The conductive layer 248b functions as a terminal Y. A potential L is supplied to the conductive layer 248c. The conductive layer 248d functions as a terminal A.

[0511] By configuring a NOT-type circuit in which all transistors Tr11 formed on the substrate 311 are p-type transistors and all transistors Tr12 formed above them are n-type transistors, it is possible to simplify complex processes such as the formation of element isolation layers, and to improve the productivity of semiconductor devices including the circuit.

[0512] [NOR Circuit] Fig. 42A is a circuit diagram showing a configuration example of a two-input, one-output NOR circuit (NOR). Fig. 42B shows a circuit symbol for the NOR circuit. The NOR circuit shown in Fig. 42A includes transistors Tr21, Tr22, Tr23, and Tr24. Si transistors functioning as p-channel transistors are used as the transistors Tr21 and Tr22, and OS transistors functioning as n-channel transistors are used as the transistors Tr23 and Tr24.

[0513] 42A , a potential H is supplied to one of the source and drain of transistor Tr21. The other of the source and drain of transistor Tr21 is connected to one of the source and drain of transistor Tr22. The other of the source and drain of transistor Tr22 is connected to one of the source and drain of transistor Tr23, one of the source and drain of transistor Tr24, and terminal Y. A potential L is supplied to the other of the source and drain of transistor Tr23 and the other of the source and drain of transistor Tr24.

[0514] The gate of the transistor Tr21 is connected to the gate of the transistor Tr23 and the terminal A. The gate of the transistor Tr22 is connected to the gate of the transistor Tr24 and the terminal B.

[0515] 42A and 42B has a function of outputting a potential H from a terminal Y when a potential L is input to both a terminal A and a terminal B. In addition, the NOR circuit has a function of outputting a potential L from a terminal Y when a potential H is input to one or both of the terminals A and B.

[0516] Furthermore, as shown in FIG. 42C, an OR circuit can be realized by connecting the input of a NOT circuit to the output of a NOR circuit.

[0517] [NAND Circuit] Fig. 42D is a circuit diagram showing a configuration example of a two-input, one-output NAND circuit (NAND). Fig. 42E shows a circuit symbol of the NAND circuit. The NAND circuit shown in Fig. 42D includes transistors Tr31, Tr32, Tr33, and Tr34. Si transistors functioning as p-channel transistors are used for the transistors Tr31 and Tr32, and OS transistors functioning as n-channel transistors are used for the transistors Tr33 and Tr34.

[0518] 42D, a potential H is supplied to one of the source and drain of transistor Tr31 and one of the source and drain of transistor Tr32. The other of the source and drain of transistor Tr31 and the other of the source and drain of transistor Tr32 are connected to one of the source and drain of transistor Tr33 and terminal Y. The other of the source and drain of transistor Tr33 is connected to one of the source and drain of transistor Tr34. A potential L is supplied to the other of the source and drain of transistor Tr34.

[0519] The gate of the transistor Tr31 is connected to the gate of the transistor Tr34 and the terminal B. The gate of the transistor Tr32 is connected to the gate of the transistor Tr33 and the terminal A.

[0520] 42D and 42E has a function of outputting a potential L from a terminal Y when a potential H is input to both a terminal A and a terminal B. In addition, the NAND circuit has a function of outputting a potential H from a terminal Y when a potential L is input to one or both of the terminals A and B.

[0521] Furthermore, as shown in FIG. 42F, an AND circuit can be realized by combining a NAND circuit with a NOT circuit.

[0522] [DFF Circuit] Fig. 43A is a circuit diagram showing an example of the configuration of a D flip-flop circuit (DFF). Fig. 43B shows the circuit symbol of the D flip-flop circuit. The DFF has a clock signal input terminal CK, an input terminal D, and an output terminal Q.

[0523] 43A includes transistors Tr41 to Tr49, transistors Tr51 to Tr59, transistor Tr61, transistor Tr62, transistor Tr71, and transistor Tr72. Si transistors functioning as p-channel transistors are used as the transistors Tr41 to Tr49, transistors Tr61, and transistor Tr62, and OS transistors functioning as n-channel transistors are used as the transistors Tr51 to Tr59, transistors Tr71, and transistor Tr72.

[0524] A potential H is supplied to one of the source and drain of transistor Tr41, one of the source and drain of transistor Tr42, one of the source and drain of transistor Tr44, one of the source and drain of transistor Tr46, one of the source and drain of transistor Tr48, one of the source and drain of transistor Tr61, and one of the source and drain of transistor Tr62.

[0525] The other of the source and drain of transistor Tr41 is connected to one of the source and drain of transistor Tr51, the gate of transistor Tr44, the gate of transistor Tr46, the gate of transistor Tr53, and the gate of transistor Tr59. The gate of transistor Tr41 is connected to clock signal input terminal CK, the gate of transistor Tr51, the gate of transistor Tr42, the gate of transistor Tr48, the gate of transistor Tr55, and the gate of transistor Tr57.

[0526] The other of the source and drain of transistor Tr42 is connected to one of the source and drain of transistor Tr43. The other of the source and drain of transistor Tr44 is connected to one of the source and drain of transistor Tr45. The other of the source and drain of transistor Tr43 is connected to the other of the source and drain of transistor Tr45, one of the source and drain of transistor Tr52, one of the source and drain of transistor Tr54, the gate of transistor Tr61, and the gate of transistor Tr71. The gate of transistor Tr43 is connected to the gate of transistor Tr52 and input terminal D.

[0527] The other of the source and drain of transistor Tr52 is connected to one of the source and drain of transistor Tr53. The other of the source and drain of transistor Tr54 is connected to one of the source and drain of transistor Tr55. The gate of transistor Tr45 is connected to the gate of transistor Tr54, the other of the source and drain of transistor Tr61, one of the source and drain of transistor Tr71, the gate of transistor Tr47, and the gate of transistor Tr56. The other of the source and drain of transistor Tr46 is connected to one of the source and drain of transistor Tr47. The other of the source and drain of transistor Tr48 is connected to one of the source and drain of transistor Tr49.

[0528] The other of the source and drain of transistor Tr47 is connected to one of the source and drain of transistor Tr56, the other of the source and drain of transistor Tr49, one of the source and drain of transistor Tr58, the gate of transistor Tr62, and the gate of transistor Tr72. The other of the source and drain of transistor Tr62 is connected to one of the source and drain of transistor Tr72, the gate of transistor Tr49, the gate of transistor Tr58, and output terminal Q.

[0529] The other of the source and drain of transistor Tr56 is connected to one of the source and drain of transistor Tr57. The other of the source and drain of transistor Tr58 is connected to one of the source and drain of transistor Tr59. A potential L is supplied to the other of the source and drain of transistor Tr51, the other of the source and drain of transistor Tr53, the other of the source and drain of transistor Tr55, the other of the source and drain of transistor Tr71, the other of the source and drain of transistor Tr57, the other of the source and drain of transistor Tr59, and the other of the source and drain of transistor Tr72.

[0530] 43A and 43B has a function in which, while a potential H is being input to the clock signal input terminal CK, information (potential) supplied to the input terminal D is written to the DFF, and when the signal input to the clock signal input terminal CK changes from potential H to potential L, the information is held until the next time a potential H is input to the clock signal input terminal CK. In addition, a signal (potential H or potential L) based on the information held by the DFF is always output from the output terminal Q.

[0531] FIG. 44A is a block diagram showing an example configuration of a shift register circuit (SR). The SR includes multiple DFFs. In this specification, the first-stage (first) DFF is referred to as "DFF[1]," and the potential (data) output from the output terminal Q of DFF[1] is referred to as "DATA OUT[1]." FIG. 44A shows a block diagram of an SR including four stages (four) of DFFs (DFF[1] to DFF[4]). In FIG. 44A, the data output from the output terminals Q of DFF[1] to DFF[4] are referred to as DATA OUT[1] to DATA OUT[4].

[0532] 44B is a timing chart illustrating the operation of the SR. The clock signal CLK is input to the clock signal input terminal CK of the odd-numbered DFF. The inverted signal of the clock signal CLK is input to the clock signal input terminal CK of the even-numbered DFF.

[0533] A pulse signal SPL is input to the input terminal D of DFF[1]. DFF[1] holds a signal corresponding to the input signal SPL in synchronization with the clock signal CLK and outputs it as data OUT[1]. Note that data OUT[1] has a value corresponding to the data held by DFF[1].

[0534] Furthermore, data OUT[1] is input to input terminal D of DFF[2]. DFF[2] holds a signal corresponding to the input data OUT[1] in synchronization with clock signal CLK and outputs it as data OUT[2]. Similarly, data OUT[2] is input to input terminal D of DFF[3], and data OUT[3] is input to input terminal D of DFF[4].

[0535] In this way, the SR has the function of sequentially transferring the input signal SPL to the subsequent DFF in synchronization with the clock signal CLK, and also has the function of sequentially switching the potential of the data OUT output from the multiple DFFs in synchronization with the clock signal CLK.

[0536] Furthermore, it is preferable to provide an overlapping structure between a Si transistor and an OS transistor. By providing an overlapping structure between a Si transistor and an OS transistor, a circuit with a small occupancy area can be realized. Furthermore, an OS transistor operates stably even in a high-temperature environment and exhibits little fluctuation in characteristics. Therefore, an OS transistor is less susceptible to the heat generated by a Si transistor and can operate stably. Furthermore, by providing an overlapping structure between a Si transistor and an OS transistor, the connection distance between them can be made extremely short. As a result, wiring resistance and parasitic capacitance are reduced, enabling the circuit to operate at high speed. Furthermore, the power consumption of the circuit is reduced.

[0537] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0538] Embodiment 6 In this embodiment, application examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 45A to 46E.

[0539] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0540] Furthermore, a display device including the semiconductor device of one embodiment of the present invention can be used as a display portion of various electronic devices. A display device including the semiconductor device of one embodiment of the present invention can easily achieve high definition and high resolution.

[0541] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0542] In particular, the display device of one embodiment of the present invention can have high resolution and can therefore be suitably used in electronic devices having a relatively small display area. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and mixed reality (MR) devices.

[0543] The display device of one embodiment of the present invention preferably has extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 7000 ppi or more. By using a display device having such high resolution and / or high resolution, it is possible to further enhance the sense of realism, depth, and the like. The display device of one embodiment of the present invention is not particularly limited in terms of the screen ratio (aspect ratio). For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, or 16:10.

[0544] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0545] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0546] [Electronic Component] FIG. 45A shows a perspective view of a substrate (mounting substrate 819) on which electronic component 810 is mounted. Electronic component 810 shown in FIG. 45A has semiconductor device 811 inside mold 814. FIG. 45A omits some parts to show the interior of electronic component 810. Electronic component 810 has lands 815 on the outside of mold 814. Lands 815 are connected to electrode pads 816, and electrode pads 816 are connected to semiconductor device 811 via wires 817. Electronic component 810 is mounted on, for example, a printed circuit board 818. A plurality of such electronic components are combined and connected on printed circuit board 818 to complete mounting substrate 819.

[0547] The semiconductor device 811 also includes a drive circuit layer 812 and a memory layer 813. The memory layer 813 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 812 and the memory layer 813 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 812 and the memory layer 813, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0548] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0549] Furthermore, it is preferable that the plurality of memory cell arrays included in the memory layer 813 be formed using OS transistors and that the plurality of memory cell arrays be monolithically stacked. By forming the plurality of memory cell arrays in a monolithic stacked structure, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 813, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0550] The semiconductor device 811 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0551] 45B shows a perspective view of an electronic component 820. The electronic component 820 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 820 has an interposer 821 provided on a package substrate 822 (printed circuit board), and a semiconductor device 824 and a plurality of semiconductor devices 811 provided on the interposer 821.

[0552] In the electronic component 820, the semiconductor device 811 is used as a high bandwidth memory (HBM), and the semiconductor device 824 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0553] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 822. For example, a silicon interposer or a resin interposer can be used as the interposer 821.

[0554] The interposer 821 has a plurality of wirings and functions to connect a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or in multiple layers. The interposer 821 also functions to connect the integrated circuits provided on the interposer 821 to electrodes provided on the package substrate 822. For these reasons, the interposer may be called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 821, and the integrated circuits and the package substrate 822 are connected using the through electrodes. In addition, in a silicon interposer, TSVs may also be used as through electrodes.

[0555] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0556] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0557] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space is required to accommodate the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 820, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

[0558] A heat sink (heat dissipation plate) may be provided so as to overlap the electronic component 820. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 821. For example, in the electronic component 820 shown in this embodiment, it is preferable to align the height of the semiconductor device 811 and the height of the semiconductor device 824.

[0559] Electrodes 823 may be provided on the bottom of the package substrate 822 in order to mount the electronic component 820 on another substrate. FIG. 45B shows an example in which the electrodes 823 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 822, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 823 may be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 822, PGA (Pin Grid Array) mounting can be achieved.

[0560] The electronic component 820 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0561] [Mainframe] Next, Fig. 46A shows a perspective view of a mainframe 830. The mainframe 830 shown in Fig. 46A has a rack 831 housing a plurality of rack-mounted computers 832. The mainframe 830 may also be called a supercomputer.

[0562] The computer 832 can have the configuration shown in the perspective view in Fig. 46B, for example. In Fig. 46B, the computer 832 has a motherboard 842, which has a plurality of slots 843 and a plurality of connection terminals. A PC card 833 is inserted into the slot 843. In addition, the PC card 833 has connection terminals 835, 836, and 837, which are each connected to the motherboard 842.

[0563] A PC card 833 shown in Figure 46C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 833 has a board 834. The board 834 also has a connection terminal 835, a connection terminal 836, a connection terminal 837, a semicon...

Claims

a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, and a second insulating layer; the second conductive layer is in contact with an upper surface of the first conductive layer; the third conductive layer is in contact with an upper surface of the second conductive layer; the first insulating layer is located on the third conductive layer; the fourth conductive layer is located on the first insulating layer; the third conductive layer, the fourth conductive layer, and the first insulating layer have openings at positions overlapping with the second conductive layer; the semiconductor layer has a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the third conductive layer at the opening, and a region in contact with the fourth conductive layer; the second insulating layer is located on the semiconductor layer; the fifth conductive layer is located on the second insulating layer; the fifth conductive layer has a region facing the semiconductor layer with the second insulating layer interposed therebetween within the opening, the semiconductor layer comprises indium oxide; the second conductive layer comprises zirconium, titanium, or tin; The third conductive layer includes an oxide containing indium and a metal element. 　 a semiconductor layer, a protective layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, and a second insulating layer; the second conductive layer is in contact with an upper surface of the first conductive layer; the third conductive layer is in contact with an upper surface of the second conductive layer; the first insulating layer is located on the third conductive layer; the fourth conductive layer is located on the first insulating layer; the third conductive layer, the fourth conductive layer, and the first insulating layer have openings at positions overlapping with the second conductive layer; the semiconductor layer has a region located inside the opening and a region located on the fourth conductive layer, the semiconductor layer has a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the third conductive layer at the opening, and a region in contact with the fourth conductive layer; the protective layer has a region located on the semiconductor layer and a region inside the opening that faces the fourth conductive layer with the semiconductor layer interposed therebetween; a height of a lower end of the protective layer from a reference plane is higher than a height of an upper surface of the third conductive layer from the reference plane; the second insulating layer has a region located on the protective layer and a region in contact with a side surface of the semiconductor layer inside the opening, the fifth conductive layer is located on the second insulating layer; the fifth conductive layer has a region facing the semiconductor layer with the second insulating layer interposed therebetween within the opening, the semiconductor layer comprises indium oxide; the second conductive layer comprises zirconium, titanium, or tin; the third conductive layer includes an oxide containing indium and a metal element; The semiconductor device has a lower oxygen permeability through the protective layer than through the semiconductor layer. 　 In claim 2, The protective layer is a semiconductor device having an oxide semiconductor or an insulator. 　 In claim 3, the oxide semiconductor contains indium and an element M; The element M is one or more elements selected from zinc, aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. 　 In claim 3, The oxide semiconductor includes indium, gallium, and zinc. 　 In claim 3, The semiconductor device, wherein the insulator comprises silicon nitride. 　 a semiconductor layer, a protective layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, and a second insulating layer; the second conductive layer is in contact with an upper surface of the first conductive layer; the third conductive layer is in contact with an upper surface of the second conductive layer; the first insulating layer is located on the third conductive layer; the fourth conductive layer is located on the first insulating layer; the third conductive layer, the fourth conductive layer, and the first insulating layer have openings at positions overlapping with the second conductive layer; the semiconductor layer has a region located inside the opening and a region located on the fourth conductive layer, the semiconductor layer has a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the third conductive layer at the opening, and a region in contact with the fourth conductive layer; the protective layer has a region located on the semiconductor layer and a region inside the opening that faces the fourth conductive layer with the semiconductor layer interposed therebetween; a height of a lower end of the protective layer from a reference plane is higher than a height of an upper surface of the third conductive layer from the reference plane; the second insulating layer has a region located on the protective layer and a region in contact with a side surface of the semiconductor layer inside the opening, the fifth conductive layer is located on the second insulating layer; the fifth conductive layer has a region facing the semiconductor layer with the second insulating layer interposed therebetween within the opening, the semiconductor layer comprises indium oxide; the second conductive layer comprises zirconium, titanium, or tin; the third conductive layer includes an oxide containing indium and a metal element; the protective layer comprises indium and an element M; The element M is one or more elements selected from zinc, aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. 　 In any one of claims 2 to 7, the first insulating layer comprises an oxide layer; the second insulating layer includes a layer including silicon oxide; The oxygen concentration of the silicon oxide layer is higher than the oxygen concentration of the oxide layer. 　 In any one of claims 2 to 7, The semiconductor device, wherein the oxygen concentration in the region of the semiconductor layer that is in contact with the protective layer is lower than the oxygen concentration in the region of the semiconductor layer that is in contact with the second insulating layer. 　 In any one of claims 1 to 7, The semiconductor device wherein the metal element is tin or zinc. 　 In any one of claims 1 to 7, A semiconductor device in which the electrical conductivity of the first conductive layer is higher than the electrical conductivity of the second conductive layer.

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