Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a highly-reliable semiconductor device. The semiconductor device comprises: a semiconductor layer; first to third conductive layers; and first to third insulating layers. The first insulating layer has a portion that is located on the first conductive layer and has a first opening that reaches the first conductive layer. The second insulating layer has a portion in contact with a lateral surface of the first opening in the first insulating layer. The second conductive layer is located on the first insulating layer and the second insulating layer. The second conductive layer and the second insulating layer have a second opening that reaches the first conductive layer. The semiconductor layer has, in the second opening, a portion in contact with a lateral surface of the second conductive layer, a portion in contact with a lateral surface of the second insulating layer, and a portion in contact with the upper surface of the first conductive layer. The third insulating layer covers the semiconductor layer. The third conductive layer is located on the third insulating layer. The upper surface of the second insulating layer has a portion in contact with the lower surface of the second conductive layer.

Description

Semiconductor device and method for manufacturing the semiconductor device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing the transistor and the semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0005] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a low-power central processing unit (CPU) that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor.

[0006] Examples of oxide semiconductors that can be used in the active layer of a transistor include indium oxide and indium gallium zinc oxide. ２ O ３ Non-Patent Document 2 discloses a thin film transistor using hydrogenated polycrystalline indium oxide formed by low-temperature solid phase crystallization as an active layer.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Dhananjay and C. W. Chu, “Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process” Appl. Phys. Lett. 91, 132111 (2007). Y. Magari et al. , "High-mobility hydrogenated polycrystalline In 2 O 3 (In 2 O 3 : H) thin-film transistors", Nature Communications, 13, 1078 (2022) Takashi Koida, "High-mobility transparent conductive film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0009] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with large on-state current.An object of one embodiment of the present invention is to provide a transistor with small parasitic capacitance.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, or memory device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device or memory device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One embodiment of the present invention is a semiconductor device including a semiconductor layer, first to third conductive layers, and first to third insulating layers. The first insulating layer has a portion located over the first conductive layer and a first opening reaching the first conductive layer. The second insulating layer has a portion in contact with a side surface of the first insulating layer in the first opening. The second conductive layer is located over the first insulating layer and the second insulating layer. The second conductive layer and the second insulating layer have a second opening reaching the first conductive layer. The semiconductor layer has, in the second opening, a portion in contact with a side surface of the second conductive layer, a portion in contact with a side surface of the second insulating layer, and a portion in contact with a top surface of the first conductive layer. The third insulating layer covers the semiconductor layer. The third conductive layer is located over the third insulating layer. The top surface of the second insulating layer has a portion in contact with a bottom surface of the second conductive layer.

[0012] In the semiconductor device, the width of the second insulating layer is preferably not less than 3 nm and not more than 10 nm.

[0013] In the above semiconductor device, the height of the upper surface of the second insulating layer is preferably the same as the height of the upper surface of the first insulating layer.

[0014] In the semiconductor device, it is preferable that a side edge of the second opening of the second conductive layer coincides with a side edge of the second opening of the second insulating layer in plan view.

[0015] In the above semiconductor device, the second insulating layer preferably has a portion located between the first insulating layer and the second conductive layer.

[0016] In the above semiconductor device, the second insulating layer preferably contains hafnium and oxygen.

[0017] In the above semiconductor device, it is preferable that the second insulating layer has a stacked structure of a first layer and a second layer on the first layer, the first layer containing hafnium and oxygen, and the second layer containing silicon and oxygen.

[0018] Another embodiment of the present invention is a method for manufacturing a semiconductor device, including: forming a first conductive layer; forming a first insulating layer to cover the first conductive layer; forming a first opening in the first insulating layer that reaches the first conductive layer; forming a second insulating layer and a layer over the second insulating layer to fill the first opening; forming a second conductive layer over the first insulating layer, the second insulating layer, and the layer; removing part of the second conductive layer, the layer, and part of the second insulating layer to form a second opening in the second conductive layer and the second insulating layer, the outline of which is located inside the outline of the first opening in a plan view; forming a semiconductor layer to cover sidewalls and a bottom of the second opening; forming a third insulating layer over the semiconductor layer; and forming a third conductive layer over the third insulating layer.

[0019] Another embodiment of the present invention is a semiconductor device including a semiconductor layer, first to fourth conductive layers, and first to fourth insulating layers. The first insulating layer has a portion located on the first conductive layer and has a groove reaching the first conductive layer. The second insulating layer is located on the first conductive layer and has a portion in contact with a first side surface of the groove of the first insulating layer. The third insulating layer is located on the first conductive layer and has a portion in contact with a second side surface opposite to the first side surface. The second conductive layer is located on the first insulating layer and the second insulating layer. The third conductive layer is located on the first insulating layer and the third insulating layer. The semiconductor layer has a portion in contact with the second conductive layer, a portion in contact with the third conductive layer, and, in the groove, a portion in contact with the second insulating layer, a portion in contact with the third insulating layer, and a portion in contact with the first conductive layer. The fourth insulating layer covers the semiconductor layer. The fourth conductive layer is located on the fourth insulating layer and fills at least a portion of the trench. The upper surface of the second insulating layer has a portion that contacts the lower surface of the second conductive layer. The upper surface of the third insulating layer has a portion that contacts the lower surface of the third conductive layer.

[0020] In the semiconductor device, the width of the second insulating layer is preferably not less than 3 nm and not more than 10 nm.

[0021] In the above-described semiconductor device, it is preferable that the height of the upper surface of the second insulating layer is the same as the height of the upper surface of the first insulating layer, and that the height of the upper surface of the third insulating layer is the same as the height of the upper surface of the first insulating layer.

[0022] In the above-described semiconductor device, it is preferable that, in a plan view, a side end of the second conductive layer facing the third conductive layer coincides with a side end of the second insulating layer facing the third insulating layer.

[0023] In the above semiconductor device, it is preferable that the semiconductor device has a fifth conductive layer electrically connected to the second conductive layer, a sixth conductive layer electrically connected to the third conductive layer, and a seventh conductive layer electrically connected to the fifth conductive layer and the sixth conductive layer, and that the direction in which the seventh conductive layer extends and the direction in which the groove portion extends intersect with each other.

[0024] In the above semiconductor device, the second insulating layer preferably contains hafnium and oxygen.

[0025] Another aspect of the present invention is a method for forming a first conductive layer, forming a first insulating layer so as to cover the first conductive layer, forming a groove in the first insulating layer that reaches the first conductive layer, forming a second insulating layer and a layer on the second insulating layer so as to fill the groove, forming a second conductive layer on the first insulating layer, the second insulating layer, and the layer, removing a portion of the second conductive layer that overlaps with the groove, forming a third conductive layer and a fourth conductive layer from the second conductive layer, and removing the layer. a portion of the second insulating layer located between the third conductive layer and the fourth conductive layer is removed to form a third insulating layer and a fourth insulating layer from the second insulating layer; a semiconductor layer is formed in contact with a top surface and side surfaces of the third conductive layer, the side surfaces of the third insulating layer, the top surface and side surfaces of the fourth conductive layer, the side surfaces of the fourth insulating layer, and the first conductive layer; a fifth insulating layer is formed on the semiconductor layer; and a fifth conductive layer is formed on the fifth insulating layer.

[0026] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, or memory device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device or memory device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0028] FIGS. 1A, 1B, 1C, and 1D are diagrams illustrating structural examples of semiconductor devices. FIGS. 2A and 2B are diagrams illustrating structural examples of semiconductor devices. FIGS. 3A, 3B, 3C, and 3D are diagrams illustrating structural examples of semiconductor devices. FIGS. 4A and 4B are diagrams illustrating structural examples of semiconductor devices. FIGS. 5A, 5B, 5C, and 5D are diagrams illustrating structural examples of semiconductor devices. FIGS. 6A and 6B are diagrams illustrating structural examples of semiconductor devices. FIGS. 7A, 7B, 7C, 7D, 7E, and 7F are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 8A, 8B, 8C, 8D, 8E, and 8F are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 9A, 9B, and 9C are diagrams illustrating structural examples of semiconductor devices. FIGS. 10A, 10B, 10C, and 10D are diagrams illustrating structural examples of semiconductor devices. FIGS. 11A, 11B, and 11C are structural examples of semiconductor devices. FIGS. 12A and 12B are diagrams illustrating a structural example of a semiconductor device. FIGS. 13A, 13B, and 13C are diagrams illustrating a structural example of a semiconductor device. FIGS. 14A, 14B, 14C, 14D, and 14E are diagrams illustrating a structural example of a semiconductor device. FIGS. 15A, 15B, 15C, and 15D are diagrams illustrating a structural example of a semiconductor device. FIGS. 16A, 16B, 16C, 16D, 16E, and 16F are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 17A, 17B, 17C, 17D, 17E, and 17F are diagrams illustrating an example of a manufacturing method of a semiconductor device. FIGS. 18A and 18B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 18C is a cross-sectional view illustrating an indium oxide film. FIGS. 19A, 19B, and 19C are diagrams illustrating a structural example of a memory device. 20A, 20B, and 20C are diagrams illustrating an example of the configuration of a memory device. FIGS. 21A and 21B are diagrams illustrating an example of the configuration of a memory device. FIGS. 22A and 22B are diagrams illustrating an example of the configuration of a memory device. FIG. 23 is a diagram illustrating an example of the configuration of a memory device. FIG. 24 is a block diagram illustrating an example of the configuration of a semiconductor device. FIGS. 25A, 25B, 25C, 25D, 25E, 25F, 25G, and 25H are diagrams illustrating an example of the circuit configuration of a memory cell.26A and 26B are perspective views illustrating an example of the configuration of a semiconductor device. FIG. 27 is a block diagram illustrating a CPU. FIGS. 28A and 28B are perspective views of a semiconductor device. FIGS. 29A and 29B are perspective views of a semiconductor device. FIG. 30A is an equivalent circuit diagram of a logic circuit. FIG. 30B is a circuit symbol for the logic circuit. FIG. 30C is a timing chart illustrating the operation of the logic circuit. FIG. 31 is a cross-sectional view showing an example of a semiconductor device. FIGS. 32A and 32D are equivalent circuit diagrams of logic circuits. FIGS. 32B, 32C, 32E, and 32F are circuit symbols for logic circuits. FIG. 33A is an equivalent circuit diagram of a DFF circuit. FIG. 33B is a circuit symbol for a DFF circuit. FIG. 34A is a diagram illustrating an example of the configuration of a shift register circuit. FIG. 34B is a timing chart illustrating the operation of the shift register circuit. FIGS. 35A and 35B are diagrams illustrating an example of an electronic component. FIGS. 36A, 36B, and 36C are diagrams illustrating an example of a mainframe computer. Fig. 36D is a diagram showing an example of space equipment. Fig. 36E is a diagram showing an example of a storage system applicable to a data center.

[0029] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0030] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0031] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0032] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0033] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0034] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0035] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0036] In this specification and the like, an oxynitride is a material containing oxygen and nitrogen, and the nitrogen and oxygen contents in the composition are not limited. That is, the oxynitride includes a material whose composition contains more oxygen than nitrogen, and a material whose composition contains more nitrogen than oxygen.

[0037] In this specification and the like, the words "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0038] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0039] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0040] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0041] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0042] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0043] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0044] In this specification, "having the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as the surface of a substrate) are the same in a cross-sectional view. For example, in the case of having two layers (here, layer A and layer B) with different heights relative to the reference surface, the difference in height between the top surface of layer A and the top surface of layer B is 10 nm or less, and this is also referred to as "having the same height."

[0045] In this specification, the term "side edges coincide" means that at least a portion of the contours of the stacked layers overlap in a planar view. For example, in the case of two stacked layers (here, Layer A and Layer B), the term "side edges coincide" also applies when the shortest distance from the side edge of Layer A to the side edge of Layer B in a planar view is 10 nm or less.

[0046] In general, it may be difficult to clearly distinguish between an "exact match" and an "approximate match." For this reason, in this specification and elsewhere, "match" may include both an exact match and an approximate match.

[0047] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. Note that in this specification, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." Furthermore, the X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0048] In this specification and the like, a cubic crystal structure may be referred to as a cubic crystal, a cubic crystal structure, etc. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0049] In this specification and the like, a high power supply potential VDD (hereinafter simply referred to as "VDD") refers to a power supply potential that is higher than a low power supply potential VSS (hereinafter simply referred to as "VSS"). Also, the low power supply potential VSS refers to a power supply potential that is lower than the high power supply potential VDD.

[0050] The potential H is a potential that turns on an n-channel field effect transistor (also called an "n-type transistor") and turns off a p-channel field effect transistor (also called a "p-type transistor"). The potential L is a potential that turns off an n-type transistor and turns on a p-type transistor. Therefore, the potential H is higher than the potential L. The potential H may be equal to VDD, and the potential L may be equal to VSS.

[0051] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting restrictions, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0052] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0053] Embodiment 1 In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention includes a transistor.

[0054] <Configuration Example of Semiconductor Device> A configuration example of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 1A to 6B . FIG. 1A is a plan view of a semiconductor device including a transistor 50. FIG. 1B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 1A . FIG. 1C is a cross-sectional view taken along dashed-dotted line B1-B2 in FIG. 1A . FIG. 1D is a cross-sectional view taken along dashed-dotted line C1-C2 in FIG. 1B . Note that some elements are omitted in the plan view of FIG. 1A for clarity. Some elements may also be omitted in the subsequent plan views. FIGS. 2A and 2B are schematic perspective views of the semiconductor device shown in FIGS. 1A to 1D . In FIG. 2A , some insulating layers are omitted or are indicated by dotted lines to make the structure easier to understand. FIG. 2B is a schematic perspective view of a portion of FIG. 2A cut away.

[0055] 1A to 1D includes an insulating layer 87 on a substrate (not shown), insulating layers 62 and 74 on the insulating layer 87, a transistor 50 on the insulating layer 87, and an insulating layer 88 on the transistor 50. At least one of the insulating layer 87, the insulating layer 62, the insulating layer 74, and the insulating layer 88 may be considered a component of the transistor 50.

[0056] The transistor 50 includes a conductive layer 55 on an insulating layer 87, a conductive layer 56 on an insulating layer 62, a semiconductor layer 51, an insulating layer 52 on the semiconductor layer 51, and a conductive layer 53 on the insulating layer 52. The insulating layer 62 has a portion located on the conductive layer 55, and the insulating layer 74 has a portion located on the conductive layer 55.

[0057] In the transistor 50, the conductive layer 53 functions as a gate electrode, and the insulating layer 52 functions as a gate insulating layer. The conductive layer 55 functions as one of a source electrode and a drain electrode, and the conductive layer 56 functions as the other of the source electrode and the drain electrode. The conductive layer 53 has a region that functions as a gate wiring.

[0058] 1B and 1C, the insulating layer 62 has an opening 68 that reaches the conductive layer 55. 1A and 1D show an example in which the opening 68 is circular in plan view. By making the opening 68 circular in plan view, the processing accuracy when forming the opening 68 can be improved, and an opening of a fine size can be formed.

[0059] The insulating layer 74 has a portion located in the opening 68. The insulating layer 74 is provided to reflect the shape of the opening 68. The insulating layer 74 has a portion that contacts the side surface of the insulating layer 62 at the opening 68. The insulating layer 74 has a portion that overlaps with the conductive layer 56. For example, the upper surface of the insulating layer 74 has a portion that contacts the lower surface of the conductive layer 56. The height of the upper surface of the insulating layer 74 matches the height of the upper surface of the insulating layer 62.

[0060] Conductive layer 56 is located on insulating layer 62 and insulating layer 74 .

[0061] As shown in FIGS. 1B and 1C, insulating layer 74 and conductive layer 56 have openings 65 that reach conductive layer 55 .

[0062] Each of the semiconductor layer 51, the insulating layer 52, and the conductive layer 53 has a portion located in the opening 65. Furthermore, the portions of the semiconductor layer 51, the insulating layer 52, and the conductive layer 53 located in the opening 65 are provided to reflect the shape of the opening 65.

[0063] The semiconductor layer 51 is provided so as to cover the bottom and sidewalls of the opening 65. The semiconductor layer 51 has a recess that reflects the shape of the opening 65. The semiconductor layer 51 has a portion that contacts the upper surface of the conductive layer 56 outside the opening 65. In the opening 65, the semiconductor layer 51 also has a portion that contacts the side surface of the conductive layer 56, a portion that contacts the side surface of the insulating layer 74, and a portion that contacts the upper surface of the conductive layer 55.

[0064] The insulating layer 52 is provided to cover the semiconductor layer 51 and the conductive layer 56. The insulating layer 52 has a recess that reflects the shape of the recess of the semiconductor layer 51. The insulating layer 52 has a portion that contacts the side surface of the semiconductor layer 51 and the side surface of the conductive layer 56 outside the opening 65.

[0065] The conductive layer 53 is provided so as to fill at least a part of the recessed portion of the insulating layer 52. In the opening 65, the conductive layer 53 has a region that overlaps with the semiconductor layer 51 with the insulating layer 52 sandwiched therebetween.

[0066] The semiconductor layer 51 has a region that overlaps with the conductive layer 53 with the insulating layer 52 interposed therebetween. At least a part of this region functions as a channel formation region of the transistor 50. One of the region of the semiconductor layer 51 near the conductive layer 55 and the region of the semiconductor layer 51 near the conductive layer 56 functions as a source region, and the other functions as a drain region. In other words, the channel formation region is sandwiched between the source region and the drain region. Note that the source region and the drain region can be interchanged.

[0067] The semiconductor layer 51 is provided in the opening 65, and one of the source electrode and the drain electrode (the conductive layer 55 here) is located below, while the other of the source electrode and the drain electrode (the conductive layer 56 here) is located above. Thus, the channel of the transistor 50 is formed along the sidewall of the opening 65. That is, the transistor 50 has a structure in which current flows vertically. As a result, the transistor 50 can occupy a smaller area than a planar transistor in which a channel formation region, a source region, and a drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased. Note that the channel length direction of the transistor 50 can be said to have a component in the height direction (vertical direction). Therefore, the transistor 50 can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0068] A metal oxide functioning as a semiconductor (hereinafter also referred to as an oxide semiconductor) can be used for the semiconductor layer 51. In this case, the transistor 50 can be said to be an OS transistor.

[0069] For example, an oxide containing indium is preferably used for the semiconductor layer 51, and indium oxide is particularly preferably used. The band gap of an oxide containing indium is 2.0 eV or more, or 2.5 eV or more. By using a metal oxide having a wider band gap than silicon for the semiconductor layer 51, the off-state current of the transistor can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0070] For indium oxide that can be used for the semiconductor layer 51, refer to the description in Embodiment Mode 2. Here, detailed description will be omitted.

[0071] An OS transistor has an oxygen vacancy (V Ｏ If there are impurities and oxygen vacancies, the electrical characteristics may be easily changed and reliability may be reduced. Ｏ H) may generate electrons that serve as carriers. Therefore, if oxygen vacancies and impurities are contained in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0072] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor preferably have a high carrier concentration and low resistance due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element. That is, the source and drain regions of an OS transistor preferably have a high carrier concentration compared to the channel formation region and are n-type regions (low-resistance regions).

[0073] Therefore, in one embodiment of the present invention, an insulating layer having a function of capturing or fixing hydrogen (also referred to as an insulating layer having a gettering function) is provided in contact with or near the semiconductor layer 51. This allows hydrogen contained in the semiconductor layer 51 to be captured or fixed, thereby reducing the amount of hydrogen contained in the semiconductor layer 51. As the insulating layer, aluminum oxide, hafnium oxide, hafnium zirconium oxide, an oxide containing hafnium and silicon, or the like can be used. In the semiconductor device described in this embodiment, the insulating layer is the insulating layer 74, for example.

[0074] 1B , the width of the insulating layer 74 is defined as width H74. Note that width H74 may vary in the depth direction of opening 68 or opening 65. In particular, width H74 may be defined as the shortest distance between the end of insulating layer 74 that contacts the upper end of insulating layer 62 and the side surface of insulating layer 74 that contacts semiconductor layer 51 in a cross-sectional view. Width H74 may also be defined as the shortest distance between the lowest position of the side surface of insulating layer 74 that contacts insulating layer 62 and the side surface of insulating layer 74 that contacts semiconductor layer 51 in a cross-sectional view.

[0075] It is preferable that the width H74 be large. Increasing the width H74 can enhance the functionality of the insulating layer 74. On the other hand, decreasing the width H74 can reduce the width of the opening 68 without reducing the width of the opening 65. This allows for miniaturization or high integration of the semiconductor device. From the above, the width H74 is preferably, for example, 1 nm or more and 20 nm or less, more preferably 2 nm or more and 15 nm or less, and even more preferably 3 nm or more and 10 nm or less.

[0076] In a plan view, it is preferable that the side edge of the conductive layer 56 in the opening 65 and the side edge of the insulating layer 74 in the opening 65 coincide with each other. In this case, in a plan view, the insulating layer 74 overlaps with the conductive layer 56 but does not overlap with the opening 65. With this configuration, the opening 65 can be formed in the conductive layer 56 and the insulating layer 74 at the same time. Furthermore, the film thickness distribution of the semiconductor layer 51 and the like provided in the opening 65 can be made uniform. Furthermore, it is possible to prevent the semiconductor layer 51 and the like from being divided by a step or the like between the conductive layer 56 and the insulating layer 74.

[0077] FIG. 1B illustrates a configuration in which the height of the upper surface of the conductive layer 55 in contact with the insulating layer 62 is the same as the height of the upper surface of the conductive layer 55 in contact with the insulating layer 74. However, the present invention is not limited to this. For example, as shown in FIG. 3A, the conductive layer 55 can have a recess (hereinafter sometimes referred to as a first recess) that overlaps with the insulating layer 74. By having the first recess in the conductive layer 55, the volume of the insulating layer 74 can be increased compared to when the first recess is not present, and further, the contact area between the insulating layer 74 and the semiconductor layer 51 can be increased. Therefore, hydrogen contained in the semiconductor layer 51 can be efficiently reduced. Note that the conductive layer 55 shown in FIG. 1B does not have a first recess at the position that overlaps with the insulating layer 74.

[0078] 1B illustrates a configuration in which the insulating layer 74 is provided in the opening 68. However, the present invention is not limited to this. For example, as shown in FIG. 3B , the insulating layer 74 may have a portion in contact with the upper surface of the insulating layer 62. In other words, it may have a portion located between the insulating layer 62 and the conductive layer 56. This increases the volume of the insulating layer 74, thereby further reducing the amount of hydrogen contained in the semiconductor layer 51.

[0079] 3A, a layer 91 may be provided between the conductive layer 56 and the insulating layer 74 (see FIG. 3C). The layer 91 will be described later.

[0080] FIG. 3B shows a configuration in which the film thickness of the portion of insulating layer 74 located on insulating layer 62 is the same as or approximately the same as width H74. Note that the present invention is not limited to this configuration as long as insulating layer 74 has a portion located on insulating layer 62. The film thickness of the portion of insulating layer 74 located on insulating layer 62 may differ from width H74. FIG. 3D shows a configuration in which the film thickness of the portion of insulating layer 74 located on insulating layer 62 is greater than width H74. This increases the volume of insulating layer 74 compared to the configuration shown in FIG. 3B, thereby further reducing hydrogen contained in semiconductor layer 51. Note that in this specification and the like, "same as or approximately the same" refers to a value greater than 0.9 times and less than 1.1 times the value.

[0081] 3B shows a configuration in which, in a plan view, the side edge of the opening 65 of the conductive layer 56 and the side edge of the opening 65 of the insulating layer 74 coincide with each other. However, the present invention is not limited to this. For example, as shown in FIG. 4A , in a plan view, the insulating layer 74 may have a portion that overlaps with the opening of the conductive layer 56.

[0082] FIG. 1B shows an example in which the insulating layer 74 has a single layer structure. The insulating layer 74 can have a stacked structure of two or more layers. In this case, the insulating layer 74 is preferably formed of two or more types of films. By forming the insulating layer 74 into two or more types of films, multiple functions can be imparted to the insulating layer 74. Examples of the functions of the insulating layer 74 include a function of supplying oxygen to the semiconductor layer 51, a function of capturing or fixing hydrogen in the semiconductor layer 51, and a function of suppressing diffusion of hydrogen into the semiconductor layer 51.

[0083] 4B shows an example in which the insulating layer 74 has a two-layer structure of an insulating layer 74_1 and an insulating layer 74_2 on the insulating layer 74_1. For example, it is preferable to use an insulating material that has a function of capturing or fixing hydrogen as the insulating layer 74_1, and an insulating material that releases oxygen when heat is applied as the insulating layer 74_2. With this structure, the insulating layer 74_2 releases oxygen due to heat applied during the manufacturing process of the semiconductor device, and the oxygen can be supplied to the semiconductor layer 51. Supplying oxygen to the semiconductor layer 51, particularly to the channel formation region, can prevent oxygen vacancies or V Ｏ It is possible to reduce H. It is also possible to reduce hydrogen contained in the semiconductor layer 51. For example, hafnium oxide can be used for the insulating layer 74_1, and silicon oxide can be used for the insulating layer 74_2.

[0084] As described above, by providing the insulating layer 74, a highly reliable transistor having good electrical characteristics can be provided. Also, a highly reliable semiconductor device can be provided.

[0085] The semiconductor layer 51 can be made of a semiconductor material described in the section [Semiconductor Layer] below.

[0086] FIG. 1B shows an example in which the semiconductor layer 51 has a single-layer structure. The semiconductor layer 51 can have a stacked structure of two or more layers. For example, as shown in FIG. 5A , the semiconductor layer 51 can have a two-layer structure including a semiconductor layer 51_1 in contact with the sidewall of the opening 65 and a semiconductor layer 51_2 on the semiconductor layer 51_1. In this case, it is preferable to use a metal oxide (typically indium oxide) applicable to the semiconductor layer 51 described above as the semiconductor layer 51, and a metal oxide whose conduction band minimum is located closer to the vacuum level than the conduction band minimum of the semiconductor layer 51_1 as the semiconductor layer 51_2. In this case, the semiconductor layer 51_1 can mainly function as a current path (channel). That is, the semiconductor layer 51_1 has a channel formation region on the surface on the semiconductor layer 51_2 side and in the vicinity thereof.

[0087] The above-described structure can reduce carriers trapped at the interface of the semiconductor layer 51_1 and in the vicinity thereof. In addition, the channel can be located away from the surface of the insulating layer 52, thereby reducing the influence of surface scattering. This can increase the field-effect mobility of the transistor.

[0088] Examples of metal oxides that can be used for the semiconductor layer 51_2 include indium gallium oxide (In—Ga oxide), indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium tin zinc oxide (In—Sn—Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In—Ti—Zn oxide), and indium tin oxide containing silicon oxide (ITSO). Alternatively, zinc oxide, aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), aluminum tin oxide (Al—Sn oxide), and the like can be used.

[0089] Specifically, the In—Zn oxide used in the semiconductor layer 51_2 can have a composition of In:Zn=1:1 (atomic ratio) or thereabouts, In:Zn=2:1 (atomic ratio) or thereabouts, or In:Zn=4:1 (atomic ratio) or thereabouts. Furthermore, the IGZO used in the semiconductor layer 51_2 can have a composition of In:Ga:Zn=1:1:1 (atomic ratio) or thereabouts, In:Ga:Zn=1:3:2 (atomic ratio) or thereabouts, or In:Ga:Zn=1:3:4 (atomic ratio) or thereabouts. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio.

[0090] The crystallinity of the metal oxide included in the semiconductor layer 51_2 is not particularly limited. For example, the semiconductor layer 51_2 may include at least one of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).

[0091] 5A shows a configuration in which the semiconductor layer 51_2 covers the side surface and the top surface of the semiconductor layer 51_1 in the opening 65, but the present invention is not limited to this. For example, as shown in FIG. 5B , the semiconductor layer 51_2 can be provided so as to cover the top surface of the semiconductor layer 51_1 outside the opening 65, the upper end of the opening 65, and the side surface near the upper end of the opening 65. This prevents the region of the semiconductor layer 51_1 covered with the semiconductor layer 51_2 from becoming i-type or substantially i-type in a step (e.g., microwave treatment described later) after the formation of the semiconductor layer 52_2, and allows the region to function as a source region or a drain region.

[0092] 5C , the semiconductor device of one embodiment of the present invention can include a seed layer 57 between the conductive layer 56 and the semiconductor layer 51. The seed layer 57 can increase the crystallinity of the semiconductor layer 51. The seed layer 57 functions as a seed or a nucleus for increasing the crystallinity of the semiconductor layer 51, and therefore can also be called a seed crystal, a crystal nucleus, or the like.

[0093] When indium oxide is used for the semiconductor layer 51, an oxide containing indium (typically indium oxide), an oxide containing one or both of yttrium and zirconium, erbium oxide, or the like can be used for the seed layer 57. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and oxides containing yttrium and zirconium. These oxides can have a cubic crystal structure. Since the crystal structure of indium oxide is cubic, using these oxides for the seed layer 57 can promote epitaxial growth and improve the crystallinity of the semiconductor layer 51.

[0094] Alternatively, an oxide having a hexagonal or trigonal crystal structure may be used for the seed layer 57. Examples of oxides having a hexagonal or trigonal crystal structure include zinc oxide, In—Ga oxide, gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), Al—Zn oxide, In—Ga—Zn oxide, In—Al—Zn oxide, and In—Sn—Zn oxide. It is preferable to use In—Ga—Zn oxide for the seed layer 57. In this case, the seed layer 57 contains indium, gallium, zinc, and oxygen. Specifically, it is preferable to use a composition in which the atomic ratio of In:Ga:Zn is 1:1:1 or thereabouts, or a composition in which the atomic ratio of In:Ga:Zn is 1:3:2 or thereabouts.

[0095] In—Ga—Zn oxide, In—Sn—Zn oxide, and the like tend to have a CAAC (C-Axis Aligned Crystalline) structure. When an oxide having a CAAC structure is used for the seed layer 57, the c-axis direction of the seed layer 57 is perpendicular or approximately perpendicular to the surface of the insulating layer 87. Therefore, by using an oxide that tends to have a CAAC structure for the seed layer 57, it is possible to improve the controllability of the crystal plane of the crystal grains of the semiconductor layer 51.

[0096] The insulating layer 52 can be made of an insulating material described in the section [Insulating Layer] below.

[0097] 1B and 1C show an example in which the insulating layer 52 has a single layer structure. The insulating layer 52 can have a stacked structure of two or more layers. In this case, the insulating layer 52 is preferably formed of two or more types of films. By forming the insulating layer 52 into two or more types of films, multiple functions can be imparted to the insulating layer 52. Examples of the functions of the insulating layer 52 include a function of supplying oxygen to the semiconductor layer 51, a function of capturing or fixing hydrogen in the semiconductor layer 51, and a function of suppressing diffusion of hydrogen into the semiconductor layer 51.

[0098] For example, when the insulating layer 52 has a function of capturing or fixing hydrogen, the semiconductor device of this embodiment includes the insulating layer 74 and the insulating layer 52 as insulating layers having a function of capturing or fixing hydrogen in contact with or near the semiconductor layer 51. Therefore, hydrogen contained in the semiconductor layer 51 can be further reduced.

[0099] The insulating layer 52 is preferably a thin film. For example, by setting the thickness of the insulating layer 52 to be 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as the S value) can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is kept constant in the subthreshold region.

[0100] The insulating layer 52 can have, for example, a four-layer structure in which an aluminum oxide film, a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 51 side. The thicknesses of the aluminum oxide film, the hafnium oxide film, the silicon oxide film, and the silicon nitride film are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. Alternatively, the insulating layer 52 can have, for example, a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 51 side. The thicknesses of the aluminum oxide film, the silicon oxide film, the hafnium oxide film, and the silicon nitride film are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With this structure, excess oxygen in the semiconductor layer 51 can be discharged to the insulating layer 52, thereby reducing the amount of excess oxygen in the semiconductor layer 51. Furthermore, hydrogen in the semiconductor layer 51 can be captured or fixed. Therefore, the electrical characteristics and reliability of the transistor 50 can be improved.

[0101] When a silicon nitride film, a hafnium oxide film, and a silicon oxide film are used as the insulating layer 62, the insulating layer 74_1, and the insulating layer 74_2, respectively, the insulating layer 52 can also have a three-layer structure in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 51 side. Even with such a configuration, the above-mentioned effects can be achieved.

[0102] The conductive layer 53 can be formed using a conductive material described in the section "Conductive Layer" below. The conductive layer 53 is preferably formed using a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layer 53 may also have a stacked structure. For example, the conductive layer 53 can have a stacked structure of a titanium nitride film and a tungsten film on the titanium nitride film.

[0103] 5D , the semiconductor device of one embodiment of the present invention can include a conductive layer 60 facing the semiconductor layer 51 with an insulating layer 74 sandwiched therebetween. The conductive layer 60 has an opening that overlaps with the opening 68. The opening can be considered to be part of the opening 68. The conductive layer 60 extends in the X direction.

[0104] In the transistor 50 shown in FIG. 5D , one of the conductive layer 53 and the conductive layer 60 can be used as a gate electrode and the other as a back gate electrode. The transistor 50 may have a particularly preferable structure in which the conductive layer 53 is used as a gate electrode and the conductive layer 60 is used as a back gate electrode. By using the conductive layer 53, which has a wider region facing the semiconductor layer 51 than the conductive layer 60, as the gate electrode, the gate electric field is applied to the semiconductor layer 51 more efficiently, which may improve the electrical characteristics of the transistor. Note that when the conductive layer 53 functions as a gate electrode and the conductive layer 60 functions as a back gate electrode, the insulating layer 52 functions as a gate insulating layer and the insulating layer 74 functions as a back gate insulating layer. The conductive layer 60 has a region that functions as a back gate wiring.

[0105] 5D includes a back gate electrode, and therefore, the threshold voltage of the transistor 50 can be controlled by the potential applied to the back gate electrode. Therefore, by controlling the threshold voltage, a normally-off transistor can be easily realized.

[0106] The conductive layer 60 can be made of a conductive material that can be used for the conductive layer 53 .

[0107] 1A and 1D show an example in which the opening 65 is circular in plan view. The circular shape improves the processing accuracy when forming the opening 65, allowing for the formation of a fine-sized opening. Furthermore, by forming the opening 65 so that it is circular in plan view, the semiconductor layer 51, the insulating layer 52, and the conductive layer 53 are arranged concentrically. This allows the distance between the conductive layer 53 and the semiconductor layer 51 to be approximately uniform, allowing for the gate electric field to be applied to the semiconductor layer 51 approximately uniformly. Furthermore, the side surface of the conductive layer 53 located at the center of the opening 65 faces the side surface of the semiconductor layer 51 via the insulating layer 52. In other words, the entire periphery of the semiconductor layer 51 forms a channel formation region in plan view. In this case, the channel width of the transistor 50 is determined by the outer periphery length, inner periphery length, or intermediate length between the outer and inner peripheries of the semiconductor layer 51. When the opening 65 is circular in plan view, the channel width can be calculated, for example, by multiplying the width (diameter) of the opening 65 by pi (π).

[0108] Increasing the width of the opening 65 increases the channel width per unit area, thereby increasing the on-state current. On the other hand, decreasing the width of the opening 65 reduces the area occupied by the transistor 50, thereby enabling a semiconductor device to be highly integrated. Note that the area occupied by the transistor 50, for example, the area of ​​the transistor 50 in a plan view, is roughly determined by the width of the opening 65.

[0109] The width of the opening 65 is set depending on the film thickness of each of the semiconductor layer 51, the insulating layer 52, and the conductive layer 53 provided in the opening 65. The width of the opening 65 is, for example, preferably 5 nm to 100 nm, more preferably 10 nm to 60 nm, more preferably 20 nm to 50 nm, still more preferably 20 nm to 40 nm, and still more preferably 20 nm to 30 nm.

[0110] The width of the opening 65 may vary in the depth direction. Here, the width of the opening 65 is particularly defined as the shortest distance between the two side surfaces of the conductive layer 56 on the opening side in a cross-sectional view. In other words, the minimum width of the opening in the conductive layer 56 is defined as the width of the opening 65.

[0111] The width of the opening 68 is preferably larger than the width of the opening 65. This allows the insulating layer 74 to be provided so as to be located outside the opening 65 in a plan view. Therefore, compared to when the insulating layer 74 is provided inside the opening 65, the channel width per unit area can be increased, and the on-current can be increased. Furthermore, the width of the opening 68 is preferably smaller than the width of the conductive layer 55. This makes it easier to align the conductive layer 55 and the opening 68, and can increase the manufacturing yield.

[0112] In addition, the shape of the opening 65 in plan view is not limited to being circular, but may be, for example, a circle or an approximately circle such as an oval, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or any other polygon with rounded corners. The circle is not limited to a perfect circle. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees).

[0113] The channel length of the transistor 50 is the distance between the source region and the drain region. In other words, the channel length of the transistor 50 is roughly determined by the thickness of the insulating layer 62 on the conductive layer 55 or the height of the insulating layer 74 on the conductive layer 55. Therefore, the channel length of the transistor 50 does not affect the area occupied by the transistor 50, for example, the area of ​​the transistor 50 in a planar view. For example, the channel length of the transistor 50 can be considered as the distance between the edge of the region where the semiconductor layer 51 and the conductive layer 55 contact each other and the edge of the region where the semiconductor layer 51 and the conductive layer 56 contact each other in a cross-sectional view. In this case, the channel length of the transistor 50 corresponds to the height of the opening 68 of the insulating layer 74 in a cross-sectional view.

[0114] The height of the insulating layer 74 on the conductive layer 55 can be 0.1 nm to 500 nm, 1 nm to 300 nm, 5 nm to 100 nm, 5 nm to 60 nm, 5 nm to 50 nm, 5 nm to 40 nm, 5 nm to 30 nm, 5 nm to 20 nm, or 5 nm to 10 nm. Typically, the height can be 1 nm to 300 nm, preferably 5 nm to 100 nm. This can improve productivity and yield in the formation of the insulating layer 62, the opening 65, and the like. Furthermore, the on-state current of the transistor 50 can be increased, thereby improving frequency characteristics.

[0115] As shown in FIGS. 1B and 1C , the conductive layer 55 has a recess overlapping the opening 65. Note that this recess may be referred to as a second recess to distinguish it from the first recess described above. By having the second recess in the conductive layer 55, the height of the lower surface of the insulating layer 52 and the height of the lower surface of the conductive layer 53 within the opening 65 can be lower than the height of the upper surface of the conductive layer 55 in contact with the insulating layer 62, compared to when the conductive layer 55 does not have the second recess. This makes it easier to apply a gate electric field to the semiconductor layer 51, thereby improving the electrical characteristics of the transistor 50. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the upper surface of the insulating layer 87 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the upper surface of a substrate on which a transistor or a semiconductor device is provided may also be used as the reference.

[0116] Furthermore, since the conductive layer 55 has the second recess, the semiconductor layer 51 comes into contact with the bottom and sidewalls of the second recess of the conductive layer 55, thereby increasing the contact area between the semiconductor layer 51 and the conductive layer 55. Therefore, the contact resistance between the semiconductor layer 51 and the conductive layer 55 can be reduced.

[0117] In the semiconductor device shown in FIG. 3A , the conductive layer 55 has a first recess and a second recess located inside the first recess. The second recess is deeper than the first recess. In other words, the bottom surface of the second recess is located lower (closer to the insulating layer 87) than the bottom surface of the first recess. When forming the opening 68, the first recess is provided in the conductive layer 55, and when forming the opening 65, the second recess is provided in the conductive layer 55. Therefore, in FIG. 3A , the sidewall of the first recess coincides with the side surface of the insulating layer 62 in the opening 68, and the sidewall of the second recess coincides with the side surface of the insulating layer 74 on the semiconductor layer 51 side.

[0118] The bottom of the second recess preferably has a curved portion. The semiconductor layer 51, insulating layer 52, and the like provided on the curved portion may also have a curved portion. This reduces electric field concentration on the insulating layer 52 near the second recess, improves the dielectric strength of the transistor 50, and suppresses electrostatic breakdown of the transistor 50. This can therefore improve the reliability of the semiconductor device.

[0119] 1C shows a configuration in which the end of the conductive layer 56 and the end of the semiconductor layer 51 coincide with each other outside the opening 65. The conductive layer 56 and the semiconductor layer 51 can be fabricated by processing using the same mask. This is preferable because it reduces the number of masks required to fabricate a semiconductor device. However, the present invention is not limited to this. For example, a structure in which the end of the semiconductor layer 51 is located inside or outside the end of the conductive layer 56 in the X or Y direction may be used.

[0120] 1A, the transistor 50 is provided at the intersection of a conductive layer 53 extending in the X direction and a conductive layer 56 extending in the Y direction. In this way, the transistor 50 can be said to have a structure that allows for high integration.

[0121] 1A to 1D , in a plan view, the side edge of the conductive layer 56 in the opening 65 and the side edge of the insulating layer 74 in the opening 65 are aligned. However, the present invention is not limited to this. For example, in the opening 65, the side surface of the conductive layer 56 and the side surface of the insulating layer 74 may be discontinuous. Furthermore, in the opening 65, the inclination of the side surface of the conductive layer 56 and the inclination of the side surface of the insulating layer 74 may differ from each other. In this case, part of the side wall of the opening 65 has a tapered shape.

[0122] By tapering the sidewalls of the opening 65, the coverage of the film (such as the semiconductor layer 51) formed in the opening 65 is improved, and defects such as voids can be reduced. When the sidewalls of the opening 65 are tapered, for example, the taper angle (referred to as the first angle) of the side surface of the conductive layer 56 in the opening 65 and the taper angle (referred to as the second angle) of the side surface of the insulating layer 74 in the opening 65 are preferably 45 degrees or more and less than 90 degrees. Specifically, a taper angle of 80 degrees or more and less than 90 degrees is preferable, as this allows for miniaturization or high integration of the semiconductor device. Alternatively, a taper angle of 45 degrees or more and less than 80 degrees, or 50 degrees or more and less than 75 degrees is preferable, as this improves the coverage of the film formed in the opening 65.

[0123] Furthermore, for example, it is preferable that the first angle be smaller than the second angle. With this configuration, the coverage of the semiconductor layer 51 and the like on the side surface of the conductive layer 56 in the opening 65 is improved, and defects such as voids can be reduced. Furthermore, when the conductive layer 56 has a layered structure, the inclination of the side surface of each layer in the opening 65 may be different.

[0124] The conductive layers 55 and 56 can be formed using the conductive materials described in the section "Conductive Layer" below. In particular, it is preferable to use, for the conductive layers 55 and 56, a conductive material that is resistant to oxidation, a material that maintains its conductivity even when absorbing oxygen, or a conductive material that has a function of suppressing oxygen diffusion. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen (also referred to as an oxide conductor). This can suppress a decrease in the conductivity of the conductive layers 55 and 56.

[0125] It is particularly preferable to use an oxide conductor for the conductive layer 55 and the conductive layer 56. For example, it is particularly preferable to use ITO, ITO containing silicon (In-Sn-Si oxide, also referred to as ITSO), In-Zn oxide, In-Ti oxide, or the like. These materials are preferable because they are materials that more easily maintain conductivity even after absorbing oxygen than materials composed of metal elements (also referred to as metal materials). In addition, these materials are preferable because they can reduce the contact resistance between the conductive layer 55 and the semiconductor layer 51 and the contact resistance between the conductive layer 56 and the semiconductor layer 51.

[0126] Furthermore, by using an oxide conductor (typically ITO) having a cubic crystal structure for one or both of the conductive layers 55 and 56, one or both of the conductive layers 55 and 56 can be used as a seed layer to promote epitaxial growth of the semiconductor layer 51 and improve the crystallinity of the semiconductor layer 51. In this case, one or both of the conductive layers 55 and 56 functions as the seed layer 57 described above.

[0127] Furthermore, when an oxide conductor is used for the conductive layer 55 and the conductive layer 56, the conductive layer 55 may function as one of the source region and the drain region, and the conductive layer 56 may function as the other of the source region and the drain region. This allows the entire semiconductor layer 51 to be i-type (intrinsic) or substantially i-type. In other words, it is not necessary to separately form an i-type (intrinsic) or substantially i-type region and an n-type region (low-resistance region) in the semiconductor layer 51. Therefore, even when the distance between the conductive layer 55 and the conductive layer 56 is short, a channel formation region can be provided, and a transistor exhibiting good electrical characteristics can be obtained. Therefore, miniaturization or high integration of a semiconductor device can be achieved.

[0128] 1B and 1C show an example in which the conductive layer 55 and the conductive layer 56 each have a single-layer structure. Each of the conductive layer 55 and the conductive layer 56 can have a stacked structure of two or more layers. For example, when the conductive layer 55 and the conductive layer 56 each have a stacked structure, the oxide conductor can be used for a layer (referred to as a first layer) in the stacked structure that has the largest contact area with the semiconductor layer 51, thereby reducing the contact resistance between the conductive layer 55 and the semiconductor layer 51 and between the conductive layer 56 and the semiconductor layer 51. Furthermore, it is preferable to use a material with higher conductivity than the first layer for a layer (referred to as a second layer) in the stacked structure that has a smaller contact area with the semiconductor layer 51 than the first layer or that does not contact the semiconductor layer 51. This can increase the conductivity of the conductive layer 56. Specifically, tungsten can be used for the second layer.

[0129] When the second layer is in contact with the semiconductor layer 51, zirconium can also be used for the second layer. By using zirconium for the second layer, zirconium can be mixed into the semiconductor layer 51 near the second layer, thereby forming a low resistance region. Instead of zirconium, molybdenum, titanium, tin, or the like can also be used for the second layer.

[0130] The insulating layer 62 preferably includes a barrier insulating layer against hydrogen. This can suppress diffusion of hydrogen into the semiconductor layer 51. Silicon nitride can be used as the insulating layer 62. Silicon nitride also has a barrier property against oxygen. Therefore, when the insulating layer 62 includes a silicon nitride film, oxygen can be suppressed from being extracted from the semiconductor layer 51 and oxygen vacancies can be suppressed from being formed in the semiconductor layer 51. Furthermore, when the insulating layer 62 includes a silicon nitride film, excess oxygen can be prevented from being supplied to the semiconductor layer 51. Therefore, excess oxygen can be prevented from occurring in the channel formation region of the semiconductor layer 51, thereby improving the reliability of the transistor 50.

[0131] Since the insulating layer 62 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wirings. It is also preferable that the concentration of impurities such as water and hydrogen in the insulating layer 62 is reduced. This makes it possible to suppress the intrusion of impurities such as hydrogen and water into the channel formation region of the semiconductor layer 51.

[0132] The insulating layer 62 may be made of an insulating material that releases oxygen when heat is applied. When heat is applied during the manufacturing process of the semiconductor device, the insulating layer 62 releases oxygen, and the oxygen can be supplied to the semiconductor layer 51 through the insulating layer 74. By supplying oxygen to the semiconductor layer 51, particularly to the channel formation region, oxygen vacancies or V Ｏ It is possible to reduce H. Therefore, a transistor can be provided that exhibits favorable electrical characteristics and has high reliability. The insulating layer 62 can be formed using, for example, silicon oxide or silicon oxynitride.

[0133] 1B and other figures show an example in which the insulating layer 62 has a single-layer structure. Note that the insulating layer 62 can have a stacked structure of two or more layers. For example, as shown in FIG. 6A, the insulating layer 62 can have a three-layer structure including an insulating layer 62_1, an insulating layer 62_2 on the insulating layer 62_1, and an insulating layer 62_3 on the insulating layer 62_2.

[0134] The insulating layers 62_1 and 62_3 are preferably barrier insulating layers against oxygen. This can prevent the conductive layers 55 and 56 from being oxidized and increasing their electrical resistance. The insulating layer 62_2 is preferably made of a material having a lower relative dielectric constant than the insulating layers 62_1 and 62_3. This can prevent, for example, parasitic capacitance from being formed between the conductive layers 55 and 56, thereby providing a semiconductor device capable of high-speed operation.

[0135] 6A shows a configuration in which the top surface of the insulating layer 62_2 is flat. However, the present invention is not limited to this. For example, as shown in FIG. 6B, the insulating layer 62 may have a three-layer structure including an insulating layer 62_1 having a flat top surface, an insulating layer 62_2 on the insulating layer 62_1, and an insulating layer 62_3 on the insulating layer 62_2. By flattening the top surface of at least one of the insulating layers 62_1 and 62_2, the top surface of the insulating layer 62_3 can be flattened. This facilitates subsequent processes and increases the yield of semiconductor devices.

[0136] The insulating layer 87 preferably has a barrier property against hydrogen. When the insulating layer 87 provided below the semiconductor layer 51 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 50 to the semiconductor layer 51 can be suppressed.

[0137] Since the insulating layer 87 functions as an interlayer film, a material with a low dielectric constant can be used. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0138] FIG. 1B and other figures show an example in which the insulating layer 87 has a single-layer structure. However, the insulating layer 87 can have a stacked structure of two or more layers. For example, the insulating layer 87 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. For example, it is preferable to use a material with a low relative dielectric constant as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer in contact with the conductive layer 55. Specifically, it is preferable to use a silicon oxide film as the first insulating layer and a silicon nitride film as the second insulating layer.

[0139] An insulating layer 88 is provided over the conductive layer 53 and the insulating layer 52. The insulating layer 88 preferably has a function of suppressing hydrogen diffusion. For example, the insulating layer 88 is preferably made of silicon nitride, which has a high hydrogen barrier property.

[0140] In this way, by surrounding the top and bottom of the transistor 50 with barrier insulating layers against hydrogen, it is possible to suppress the diffusion of hydrogen into the semiconductor layer 51, and to reduce the V ＯH can be reduced. As a result, the electrical characteristics and reliability of the transistor 50 can be improved.

[0141] 7A to 8F, an example of a manufacturing method of a semiconductor device of one embodiment of the present invention will be described. 7A to 7D correspond to the cross-sectional view shown in FIG. 1B, 7E and 7F correspond to the plan view shown in FIG. 1A, 8A to 8E correspond to the cross-sectional view shown in FIG. 4B, and 8F corresponds to the plan view shown in FIG. 1A.

[0142] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), atomic layer deposition (ALD), etc. Examples of CVD methods include plasma enhanced chemical vapor deposition (PECVD), thermal CVD, and photo CVD. Thermal CVD methods include metal organic chemical vapor deposition (MOCVD) and metal chemical vapor deposition (metal CVD).

[0143] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, slit coating, roll coating, curtain coating, etc.

[0144] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0145] For the etching, a dry etching method, a wet etching method, or the like can be used.

[0146] First, an example of a method for manufacturing the semiconductor device shown in FIGS. 1A to 1D will be described.

[0147] First, an insulating layer 87 is formed on a substrate (not shown).

[0148] Subsequently, a conductive layer 55 is formed on the insulating layer 87. Fig. 7A shows an example in which the side surface of the conductive layer 55 is perpendicular to the surface on which the conductive layer 55 is to be formed. Note that, depending on the processing conditions of the conductive film that becomes the conductive layer 55, the side surface of the conductive layer 55 may have a tapered shape that is inclined with respect to the surface on which the conductive layer 55 is to be formed.

[0149] Subsequently, an insulating layer 62 is formed on the conductive layer 55. As shown in FIG. 7A , the insulating layer 62 is preferably subjected to planarization treatment. Note that when the insulating layer 62 has a stacked structure, it is preferable to perform planarization treatment on at least one layer. As the planarization treatment, for example, a chemical mechanical polishing (CMP) method can be used.

[0150] It is preferable to perform heat treatment after forming the insulating layer 62. This can reduce the hydrogen concentration in the insulating layer 62.

[0151] The apparatus used for the heat treatment is not particularly limited, and may be an apparatus that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) apparatus such as an LRTA (Lamp Rapid Thermal Anneal) apparatus or a GRTA (Gas Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using high-temperature gas.

[0152] Subsequently, an opening 68 is formed in the insulating layer 62 so as to reach the conductive layer 55 (FIG. 7A).

[0153] Subsequently, an insulating layer 74 is formed on the insulating layer 62 and the conductive layer 55 (FIG. 7A). The insulating layer 74 is provided so as to cover the sidewalls and bottom of the opening 68. The thickness of the insulating layer 74 is set to be the same as or larger than the width H74.

[0154] Next, a layer 91 is formed on the insulating layer 74 ( FIG. 7A ). At this time, the layer 91 is provided so as to fill the opening 68. Because the layer 91 will be removed in a later step, it is preferable to use a material having an etching rate different from that of the insulating layer 74. Specifically, it is preferable that the ratio of the etching rate of the layer 91 to the etching rate of the insulating layer 74 (hereinafter also referred to as selectivity) is large. When a hafnium oxide film is used as the insulating layer 74, for example, a silicon oxide film, an SOC (spin on carbon) film, or an SOG (spin on glass) film can be used as the layer 91.

[0155] Next, CMP processing is performed until the top surface of the insulating layer 62 is exposed. As a result, an insulating layer 74 and a layer 91 are formed so as to fill the opening 68 ( FIG. 7B ). For example, using a silicon nitride film as the insulating layer 62 makes it easier to detect the end point of the CMP processing. Note that when the insulating layer 62 has a stacked structure, it is preferable to use a silicon nitride film as the uppermost layer.

[0156] Subsequently, the conductive layer 56 is deposited on the insulating layer 62, the insulating layer 74, and the layer 91 (FIG. 7C).

[0157] Next, an opening 65 is formed in the conductive layer 56 and the insulating layer 74. For example, a resist mask is formed in a region other than the region where the opening 65 will be formed, and the conductive layer 56, the layer 91, and the insulating layer 74 in the region where the resist mask is not formed are removed by etching. After the etching process, the resist mask is removed ( FIG. 7D ).

[0158] The etching process can be performed using a dry etching method or a wet etching method. Dry etching is suitable for fine processing. The conductive layer 56, the layer 91, and the insulating layer 74 may be processed under different conditions.

[0159] The width of the opening 65 is preferably equal to or greater than the width of the opening 68 minus twice the film thickness of the insulating layer 74, and is smaller than the width of the opening 68. By making the width of the opening 65 smaller than the width of the opening 68, alignment of the opening 65 and the opening 68 becomes easier, and the manufacturing yield can be increased. Furthermore, the opening 65 can be formed so that the outline of the opening 65 is located inside the outline of the opening 68 in a plan view. Furthermore, the insulating layer 74 can be provided so that it is located outside the opening 65 in a plan view. As the opening 65 is formed, the insulating layer 74 is formed in a cylindrical shape (also referred to as a tube shape or a hollow columnar shape).

[0160] 7E shows a configuration in which the center (or center of gravity) of opening 68 seen from the Z direction coincides with the center (or center of gravity) of opening 65 seen from the Z direction, while Fig. 7F shows a configuration in which the center (or center of gravity) of opening 68 seen from the Z direction is offset in the X and Y directions from the center (or center of gravity) of opening 65 seen from the Z direction. Even in a configuration in which the center (or center of gravity) of opening 68 seen from the Z direction is offset in the X and Y directions from the center (or center of gravity) of opening 65 seen from the Z direction as shown in Fig. 7F, insulating layer 74 can be provided so as to be located outside opening 65 in which semiconductor layer 51 is provided.

[0161] When forming the opening 65, it is preferable to remove a part of the conductive layer 55 in the region overlapping with the opening 65 to provide a recess (the second recess described above) in the conductive layer 55.

[0162] Next, the semiconductor layer 51 is formed so as to cover the sidewalls and bottom of the opening 65. The semiconductor layer 51 can be formed by depositing a semiconductor film that will become the semiconductor layer 51 and then processing the semiconductor film. Note that the semiconductor film and the conductive layer 56 can be processed using the same mask. This is preferable because the number of masks required to form the semiconductor layer can be reduced.

[0163] The semiconductor layer 51 is preferably formed by ALD. Since ALD is a film formation method with superior coverage compared to sputtering, forming the semiconductor layer 51 by ALD can improve the coverage of the semiconductor layer 51. Furthermore, rather than using sputtering, which bombards particles against a surface to be formed, ALD, which deposits atoms one by one during film formation, can suppress the generation of crystal nuclei in the film. For example, a precursor and an oxidizing agent can be used to form the semiconductor layer 51. The precursor preferably contains indium. In this case, a film containing indium and oxygen is formed as the semiconductor layer 51. When the precursor contains indium, thermal ALD can be used as the ALD.

[0164] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolato)indium.

[0165] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the indium-containing precursor. Examples of the inorganic precursor containing indium include halogen-based indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0166] It is preferable to use a precursor having a low impurity concentration, i.e., a high purity, in the method for forming the semiconductor layer 51. For example, by using a precursor having a purity of 3N (99.9%) or higher, preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher, it is possible to reduce the impurities in the semiconductor layer 51.

[0167] The gallium content and aluminum content of the indium-containing precursor are each preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, still more preferably 50 ppm or less, still more preferably 10 ppm or less, and still more preferably 1 ppm or less. By using a precursor with a low gallium content, the gallium concentration in the semiconductor layer 51 can be reduced, thereby improving the reliability of the transistor. Furthermore, by using a precursor with a low aluminum content, the aluminum concentration in the semiconductor layer 51 can be reduced, thereby improving the crystallinity of the semiconductor layer 51.

[0168] Furthermore, as the precursor used in this embodiment, it is preferable to use a precursor purified by performing distillation (also referred to as rectification or precision distillation) two or more times. Using such a precursor facilitates the formation of a metal oxide film with few impurities, which is preferable. Performing distillation multiple times can further suppress impurities originating from the starting materials used in the precursor production from remaining in the precursor, which is preferable. Note that the present invention is not limited to the above, and a precursor purified by a single distillation, i.e., simple distillation, may also be used. Simple distillation can reduce production costs, which is preferable. By performing distillation one or more times, the aluminum content of the indium-containing precursor can be reduced to 100 ppm or less, 1 ppm or less, or 1 ppb (0.001 ppm) or less.

[0169] As an oxidizing agent, ozone (O ３ ), oxygen (O ２ ), water (H ２ O), hydrogen peroxide (H ２ O ２The oxidizing agent preferably contains at least one of ozone and oxygen. By using ozone, oxygen, or the like that does not contain hydrogen as the oxidizing agent, the amount of hydrogen mixed into the semiconductor layer 51 can be reduced.

[0170] In this specification and the like, unless otherwise specified, when ozone, oxygen, or water is used as an oxidizing agent, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, or ion state.

[0171] The substrate heating temperature when introducing the precursor into the reaction chamber is preferably set to a temperature corresponding to the decomposition temperature of the precursor. Here, in the case of a thermal ALD method using triethylindium as the indium-containing precursor, the substrate heating temperature can be, for example, 100° C. to 350° C., preferably 150° C. to 300° C. When the seed layer 57 is provided, the substrate heating temperature can be set to room temperature (25° C.) to 300° C., preferably room temperature to 200° C., more preferably room temperature to 150° C.

[0172] The semiconductor layer 51 can also be formed by a sputtering method, a CVD method, an MBE method, or a PLD method. For example, when the semiconductor layer 51 is formed by a sputtering method, the sputtering gas is hydrogen (H ２ ) is preferably contained. By introducing hydrogen when forming the semiconductor layer 51 by a sputtering method, the semiconductor layer 51 can be formed with low crystallinity. Furthermore, when forming the semiconductor layer 51, generation of crystal nuclei can be suppressed or disappearance of crystal nuclei can be promoted. Note that as the sputtering gas, a noble gas (typically argon) or a simple gas of oxygen, or a mixed gas of a noble gas and oxygen, or the like can also be used.

[0173] Furthermore, when the semiconductor layer 51 is formed by sputtering, the substrate temperature during deposition of the semiconductor layer 51 is preferably from room temperature (25° C.) to 250° C., more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, setting the substrate temperature from room temperature to 140° C. is preferable because it increases productivity. It is also preferable because it can suppress the generation of crystal nuclei. The semiconductor layer can also be deposited at room temperature or without heating the substrate.

[0174] After forming the semiconductor layer 51 with low crystallinity by sputtering, it is preferable to perform heat treatment. The heat treatment can be performed, for example, at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C., and more preferably 320° C. to 450° C. The heat treatment can increase the crystal grain size in the semiconductor layer 51. As described above, the semiconductor layer 51 with crystallinity can be formed. Furthermore, the heat treatment can reduce hydrogen contained in the semiconductor layer 51.

[0175] The heat treatment is carried out in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm (0.001%) or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content is preferably about 20%. The heat treatment may also be carried out under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0176] It is also preferable that the gas used in the heat treatment is highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb (1×10 −３ ppm) or less, and 0.1 ppb (1 x 10 −４ ppm) or less, and 0.05 ppb (5 × 10 −５ By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the semiconductor layer 51 as much as possible.

[0177] There are no particular limitations on the apparatus used for the heat treatment, and the above-mentioned apparatus can be used.

[0178] When the semiconductor layer 51 has a stacked structure, the semiconductor layer 51 can also be formed by, for example, a sputtering method and an ALD method. For example, when the semiconductor layer 51 has a two-layer structure including a semiconductor layer 51_1 and a semiconductor layer 51_2, the semiconductor layer 51_1 can be formed by an ALD method, and the semiconductor layer 51_2 can be formed by a sputtering method. Since the ALD method is a film formation method with superior coverage compared to the sputtering method, forming the semiconductor layer 51_1 by the ALD method can improve the coverage of the semiconductor layer 51. Furthermore, damage to the base (here, the conductive layer 55 or the conductive layer 56) can be reduced, the formation of a mixed layer at the interface between the base and the semiconductor layer 51 can be suppressed, and the crystallinity can be improved. Furthermore, forming the semiconductor layer 51_2 by a sputtering method can improve productivity. At this time, as shown in FIG. 5B, the semiconductor layer 51_2 is formed so as to cover the upper surface of the semiconductor layer 51_1 outside the opening 65 and the upper end of the semiconductor layer 51_1 in the opening 65.

[0179] Alternatively, the semiconductor layer 51_1 may be formed by sputtering, and the semiconductor layer 51_2 may be formed by ALD. Even if pinholes or discontinuities are formed in the semiconductor layer 51_1 formed by sputtering, the portions overlapping the pinholes or discontinuities can be filled with the semiconductor layer 51_2 formed by ALD, which has good coverage. In this case, as shown in FIG. 5A , the semiconductor layer 51_2 is formed so as to cover the semiconductor layer 51_1.

[0180] It is preferable to perform heat treatment after forming the semiconductor layer 51. The temperature of the heat treatment is preferably 100° C. or higher and 750° C. or lower, more preferably 250° C. or higher and 650° C. or lower, and even more preferably 350° C. or higher and 450° C. or lower. For details of the heat treatment, refer to the above description.

[0181] Furthermore, it is preferable that the gas used in the heat treatment is highly purified. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the semiconductor layer 51 as much as possible. Alternatively, it is possible to reduce impurities such as carbon and hydrogen from the semiconductor layer 51 and to achieve high purity.

[0182] Furthermore, microwave treatment may be performed after the semiconductor layer 51 is formed. By performing the microwave treatment, the concentration of impurities such as hydrogen or water contained in the semiconductor layer 51 can be reduced. Furthermore, the crystallinity of the semiconductor layer 51 may be improved. Note that the details of the microwave treatment will be described later.

[0183] Subsequently, the insulating layer 52 is formed on the semiconductor layer 51. It is preferable to use the ALD process two or more times in forming the insulating layer 52 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 52 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 52. Furthermore, it is possible to increase productivity by successively forming, for example, two or more types of insulating films using the ALD process.

[0184] Next, it is preferable to perform microwave treatment in an oxygen-containing atmosphere. Here, microwave treatment refers to treatment using, for example, a device having a power source that generates high-density plasma using microwaves. In addition, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0185] In the microwave treatment, it is preferable to use a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, it can be 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves to the microwave treatment device is preferably 1000 W to 10,000 W, preferably 2000 W to 5,000 W. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the film.

[0186] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, and more preferably from 300 to 700 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and even more preferably from 400 to 450°C.

[0187] Alternatively, after the microwave treatment or plasma treatment, a heat treatment may be performed successively without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0188] The microwave treatment can be carried out using, for example, oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and less than or equal to 100%, more preferably greater than 0% and less than or equal to 50%, even more preferably greater than or equal to 10% and less than or equal to 40%, and even more preferably greater than or equal to 10% and less than or equal to 30%.

[0189] When the insulating layer 52 has a stacked structure, the microwave treatment is not necessarily performed after the formation of the insulating layer 52. For example, when two or more layers are stacked as the insulating layer 52, the microwave treatment may be performed before the formation of a layer in contact with the conductive layer 53, or after the formation of a layer in contact with the semiconductor layer 51, or after the formation of a layer provided between them. The microwave treatment may be performed multiple times (at least two times or more).

[0190] By performing microwave treatment in an atmosphere containing oxygen, the oxygen radicals are supplied to the semiconductor layer, and V in the semiconductor layer 51 Ｏ H and oxygen vacancies can be reduced.

[0191] In addition, in a configuration in which the semiconductor layer 51_2 is provided so as to cover the upper surface of the semiconductor layer 51_1 outside the opening 65, the upper end of the opening 65, and the side surface near the upper end of the opening 65 (see Figure 5B), by performing the microwave treatment, the supply of the oxygen radicals to the region of the semiconductor layer 51_1 covered by the semiconductor layer 51_2 can be suppressed, and the region can be suppressed from becoming i-type or substantially i-type.

[0192] Subsequently, a conductive layer 53 is formed over the insulating layer 52. The conductive layer 53 can be formed by depositing a conductive film to be the conductive layer 53 and then processing the conductive film. In this manner, the transistor 50 can be manufactured.

[0193] Subsequently, an insulating layer 88 is formed over the insulating layer 52 and the conductive layer 53. Through the above steps, the semiconductor device illustrated in FIGS. 1A to 1D can be manufactured. By using such a manufacturing method, a transistor that can be miniaturized can be provided. Alternatively, a transistor that occupies a small area can be provided.

[0194] 7A shows a configuration in which the upper surface of the conductive layer 55 is flat after the opening 68 is formed. Note that after the opening 68 is formed, the thickness of the conductive layer 55 at the portion overlapping the opening 68 may become thin. In this case, the first recess described above is formed in the conductive layer 55. After the first recess is formed, the steps subsequent to the formation of the opening 68 are performed, thereby fabricating the semiconductor device shown in FIG.

[0195] 7B shows a configuration in which the CMP process is performed until the top surface of the insulating layer 62 is exposed. However, the present invention is not limited to this. For example, the above process can be performed until the top surface of the insulating layer 74 is exposed. After the above process is performed until the top surface of the insulating layer 74 is exposed, the steps subsequent to this process are performed, thereby fabricating the semiconductor device shown in FIG. 3B.

[0196] Alternatively, for example, the above treatment can be performed within a range in which at least a portion of layer 91 located outside opening 68 remains. After at least a portion of layer 91 remains outside opening 68 by the above treatment, the semiconductor device shown in Fig. 3C can be fabricated by performing the steps subsequent to this treatment. When conductive layer 56 is removed by etching, if the selectivity of insulating layer 74 relative to conductive layer 56 is low, providing layer 91 with a high selectivity relative to conductive layer 56 makes it easier to form opening 68, which is preferable.

[0197] When the width of opening 65 is set to be larger than the width of opening 68 minus twice the film thickness of insulating layer 74 but smaller than the width of opening 68, removing insulating layer 74 at a position overlapping opening 65 may result in width H74 being smaller than the thickness of insulating layer 74. In this case, by performing the above process until the top surface of insulating layer 74 is exposed, the semiconductor device shown in FIG.

[0198] Note that when the width of opening 65 is set to be larger than the width of opening 68 minus twice the film thickness of insulating layer 74 but smaller than the width of opening 68, depending on the conditions of the etching process, a portion of insulating layer 74 overlapping with opening 65 may remain after the opening is formed in insulating layer 74. By performing the etching process and subsequent steps, the semiconductor device shown in FIG.

[0199] In the above-described exemplary method for manufacturing a semiconductor device, a seed layer 57 can also be formed on the conductive layer 56. For example, the seed layer 57 can be formed after the conductive layer 56 is formed and before the opening 65 is formed. By forming the opening 65 and performing the subsequent steps, the semiconductor device shown in FIG. 5C can be manufactured. Alternatively, for example, the seed layer 57 can be formed after the opening 65 is formed and before the semiconductor layer 51 is formed.

[0200] The film that will become the seed layer 57 is preferably formed by sputtering, which can improve the crystallinity of the seed layer 57.

[0201] The seed layer 57 preferably has a thin thickness, for example, thinner than the thickness of the semiconductor layer 51. Specifically, the seed layer 57 preferably has a region with a thickness of 0.1 nm or more and less than 2 nm, and more preferably has a region with a thickness of 0.5 nm or more and less than 2 nm.

[0202] The seed layer 57 may be island-shaped or striped in plan view. The island-shaped or striped seed layer 57 may be tapered. The number of seed layers 57 may be one or more. After the semiconductor layer 51 is formed, the seed layer 57 and the semiconductor layer 51 in the region overlapping with the seed layer 57 may be removed.

[0203] As described above, when the conductive layer 56 functions as a seed layer, the crystallinity of the semiconductor layer 51 can be improved without providing the seed layer 57. When the conductive layer 56 or the seed layer 57 that functions as a seed layer is provided, the crystallinity can be improved even if the semiconductor layer 51 is a thin film. For example, the thickness of the semiconductor layer 51 can be set to 1 nm or more and 50 nm or less, preferably 2.5 nm or more and 30 nm or less, more preferably 2.5 nm or more and 20 nm or less, more preferably 5 nm or more and 20 nm or less, and more preferably 5 nm or more and 10 nm or less. Note that it is sufficient that at least a portion of the semiconductor layer 51 has a region with the above-described thickness.

[0204] Next, an example of a method for manufacturing the semiconductor device shown in Fig. 4B will be described. Note that descriptions of parts that overlap with the above will be omitted, and only differences will be described in detail.

[0205] The steps up to the formation of the opening 68 are the same as those described above, and therefore will not be described here.

[0206] Subsequently, an insulating layer 74 is formed on the insulating layer 62 and the conductive layer 55 ( FIG. 8A ). Here, an insulating layer 74_1 and an insulating layer 74_2 are formed in this order as the insulating layer 74. For example, a hafnium oxide film is formed as the insulating layer 74_1, and a silicon oxide film is formed as the insulating layer 74_2.

[0207] Next, a layer 91 is formed on the insulating layer 74 ( FIG. 8A ). At this time, the layer 91 is provided so as to cover the opening 68. Because the layer 91 will be removed in a later step, it is preferable to use a material having an etching rate different from that of the insulating layer 74. Specifically, it is preferable that the selectivity of the layer 91 relative to the insulating layer 74 is large. When a silicon oxide film is used as the insulating layer 74_2, for example, an IGZO film can be used as the layer 91.

[0208] When an IGZO film formed by sputtering is used as the layer 91, a gap sandwiched between the layer 91 and the insulating layer 74_2 may be formed in the opening 68 (see FIG. 8A).

[0209] Next, a CMP process is performed until the upper surface of the insulating layer 62 is exposed, thereby forming an insulating layer 74_1, an insulating layer 74_2, and a layer 91 in the opening 68 (FIG. 8B).

[0210] Subsequently, the conductive layer 56 is formed on the insulating layer 62, the insulating layer 74_1, the insulating layer 74_2, and the layer 91 (FIG. 8C).

[0211] Next, an opening that will become part of the opening 65 is formed in the conductive layer 56. For example, a resist mask (not shown) is formed in an area other than the area that will become the opening 65, and the conductive layer 56 in the area where the resist mask is not formed is removed by etching ( FIG. 8D ).

[0212] Next, the layer 91 is removed. The layer 91 can be removed by, for example, wet etching. When an IGZO film is used as the layer 91, the wet etching can be performed using an organic acid such as citric acid or oxalic acid as an etching solution. Note that the method for removing the layer 91 is not limited to wet etching, and it can also be performed by dry etching.

[0213] Subsequently, the insulating layers 74_2 and 74_1 in the regions overlapping with the opening 65 are removed by etching ( FIG. 8E ). As described above, the opening 65 can be formed in the conductive layer 56, the insulating layer 74_2, and the insulating layer 74_1. The resist mask may be removed after processing the conductive layer 56 or after processing the insulating layer 74_1.

[0214] The width of the opening 65 is preferably equal to or greater than the width of the opening 68 minus twice the film thickness of the insulating layer 74_1 and twice the film thickness of the insulating layer 74_2, and smaller than the width of the opening 68. This allows the insulating layer 74 to be provided so as to be located outside the opening 65 in a plan view. When the opening 65 is formed, the insulating layer 74 is formed in a cylindrical shape (also referred to as a tube shape or a hollow columnar shape).

[0215] 8F illustrates a configuration in which the center (or center of gravity) of the opening 68 as viewed from the Z direction is offset in the X and Y directions from the center (or center of gravity) of the opening 65 as viewed from the Z direction. Even in a configuration in which the center (or center of gravity) of the opening 68 as viewed from the Z direction is offset in the X and Y directions from the center (or center of gravity) of the opening 65 as viewed from the Z direction, as shown in FIG. 8F, the insulating layer 74 can be provided so as to be positioned outside the opening 65 in which the semiconductor layer 51 is provided. Note that if the sidewall of the opening 65 near the conductive layer 56 is formed by the side surface of the insulating layer 74, the volume of the insulating layer 74_2 will be constant. This ensures that the amount of oxygen supplied from the insulating layer 74 to the semiconductor layer 51 in each transistor 50 is approximately the same. This suppresses variation in the electrical characteristics of the transistors 50 within the substrate plane.

[0216] The steps after the formation of the opening 65 are the same as those described above, and therefore will not be described here.

[0217] Through the above steps, the semiconductor device shown in FIG. 4B can be manufactured.

[0218] 9A to 15D , examples of the configuration of a transistor that is partially different from the configuration of the transistor 50 will be described. Note that descriptions of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be denoted by the same reference numerals and their descriptions may be omitted.

[0219] Fig. 9A is a plan view of a semiconductor device having a transistor 50A. Fig. 9B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 9A. Fig. 9C is a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 9A. Note that Fig. 1D can be referred to for a cross-sectional view taken along dashed dotted line C1-C2 in Fig. 9B.

[0220] The semiconductor device shown in FIGS. 9A to 9C differs from the semiconductor device shown in FIGS. 1A to 1D mainly in that it has a conductive layer 77, an insulating layer 89, and an insulating layer 86.

[0221] In the transistor 50A, the stacked structure from the conductive layer 55 to the insulating layer 52 is similar to that of the above-described transistor 50, and therefore detailed description thereof will be omitted.

[0222] 9B and 9C , insulating layer 89 is provided so as to be located on insulating layer 52. Furthermore, insulating layer 89 is provided with openings 66 that reach insulating layer 52 at positions overlapping openings 65. Insulating layer 86 is provided on insulating layer 89.

[0223] The conductive layer 53 is provided in an island shape. The conductive layer 53 is provided so as to fill the openings 65 and 66. The conductive layer 53 contacts the insulating layer 52 and the insulating layer 89 in the opening 66. The conductive layer 53 has a portion that faces the semiconductor layer 51 with the insulating layer 52 interposed therebetween in the opening 65, and a portion that is located in the opening 66.

[0224] The conductive layer 77 is provided on the insulating layer 89, the insulating layer 86, and the conductive layer 53, and is in contact with the top surface of the conductive layer 53. The conductive layer 53 and the conductive layer 77 are connected to each other. The conductive layer 77 may be considered a component of the transistor 50A. The height of the top surface of the conductive layer 53 and the height of the top surface of the insulating layer 86 are the same.

[0225] The conductive layer 77 functions as a gate wiring. The conductive layer 77 can be formed using a material that can be used for the conductive layer 53. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 77. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0226] The portion of the conductive layer 77 that does not overlap with the opening 65 is mainly located on the insulating layer 86. Therefore, the conductive layer 77 mainly overlaps with the conductive layer 56 via the insulating layer 86 and the insulating layer 89. This makes it possible to increase the physical distance between the conductive layer 77 and the conductive layer 56 and reduce the parasitic capacitance that occurs between the conductive layer 77 and the conductive layer 56. Note that the conductive layer 77 and the conductive layer 56 may have an overlapping portion without the insulating layer 86 being therebetween.

[0227] The transistor 50A has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0228] In this embodiment, the opening 66 has a circular shape in plan view, but the present invention is not limited to this. Shapes that can be applied to the opening 66 are the same as those that can be applied to the opening 65 described above.

[0229] The width of the opening 66 may vary in the depth direction. In particular, the width of the opening 66 used here is the maximum width of the opening 66 provided in the insulating layer 89 in a cross-sectional view.

[0230] The insulating layer 89 preferably has a function of capturing or fixing hydrogen. With such a structure, hydrogen contained in the semiconductor layer 51 can be captured or fixed. Therefore, the amount of hydrogen contained in the semiconductor layer 51 can be reduced. The insulating layer 89 can be made of aluminum oxide, hafnium oxide, hafnium zirconium oxide, an oxide containing hafnium and silicon, or the like.

[0231] The insulating layer 89 can also be a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen from above the insulating layer 89 into the semiconductor layer 51. Silicon nitride and silicon oxynitride are suitable for use as the insulating layer 89 because they are less permeable to oxygen and hydrogen, respectively.

[0232] Alternatively, the insulating layer 89 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. The insulating layer 89 may have, for example, a stacked film of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0233] The insulating layer 86 functions as an interlayer film, so it is preferable to use a material with a low relative dielectric constant, such as a silicon oxide film.

[0234] In the transistors 50 and 50A, at least some of the components of the transistors are provided in the opening 65 that is circular in plan view, but the present invention is not limited to this. At least some of the components of the transistors can be provided in a groove that is formed to extend.

[0235] FIG. 10A is a plan view of a semiconductor device having a transistor 50B. FIG. 10B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 10A. FIG. 10C is a cross-sectional view taken along dashed-dotted line B1-B2 in FIG. 10A. FIG. 10D is a cross-sectional view taken along dashed-dotted line C1-C2 in FIG. 10B. FIGS. 11A to 11C are schematic perspective views of the semiconductor device shown in FIGS. 10A to 10D. In FIG. 11A, some insulating layers are omitted or are shown by dotted lines to make the structure easier to understand. FIG. 11B is a schematic perspective view with a portion of FIG. 11A cut away. FIG. 11C is a schematic perspective view including a horizontal cross-sectional view of FIG. 10D.

[0236] 1A to 1D in that some of the components are provided in a groove 67 instead of the opening 65. The transistor 50B also differs from the transistor 50 in that the conductive layer 56 is separated into a conductive layer 56a and a conductive layer 56b, and the insulating layer 74 is separated into an insulating layer 74a and an insulating layer 74b.

[0237] The insulating layer 62 has a groove 67 that reaches the conductive layer 55. The groove 67 extends in the X direction. The insulating layer 74a is on the conductive layer 55 and has a portion that contacts the side surface of the insulating layer 62 at the groove 67, and the insulating layer 74b is on the conductive layer 55 and has a portion that contacts the side surface of the insulating layer 62 opposite the side surface. The insulating layer 74a has a portion that overlaps with the conductive layer 56a, and the insulating layer 74b has a portion that overlaps with the conductive layer 56b. The upper surface of the insulating layer 74a has a portion that contacts the lower surface of the conductive layer 56a, and the upper surface of the insulating layer 74b has a portion that contacts the lower surface of the conductive layer 56b.

[0238] The conductive layer 56a is located on the insulating layer 62 and the insulating layer 74a, and the conductive layer 56b is located on the insulating layer 62 and the insulating layer 74b. The semiconductor layer 51, the insulating layer 52, and the conductive layer 53 each have a portion located in the groove portion 67.

[0239] The semiconductor layer 51 is provided in an island shape. The semiconductor layer 51 is provided so as to fit along part of the bottom of the groove 67, the side surface of the insulating layer 74a, and the side surface of the insulating layer 74b. Outside the groove 67, the semiconductor layer 51 has a portion in contact with the top surface of the conductive layer 56a and a portion in contact with the top surface of the conductive layer 56b. In the groove 67, the semiconductor layer 51 also has a portion in contact with the side surface of the conductive layer 56a, a portion in contact with the side surface of the conductive layer 56b, a portion in contact with the insulating layer 74a, a portion in contact with the insulating layer 74b, and a portion in contact with the top surface of the conductive layer 55.

[0240] The insulating layer 52 is provided to cover the semiconductor layer 51, the conductive layer 56a, and the conductive layer 56b.

[0241] The conductive layer 53 is provided on the insulating layer 52 so as to fill at least a part of the groove 67. The conductive layer 53 is provided to extend in the direction in which the groove 67 extends.

[0242] The conductive layer 55 functions as one of a source electrode and a drain electrode of the transistor 50B, and the conductive layer 56a and the conductive layer 56b function as the other of the source electrode and the drain electrode of the transistor 50B. A channel is also formed along the sidewall of the groove 67 in the transistor 50B.

[0243] 10B , the height of the upper surface of insulating layer 74a and the height of the upper surface of insulating layer 74b each match the height of the upper surface of insulating layer 62. As described with reference to FIG. 3B , insulating layer 74a and insulating layer 74b may each have a portion that contacts the upper surface of insulating layer 62. In other words, insulating layer 74a may have a portion located between insulating layer 62 and conductive layer 56a, and insulating layer 74b may have a portion located between insulating layer 62 and conductive layer 56b.

[0244] As explained above in the <Configuration example of semiconductor device>, it is preferable that, in a planar view, the end of the side surface of conductive layer 56a facing conductive layer 56b coincides with the end of the side surface of insulating layer 74a facing insulating layer 74b.

[0245] 10A to 10D includes an insulating layer 88 on the transistor 50B and an insulating layer 86 on the insulating layer 88. An opening reaching the conductive layer 56a is provided in the insulating layer 86, the insulating layer 88, the insulating layer 52, and the semiconductor layer 51, and a conductive layer 76a is provided in the opening. An opening reaching the conductive layer 56b is provided in the insulating layer 86, the insulating layer 88, the insulating layer 52, and the semiconductor layer 51, and a conductive layer 76b is provided in the opening. The conductive layer 76a is in contact with the conductive layer 56a, and the conductive layer 76b is in contact with the conductive layer 56b. The lower portion of the conductive layer 76a may be formed to be embedded in the conductive layer 56a. Similarly, the lower portion of the conductive layer 76b may be formed to be embedded in the conductive layer 56b.

[0246] The conductive layers 76a and 76b function as vias that connect wirings or the like provided on the transistor 50B to the source or drain of the transistor 50B. The conductive layers 76a and 76b can be formed using the conductive materials described in the "Conductive Layer" section below. The conductive layers 76a and 76b are preferably formed using a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layers 76a and 76b may also have a stacked structure. For example, a stacked structure of a titanium nitride film and a tungsten film on the titanium nitride film can be used.

[0247] An insulating layer can be provided between the sidewall of the opening of the insulating layer 86 or the like and the conductive layer 76a. The insulating layer can have a barrier insulating layer against hydrogen. For example, silicon nitride can be used as the insulating layer. This can prevent impurities such as water and hydrogen contained in the insulating layer 86 or the like from being mixed into the semiconductor layer 51 through the conductive layer 76a. In addition, it can prevent oxygen contained in the insulating layer 86 from being absorbed by the conductive layer 76a. Note that the insulating layer can be provided between the sidewall of the opening of the insulating layer 86 or the like and the conductive layer 76b.

[0248] The conductive layer 78 is provided on the insulating layer 86. The conductive layer 78 is connected to the conductive layer 56a via the conductive layer 76a and to the conductive layer 56b via the conductive layer 76b. The conductive layer 78 functions as the other of the source wiring and the drain wiring. The conductive layer 78 extends in the Y direction. In other words, the direction in which the conductive layer 78 extends intersects with the direction in which the trench 67 extends.

[0249] In the transistors 50 and 50A, the conductive layer 56 is provided to extend, so the width of the conductive layer 56 in the X direction (short side) needs to be larger than the width of the opening 65. On the other hand, in the transistor 50B, the conductive layers 56a and 56b are connected via the conductive layer 78, so the widths of the conductive layers 56a and 56b in the X direction can be reduced, allowing for miniaturization of the semiconductor device. On the other hand, in the transistors 50 and 50A, it is not necessary to process the semiconductor layer 51 located in the opening 65, so processing the semiconductor layer 51 is easier, and productivity of the semiconductor device can be improved.

[0250] A side surface of the conductive layer 53 located in the groove 67 faces a side surface of the semiconductor layer 51 with the insulating layer 52 interposed therebetween. Therefore, the channel width of the transistor 50B is determined by the width in the X direction of the semiconductor layer 51 (width D shown in FIG. 10D ). The channel width of the transistor 50B can be calculated as twice the width in the X direction of the semiconductor layer 51.

[0251] FIG. 10B and other figures show an example in which the insulating layer 62 has a single-layer structure. The insulating layer 62 can also have a stacked structure of two or more layers. As shown in FIGS. 12A and 12B , the insulating layer 62 can have a three-layer structure including an insulating layer 62_1, an insulating layer 62_2 on the insulating layer 62_1, and an insulating layer 62_3 on the insulating layer 62_2. Providing the insulating layer 62_1 can prevent a portion of the insulating layer 87 from being exposed when forming a groove 67 in the insulating layer 62_2. This can increase the manufacturing yield of the semiconductor device and provide a semiconductor device that can be manufactured at low cost. For a plan view of the semiconductor device shown in FIGS. 12A and 12B , see FIG. 10A . For a cross-sectional view of the semiconductor device taken along the dashed-dotted line C1-C2 in FIG. 12A , see FIG. 10D .

[0252] In the transistor 50B, the height of the top surface of the conductive layer 53 is higher than the height of the top surface of the insulating layer 52. However, the present invention is not limited to this. The height of the top surface of the conductive layer 53 may be the same as the height of the top surface of the insulating layer 52 or may be lower than the height of the top surface of the insulating layer 52.

[0253] Fig. 13A is a plan view of a semiconductor device including a transistor 50C. Fig. 13B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 13A. Fig. 13C is a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 13A. Note that Fig. 10D can be referred to for a cross-sectional view taken along dashed dotted line C1-C2 in Fig. 13B.

[0254] In the transistor 50C, the top surface of the conductive layer 53 is located lower than the top surface of the insulating layer 52. This allows the physical distance between the conductive layer 53 and the conductive layer 78 to be increased, and the parasitic capacitance generated between the conductive layer 53 and the conductive layer 78 to be reduced.

[0255] The transistor 50C has a structure in which the parasitic capacitance generated between the other of the source wiring and the drain wiring and the gate wiring is reduced. Therefore, the frequency characteristics of a circuit using this transistor can be improved. On the other hand, in the transistor 50B, the cross-sectional area of ​​the conductive layer 53 functioning as the gate wiring can be increased, thereby reducing wiring resistance. Therefore, the power consumption of the semiconductor device can be reduced.

[0256] The conductive layer 53 of the transistor 50C can be formed by processing the entire surface of a conductive film that will become the conductive layer 53 by anisotropic etching. This reduces the number of manufacturing steps of a semiconductor device compared to forming the conductive layer 53 by photolithography. On the other hand, the conductive layer 53 of the transistor 50B can be formed by, for example, photolithography. That is, the conductive layer 53 can be formed by forming a mask on the conductive film that will become the conductive layer 53 and removing part of the conductive film by etching or the like. This makes it easier to form the conductive layer 53 in a desired shape compared to forming the conductive layer 53 by anisotropic etching.

[0257] Although the transistor 50C has been described as having one conductive layer 53 provided in one groove 67, the present invention is not limited to this. For example, two conductive layers 53 may be provided in one groove 67.

[0258] Fig. 14A is a plan view of a semiconductor device having a transistor 50D. Fig. 14B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 14A. Fig. 14C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 14A. Fig. 14D is a horizontal cross-sectional view taken along dashed dotted line B1-B2 in Fig. 14A. Fig. 14E is a cross-sectional view taken along dashed dotted line C1-C2 in Fig. 14B. The configurations shown in Figs. 14A to 14D show an example in which a transistor is provided using one of a pair of opposing side surfaces of groove portion 67.

[0259] The transistor 50D includes a conductive layer 55a, a conductive layer 56a, a semiconductor layer 51, an insulating layer 52, and a conductive layer 53. In the transistor 50D, the conductive layer 53 functions as a gate electrode, and the insulating layer 52 functions as a gate insulating layer. The conductive layer 55a functions as one of a source electrode and a drain electrode, and the conductive layer 56a functions as the other of the source electrode and the drain electrode.

[0260] The insulating layer 401 is provided on the insulating layer 62. The height of the top surface of the insulating layer 401 is equal to the height of the top surface of the conductive layer 56a and the height of the top surface of the conductive layer 56b. The insulating layer 401 can be formed, for example, by forming conductive layers that will become the conductive layers 56a and 56b, then depositing the insulating layer 401, and then performing a CMP process until the top surfaces of the conductive layers are exposed.

[0261] The groove 67 is located between the conductive layer 56a and the conductive layer 56b that are spaced apart from each other in a plan view.

[0262] The semiconductor layer 51 is provided so that at least a portion thereof is located in the groove portion 67. The semiconductor layer 51 has a portion in contact with the conductive layer 55a and a portion in contact with the conductive layer 56a. The insulating layer 52 is provided so as to cover the semiconductor layer 51. The conductive layer 53 is provided so as to have a portion overlapping with the semiconductor layer 51 with the insulating layer 52 interposed therebetween.

[0263] The insulating layer 402 is provided along the side surface of the conductive layer 53. The insulating layer 86 is provided on the insulating layer 52 and the conductive layer 53, the insulating layer 404 is provided on the insulating layer 402 and the insulating layer 86, the insulating layer 405 is provided on the insulating layer 404, and the conductive layer 78 is provided on the insulating layer 404 and the insulating layer 405. The height of the top surface of the insulating layer 404 is the same as the height of the top surface of the insulating layer 405.

[0264] The conductive layer 55a and the conductive layer 55b are provided separately with the insulating layer 404 and the insulating layer 405 sandwiched therebetween.

[0265] 14A to 14E , a first transistor can be provided using one of a pair of opposing side surfaces of the groove 67, and a second transistor can be provided using the other. This allows a semiconductor device with a high degree of transistor integration to be manufactured. Note that the first transistor and the second transistor have a symmetrical structure with respect to the insulating layer 405. Therefore, the structure of the second transistor can be understood by referring to the structure of the first transistor by replacing the conductive layer 55a with the conductive layer 55b and the conductive layer 56a with the conductive layer 56b.

[0266] In the transistor 50B, the conductive layer functioning as the gate wiring is provided so as to extend in the direction in which the groove portion 67 extends. However, the present invention is not limited to this. The direction in which the conductive layer functioning as the gate wiring extends may also intersect with the direction in which the groove portion 67 extends.

[0267] Fig. 15A is a plan view of a semiconductor device having a transistor 50E. Fig. 15B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 15A. Fig. 15C is a horizontal cross-sectional view taken along dashed dotted line B1-B2 in Fig. 15A. Fig. 15D is a cross-sectional view taken along dashed dotted line C1-C2 in Fig. 15B.

[0268] The semiconductor device shown in FIGS. 15A to 15D differs from the semiconductor device shown in FIGS. 10A to 10D mainly in that a conductive layer 77 is provided.

[0269] The conductive layer 53 is provided in an island shape. The conductive layer 77 is provided on the insulating layer 86 and the conductive layer 53, and is in contact with the top surface of the conductive layer 53. The conductive layer 53 and the conductive layer 77 are connected. The conductive layer 77 may be considered a component of the transistor 50E. The height of the top surface of the conductive layer 53 and the height of the top surface of the insulating layer 86 are the same. The conductive layer 77 functions as a gate wiring.

[0270] The conductive layers 56a and 56b are each provided to extend in the direction in which the groove 67 extends (X direction).

[0271] In the transistor 50E, the conductive layer 53 functions as a gate electrode, the insulating layer 52 functions as a gate insulating layer, the conductive layer 55 functions as one of a source electrode and a drain electrode, and the conductive layer 56a and the conductive layer 56b function as the other of the source electrode and the drain electrode.

[0272] <Manufacturing Method Example 2> Below, an example of a manufacturing method of the semiconductor device shown in Figures 10A to 10D will be described with reference to Figures 16A to 17F. Figures 16A, 16C, 16E, 17A, 17C, and 17E correspond to the plan view shown in Figure 10A, and Figures 16B, 16D, 16F, 17B, 17D, and 17F correspond to the cross-sectional views shown in Figure 10B. Note that descriptions of parts that overlap with those described above will be omitted, and only differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0273] The steps up to the formation of the insulating layer 62 are the same as those described above, and therefore will not be described here.

[0274] Next, a groove 67 is formed in the insulating layer 62, reaching the conductive layer 55 (FIGS. 16A and 16B). At this time, in the groove 67, the insulating layer 87 in a region that does not overlap with the conductive layer 55 may be exposed.

[0275] Subsequently, an insulating layer 74 and a layer 91 are formed in this order on the insulating layer 62 and the conductive layer 55 (FIGS. 16A and 16B).

[0276] Next, a CMP process is performed until the upper surface of the insulating layer 62 is exposed, thereby forming an insulating layer 74 and a layer 91 so as to fill the trench 67 (FIGS. 16C and 16D).

[0277] Next, a conductive layer 56f is formed on the insulating layer 62, the insulating layer 74, and the layer 91 (FIGS. 16E and 16F). The conductive layer 56f can be formed by depositing a conductive film that will become the conductive layer 56 and then processing the conductive film.

[0278] Next, a portion of the conductive layer 56f, the layer 91, and a portion of the insulating layer 74 are removed. For example, a resist mask (not shown) is formed in the groove 67 except for the region that does not overlap with the insulating layer 74a and the insulating layer 74b, and the conductive layer 56f, the layer 91, and the insulating layer 74 in the region where the resist mask is not formed are removed by etching ( FIGS. 17A and 17B ). By this etching process, the portion of the conductive layer 56f that overlaps with the groove 67 is removed, forming the conductive layers 56a and 56b from the conductive layer 56f, and the portion of the insulating layer 74 located between the conductive layers 56a and 56b is removed, forming the insulating layers 74a and 74b from the insulating layer 74. After the etching process, the resist mask is removed.

[0279] The shortest distance between the opposing side surfaces of the conductive layers 56a and 56b is preferably equal to or greater than the width of the groove 67 minus twice the film thickness of the insulating layer 74, and smaller than the width of the groove 67. This allows the insulating layer 74a to be formed so as to overlap the conductive layer 56a, and the insulating layer 74b to be formed so as to overlap the conductive layer 56b.

[0280] When performing the etching process, it is preferable to remove a portion of the conductive layer 55 in the region between the conductive layer 56a and the conductive layer 56b to provide a recess (the second recess described above) in the conductive layer 55.

[0281] Next, a semiconductor layer 51 is formed so as to cover the conductive layers 56a and 56b, etc. (FIGS. 17C and 17D). The semiconductor layer 51 can be formed by depositing a semiconductor film that will become the semiconductor layer 51 and then processing the semiconductor film. The semiconductor layer 51 is formed so as to be in contact with the upper and side surfaces of the conductive layer 56a, the side surfaces of the insulating layer 74a, the upper and side surfaces of the conductive layer 56b, the side surfaces of the insulating layer 74b, and the conductive layer 55.

[0282] If the selectivity of the insulating layers 74a and 74b to the semiconductor layer 51 is small, exposed regions of the insulating layers 74a and 74b may be removed when the semiconductor film is processed, leaving portions of the insulating layers 74a and 74b that overlap with the semiconductor layer 51 (see FIG. 17C ).

[0283] Subsequently, an insulating layer 52 is formed on the semiconductor layer 51 .

[0284] Next, a conductive layer 53 is formed over the insulating layer 52 (FIGS. 17E and 17F). The conductive layer 53 can be formed by depositing a conductive film that will become the conductive layer 53 and then processing the conductive film. In this manner, the transistor 50B can be manufactured.

[0285] Subsequently, an insulating layer 88 and an insulating layer 86 are formed in this order over the insulating layer 52 and the conductive layer 53. After the insulating layer 86 is formed, planarization treatment is performed to planarize the insulating layer 86. As the planarization treatment, for example, a CMP method can be used.

[0286] Next, the conductive layer 76 a and the conductive layer 76 b are formed. First, a first opening reaching the conductive layer 56 a and a second opening reaching the conductive layer 56 b are formed in the insulating layer 86, the insulating layer 88, the insulating layer 52, and the semiconductor layer 51, then a conductive film is formed so as to fill the first opening and the second opening, and then a CMP process is performed until the top surface of the insulating layer 86 is exposed, thereby forming the conductive layer 76 a and the conductive layer 76 b.

[0287] Subsequently, a conductive layer 78 is formed. Through the above steps, the semiconductor device shown in FIGS.

[0288] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0289] [Semiconductor Layer] Metal oxides other than indium oxide can also be used for the semiconductor layer 51. The metal oxide preferably contains at least one of indium and zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a higher bond energy with oxygen than indium.

[0290] Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, antimony, etc. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.

[0291] Examples of metal oxides that can be used for the semiconductor layer 51 include zinc oxide, In—Zn oxide, ITO, In—Ti oxide, In—Ga oxide, indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), Ga—Zn oxide, Al—Zn oxide, In—Al—Zn oxide, In—Sn—Zn oxide, In—Ti—Zn oxide, In—Ga—Zn oxide, indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as “IGZTO”), and indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as “IGAZO” or “IAGZO”). Alternatively, ITSO, gallium tin oxide (Ga—Sn oxide), and Al—Sn oxide can be used. These oxides can be used as insulating materials containing oxygen (also called oxide insulators) or oxide conductors depending on film formation conditions, composition, crystallinity, heat treatment after formation, and the like.

[0292] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide that functions as a semiconductor, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0293] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0294] The field-effect mobility of a transistor can be increased by increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide.Typically, the field-effect mobility of a transistor can be significantly increased by using single-crystal or polycrystalline indium oxide (also referred to as indium oxide) for a semiconductor layer.Furthermore, a transistor using single-crystal or polycrystalline indium oxide for a semiconductor layer can achieve good frequency characteristics.

[0295] A semiconductor material other than metal oxide may be used for the semiconductor layer 51. Examples of the semiconductor material include a semiconductor made of a single element and a compound semiconductor.

[0296] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0297] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0298] Furthermore, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as a material that can be used for the semiconductor layer 51. Specifically, the transition metal chalcogenide is molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0299] The crystallinity of the semiconductor material used for the semiconductor layer 51 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0300] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 52, insulating layer 62, insulating layer 84, insulating layer 85, insulating layer 86, insulating layer 87, insulating layer 88, insulating layer 89, insulating layer 401, insulating layer 402, insulating layer 404, insulating layer 405, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, and an oxynitride insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and an oxide film containing aluminum and hafnium. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. An organic insulating film may also be used for an insulating layer included in a semiconductor device.

[0301] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, using a material with a low dielectric constant for the insulating layer functioning as an interlayer film can reduce the parasitic capacitance generated between wirings. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0302] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, oxides containing hafnium and zirconium, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0303] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide and silicon oxynitride, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0304] Furthermore, a material capable of exhibiting ferroelectricity may be used for an insulating layer of a semiconductor device. As the material capable of exhibiting ferroelectricity, an oxide containing one or both of hafnium and zirconium is preferably used. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, as the material capable of exhibiting ferroelectricity, a material obtained by adding an element J1 (here, the element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to a metal oxide containing one of hafnium and zirconium may be used.

[0305] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0306] Furthermore, examples of materials that may have ferroelectricity include metal nitrides containing nitrogen and at least one of element M1 and element M2. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, examples of materials that may have ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0307] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Furthermore, examples of materials that can have ferroelectricity include lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0308] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, a material in which nitrogen is added to the above-mentioned metal oxides, or a material in which oxygen is added to the above-mentioned metal nitrides, may also be used.

[0309] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound of a plurality of materials selected from the materials listed above can be used. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material capable of exhibiting ferroelectricity.

[0310] In this specification, a layer of a material that may have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide layer, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide layer, or a metal nitride film may be referred to as a ferroelectric device.

[0311] The ferroelectric layer preferably contains crystals having an orthorhombic crystal structure, since this allows ferroelectricity to be exhibited. The crystal structure of the crystals contained in the ferroelectric layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure having an amorphous structure and a crystalline structure.

[0312] A metal oxide containing one or both of hafnium and zirconium is also an insulating material that has a function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing one or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor including the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0313] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or an oxynitride such as silicon oxynitride.

[0314] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium. Examples of nitrides include aluminum nitride, aluminum titanium nitride, and silicon nitride. Examples of oxynitrides include silicon oxynitride. Examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0315] An insulating layer such as a gate insulating layer that is in contact with or near an oxide semiconductor layer preferably has a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with or near an oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0316] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0317] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium, oxides containing hafnium and silicon, etc. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium.

[0318] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0319] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0320] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0321] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule or OH − . Furthermore, unless otherwise specified, impurities when described as a corresponding substance refer to impurities in a channel formation region or a semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0322] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxides containing hafnium and zirconium, silicon nitride, and silicon oxynitride.

[0323] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon oxynitride. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium, and oxides containing hafnium and silicon.

[0324] [Conductive Layer] For the conductive layers (conductive layer 53, conductive layer 55, conductive layer 55a, conductive layer 55b, conductive layer 56, conductive layer 56a, conductive layer 56b, conductive layer 60, conductive layer 76a, conductive layer 76b, conductive layer 77, conductive layer 78, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0325] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In—Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0326] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0327] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0328] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0329] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0330] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0331] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0332] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0333] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0334] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 18A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 18B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0335] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 18B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 18A (see Non-Patent Document 3). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 18A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 18A.

[0336] 18A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10１４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0337] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0338] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0339] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0340] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 18A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0341] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0342] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 9B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei is finally achieved, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the transistor may no longer function. On the other hand, in indium oxide, as shown in FIG. 9A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei is finally achieved, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0343] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0344] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0345] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0346] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0347] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0348] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0349] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0350] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0351] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0352] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0353] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0354] In addition, the indium oxide film in this specification and the like has a high film density. ２ O ３ The film densities of the films are shown in Table 1.

[0355]

[0356] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the condition of the base of the indium oxide film, Samples 1 to 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition of the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the formation of the indium oxide film, with Sample 1, Sample 4, and Sample 5 being no heat treatment (as-deposited), Sample 2 being baked at 350°C in a CDA atmosphere, Sample 3 being baked at 650°C in a CDA atmosphere, and Sample 6 being baked at 250°C in a vacuum atmosphere.

[0357] In Table 1, CDA stands for clean dry air. It is preferable that the atmosphere used in the heat treatment (condition 3) after the formation of the indium oxide film contains as little hydrogen and water as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower, as the atmosphere.

[0358] As shown in Table 1, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment removes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) from the film, thereby increasing the purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. ３ The theoretical film density of an indium oxide film is 7.18 g / cm ３ In this specification, the range of the film density of the indium oxide film is 6.70 g / cm ３ 7.18g / cm or more ３ Preferably, it is 6.90 g / cm or less.３ 7.18g / cm or more ３ More preferably, it is 7.00 g / cm or less. ３ 7.18g / cm or more ３ The following is the result.

[0359] The film density can be evaluated by, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated by cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image.

[0360] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0361] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 18C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0362] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0363] Furthermore, as shown in FIG. 18C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the film and is released as water molecules. The oxygen and hydrogen diffuse in the indium oxide film by heat treatment. The temperature of the heat treatment is 200° C. or higher and 700° C. or lower, preferably 350° C. or higher and 650° C. or lower, and more preferably 400° C. or higher and 500° C. or lower.

[0364] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0365] Table 2 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 2, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0366]

[0367] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0368] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0369] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0370] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0371] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0372] Here, a comparison is made among a transistor having a crystalline indium oxide film, a transistor having an IGZO (a compound oxide of In, Ga, and Zn) film, and a transistor having a silicon (Si) film. The comparison is shown in Table 3.

[0373]

[0374] In Table 3, transistors having a crystalline indium oxide film are intended for use in LSIs and are clearly indicated as crystalline IO (LSI). Hereinafter, this may be simply referred to as crystalline IO. Transistors having an IGZO film are intended for use in displays and are clearly indicated as IGZO (Display). Hereinafter, this may be simply referred to as IGZO. Transistors having a Si film are also clearly indicated as Si. In Table 3, ◎ represents +2 points, ○ represents +1 point, △ represents 0 points, and × represents −1 point, respectively. Total is the total value of the ◎, ○, △, and × points shown in Table 3. A higher score indicates better characteristics than a lower score.

[0375] In Table 3, the first comparison item is extremely small off-state current, with crystalline IO and IGZO being superior to Si. The second comparison item is on-state current (Ion) characteristics, with crystalline IO and Si being superior to IGZO. The third comparison item is reliability, with crystalline IO and Si being superior to IGZO. The fourth comparison item is miniaturization of channel length, with crystalline IO and IGZO being superior to Si. In the section on miniaturization of channel length, VFET represents a vertical transistor, UFET represents a transistor with a U-shape structure, and 3D structure represents a three-dimensional structure. The fifth comparison item is cutoff frequency, with the characteristics increasing in the order of crystalline IO, Si, and IGZO. The sixth comparison item is improvement in integration, with Si being superior to crystalline IO and IGZO. The seventh comparison item is threshold voltage controllability (Vth controllability), in which Si is superior to crystalline IO and IGZO. The eighth comparison item is radiation resistance, in which crystalline IO and IGZO are superior to Si. The ninth comparison item is 3D (multi-level) integrated structure, in which crystalline IO and IGZO are superior to Si. The tenth comparison item is the possibility of self-heating, in which crystalline IO and IGZO are superior to Si.

[0376] As shown in Table 3, the total score for crystalline IO (LSI) is 9 points, for IGZO (Display) is 4 points, and for Si is 3 points. As described above, the semiconductor device of one embodiment of the present invention, in particular the semiconductor device including a crystalline indium oxide film, has the potential to replace a semiconductor device using Si.

[0377] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0378] 19A to 23. The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0379] The configuration of a memory device having memory cells will be described with reference to Figures 19A to 20C. Figure 19A is a plan view of a memory device having memory cells 150. Figure 19B is a cross-sectional view taken along dashed line A1-A2 in Figure 19A. Figure 19C is a cross-sectional view taken along dashed line B1-B2 in Figure 19A.

[0380] 19A to 19C includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a memory cell 150 over the conductive layer 110, an insulating layer 180 over the conductive layer 110, and an insulating layer 62 over the insulating layer 180. The insulating layer 140 and the insulating layer 180 function as interlayer films. The conductive layer 110 functions as wiring.

[0381] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 50 over the capacitor 100 .

[0382] The capacitor 100 includes a conductive layer 115 on the conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 55 on the insulating layer 130. The conductive layer 55 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. In other words, the capacitor 100 constitutes a metal-insulator-metal (MIM) capacitor.

[0383] As shown in FIGS. 19B and 19C , an opening 190 is provided in the insulating layer 180, reaching the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190. The conductive layer 115 has a region in contact with the top surface of the conductive layer 110 in the opening 190 and a region in contact with the side surface of the insulating layer 180 in the opening 190. At least a portion of the insulating layer 130 is disposed in the opening 190. At least a portion of the conductive layer 55 is disposed in the opening 190. The conductive layer 55 is disposed so as to fill the opening 190. A capacitor 100 having such a configuration may be referred to as a trench capacitor or a trench capacitor. The films disposed in the opening 190 are preferably formed using an ALD method. This improves the coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 55 are preferably formed using an ALD method.

[0384] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across a dielectric not only on the bottom surface but also on the side surface of the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, this can promote miniaturization or high integration of memory devices.

[0385] 19B and 19C show an example in which the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110 and the opening 190 is circular in plan view. With such a configuration, miniaturization or high integration of the memory device can be achieved.

[0386] The conductive layer 110 functions as wiring CAL, which will be described later, and can be provided in, for example, a strip shape. Note that the strip shape refers to a shape having an area extending in a certain direction (for example, the X direction, the Y direction, or the Z direction).

[0387] The conductive layer 110 can be formed as a single layer or a stacked layer using the conductive material described in [Conductive Layer] in Embodiment 1. For example, a conductive material with high conductivity, such as tungsten, can be used for the conductive layer 110. By using a conductive material with high conductivity, the conductivity of the conductive layer 110 can be improved, and the conductive layer 110 can function sufficiently as a wiring CAL.

[0388] The conductive layer 115 has a region with rounded corners in the recess of the conductive layer 110. This makes it possible to suppress electric field concentration in the insulating layer 130 near the region, compared to when the region has a corner (right angle or acute angle) in cross-sectional view, for example. Therefore, it is possible to suppress dielectric breakdown of the insulating layer 130 and provide a highly reliable memory device.

[0389] The conductive layer 115 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion, and is used in a single layer or a stacked layer. For example, titanium nitride or ITSO may be used. Alternatively, for example, a structure in which a titanium nitride film is stacked on a tungsten film may be used. Alternatively, for example, a structure in which a tungsten film is stacked on a first titanium nitride film and a second titanium nitride film is stacked on the tungsten film may be used. With such a structure, when an oxide is used for the insulating layer 130, the insulating layer 130 can suppress oxidation of the conductive layer 115. Furthermore, when an oxide is used for the insulating layer 180, the insulating layer 180 can suppress oxidation of the conductive layer 115.

[0390] The insulating layer 130 is provided so as to contact the upper surface and side surfaces of the conductive layer 115. In other words, the insulating layer 130 is preferably structured to cover the side edges of the conductive layer 110. This can prevent the conductive layer 115 and the conductive layer 55 from shorting out.

[0391] It is preferable to use a high-k material for the insulating layer 130. By using a high-k material for the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitor 100 can be sufficiently ensured.

[0392] Furthermore, the insulating layer 130 is preferably formed by stacking insulating layers made of a high-k material, and preferably by using a stack structure of a high-k material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By stacking insulating layers having a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0393] Furthermore, a material that can have ferroelectricity may be used as the insulating layer 130. For details of the material that can have ferroelectricity, the description in Embodiment 1 can be referred to.

[0394] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor element 100, the memory device described in this embodiment functions as a ferroelectric memory.

[0395] The conductive layer 55 is provided in contact with the upper surface of the insulating layer 130. The side edges of the conductive layer 55 can be structured to coincide with the side edges of the insulating layer 130. By using this structure, the conductive layer 55 and the insulating layer 130 can be formed using the same mask, which can simplify the manufacturing process of the memory device. Note that the side edges of the conductive layer 55 may be structured to be located inside the side edges of the insulating layer 130 in either the X direction or the Y direction.

[0396] Since the insulating layer 180 functions as an interlayer film, it is preferable that the dielectric constant is low. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance occurring between wirings can be reduced.

[0397] The transistor 50 can be described in the first embodiment (transistor 50 shown in FIG. 1 ), and therefore a detailed description thereof will be omitted. The transistor included in the memory cell 150 is not limited to the transistor 50, and each of the transistors exemplified in the first embodiment can be applied. A transistor having a planar structure or a GAA (Gate All Around) structure (including a GAA nanosheet structure) can also be applied.

[0398] As shown in FIGS. 19A to 19C , the transistor 50 is provided to overlap with the capacitor 100. The opening 65, where part of the structure of the transistor 50 is provided, overlaps with the opening 190, where part of the structure of the capacitor 100 is provided. In particular, the conductive layer 55 functions as one of the source electrode and drain electrode of the transistor 50 and as the upper electrode of the capacitor 100. Therefore, the transistor 50 and the capacitor 100 share part of their structures. This structure allows the transistor 50 and the capacitor 100 to be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, thereby enabling the memory cells 150 to be densely arranged and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated. FIGS. 19B and 19C show an example in which the width of the opening 190 is smaller than the width of the opening 65. The relationship between the width of the opening 190 and the width of the opening 65 is not particularly limited. From the viewpoint of miniaturization, it is preferable that the width of the opening 190 be equal to or smaller than the width of the opening 65 .

[0399] Furthermore, by providing the transistor 50 above the capacitor 100, the transistor 50 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 50, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of the electrical characteristics, can be suppressed.

[0400] As shown in FIGS. 19A to 19C, the conductive layer 53 is provided extending in the X direction, and the conductive layer 56 is provided extending in the Y direction.

[0401] 19A to 19C function as a memory cell, which will be described in detail in a later embodiment.

[0402] The memory cell 150 may have a transistor instead of the capacitor element. In this case, the memory cell 150 has two transistors.

[0403] Fig. 20A is a plan view of the storage device, Fig. 20B is a cross-sectional view taken along dashed dotted lines A1-A2 in Fig. 20A, and Fig. 20C is a cross-sectional view taken along dashed dotted lines B1-B2 in Fig. 20A.

[0404] 20A to 20C includes a memory cell 150 over an insulating layer 87. The memory cell 150 includes a transistor 50a and a transistor 50b over the transistor 50a.

[0405] The transistors 50a and 50b can be described in detail in the same manner as in the transistor 50 in Embodiment 1 (the transistor 50 in FIG. 1 ), and therefore will not be described in detail again. The transistors included in the memory cell 150 are not limited to the combination of the transistors 50a and 50b, and one or more of the transistors exemplified in Embodiment 1 can be used. In addition, a transistor with a planar structure or a Gate All Around (GAA) structure can be used as one of the transistors 50a and 50b.

[0406] In the memory cell 150 shown in Figures 20A to 20C, the capacitance generated between the conductive layer 56 of the transistor 50a and the conductive layer 55 of the transistor 50b can be used, so that data can be retained without forming a separate capacitor.

[0407] As shown in FIGS. 20A and 20B , the transistor 50b is provided so as to overlap with the transistor 50a. The opening 65 where part of the structure of the transistor 50b is provided overlaps with the opening 65 where part of the structure of the transistor 50a is provided. In particular, the conductive layer 55 functions as one of the source electrode and drain electrode of the transistor 50b and as the gate electrode of the transistor 50a. Therefore, the transistors 50b and 50a share part of their structures. This structure allows the transistors 50b and 50a to be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cells 150, allowing the memory cells 150 to be arranged at a high density and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0408] As shown in FIGS. 20A to 20C, the conductive layer 53 is provided to extend in the X direction, and the conductive layer 56 of the transistor 50b is provided to extend in the Y direction.

[0409] 20A to 20C function as a memory cell, which will be described in detail in a later embodiment.

[0410] The memory cell 150 described in this embodiment can be used as a memory cell of a storage device. The transistor 50 is an OS transistor. Because the off-state current of the transistor 50 is small, the use of the transistor 50 in a storage device allows stored data to be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced. Furthermore, the high frequency characteristics of the transistor 50 enable high-speed reading and writing of data from and to the storage device.

[0411] A memory cell array can be configured by arranging a plurality of memory cells 150 in a matrix.

[0412] 21A to 22B show plan views of a memory device in which 6×3 memory cells are arranged in a matrix in the X and Y directions. Note that in Figs. 21A to 22B, some of the components of memory cell 150 are omitted to avoid complexity.

[0413] 21A shows a configuration in which memory cells 150 having transistors (for example, transistors 50 shown in FIGS. 1A to 1D ) whose components are partially provided in openings 65 are arranged in a matrix. As shown in FIG. 21A , 6×3 openings 65 are also arranged in a matrix.

[0414] 21B shows a configuration in which memory cells 150 having transistors (e.g., transistor 50C shown in FIGS. 13A to 13C ) with some of their components provided in grooves 67 are arranged in a matrix. As shown in FIG. 21B, three grooves 67 extending in the X direction are arranged. FIG. 21B also shows a configuration in which six memory cells are provided in each groove 67, resulting in an arrangement of 18 memory cells. From the above, if the number of memory cells arranged in one groove is m and the number of grooves in the memory cell array is n, then (m×n) memory cells (m and n are integers of 2 or greater, independently of each other) are arranged in the memory cell array.

[0415] The present invention is not limited to the above. For example, a groove 67 may be provided for each data unit. Specifically, two grooves 67 may be provided for each data unit. ｋ (k is an integer equal to or greater than 1) memory cells can be provided. In Fig. 22A, a groove 67 is provided every two memory cells 150 (two bits) in the X direction. In Fig. 22B, a groove 67 is provided every four memory cells 150 (four bits, one nibble) in the X direction.

[0416] A memory cell array can be configured by arranging the memory cells 150 in a three-dimensional matrix. By stacking layers (also called memory layers) each having a plurality of memory cells, the cells can be integrated and arranged without increasing the area occupied by the memory cell array. In other words, a 3D memory cell array can be configured.

[0417] FIG. 23 shows an example of a cross-sectional configuration of a memory device in which a memory layer is stacked on a layer in which a driver circuit including a sense amplifier is provided.

[0418] 23, a memory cell 150 is provided above a transistor 300. The transistor 300 is one of the transistors included in the sense amplifier. For the memory cell 150 shown in FIG. 23, the description of the memory cell 150 described above can be referred to.

[0419] 23, the bit lines can be shortened by providing a sense amplifier so as to overlap the memory cells 150. This reduces the bit line capacitance, enabling the memory device to be driven at high speed.

[0420] 23 can correspond to the semiconductor device 900 described in Embodiment 4. Specifically, the transistor 300 corresponds to a transistor included in a sense amplifier 927 in the semiconductor device 900. The memory cell 150 corresponds to a memory cell 950.

[0421] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel or n-channel transistor. The substrate 311 preferably contains a silicon-based semiconductor, specifically, single-crystal silicon.

[0422] Alternatively, the substrate 311 may be a structure in which a single-crystal oxide semiconductor film (typically, an indium oxide film) is provided on a stabilized zirconia substrate. The indium oxide film formed on the stabilized zirconia substrate has single crystallinity. By using a part of the indium oxide film as the semiconductor region 313, the field-effect mobility of the transistor 300 can be increased. Furthermore, the reliability of the transistor 300 can be improved.

[0423] Here, in the transistor 300 shown in FIG. 23 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0424] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer functioning as a plug or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0425] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 300. A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as plugs or wirings.

[0426] The insulating layer serving as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0427] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in Fig. 23, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0428] The insulating layer 352, the insulating layer 354, and the like, which function as interlayer films, can be formed using the above-described insulating layer that can be used in a semiconductor device or a memory device.

[0429] For conductive layers functioning as plugs or wirings, such as the conductive layer 328, the conductive layer 330, and the conductive layer 356, a conductive material applicable to the conductive layer 56 can be used. A high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity is preferably used, and tungsten is preferably used. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

[0430] The conductive layer 56 of the transistor 50 is connected to the low-resistance region 314b through the conductive layer 381, the conductive layer 382, ​​the conductive layer 383, the conductive layer 384, the conductive layer 371, the conductive layer 356, the conductive layer 330, and the conductive layer 328.

[0431] The conductive layer 381 is buried in the insulating layer 62. The conductive layer 382 is provided over the insulating layer 130 and buried in the insulating layer 62. The conductive layer 382 can be manufactured using the same material and in the same process as the conductive layer 55. The conductive layer 383 is buried in the insulating layer 180 and the insulating layer 130. The conductive layer 384 is buried in the insulating layer 180. The conductive layer 384 can be manufactured using the same material and in the same process as the conductive layer 110. The conductive layer 371 is buried in the insulating layer 372. The transistor 300 and the conductive layer 110 are insulated by the insulating layer 372.

[0432] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0433] Embodiment 4 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0434] Fig. 24 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 24 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 24 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0435] The memory cell 950 can be any of the memory devices described in Embodiment 3 (such as the memory cell 150 ).

[0436] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0437] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0438] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0439] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0440] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0441] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0442] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0443] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0444] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ The signal PON1 controls the on / off of the PSW 931, and the signal PON2 controls the on / off of the PSW 932. In FIG. 24, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0445] 25A to 25H, other examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0446] 25A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0447] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0448] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0449] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0450] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0451] 19A to 19C is an example of the memory cell 951 shown in Fig. 25A. For example, the transistor M1 corresponds to the transistor 50, and the capacitor CA corresponds to the capacitor 100. The wiring BIL corresponds to the conductive layer 56, the wiring WOL corresponds to the conductive layer 53, and the wiring CAL corresponds to the conductive layer 110.

[0452] 19A , the wiring BIL (conductive layer 56) and the wiring WOL (conductive layer 53) are provided so as to intersect with each other. Furthermore, the wiring CAL (conductive layer 110) is provided parallel to the wiring WOL (conductive layer 53). However, the present invention is not limited to this. For example, the wiring CAL may be provided parallel to the wiring BIL (conductive layer 56).

[0453] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, a configuration in which one wiring BIL is provided in common for two or more memory cells may be used. Alternatively, for example, the configuration of the memory cell 952 shown in FIG. 25B may be used. The memory cell 952 is an example in which the memory cell 952 does not include the capacitor element CA and the wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0454] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0455] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of having an extremely small off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, because the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0456] 25C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0457] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0458] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0459] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0460] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0461] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 25D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0462] 25E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 25F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0463] Note that it is preferable to use an OS transistor for at least the transistor M2. In particular, it is preferable to use OS transistors for the transistors M2 and M3. By using an OS transistor as the transistor M2, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cells 953 to 956.

[0464] The memory cells 953 to 956 in which an OS transistor is used as the transistor M2 are one embodiment of NOSRAM.

[0465] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0466] 20A to 20C is an example of the memory cell 955 shown in Fig. 25E. For example, the transistor M2 corresponds to the transistor 50b, and the transistor M3 corresponds to the transistor 50a. The wiring WBL corresponds to the conductive layer 56 of the transistor 50b, and the wiring WOL corresponds to the conductive layer 53.

[0467] In FIG. 20A, the wiring WBL (the conductive layer 56 included in the transistor 50b) and the wiring WOL (the conductive layer 53) are provided so as to intersect with each other.

[0468] 25G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0469] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0470] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0471] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0472] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0473] Note that at least the transistor M4 is preferably an OS transistor.

[0474] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0475] 25H shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 25H is a memory cell of an SRAM capable of backing up data.

[0476] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0477] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0478] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0479] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0480] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0481] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0482] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0483] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0484] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0485] Data is read by precharging the wirings BIL and BILB to a predetermined potential in advance, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL, so that the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. Also, the potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. In the wirings BIL and BILB, the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1 change from the precharged potentials, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0486] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

[0487] Note that Si transistors may be used as the transistors MS1 to MS4.

[0488] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 26A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 26B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0489] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0490] 27 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 27 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0491] The arithmetic device 960 shown in FIG. 27 has an ALU 962 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 969 and the cache interface 969i may also be provided on separate chips.

[0492] The cache 969 is connected to a main memory provided on a separate chip via a cache interface 969i. The cache interface 969i has a function of supplying part of the data held in the main memory to the cache 969. The cache interface 969i also has a function of outputting part of the data held in the cache 969 to the ALU 962, register 966, etc. via the bus interface 968.

[0493] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have a function of supplying data held in the memory array 920 to the cache 969. In this case, it is preferable that a drive circuit 910 be provided as part of the cache interface 969i.

[0494] It is also possible to use only the memory array 920 as a cache without providing the cache 969 .

[0495] The arithmetic device 960 shown in FIG. 27 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 27 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0496] An instruction input to the arithmetic unit 960 via the bus interface 968 is input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, the interrupt controller 964, the register controller 967, and the timing controller 965.

[0497] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals for controlling the operation of the ALU 962. Furthermore, the interrupt controller 964 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 967 generates an address for the register 966 and reads and writes data from and to the register 966 depending on the state of the arithmetic unit 960.

[0498] Furthermore, the timing controller 965 generates signals that control the timing of the operations of the ALU 962, the ALU controller 962c, the instruction decoder 963, the interrupt controller 964, and the register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0499] 27, the register controller 967 selects the holding operation in the register 966 in accordance with an instruction from the ALU 962. That is, it selects whether the memory cells in the register 966 will hold data using flip-flops or using capacitors. If holding data using flip-flops is selected, a power supply potential is supplied to the memory cells in the register 966. If holding data using capacitors is selected, the data is rewritten to the capacitors, and the supply of power supply potential to the memory cells in the register 966 can be stopped.

[0500] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 28A and 28B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 28B.

[0501] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0502] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0503] Here, the arithmetic unit 960 does not have a cache 969, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0504] When the cache 969 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0505] 28B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0506] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0507] When the memory array 920L1 is used as a cache, the driver 910L1 may function as part of the cache interface 969i, or may be configured to be connected to the cache interface 969i. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 969i, or may be configured to be connected thereto.

[0508] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0509] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0510] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 29A shows a perspective view of a semiconductor device 970B.

[0511] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Figure 29A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0512] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0513] Also, multiple memory arrays may be stacked. Figure 29B shows a perspective view of a semiconductor device 970C.

[0514] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0515] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0516] Embodiment 5 In this embodiment, an example of a CMOS circuit configuration using a Si transistor and an OS transistor according to one embodiment of the present invention will be described.

[0517] Si transistors have higher field-effect mobility and faster operation speed than OS transistors. Furthermore, OS transistors have significantly lower off-state current than Si transistors. In particular, OS transistors that use indium oxide for the semiconductor layer in which a channel is formed have significantly lower off-state current and higher field-effect mobility comparable to that of Si transistors. A CMOS circuit with low power consumption and high-speed operation can be realized by using an OS transistor and a Si transistor in combination.

[0518] In this embodiment, examples of circuits using Si transistors and OS transistors will be described, including a NOT circuit, a NOR circuit, and a NAND circuit, which are logic circuits. Also, examples of delay flip-flop (DFF) circuits and a shift register circuit using the DFF circuits will be described.

[0519] [NOT Circuit] Figure 30A is a circuit diagram showing an example configuration of a NOT circuit (NOT). A NOT circuit is also called an inversion circuit, inverter circuit, etc. Figure 30B shows the circuit symbol for a NOT circuit. Figure 30C is a timing chart explaining the operation of the NOT circuit.

[0520] The NOT circuit shown in FIG. 30A includes transistors Tr11 and Tr12. The transistor Tr11 is a Si transistor functioning as a p-type transistor, and the transistor Tr12 is an OS transistor functioning as an n-type transistor. A potential H (e.g., a high power supply potential VDD) is supplied to one of the source and the drain of the transistor Tr11. The other of the source and the drain of the transistor Tr11 is connected to one of the source and the drain of the transistor Tr12 and to a terminal Y. A potential L (e.g., a low power supply potential VSS) is supplied to the other of the source and the drain of the transistor Tr12. The gates of the transistors Tr11 and Tr12 are connected to a terminal A.

[0521] 30A, terminal A functions as an input terminal, and terminal Y functions as an output terminal. When a potential H is input to terminal A of the NOT circuit, a potential L is output from terminal Y, and when a potential L is input to terminal A, a potential H is output from terminal Y (see FIG. 30C).

[0522] 30C, the NOT circuit has the function of correcting an input signal distorted by wiring resistance, parasitic capacitance, noise, etc., to a signal that is distorted or has reduced distortion, and outputting the corrected signal. The NOT circuit also has the function of amplifying the voltage amplitude of the input signal, and the output of the NOT circuit is supplied to a load such as a capacitance element Cx and a transistor Trx.

[0523] An example of the structure of a NOT circuit will now be described with reference to FIG. 31 . As shown in FIG. 31 , a transistor Tr12 is provided above a transistor Tr11. An insulating layer 88, an insulating layer 86, an insulating layer 84, and an insulating layer 85 are stacked in this order on the transistor Tr12, and a wiring region 287 is provided on the insulating layer 85. The wiring region 287 includes an insulating layer 293 on the insulating layer 85, and an insulating layer 288 and conductive layers 248a to 248d on the insulating layer 293. The conductive layers 248a to 248d are embedded in the insulating layer 288.

[0524] The transistor Tr11 is a modified example of the transistor 300 shown in Fig. 23 and has a so-called planar configuration. The same components of the transistor Tr11 as those of the transistor 300 shown in Fig. 23 are denoted by the same reference numerals. For details of the transistor Tr11, the description of the transistor 300 can be referred to.

[0525] The transistor Tr12 can be described with reference to the description of the transistor 50 in the first embodiment (the transistor 50 shown in FIGS. 1A to 1D), and therefore detailed description thereof will be omitted.

[0526] The low-resistance region 314a functions as one of the source and drain of the transistor Tr11, and is connected to a conductive layer 248a provided in the wiring region 287 via one or more conductive layers functioning as a plug or wiring. A potential H is supplied to the conductive layer 248a.

[0527] The low-resistance region 314b functions as the other of the source and drain of the transistor Tr11, and is connected to a conductive layer 55 that functions as one of the source and drain of the transistor Tr12. The conductive layer 55 is connected to a conductive layer 248b provided in the wiring region 287 via one or more conductive layers that function as a plug or wiring. The conductive layer 248b functions as a terminal Y.

[0528] The conductive layer 56 functions as the other of the source and the drain of the transistor Tr12, and is connected to a conductive layer 248c provided in the wiring region 287 via one or more conductive layers functioning as a plug or a wiring. A potential L is supplied to the conductive layer 248c.

[0529] The conductive layer 316 functions as the gate electrode of the transistor Tr11 and is connected to the conductive layer 248d provided in the wiring region 287 via one or more conductive layers functioning as a plug or wiring. The conductive layer 53 functions as the gate electrode of the transistor Tr12 and is connected to the conductive layer 248d via one or more conductive layers functioning as a plug or wiring. The conductive layer 248d functions as the terminal A.

[0530] By configuring a NOT-type circuit in which all transistors Tr11 formed on the substrate 311 are p-type transistors and all transistors Tr12 formed above them are n-type transistors, it is possible to simplify complex processes such as the formation of element isolation layers, and to improve the productivity of semiconductor devices including the circuit.

[0531] [NOR Circuit] Fig. 32A is a circuit diagram showing an example of the configuration of a two-input, one-output NOR circuit (NOR). Fig. 32B shows a circuit symbol for the NOR circuit. The NOR circuit shown in Fig. 32A includes transistors Tr21, Tr22, Tr23, and Tr24. Si transistors functioning as p-channel transistors are used as the transistors Tr21 and Tr22, and OS transistors functioning as n-channel transistors are used as the transistors Tr23 and Tr24.

[0532] 32A , a potential H is supplied to one of the source or drain of transistor Tr21. The other of the source or drain of transistor Tr21 is connected to one of the source or drain of transistor Tr22. The other of the source or drain of transistor Tr22 is connected to one of the source or drain of transistor Tr23, one of the source or drain of transistor Tr24, and terminal Y. A potential L is supplied to the other of the source or drain of transistor Tr23 and the other of the source or drain of transistor Tr24.

[0533] The gate of the transistor Tr21 is connected to the gate of the transistor Tr23 and the terminal A. The gate of the transistor Tr22 is connected to the gate of the transistor Tr24 and the terminal B.

[0534] 32A and 32B has a function of outputting a potential H from a terminal Y when a potential L is input to both a terminal A and a terminal B. In addition, the NOR circuit has a function of outputting a potential L from a terminal Y when a potential H is input to one or both of the terminals A and B.

[0535] Furthermore, as shown in FIG. 32C, an OR circuit can be realized by connecting the input of a NOT circuit to the output of a NOR circuit.

[0536] [NAND Circuit] Fig. 32D is a circuit diagram showing a configuration example of a two-input, one-output NAND circuit (NAND). Fig. 32E shows a circuit symbol of the NAND circuit. The NAND circuit shown in Fig. 32D includes transistors Tr31, Tr32, Tr33, and Tr34. Si transistors functioning as p-channel transistors are used as the transistors Tr31 and Tr32, and OS transistors functioning as n-channel transistors are used as the transistors Tr33 and Tr34.

[0537] 32D, a potential H is supplied to one of the source or drain of transistor Tr31 and one of the source or drain of transistor Tr32. The other of the source or drain of transistor Tr31 and the other of the source or drain of transistor Tr32 are connected to one of the source or drain of transistor Tr33 and terminal Y. The other of the source or drain of transistor Tr33 is connected to one of the source or drain of transistor Tr34. A potential L is supplied to the other of the source or drain of transistor Tr34.

[0538] The gate of the transistor Tr31 is connected to the gate of the transistor Tr34 and the terminal B. The gate of the transistor Tr32 is connected to the gate of the transistor Tr33 and the terminal A.

[0539] 32D and 32E has a function of outputting a potential L from a terminal Y when a potential H is input to both the terminal A and the terminal B. In addition, the NAND circuit has a function of outputting a potential H from a terminal Y when a potential L is input to one or both of the terminal A and the terminal B.

[0540] Furthermore, as shown in FIG. 32F, an AND circuit can be realized by combining a NAND circuit with a NOT circuit.

[0541] [DFF Circuit] Fig. 33A is a circuit diagram showing an example of the configuration of a D flip-flop circuit (DFF). Fig. 33B shows the circuit symbol of the D flip-flop circuit. The DFF has a clock signal input terminal CK, an input terminal D, and an output terminal Q.

[0542] 33A includes transistors Tr41 to Tr49, transistors Tr51 to Tr59, transistor Tr61, transistor Tr62, transistor Tr71, and transistor Tr72. Si transistors functioning as p-channel transistors are used as the transistors Tr41 to Tr49, transistors Tr61, and transistor Tr62, and OS transistors functioning as n-channel transistors are used as the transistors Tr51 to Tr59, transistors Tr71, and transistor Tr72.

[0543] A potential H is supplied to one of the source or drain of transistor Tr41, one of the source or drain of transistor Tr42, one of the source or drain of transistor Tr44, one of the source or drain of transistor Tr46, one of the source or drain of transistor Tr48, one of the source or drain of transistor Tr61, and one of the source or drain of transistor Tr62.

[0544] The other of the source or drain of transistor Tr41 is connected to one of the source or drain of transistor Tr51, the gate of transistor Tr44, the gate of transistor Tr46, the gate of transistor Tr53, and the gate of transistor Tr59. The gate of transistor Tr41 is connected to clock signal input terminal CK, the gate of transistor Tr51, the gate of transistor Tr42, the gate of transistor Tr48, the gate of transistor Tr55, and the gate of transistor Tr57.

[0545] The other of the source or drain of transistor Tr42 is connected to one of the source or drain of transistor Tr43. The other of the source or drain of transistor Tr44 is connected to one of the source or drain of transistor Tr45. The other of the source or drain of transistor Tr43 is connected to the other of the source or drain of transistor Tr45, one of the source or drain of transistor Tr52, one of the source or drain of transistor Tr54, the gate of transistor Tr61, and the gate of transistor Tr71. The gate of transistor Tr43 is connected to the gate of transistor Tr52 and input terminal D.

[0546] The other of the source or drain of transistor Tr52 is connected to one of the source or drain of transistor Tr53. The other of the source or drain of transistor Tr54 is connected to one of the source or drain of transistor Tr55. The gate of transistor Tr45 is connected to the gate of transistor Tr54, the other of the source or drain of transistor Tr61, one of the source or drain of transistor Tr71, the gate of transistor Tr47, and the gate of transistor Tr56. The other of the source or drain of transistor Tr46 is connected to one of the source or drain of transistor Tr47. The other of the source or drain of transistor Tr48 is connected to one of the source or drain of transistor Tr49.

[0547] The other of the source or drain of transistor Tr47 is connected to one of the source or drain of transistor Tr56, the other of the source or drain of transistor Tr49, one of the source or drain of transistor Tr58, the gate of transistor Tr62, and the gate of transistor Tr72. The other of the source or drain of transistor Tr62 is connected to one of the source or drain of transistor Tr72, the gate of transistor Tr49, the gate of transistor Tr58, and output terminal Q.

[0548] The other of the source or the drain of transistor Tr56 is connected to one of the source or the drain of transistor Tr57. The other of the source or the drain of transistor Tr58 is connected to one of the source or the drain of transistor Tr59. A potential L is supplied to the other of the source or the drain of transistor Tr51, the other of the source or the drain of transistor Tr53, the other of the source or the drain of transistor Tr55, the other of the source or the drain of transistor Tr71, the other of the source or the drain of transistor Tr57, the other of the source or the drain of transistor Tr59, and the other of the source or the drain of transistor Tr72.

[0549] 33A and 33B has a function in which, while a potential H is being input to the clock signal input terminal CK, information (potential) supplied to the input terminal D is written to the DFF, and when the signal input to the clock signal input terminal CK changes from potential H to potential L, the information is held until the next time potential H is input to the clock signal input terminal CK. In addition, a signal (potential H or potential L) based on the information held by the DFF is always output from the output terminal Q.

[0550] FIG. 34A is a block diagram showing an example configuration of a shift register circuit (SR). The SR includes multiple DFFs. In this specification and elsewhere, the first-stage (first) DFF is referred to as "DFF[1]," and the potential (data) output from the output terminal Q of DFF[1] is referred to as "DATA OUT[1]." FIG. 34A shows a block diagram of an SR including four stages (four) of DFFs (DFF[1] to DFF[4]). In FIG. 34A, the data output from the output terminals Q of DFF[1] to DFF[4] are referred to as DATA OUT[1] to DATA OUT[4].

[0551] 34B is a timing chart illustrating the operation of the SR. A clock signal CLK is input to the clock signal input terminal CK of the odd-numbered DFF. An inverted version of the signal CLK is input to the clock signal input terminal CK of the even-numbered DFF.

[0552] A pulse signal SPL is input to the input terminal D of DFF[1]. DFF[1] holds a signal corresponding to the input signal SPL in synchronization with the signal CLK and outputs it as data OUT[1]. Note that data OUT[1] has a value corresponding to the data held by DFF[1].

[0553] Furthermore, data OUT[1] is input to input terminal D of DFF[2]. DFF[2] holds a signal corresponding to the input data OUT[1] in synchronization with signal CLK and outputs it as data OUT[2]. Similarly, data OUT[2] is input to input terminal D of DFF[3], and data OUT[3] is input to input terminal D of DFF[4].

[0554] In this way, the SR has the function of sequentially transferring the input signal SPL to the subsequent DFF in synchronization with the signal CLK, and also has the function of sequentially switching the potential of the data OUT output from the multiple DFFs in synchronization with the signal CLK.

[0555] Furthermore, it is preferable to provide an overlapping structure between a Si transistor and an OS transistor. By providing an overlapping structure between a Si transistor and an OS transistor, a circuit with a small occupancy area can be realized. Furthermore, an OS transistor operates stably even in a high-temperature environment and exhibits little fluctuation in characteristics. Therefore, the OS transistor is less susceptible to the heat generated by the Si transistor and can operate stably. Furthermore, by providing an overlapping structure between a Si transistor and an OS transistor, the connection distance between them can be made extremely short. As a result, wiring resistance and parasitic capacitance are reduced, enabling the circuit to operate at high speed. Furthermore, the power consumption of the circuit is reduced.

[0556] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0557] Embodiment 6 In this embodiment, application examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 35A to 36E.

[0558] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0559] Furthermore, a display device including the semiconductor device of one embodiment of the present invention can be used as a display portion of various electronic devices. A display device including the semiconductor device of one embodiment of the present invention can easily achieve high definition and high resolution.

[0560] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0561] In particular, the display device of one embodiment of the present invention can have high resolution and can therefore be suitably used in electronic devices having a relatively small display area. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and mixed reality (MR) devices.

[0562] The display device of one embodiment of the present invention preferably has extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 7000 ppi or more. By using a display device having such high resolution and / or high resolution, it is possible to further enhance the sense of realism and depth. The display device of one embodiment of the present invention is not particularly limited in terms of the screen ratio (aspect ratio). For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, or 16:10.

[0563] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0564] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0565] [Electronic Component] FIG. 35A shows a perspective view of a substrate (mounting substrate 819) on which electronic component 810 is mounted. Electronic component 810 shown in FIG. 35A has semiconductor device 811 inside mold 814. FIG. 35A omits some parts to show the interior of electronic component 810. Electronic component 810 has lands 815 on the outside of mold 814. Lands 815 are connected to electrode pads 816, and electrode pads 816 are connected to semiconductor device 811 via wires 817. Electronic component 810 is mounted on, for example, a printed circuit board 818. A plurality of such electronic components are combined and connected on printed circuit board 818 to complete mounting substrate 819.

[0566] The semiconductor device 811 also includes a drive circuit layer 812 and a memory layer 813. The memory layer 813 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 812 and the memory layer 813 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 812 and the memory layer 813, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0567] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0568] It is also preferable that the memory cell arrays included in the memory layer 813 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 813, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0569] The semiconductor device 811 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into dices during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0570] 35B shows a perspective view of electronic component 820. Electronic component 820 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 820 has an interposer 821 provided on a package substrate 822 (printed circuit board), and a semiconductor device 824 and a plurality of semiconductor devices 811 provided on interposer 821.

[0571] The electronic component 820 shows an example in which the semiconductor device 811 is used as a high bandwidth memory (HBM). The semiconductor device 824 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0572] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 822. For example, a silicon interposer or a resin interposer can be used as the interposer 821.

[0573] The interposer 821 has a plurality of wirings and functions to connect a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or in multiple layers. The interposer 821 also functions to connect the integrated circuits provided on the interposer 821 to electrodes provided on the package substrate 822. For these reasons, the interposer may be called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 821, and the integrated circuits and the package substrate 822 are connected using the through electrodes. In addition, in a silicon interposer, TSVs may also be used as through electrodes.

[0574] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0575] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0576] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 820, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0577] A heat sink (heat dissipation plate) may be provided so as to overlap the electronic component 820. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 821. For example, in the electronic component 820 shown in this embodiment, it is preferable to align the height of the semiconductor device 811 and the height of the semiconductor device 824.

[0578] Electrodes 823 may be provided on the bottom of the package substrate 822 in order to mount the electronic component 820 on another substrate. FIG. 35B shows an example in which the electrodes 823 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 822, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 823 may be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 822, PGA (Pin Grid Array) mounting can be achieved.

[0579] The electronic component 820 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0580] [Mainframe] Next, Fig. 36A shows a perspective view of a mainframe 830. The mainframe 830 shown in Fig. 36A has a rack 831 housing a plurality of rack-mounted computers 832. The mainframe 830 may also be called a supercomputer.

[0581] The computer 832 can have the configuration shown in the perspective view in Fig. 36B, for example. In Fig. 36B, the computer 832 has a motherboard 842, which has a plurality of slots 843 and a plurality of connection terminals. A PC card 833 is inserted into the slot 843. In addition, the PC card 833 has connection terminals 835, 836, and 837, which are each connected to the motherboard 842.

[0582] PC card 833 shown in Figure 36C is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 833 has board 834. Board 834 also has connection terminals 835, 836, 837, semiconductor devices 838, 839, 840, and connection terminal 841. Note that Figure 36C illustrates semiconductor devices other than semiconductor devices 838, 839, and 840, but for these semiconductor devices, the following descriptions of semiconductor devices 838, 839, and 840 can be referenced.

[0583] The connection terminal 841 has a shape that allows it to be inserted into a slot 843 of the motherboard 842, and functions as an interface for connecting the PC card 833 and the motherboard 842. An example of the standard for the connection terminal 841 is PCIe.

[0584] The connection terminals 835, 836, and 837 can be, for example, interfaces for supplying power to the PC card 833, inputting signals, and the like. They can also be, for example, interfaces for outputting signals calculated by the PC card 833. Examples of standards for the connection terminals 835, 836, and 837 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from the connection terminals 835, 836, and 837, examples of standards for the respective terminals include HDMI (registered trademark).

[0585] The semiconductor device 838 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 838 can be connected to the board 834 by inserting the terminal into a socket (not shown) provided on the board 834.

[0586] The semiconductor device 839 has a plurality of terminals, and the semiconductor device 839 can be connected to the board 834 by, for example, reflow soldering the terminals to wiring provided on the board 834. Examples of the semiconductor device 839 include an FPGA, a GPU, and a CPU. For example, the electronic component 820 can be used as the semiconductor device 839.

[0587] The semiconductor device 840 has a plurality of terminals, and the semiconductor device 840 can be connected to the board 834 by, for example, soldering the terminals to wiring provided on the board 834 using a reflow method. An example of the semiconductor device 840 is a memory device. For example, the electronic component 820 can be used as the semiconductor device 840.

[0588] The mainframe computer 830 can also function as a parallel computer. By using the mainframe computer 830 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, learning and inference in artificial intelligence.

[0589] [Space Equipment] The semiconductor device according to one embodiment of the present invention is suitable for space equipment.

[0590] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, an OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in an environment where radiation may be incident. For example, an OS transistor is suitable for use in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0591] Fig. 36D shows an artificial satellite 850 as an example of space equipment. The artificial satellite 850 has a body 851, a solar panel 852, an antenna 853, a secondary battery 855, and a control device 856. Note that Fig. 36D also shows a planet 854 in space.

[0592] 36D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 855. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0593] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0594] When sunlight is irradiated onto the solar panel 852, the power required for the operation of the satellite 850 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 850 will not be generated. In order to operate the satellite 850 even in a situation where the generated power is small, it is advisable to provide a secondary battery 855 on the satellite 850. The solar panel may also be called a solar cell module.

[0595] The artificial satellite 850 can generate a signal. The signal is transmitted via an antenna 853, and can be received by, for example, a receiver installed on the ground or another artificial satellite. By receiving the signal transmitted by the artificial satellite 850, the position of the receiver that received the signal can be determined. As described above, the artificial satellite 850 can constitute a satellite positioning system.

[0596] The control device 856 has a function of controlling the artificial satellite 850. The control device 856 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 856 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0597] The artificial satellite 850 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 850 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 850 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 850 can function as, for example, an earth observation satellite.

[0598] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention is suitable for space equipment such as a spaceship, a space capsule, and a space probe.

[0599] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0600] [Data Center] The semiconductor device according to one embodiment of the present invention is suitable for a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring the immutability of data. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0601] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0602] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0603] Fig. 36E shows a storage system applicable to a data center. The storage system 860 shown in Fig. 36E has a plurality of servers 861sb as hosts 861. It also has a plurality of storage devices 863md as storage 863. The host 861 and storage 863 are shown connected via a storage area network 864 and a storage control circuit 862.

[0604] The host 861 corresponds to a computer that accesses data stored in the storage 863. The hosts 861 may be connected to each other via a network.

[0605] Although the storage 863 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 863, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0606] The cache memory described above is used in the storage control circuit 862 and the storage 863. Data exchanged between the host 861 and the storage 863 is stored in the cache memory in the storage control circuit 862 and the storage 863, and then output to the host 861 or the storage 863.

[0607] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0608] Note that the semiconductor device of one embodiment of the present invention can reduce power consumption by applying it to any one or more of electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0609] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0610] 50: transistor, 50A: transistor, 50a: transistor, 50B: transistor, 50b: transistor, 50C: transistor, 50D: transistor, 50E: transistor, 51: semiconductor layer, 51_1: semiconductor layer, 51_2: semiconductor layer, 52: insulating layer, 53: conductive layer, 55: conductive layer, 55a: conductive layer, 55b: conductive layer, 56: conductive layer, 56a: conductive layer, 56b: conductive layer, 56f: conductive layer, 57: seed layer, 60: conductive layer, 62: insulating layer, 62_1: insulating layer, 62_2: insulating layer, 62_3: insulating layer, 65: opening, 66: opening, 67 : groove portion, 68: opening, 74: insulating layer, 74_1: insulating layer, 74_2: insulating layer, 74a: insulating layer, 74b: insulating layer, 76a: conductive layer, 76b: conductive layer, 77: conductive layer, 78: conductive layer, 84: insulating layer, 85: insulating layer, 86: insulating layer, 87: insulating layer, 88: insulating layer, 89: insulating layer, 91: layer, 100: capacitor element, 110: conductive layer, 115: conductive layer, 130: insulating layer, 140: insulating layer, 150: memory cell, 180: insulating layer, 190: opening, 248a: conductive layer, 248b: conductive layer, 248c: conductive layer, 248d: conductive layer, 287: wiring region, 288: insulating layer, 293: insulating layer, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating layer, 316: conductive layer, 320: insulating layer, 322: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 350: insulating layer, 352: insulating layer, 354: insulating layer, 356: conductive layer, 371: conductive layer, 372: insulating layer, 381: conductive layer, 382: conductive layer, 383: conductive layer, 384: conductive layer, 401: insulating layer, 402: insulating layer, 404: insulating layer, 405: insulating layer, 810: electronic component, 811: semiconductor Conductor device, 812: drive circuit layer, 813: memory layer, 814: mold, 815: land, 816: electrode pad, 817: wire, 818: printed circuit board, 819: mounting board, 820: electronic component, 821: interposer, 822: package board, 823: electrode, 824: semiconductor device, 830: mainframe computer, 831: rack, 832: computer, 833: PC card, 834: board, 835: connection terminal, 836: connection terminal, 837: connection terminal, 838: semiconductor device, 839: semiconductor device, 840: semiconductor device, 841: connection terminal, 842: motherboard,843: slot, 850: satellite, 851: aircraft, 852: solar panel, 853: antenna, 854: planet, 855: secondary battery, 856: control device, 860: storage system, 861: host, 861sb: server, 862: storage control circuit, 863: storage, 863md: storage device, 864: storage area network, 900: semiconductor device, 910: drive circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 960: arithmetic unit, 961: substrate, 962: ALU, 962c: ALU controller, 963: instruction decoder, 964: interrupt controller, 965: timing controller, 966: register, 967: register controller, 968: bus interface, 969: cache, 969i: cache interface, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device,

Claims

a semiconductor layer, first to third conductive layers, and first to third insulating layers; the first insulating layer has a portion located on the first conductive layer and has a first opening reaching the first conductive layer; the second insulating layer has a portion in contact with a side surface of the first insulating layer at the first opening, the second conductive layer is located on the first insulating layer and on the second insulating layer; the second conductive layer and the second insulating layer have a second opening reaching the first conductive layer; the semiconductor layer has, in the second opening, a portion in contact with a side surface of the second conductive layer, a portion in contact with a side surface of the second insulating layer, and a portion in contact with a top surface of the first conductive layer; the third insulating layer covers the semiconductor layer; the third conductive layer is located on the third insulating layer; The semiconductor device, wherein the upper surface of the second insulating layer has a portion that contacts the lower surface of the second conductive layer. 　 In claim 1, The semiconductor device, wherein the width of the second insulating layer is 3 nm or more and 10 nm or less. 　 In claim 1, a top surface of the second insulating layer being equal in height to a top surface of the first insulating layer; 　 In claim 1, A semiconductor device, wherein, in a plan view, a side edge of the second conductive layer in the second opening and a side edge of the second insulating layer in the second opening coincide with each other. 　 In claim 1, The second insulating layer has a portion located between the first insulating layer and the second conductive layer. 　 In any one of claims 1 to 5, The semiconductor device, wherein the second insulating layer contains hafnium and oxygen. 　 In any one of claims 1 to 5, the second insulating layer has a laminated structure of a first layer and a second layer on the first layer, the first layer comprises hafnium and oxygen; The semiconductor device, wherein the second layer includes silicon and oxygen. 　 forming a first conductive layer; forming a first insulating layer to cover the first conductive layer; forming a first opening in the first insulating layer that reaches the first conductive layer; forming a second insulating layer and a layer on the second insulating layer so as to fill the first opening; forming a second conductive layer over the first insulating layer, the second insulating layer, and the first conductive layer; removing a portion of the second conductive layer, the layer, and a portion of the second insulating layer to form a second opening in the second conductive layer and the second insulating layer, the second opening having an outline positioned inside an outline of the first opening in a plan view; forming a semiconductor layer so as to cover a sidewall and a bottom of the second opening; forming a third insulating layer on the semiconductor layer; forming a third conductive layer over the third insulating layer. 　 a semiconductor layer, first to fourth conductive layers, and first to fourth insulating layers; the first insulating layer has a portion located on the first conductive layer and a groove portion reaching the first conductive layer; the second insulating layer is on the first conductive layer and has a portion in contact with a first side surface of the groove of the first insulating layer; the third insulating layer is on the first conductive layer and has a portion in contact with a second side surface opposite to the first side surface; the second conductive layer is located on the first insulating layer and on the second insulating layer; the third conductive layer is located on the first insulating layer and the third insulating layer; the semiconductor layer has a portion in contact with the second conductive layer, a portion in contact with the third conductive layer, and, in the groove, a portion in contact with the second insulating layer, a portion in contact with the third insulating layer, and a portion in contact with the first conductive layer; the fourth insulating layer covers the semiconductor layer; the fourth conductive layer is located on the fourth insulating layer and fills at least a portion of the groove; an upper surface of the second insulating layer has a portion in contact with a lower surface of the second conductive layer; a top surface of the third insulating layer having a portion in contact with a bottom surface of the third conductive layer; 　 In claim 9, The semiconductor device, wherein the width of the second insulating layer is 3 nm or more and 10 nm or less. 　 In claim 9, the height of the upper surface of the second insulating layer is the same as the height of the upper surface of the first insulating layer; a top surface of the third insulating layer being equal in height to a top surface of the first insulating layer; 　 In claim 9, A semiconductor device, wherein, in a plan view, a side end of the second conductive layer facing the third conductive layer and a side end of the second insulating layer facing the third insulating layer coincide with each other. 　 In any one of claims 9 to 12, a fifth conductive layer electrically connected to the second conductive layer; a sixth conductive layer electrically connected to the third conductive layer; a seventh conductive layer electrically connected to the fifth conductive layer and the sixth conductive layer; a direction in which the seventh conductive layer extends and a direction in which the trench extends intersect with each other. 　 In claim 13, The semiconductor device, wherein the second insulating layer contains hafnium and oxygen. 　 forming a first conductive layer; forming a first insulating layer to cover the first conductive layer; forming a groove in the first insulating layer so as to reach the first conductive layer; forming a second insulating layer and a layer on the second insulating layer so as to fill the groove; forming a second conductive layer over the first insulating layer, the second insulating layer, and the first conductive layer; a portion of the second conductive layer overlapping the groove portion is removed to form a third conductive layer and a fourth conductive layer from the second conductive layer; removing said layer; removing a portion of the second insulating layer located between the third conductive layer and the fourth conductive layer to form a third insulating layer and a fourth insulating layer from the second insulating layer; forming a semiconductor layer in contact with an upper surface and a side surface of the third conductive layer, a side surface of the third insulating layer, an upper surface and a side surface of the fourth conductive layer, a side surface of the fourth insulating layer, and the first conductive layer; forming a fifth insulating layer on the semiconductor layer; forming a fifth conductive layer on the fifth insulating layer.

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