Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device in which a high-quality semiconductor film is used. The semiconductor device comprises a sapphire substrate, a first insulating layer, and a transistor. The first insulating layer is provided on the substrate and has an opening that reaches the substrate. The transistor has a semiconductor layer. The semiconductor layer has a portion in contact with the upper surface of the first insulating layer, and a portion in contact with the upper surface of the substrate in the opening. The substrate has a single crystal structure. The first insulating layer has an amorphous structure. The semiconductor layer contains a metal oxide and has a single crystal structure.

Description

Semiconductor device and method for manufacturing the same

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, semiconductor devices have been developed and are mainly used in LSIs, CPUs, memories, etc. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0004] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0005] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0006] It is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the low leakage current property of a transistor including an oxide semiconductor. Patent Document 2 discloses a memory device that uses an oxide semiconductor and can retain stored data for a long period of time.

[0007] In addition, Non-Patent Document 1 reports a polycrystalline indium oxide film exhibiting high hole mobility and a transistor using the same. ２ O ３ The use of this in thin film transistors has been reported.

[0008] JP 2012-257187 A JP 2011-151383 A

[0009] Y. Magari et al. , “High-mobility hydrogenated polycrystalline In▲2▼O▲3▼(In▲2▼O▲3▼:H) thin-film transistors”, Nature Communications 13, 1078, (2022). Dhananjay and C. W. Chu, “Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process” Appl. Phys. Lett. 91, 132111 (2007). Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] An object of one embodiment of the present invention is to provide a semiconductor device using a high-quality semiconductor film. Another object is to provide a semiconductor device using a single-crystal oxide semiconductor film. Another object is to provide a high-performance semiconductor device. Another object is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device with low power consumption.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device having a novel structure, and to alleviate at least one of the problems of the prior art.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0013] One embodiment of the present invention is a semiconductor device including a substrate, a first insulating layer, and a transistor. The first insulating layer is provided over the substrate and has an opening that reaches the substrate. The transistor includes a semiconductor layer. The semiconductor layer has a portion in contact with a top surface of the first insulating layer and a portion in contact with a top surface of the substrate in the opening. The substrate has a single crystal structure. The first insulating layer has an amorphous structure. The semiconductor layer includes a metal oxide and has a single crystal structure.

[0014] Another embodiment of the present invention is a semiconductor device including a substrate, a first insulating layer, a second insulating layer, and a transistor. The first insulating layer is provided over the substrate and has an opening that reaches the substrate. The transistor includes a semiconductor layer. The semiconductor layer has a portion in contact with a top surface of the first insulating layer. The second insulating layer has a portion that covers part of the transistor and a portion that is in contact with a top surface of the substrate in the opening. The substrate has a single crystal structure. The first insulating layer has an amorphous structure. The semiconductor layer includes a metal oxide and has a single crystal structure.

[0015] Another embodiment of the present invention is a semiconductor device including a substrate, a first insulating layer, and a transistor. The first insulating layer is provided over the substrate and has an opening that reaches the substrate. The transistor includes a semiconductor layer and a gate insulating layer. The semiconductor layer has a portion in contact with a top surface of the first insulating layer. The gate insulating layer has a portion that overlaps with the semiconductor layer and a portion that is in contact with a top surface of the substrate in the opening. The substrate has a single crystal structure. The first insulating layer has an amorphous structure. The semiconductor layer includes a metal oxide and has a single crystal structure.

[0016] In any of the above, the substrate preferably has a cubic crystal structure, and the semiconductor layer preferably has a cubic crystal structure.

[0017] In any of the above, the substrate preferably contains an oxide containing zirconium and yttrium, the semiconductor layer preferably contains indium oxide, and the first insulating layer preferably contains silicon oxide.

[0018] Alternatively, in any of the above, the substrate preferably contains aluminum oxide (also called sapphire) having a single crystal structure, and in this case, the substrate preferably has a hexagonal crystal structure.

[0019] Another embodiment of the present invention is a method for manufacturing a semiconductor device, the method including: forming a first insulating layer over a substrate having a single crystal structure; forming an opening in the first insulating layer that reaches an upper surface of the substrate; forming a semiconductor film that is in contact with an upper surface of the first insulating layer and an upper surface of the substrate in the opening, has a single crystal region, and contains metal oxide; and removing part of the semiconductor film to form a semiconductor layer that has a portion in contact with the upper surface of the first insulating layer and a portion in contact with the upper surface of the substrate.

[0020] Another embodiment of the present invention is a method for manufacturing a semiconductor device, the method including: forming a first insulating layer over a substrate having a single crystal structure; forming an opening in the first insulating layer that reaches an upper surface of the substrate; forming a semiconductor film that is in contact with an upper surface of the first insulating layer and an upper surface of the substrate in the opening, has a single crystal region, and contains metal oxide; removing a part of the semiconductor film to form a semiconductor layer that is in contact with an upper surface of the first insulating layer and exposes an upper surface of the substrate in the opening; and forming a second insulating layer that is in contact with the upper surface of the substrate in the opening.

[0021] In any of the above, it is preferable to use a substrate containing an oxide containing zirconium and yttrium as the substrate, it is preferable to form the semiconductor layer so as to contain indium oxide, and it is preferable to form the first insulating layer so as to contain silicon oxide.

[0022] Alternatively, in any of the above, it is preferable to use a substrate containing aluminum oxide as the substrate.

[0023] According to one embodiment of the present invention, a semiconductor device using a high-quality semiconductor film can be provided. Alternatively, a semiconductor device using a single-crystal oxide semiconductor film can be provided. Alternatively, a high-performance semiconductor device can be provided. Alternatively, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a low-power semiconductor device can be provided.

[0024] Advantageous Effects of Invention According to one aspect of the present invention, it is possible to provide a semiconductor device having a novel configuration, and it is possible to at least alleviate at least one of the problems of the prior art.

[0025] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0026] FIGS. 1A and 1B are diagrams illustrating crystal alignment. FIGS. 2A and 2B are diagrams illustrating crystal alignment. FIGS. 3A, 3B, 3C, 3D, 3E, and 3F are diagrams illustrating a method for manufacturing a semiconductor film. FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor film. FIGS. 5A, 5B, 5C, and 5D are configuration examples of a semiconductor device. FIG. 6 is a configuration example of a semiconductor device. FIG. 7 is a configuration example of a semiconductor device. FIGS. 8A, 8B, 8C, and 8D are configuration examples of a semiconductor device. FIGS. 9A, 9B, 9C, and 9D are configuration examples of a semiconductor device. FIGS. 10A and 10B are configuration examples of a semiconductor device. FIGS. 11A, 11B, and 11C are configuration examples of a semiconductor device. FIGS. 12A, 12B, 12C, and 12D are configuration examples of a semiconductor device. 13A1, 13A2, 13B1, 13B2, 13C1, 13C2, 13D1, and 13D2 are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 14A1, 14A2, 14B1, 14B2, 14C1, and 14C2 are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 15A and 15B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 15C is a cross-sectional view illustrating an indium oxide film. FIG. 16 is a configuration example of a memory device. FIGS. 17A and 17B are configuration examples of memory devices. FIGS. 18A, 18B, 18C, and 18D are configuration examples of memory devices. FIG. 19 is a configuration example of a memory device. FIGS. 20A and 20B are configuration examples of a display device. FIG. 21 is a configuration example of a display device. Figures 22A, 22B, 22C, and 22D are configuration examples of electronic devices. Figures 23A, 23B, 23C, 23D, 23E, and 23F are configuration examples of electronic devices. Figures 24A, 24B, 24C, 24D, 24E, 24F, and 24G are configuration examples of electronic devices. Figures 25A and 25B are configuration examples of electronic components. Figures 26A, 26B, and 26C are configuration examples of mainframe computers.

[0027] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0028] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0029] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0030] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0031] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0032] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0033] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0034] In this specification, when two nodes are connected via an insulator such as a dielectric of a capacitive element, a gate insulating film of a transistor, or an interlayer insulating film, this is not considered to be an "electrical connection."

[0035] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0036] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0037] In the following description, expressions indicating directions such as "upper" and "lower" are basically used in accordance with the directions in the drawings. However, for ease of explanation, the directions indicated by "upper" or "lower" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a surface to be formed, a support surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the surface to be formed may be expressed as "lower" and the laminate side as "upper."

[0038] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0039] Unless otherwise specified, in this specification and the like, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0040] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting restrictions, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0041] Embodiment 1 In this embodiment, a method for manufacturing a semiconductor film according to one embodiment of the present invention will be described.

[0042] According to one embodiment of the present invention, a method for forming a metal oxide film having a single crystal region on an upper surface of an insulating layer on a single crystal substrate can be provided. According to one embodiment of the present invention, a metal oxide film having a single crystal structure or a metal oxide film having a substantially single crystal structure can be applied to a channel formation region of a transistor, thereby realizing a transistor having both high reliability and excellent electrical characteristics.

[0043] As the metal oxide, it is preferable to use an oxide containing indium, zinc, tin, or the like. In particular, it is preferable to use a metal oxide that is easily crystallized. For example, indium oxide is preferable because it easily crystallizes at low temperatures and can form a single crystal film with good crystallinity. In addition, a transistor using single crystal or polycrystalline indium oxide is preferable because it exhibits extremely high reliability.

[0044] For example, when a cubic oxide film such as indium oxide is used as the semiconductor film, it is preferable to use a single crystal substrate of the same cubic crystal system as the single crystal substrate. For example, it is preferable to use a cubic single crystal substrate such as a YSZ (yttria-stabilized zirconia) substrate, a zirconium oxide substrate, or a silicon substrate. Alternatively, a semiconductor film having a cubic single crystal structure can be formed using a tetragonal single crystal substrate. Note that the material and crystal structure of the single crystal substrate can be appropriately selected depending on the crystal structure of the target semiconductor film. For example, single crystal substrates such as silicon carbide, gallium nitride, and gallium oxide can also be used. Even when the crystal structures of the single crystal substrate and the target semiconductor film are different, epitaxial growth may be possible by providing a buffer layer to relieve strain between them.

[0045] Furthermore, the smaller the lattice mismatch between the single crystal substrate and the semiconductor film, the more preferable. Here, the lattice mismatch corresponds to the difference between the length of the unit lattice vector of the substrate and the length of the unit lattice vector of the thin film when epitaxially growing the thin film on the substrate, divided by the length of the unit lattice vector of the substrate. Instead of the unit lattice vector, a lattice constant can also be used. For example, when the substrate and the thin film have the same crystal structure, the lattice mismatch can be the difference between the two lattice constants divided by the lattice constant of the substrate.

[0046] The smaller the absolute value of the lattice mismatch between the single crystal substrate and the semiconductor film, the more preferable it is. For example, the lattice mismatch is preferably -5% to 5%, preferably -4% to 4%, more preferably -3% to 3%, and even more preferably -2% to 2%. Here, the lattice mismatch takes a positive value when the unit lattice vector of the thin film is larger than that of the substrate, and a negative value when it is smaller. When the buffer layer is provided, increasing its thickness may enable epitaxial growth even with a combination with a large lattice mismatch. In this case, the lattice mismatch between the single crystal substrate and the semiconductor film can be less than -5% or greater than 5%. For example, the lattice mismatch between the single crystal substrate and the semiconductor film may be -20% to 20%, -15% to 15%, or -10% to 10%.

[0047] Furthermore, it is preferable to use an aluminum oxide substrate (also referred to as a sapphire substrate, a sapphire glass substrate, or the like) as the single crystal substrate. A sapphire substrate can be easily made larger in area than a YSZ substrate or the like, and a conventional manufacturing line for a semiconductor device using a silicon wafer can be utilized. Furthermore, as the area of ​​the substrate increases, the manufacturing cost of a semiconductor device using the semiconductor film of one embodiment of the present invention can be reduced.

[0048] Aluminum oxide (Al ２ O ３ The crystals of quartz have a corundum-type crystal structure belonging to the hexagonal (trigonal) system. The (0001) plane in the hexagonal system and the (111) plane in the cubic system have similar atomic arrangements, so epitaxial growth is likely to occur.

[0049] As mentioned above, epitaxial growth can occur even when the crystal structures are different. For epitaxial growth to occur, it is important to consider the alignment of the crystal planes between the substrate and the film being grown.

[0050] Figures 1A and 1B show examples of atomic arrangements on one crystal plane of different crystals (crystal C1 and crystal C2). In crystal C1 and crystal C2, atoms indicated by white circles are arranged two-dimensionally and periodically. Each atomic arrangement can be represented by two unit vectors.

[0051] The crystal C1 shown in FIG. 1A has two unit vectors with lengths a １ , b １ The crystal C2 shown in FIG. 1B has two unit vectors whose lengths are a ２ , b ２ and the interior angle is the same θ as that of crystal C1.

[0052] In the crystal C1, the unit cell defined by two unit vectors is defined as an area A1, which is an integer multiple of the direction of the two unit vectors. １ ', b １ ' are respectively a １ '=n ｐ a １ , b １ '=n ｑ b １ (n ｐ , n ｑ are each independently a natural number). In this case, the area S1 of the region A1 is a １ '×b １ '×sin(θ).

[0053] Similarly, the length a of the two sides of the region A2 in the crystal C2 ２ ', b ２ ' are respectively a ２ '=n ｒ a ２ , b ２ '=n ｓ b ２ (n ｒ , n ｓ are each independently a natural number). The area S2 of the region A2 is a ２ '×b ２ '×sin(θ).

[0054] Here, a １ ' and a ２ ' difference Δa, b １ ' and b２ There exists a combination in which the difference Δb between S1 and S2′ and the difference ΔS between S1 and S2 are smallest. The smaller these values ​​are, the better the matching (the higher the degree of matching) at the joining surface of the two crystals.

[0055] At this time, a １ ' and a ２ ' difference Δa (or b １ ' and b ２ A value corresponding to the lattice mismatch can be calculated using the difference Δb between the lattice constants Δb and Δc. Thus, when considering epitaxial growth between different crystal structures (crystal systems), the lattice mismatch must be understood in a broad sense, taking into account not just the difference in lattice constants but also a "superlattice" in which the unit cell is an integer multiple of the unit lattice vector. In the case of Figures 1A and 1B, the lattice when region A1 and region A2 are each taken as a unit cell can be called a "superlattice," and therefore the lattice mismatch in this case can also be called "superlattice mismatch" to distinguish it from the lattice mismatch described above. The superlattice mismatch is included in the broad definition of lattice mismatch.

[0056] The degree of superlattice mismatch is determined by the length of the superlattice vector of the substrate (above １ ' or b １ ') and the length of the superlattice vector of the thin film (a ２ ' or b ２ The difference between the superlattice vector length (a) and the superlattice vector length (a) (i.e., Δa or Δb) is １ ' or b １ ') is equivalent to the value divided by

[0057] Furthermore, when forming a crystal C2 on a crystal C1, the area S1 of a region A1 in the crystal C1 that will become the substrate can be called the "cross-sectional area." In order for the crystal C2 to grow epitaxially on the crystal C1, it is important that not only the lattice mismatch be small, but also that the cross-sectional area of ​​the crystal C1 be small.

[0058] FIG. 2A shows the structure of sapphire (Al ２ O ３ ) and the crystal structure of the unit cell to the right of it. ２ O ３2A and 2B show the crystal structure of the (111) plane of the superlattice, and to the right of it, the crystal structure of the unit cell. Also, in Figures 2A and 2B, the unit cell of the superlattice where the lattice mismatch and cross-sectional area are smallest is shown enclosed by a solid line. The figures also show the values ​​of the lengths a' and b' of the two sides of the unit cell.

[0059] 2A and 2B, the lattice mismatch between the (0001) plane of sapphire and the (111) plane of indium oxide is 0.22%. The cross-sectional area at this time is 176.6 Å. ２ This result suggests that the combination of the (0001) plane of sapphire and the (111) plane of indium oxide has a higher matching property than the combination of the (111) plane of YSZ and the (111) plane of indium oxide.

[0060] A method for manufacturing a semiconductor film will be described below with reference to the drawings.

[0061] 3A to 3E are schematic cross-sectional views illustrating a method for fabricating a semiconductor film, which will be described below.

[0062] First, a substrate 11 is prepared ( FIG. 3A ). A single crystal substrate can be used for the substrate 11. For example, a single crystal substrate such as YSZ (yttria-stabilized zirconia), zirconium oxide, aluminum oxide (sapphire), silicon, silicon carbide, gallium nitride, or gallium oxide can be used. The substrate 11 can be made of a material that has a small lattice mismatch with the semiconductor film 21f to be formed later. The semiconductor film 21f is a film that will later become the semiconductor layer 21.

[0063] One method for evaluating the degree of lattice mismatch is the lattice mismatch ratio. The lattice mismatch ratio Δa [%] of the crystals of the formed film (e.g., semiconductor film 21f) to the crystals of the film to be formed (e.g., substrate 11) is expressed as follows: Δa=(L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the film to be formed.

[0064] The smaller the absolute value of the lattice mismatch Δa between the substrate 11 and the semiconductor film 21f, the more preferable, and it is most preferably 0. For example, Δa is preferably −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0065] For example, indium oxide with a cubic crystal structure (bixbyite type) has a lattice constant of 1.0117 nm (see ICSD (Inorganic Crystal Structure Database) col.code.14387). ０．９ Y ０．１ O １．９５ ) has a lattice constant of 0.51481 nm (see ICSD coll.code.248790). Therefore, the lattice mismatch between the crystal grains of the indium oxide film and the crystal grains of YSZ is −1.74%. Here, the content of yttrium contained in YSZ can be 2 atomic % or more and 15 atomic % or less, preferably 5 atomic % or more and 10 atomic % or less.

[0066] It should be noted that the crystal orientation of the substrate 11 and that of the semiconductor film 21f may not necessarily be the same. For example, a substrate having a hexagonal or trigonal crystal structure can be used under indium oxide having a cubic crystal structure. For example, by setting the crystal orientation of the surface of the substrate 11 to

[001] , the requirements regarding the crystal orientation necessary for epitaxial growth, in which the crystal orientation of the underside of the semiconductor film 21f is

[111] , can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, corundum structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７An example of a crystal having such a structure is In-Ga-Zn oxide (IGZO).

[0067] The semiconductor film 21f is not limited to indium oxide, and a metal oxide film containing indium, tin, or zinc as its main component can be used. Here, the term "main component" refers to a metal oxide in which the ratio of the target atoms to the total number of atoms of the metal elements that make up the metal oxide is 0.1% or more. Elements with a ratio of less than 0.1% are sometimes called impurities.

[0068] Next, an insulating layer 12 is formed on the substrate 11. After that, a part of the insulating layer 12 is removed using a processing method such as photolithography to form an opening 20 that reaches the substrate 11 ( FIG. 3B ). In the opening 20, a part of the upper surface of the substrate 11 is exposed.

[0069] The insulating layer 12 can be formed by a method such as atomic layer deposition (ALD), sputtering, chemical vapor deposition (CVD), pulsed laser deposition (PLD), molecular beam epitaxy (MBE), or a wet method.

[0070] It is preferable to use an inorganic insulating film as the insulating layer 12. Typically, silicon oxide can be used. In addition, insulating materials such as silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, yttrium oxide, and zirconium oxide can be used.

[0071] The insulating layer 12 is preferably a film having an amorphous structure. If a film having a polycrystalline or single-crystalline structure is used as the insulating layer 12, when the semiconductor film 21f is subsequently formed, the semiconductor film 21f may crystallize due to the crystalline structure of the insulating layer 12, resulting in a polycrystalline structure with small crystal grains. Therefore, by using a film having an amorphous structure for the insulating layer 12, unintended crystallization of the semiconductor film 21f can be suppressed, making it possible to obtain a semiconductor film 21f with a good crystalline structure. Note that if the lattice mismatch between the insulating layer 12 and the semiconductor film 21f is large, unintended crystallization of the semiconductor film 21f can be suppressed, and therefore a film having a polycrystalline or single-crystalline structure may be used for the insulating layer 12.

[0072] One opening 20 is formed for each transistor. Alternatively, one opening 20 can be formed for a plurality of transistors. Note that a plurality of openings 20 can also be formed for each transistor.

[0073] Next, a semiconductor film 21f is formed in contact with the upper surface of the insulating layer 12 and the upper surface of the substrate 11 in the opening 20 (FIGS. 3C and 3D). A metal oxide can be used for the semiconductor film 21f. In particular, it is preferable to use an oxide film containing indium, tin, or zinc as a main component. Among these, a transistor using single-crystal indium oxide is particularly preferable because it combines high mobility and high reliability.

[0074] The semiconductor film 21f can be formed by atomic layer deposition (ALD), sputtering, chemical vapor deposition (CVD), pulsed laser deposition (PLD), molecular beam epitaxy (MBE), wet processes, etc. In particular, it is preferable to form the semiconductor film 21f by ALD or sputtering.

[0075] The semiconductor film 21f is preferably formed using the ALD method. The ALD method deposits atoms one by one, rather than using the sputtering method, which bombards particles onto the surface to be formed. This method can suppress the generation of crystal nuclei in the film, thereby suppressing unintended polycrystallization of the semiconductor film 21f.

[0076] The semiconductor film 21f can be formed by, for example, ALD using a precursor and an oxidizing agent. When forming a film containing indium as the semiconductor film 21f, a precursor containing indium can be used. When using a precursor containing indium, it is preferable to use thermal ALD as the ALD method. Alternatively, PEALD (Plasma Enhanced ALD) using plasma can also be used.

[0077] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolato)indium.

[0078] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the indium-containing precursor. Examples of the inorganic precursor containing indium include halogen-based indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0079] In the method for forming the semiconductor film 21f, it is preferable to use a material with a low impurity concentration. In other words, it is preferable to use a high-purity material in the method for forming the semiconductor film 21f. For example, the purity is preferably 3N (99.9%) or higher, more preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher. By using a high-purity material, it is possible to reduce the impurities in the semiconductor film 21f.

[0080] The gallium content and aluminum content of the indium-containing precursor are each preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, still more preferably 50 ppm or less, even more preferably 10 ppm or less, and still more preferably 1 ppm or less. Reducing the gallium concentration in the semiconductor film 21f can improve the reliability of the transistor. Furthermore, reducing the aluminum concentration in the semiconductor film 21f can improve the crystallinity of the semiconductor film 21f.

[0081] Examples of oxidizing agents include ozone (O ３ ), oxygen (O ２ ), water (H ２ O), nitrogen dioxide (NO ２ ), nitrous oxide (N ２ O), hydrogen peroxide (H ２ O ２ ) or the like can be used, and two or more of these may be used.

[0082] When forming a single crystal or a polycrystal with a large grain size, it is preferable to use an oxidizing agent containing hydrogen in order to suppress the generation of crystal nuclei in the initial stage of film formation. For example, H ２ O or H ２ O ２ It is preferable to use O as an oxidizing agent. After forming a film with few crystal nuclei, crystal growth can be caused by heat applied during film formation or by heat treatment after film formation, thereby forming a single crystal film or a polycrystalline film with large grain size. On the other hand, when reducing the hydrogen concentration and nitrogen concentration in the film, O is used as an oxidizing agent. ２ or O ３ It is preferable to use O３ It is more preferable to use

[0083] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form two or more films with different compositions continuously.

[0084] The substrate heating temperature when introducing the precursor into the reaction chamber is preferably set to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, the substrate heating temperature can be set to, for example, 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower.

[0085] Here, the mechanism of crystal growth of the semiconductor film 21f will be described. In the following, indium oxide will be particularly used as an example, but the same can be applied to other materials.

[0086] Not only for indium oxide, but for all materials, the crystal orientation and ease of crystal growth are related to interfacial energy. Interfacial energy refers to the energy loss caused by the interface formation between a crystalline structure and an amorphous structure, and can be calculated using the following formula:

[0087]

[0088] Here, E ｉｎｔｅｒｆａｃｅ is the interfacial energy, E ａｍｏ is the total energy of the amorphous structure model, and E ｃｒｙ is the total energy of the single crystal structure model, and E ａ／ｃ is the total energy of the model in which the amorphous structure and the single crystal structure are bonded. S is the bond cross-sectional area, which is the contact area between the amorphous structure and the single crystal structure in the model in which the amorphous structure and the single crystal structure are bonded.

[0089] The smaller the interfacial energy, the smaller the energy loss due to crystallization. Therefore, crystals grow to maximize the surface area of ​​the crystal plane with low interfacial energy. In other words, the rate of crystal growth is fast in the direction along the crystal plane with low interfacial energy, and slow in the direction perpendicular to the crystal plane with low interfacial energy.

[0090] Table 1 shows the interfacial energies obtained by molecular dynamics calculations for each of the (100) plane, (110) plane, (1-10) plane, and (111) plane of an indium oxide crystal.

[0091]

[0092] From Table 1, it can be seen that indium oxide has the smallest interfacial energy in the (111) plane, the next smallest in the (110) plane, the next smallest in the (1-10) plane, and the largest in the (100) plane. Since the (111) plane has the smallest interfacial energy in indium oxide, it is presumed that indium oxide crystals grow while maximizing the surface area of ​​the (111) plane. In other words, it is presumed that indium oxide has a preferred orientation in the (111) plane. Since indium oxide is a cubic crystal, it can also be said that it has a preferred orientation in the {111} plane.

[0093] Because the semiconductor film 21f is a thin film, the length of the semiconductor film 21f in the direction along the surface of the insulating layer 12 is much greater than the thickness of the semiconductor film 21f. To increase the grain size of the crystals, the rate of crystal growth in the direction along the surface of the insulating layer 12 (first direction) is made faster than the rate of crystal growth in the thickness direction of the semiconductor film 21f (second direction).

[0094] As described above, since the crystal growth of indium oxide is anisotropic with respect to the crystal plane, the crystal orientation of the region that serves as the starting point of crystal growth is important. In one aspect of the present invention, the substrate 11 and the semiconductor film 21f are in contact with each other at the opening 20, and the semiconductor film 21f grows epitaxially at the opening 20 in a manner that reflects the crystal structure of the substrate 11, thereby making it possible to control the crystal orientation of the region that serves as the starting point of crystal growth of the semiconductor film 21f. In other words, the crystal orientation of the semiconductor film 21f can be determined by the crystal orientation of the substrate 11.

[0095] From the above-mentioned mechanism, it is presumed that the crystal growth rate in the direction along the {111} plane is faster than the crystal growth rate in the direction perpendicular to the {111} plane. Therefore, it is preferable that the first direction is parallel to the direction along the {111} plane and the second direction is parallel to the direction perpendicular to the {111} plane. This makes it possible to make the crystal growth rate in the first direction faster than the crystal growth rate in the second direction, thereby enabling the crystal grain size to be increased.

[0096] Note that the direction perpendicular to the {111} plane is a direction belonging to <111> (an individual direction of <111>), and the direction along the {111} plane is a direction perpendicular to a direction belonging to <111>. Examples of directions belonging to <111> include

[111] , [-111], [1-11], and [11-1]. Examples of directions perpendicular to

[111] include [-1-12] and [5-1-4]. Examples of directions perpendicular to [-111] include the

[110] direction and the

[101] direction. In this specification and the like, a direction belonging to <111> may be simply referred to as the <111> direction.

[0097] Therefore, the substrate 11 is a substrate that has a small lattice mismatch with the semiconductor film 21f and has a crystal orientation such that the crystal orientation <111> of the semiconductor film 21f is perpendicular to the surface of the substrate 11 (second direction). For example, when a YSZ substrate is used as the substrate 11, it is preferable to use a substrate whose surface crystal plane is the

[111] plane. Furthermore, when an aluminum oxide (sapphire) substrate is used as the substrate 11, it is preferable to use a substrate whose surface crystal plane is the

[0001] plane.

[0098] During deposition of the semiconductor film 21f, epitaxial growth (heteroepitaxial growth) of the semiconductor film 21f occurs in the region inside the opening 20 where the substrate 11 and the semiconductor film 21f are in contact, forming a region in which the crystal orientation

[111] is oriented perpendicular to the surface of the substrate 11. Subsequently, as shown by the arrow in FIG. 3C , crystal growth proceeds from the opening 20 in a direction (first direction) along the top surface of the insulating layer 12. FIG. 3C schematically illustrates the crystallized region 21c and the region 21a before crystallization, with the boundary between them indicated by a dashed line. Region 21a can also be referred to as a region having an amorphous structure.

[0099] Then, as shown by the arrow in Fig. 3D, crystal growth proceeds in a direction (second direction) perpendicular to the top surface of the insulating layer 12, and the entire semiconductor film 21f becomes a crystallized region 21c. For convenience, Fig. 3D shows a dashed line in the semiconductor film 21f at the same position as Fig. 3C, but in reality, this boundary does not exist, and the semiconductor film 21f becomes a single crystal in the thickness direction.

[0100] In this way, by using substrate 11 having an optimal crystal orientation in accordance with the possible crystal structure of semiconductor film 21f, the rate of crystal growth in the direction along the surface of insulating layer 12 (first direction) can be made faster than that in the second direction, and this makes it possible to greatly expand the crystalline region originating from opening 20 before crystal nuclei are generated near the interface between semiconductor film 21f and insulating layer 12. This makes it possible to form semiconductor film 21f having a crystalline region with large grain size centered on opening 20.

[0101] The above-mentioned crystallization can occur during the formation of the semiconductor film 21f, during slow cooling after the film formation, or in a process involving heating the substrate after the formation of the semiconductor film 21f (such as a film formation process or heat treatment).

[0102] After the semiconductor film 21f is formed, it is preferable to perform a heat treatment, which can improve the crystallinity of the semiconductor film 21f even if the crystallization is insufficient during film formation.

[0103] The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm (0.001%) or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in a nitrogen gas or inert gas atmosphere, the heat treatment can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0104] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb (1×10 −３ ppm) or less, and 0.1 ppb (1 x 10 −４ ppm) or less, and 0.05 ppb (5 × 10 −５ By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the semiconductor film 21f as much as possible.

[0105] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas.

[0106] Here, it is preferable to use a film having a smaller thermal expansion coefficient than the semiconductor film 21f as the insulating layer 12. As a result, when the substrate temperature is lowered after the semiconductor film 21f is formed, tensile stress is generated in the semiconductor film 21f, causing it to become unstable. As a result, the semiconductor film 21f tends to become more stable crystalline than amorphous, which may accelerate the progress of crystallization and make it easier to form a large-area crystalline region.

[0107] The semiconductor film 21f can also be formed by sputtering, CVD, MBE, or PLD. For example, when the semiconductor film 21f is formed by sputtering, the sputtering gas may be hydrogen (H ２ ) is preferably contained. By introducing hydrogen when forming the semiconductor film 21f by a sputtering method, the semiconductor film 21f can be formed with low crystallinity. Furthermore, when forming the semiconductor film 21f, generation of crystal nuclei can be suppressed or disappearance of crystal nuclei can be promoted. Note that, as the sputtering gas, a noble gas (typically argon) or a simple gas of oxygen, or a mixed gas of a noble gas and oxygen, or the like can also be used.

[0108] Furthermore, when the semiconductor film 21f is formed by sputtering, the substrate temperature during deposition of the semiconductor film 21f is preferably from room temperature (25°C) to 250°C, more preferably from room temperature to 200°C, and even more preferably from room temperature to 140°C. For example, setting the substrate temperature from room temperature to 140°C is preferable because it increases productivity. It is also preferable because it can suppress the generation of crystal nuclei. Alternatively, the metal oxide layer can be formed at room temperature or without heating the substrate.

[0109] After forming the semiconductor film 21f with low crystallinity by sputtering, it is preferable to perform heat treatment. The heat treatment can be performed, for example, at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C., and more preferably 320° C. to 450° C. The heat treatment can promote crystal growth and increase the size of crystal grains in the semiconductor film 21f. As described above, the semiconductor film 21f with crystallinity can be formed. Furthermore, the heat treatment can reduce excess hydrogen in the semiconductor film 21f.

[0110] As described above, the semiconductor film 21f having a large-area single crystal region can be formed on the insulating layer 12 provided on the substrate 11 having a single crystal structure.

[0111] Subsequently, unnecessary portions of the semiconductor film 21f are removed by etching, thereby forming island-shaped semiconductor layers 21 (FIG. 3E).

[0112] 3E shows an example in which a region of semiconductor film 21f overlapping with opening 20 is removed. In Fig. 3E, the upper surface of substrate 11 is exposed at opening 20. By removing semiconductor film 21f located near opening 20 in this manner, only semiconductor layer 21 located on the flat portion of insulating layer 12 can be used in a transistor, thereby achieving a highly reliable transistor.

[0113] 3E, the island-shaped semiconductor layer 21 is preferably formed by a single crystal grain. In other words, the semiconductor layer 21 can be called a single-crystal semiconductor film. Note that the entire semiconductor layer 21 is preferably a single crystal, and it is preferable that at least the portion that functions as a channel formation region does not have a crystal grain boundary and is a single crystal.

[0114] 3F, an insulating layer 13 may be formed in contact with the upper surface of the substrate 11 exposed in the opening 20. The insulating layer 13 may be provided to cover the semiconductor layer 21, the insulating layer 12, and the substrate 11. The insulating layer 13 may also be used as a gate insulating layer of a transistor. The insulating layer 13 may be formed by a method similar to that for the insulating layer 12.

[0115] 4, the semiconductor layer 21 may be processed to include a region in contact with the upper surface of the substrate 11 in the opening 20. By applying such a semiconductor layer 21 to a transistor, it becomes possible to overlap a part of the opening 20 with the transistor, thereby enabling high integration.

[0116] The above is a description of the method for manufacturing a semiconductor film. According to the method for manufacturing a semiconductor film of one embodiment of the present invention, a semiconductor film having a single crystal structure can be formed over an insulating layer formed over a substrate having a single crystal structure. By using the semiconductor film formed in this way as a semiconductor layer of a transistor, a transistor having both high field-effect mobility and high reliability can be realized.

[0117] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0118] In this embodiment, a structure example of a semiconductor device of one embodiment of the present invention and an example of a manufacturing method thereof will be described. Here, a transistor will be described as an example of a semiconductor device. The semiconductor layer described in Embodiment 1 can be applied to a semiconductor layer of the transistor exemplified below.

[0119] [Configuration Example of Semiconductor Device] Figures 5A to 5D are top views and cross-sectional views of a transistor 200. Figure 5A is a top view of the transistor 200, and Figures 5B to 5D are schematic cross-sectional views corresponding to the cutting lines A1-A2, A3-A4, and A5-A6 in Figure 5A, respectively. Figure 5B corresponds to a cross section of the transistor 200 in the channel length direction, and Figures 5C and 5D correspond to cross sections in the channel width direction, respectively. Figure 6 is an enlarged view of Figure 5B. Note that some components are omitted in Figure 5A.

[0120] The transistor 200 includes a substrate 210, an insulating layer 201 provided over the substrate 210, a semiconductor layer 230 provided over the insulating layer 201, conductive layers 242a and 242b over the semiconductor layer 230, an insulating layer 250 over the semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. An insulating layer 275 is provided to cover the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b, and an insulating layer 280 is provided over the insulating layer 275. A groove reaching the semiconductor layer 230 is provided in the insulating layer 280 and the insulating layer 275, and the conductive layer 242a and the conductive layer 242b are separated by the groove. The insulating layer 250 is provided inside the groove along surfaces of the insulating layer 280, the insulating layer 275, the conductive layer 242a, the conductive layer 242b, and the semiconductor layer 230. The conductive layer 260 is provided over the insulating layer 250 so as to fill the groove. In addition, insulating layers 282 and 285 are provided in this order to cover the insulating layer 280, the insulating layer 250, and the conductive layer 260.

[0121] The semiconductor layer 230 functions as a channel formation region of the transistor 200. The conductive layer 260 functions as a gate electrode of the transistor 200. The insulating layer 250 functions as a gate insulating layer of the transistor 200. The conductive layer 242a functions as one of a source electrode and a drain electrode of the transistor 200, and the conductive layer 242b functions as the other.

[0122] The semiconductor layer 21 exemplified in Embodiment 1 can be applied to the semiconductor layer 230. The substrate 11 and insulating layer 12 exemplified in Embodiment 1 can be applied to the substrate 210 and insulating layer 201, respectively.

[0123] The conductive layer 242a and the conductive layer 242b preferably have a stacked structure. A conductor that is resistant to oxidation, such as a metal nitride, is preferably used on the side in contact with the semiconductor layer 230. This can prevent the conductive layer 242a and the conductive layer 242b from being excessively oxidized by oxygen contained in the semiconductor layer 230. Furthermore, a metal or alloy having higher conductivity than the layer in contact with the semiconductor layer 230 is preferably used on the side not in contact with the semiconductor layer 230. This allows the conductive layer 242a and the conductive layer 242b to function as wirings or electrodes with high conductivity.

[0124] In the conductive layers 242a and 242b, a metal nitride is preferably used on the side in contact with the semiconductor layer 230, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when they absorb oxygen.

[0125] The insulating layer 201 is a film in contact with the semiconductor layer 230 and is preferably an oxide insulating film. For example, the insulating layer 201 is preferably made of silicon oxide or silicon oxynitride.

[0126] Note that an insulating layer functioning as a barrier layer may be provided between the insulating layer 201 and the semiconductor layer 230 or between the insulating layer 201 and the substrate 210. The insulating layer preferably has a barrier property against at least hydrogen. For example, examples of the barrier layer against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. This makes it possible to keep the hydrogen concentration in the semiconductor layer 230 low, thereby improving the reliability of the transistor 200.

[0127] The semiconductor layer 230 is preferably formed using a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0128] The band gap of a metal oxide functioning as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. A transistor having a metal oxide in a channel formation region like this is called an OS transistor. Because the off-state current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0129] It is preferable to use indium oxide as the semiconductor layer 230. In particular, it is preferable to use a single-crystal indium oxide film. Note that it is preferable to use a crystalline film for the semiconductor layer 230, and it is particularly preferable to use indium oxide having a single-crystal structure. However, indium oxide having a polycrystalline structure or a microcrystalline structure can also be used. By using indium oxide having a single-crystal structure, carrier scattering at crystal grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

[0130] When indium oxide having a polycrystalline structure is used, it is preferable that no crystal grain boundaries be observed at least in the channel formation region (the region overlapping with the conductive layer 260). Thus, even indium oxide having a polycrystalline structure can achieve the same effects as in the case of indium oxide having a single crystal structure.

[0131] The thickness of the semiconductor layer 230 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. By setting the thickness of the semiconductor layer 230 within the above range, the crystallinity of the semiconductor layer 230 can be improved.

[0132] Among oxide semiconductors with high crystallinity, indium oxide is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO (In—Ga—Zn—O-based oxide) film. Therefore, indium oxide can be said to be a film through which one or both of hydrogen and oxygen are more easily supplied and discharged than, for example, an IGZO film. This can be said to make it difficult for excess oxygen or excess hydrogen, which can become carriers or fixed charges, to accumulate in the semiconductor layer 230, thereby making it possible to provide a transistor with good electrical characteristics and reliability.

[0133] The semiconductor layer 230 preferably has a reduced concentration of elements that reduce crystallinity. For example, the concentration of elements such as boron and aluminum is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0134] Furthermore, since gallium has the property of easily bonding with excess oxygen atoms, a large gallium content may result in a large variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, the gallium concentration in the semiconductor layer 230 is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0135] Other metal oxides that can be used for the semiconductor layer 230 include tin oxide, zinc oxide, indium tin oxide, indium titanium oxide, indium gallium oxide, indium tungsten oxide, indium zinc oxide, indium gallium aluminum oxide, indium gallium tin oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide, indium gallium tin zinc oxide, and indium gallium aluminum zinc oxide. Alternatively, indium tin oxide, gallium tin oxide, aluminum tin oxide, and the like containing silicon can also be used. When these are used, the film preferably has at least crystallinity, and more preferably has a single crystal structure.

[0136] The insulating layer 250 functioning as a gate insulating layer preferably has a function of capturing and fixing hydrogen, thereby reducing the hydrogen concentration in the channel formation region of the semiconductor layer 230. As a result, the channel formation region can be made i-type or substantially i-type.

[0137] Here, the insulating layer 250 preferably has a stacked structure of a first layer in contact with the semiconductor layer 230, a second layer over the first layer, and a third layer over the second layer. In this case, it is preferable that the first layer has a function of capturing hydrogen and fixing hydrogen.

[0138] Examples of insulators capable of capturing and fixing hydrogen include metal oxides having an amorphous structure. For the first layer, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0139] Furthermore, it is preferable to use a high dielectric constant (high-k) material for the first layer. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material for the first layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. It is also possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulating layer.

[0140] For the first layer, it is preferable to use an oxide containing one or both of aluminum and hafnium, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0141] Next, the second layer preferably uses an insulator having a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0142] Alternatively, a fourth layer may be provided on the second layer. In this case, the fourth layer may be an insulator that can be used for the first layer. For example, hafnium oxide may be used for the fourth layer. Here, by providing the fourth layer between the third layer and the second layer, hydrogen contained in the second layer and the like can be more effectively captured and fixed.

[0143] The third layer preferably has a barrier property against oxygen. The third layer is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260, and between the insulating layer 280 and the conductive layer 260. This structure can prevent oxygen contained in the channel formation region of the semiconductor layer 230 from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. Furthermore, it can prevent oxygen contained in the semiconductor layer 230 and oxygen contained in the insulating layer 280 from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The third layer is preferably at least less permeable to oxygen than the insulating layer 280. For example, a silicon nitride film is preferably used as the third layer. In this case, the third layer is an insulator containing at least nitrogen and silicon.

[0144] Furthermore, the third layer preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230.

[0145] The insulating layer 275 preferably has a barrier property against oxygen. The insulating layer 275 is provided between the insulating layer 280 and the conductive layer 242a and between the insulating layer 280 and the conductive layer 242b. This structure can prevent oxygen contained in the insulating layer 280 from diffusing into the conductive layer 242a and the conductive layer 242b. Therefore, it is possible to prevent the conductive layer 242a and the conductive layer 242b from being oxidized by oxygen contained in the insulating layer 280, thereby increasing the resistivity and reducing the on-current. The insulating layer 275 is preferably at least less permeable to oxygen than the insulating layer 280. For example, it is preferable to use silicon nitride as the insulating layer 275. In this case, the insulating layer 275 becomes an insulator containing at least nitrogen and silicon.

[0146] In addition to the above structure, in this embodiment, the semiconductor device preferably has a structure that suppresses hydrogen from being mixed into the transistor 200 and the like. For example, an insulator that has a function of suppressing hydrogen diffusion is preferably provided so as to cover the transistor 200. In the semiconductor device described in this embodiment, the insulator is, for example, an insulating layer 282 or an insulating layer 283. Alternatively, a similar film may be provided under the transistor 200.

[0147] It is preferable that one or more of the insulating layers 282 and 283 function as a barrier insulator that prevents impurities such as water and hydrogen from diffusing into the transistor 200 from above the transistor 200. Therefore, one or more of the insulating layers 282 and 283 can prevent impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0148] The insulating layers 282 and 283 preferably include an insulator that has a function of suppressing diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulating layer 283 is preferably made of silicon nitride, which has a higher hydrogen barrier property. Furthermore, the insulating layer 282 preferably includes aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen. This can suppress diffusion of impurities such as water and hydrogen from an interlayer insulating film disposed outside the insulating layer 283 to the transistor 200 and the like. Furthermore, oxygen contained in the insulating layer 280 and the like can be suppressed from diffusing upward from the transistor 200 and the like through the insulating layer 282 and the like. Furthermore, providing a film similar to one or both of the insulating layers 282 and 283 below the transistor 200 can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 and the like.

[0149] The insulating layers 271a and 271b are inorganic insulators that function as etching stoppers and protect the conductive layers 242a and 242b when the conductive layers 242a and 242b are processed. Furthermore, since the insulating layers 271a and 271b are in contact with the conductive layers 242a and 242b, they are preferably inorganic insulators that do not easily oxidize the conductive layers 242a and 242b. For example, the insulating layers 271a and 271b may have a stacked structure, with silicon nitride used on the side in contact with the conductive layers 242a and 242b and silicon oxide used on the other side.

[0150] Openings reaching the conductive layer 242a are formed in the insulating layers 285, 283, 282, 280, 275, and 271a, and the conductive layer 240a and the insulating layer 241a are provided in the openings. The insulating layer 241a is provided in contact with the sidewall of the opening, and the conductive layer 240a is provided inside the insulating layer 241a. Furthermore, openings reaching the conductive layer 242b are formed in the insulating layers 285, 283, 282, 280, 275, and 271b, and the conductive layer 240b and the insulating layer 241b are provided in the openings. The insulating layer 241b is provided in contact with the sidewall of the opening, and the conductive layer 240b is provided inside the insulating layer 241b. The conductive layers 240 a and 240 b function as vias that connect a wiring or the like provided over the transistor 200 to the source or drain of the transistor 200 .

[0151] The conductive layers 240a and 240b are preferably made of a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layers 240a and 240b may have a stacked structure.

[0152] 6, the conductive layer 240a and the conductive layer 240b may have a two-layer laminated structure. The conductive layer 240a has a conductive layer 240a1 formed along the opening and a conductive layer 240a2 formed inside the conductive layer 240a1. The conductive layer 240b has a conductive layer 240b1 formed along the opening and a conductive layer 240b2 formed inside the conductive layer 240b1.

[0153] The conductive layers 240a1 and 240b1 are preferably made of a conductive material such as tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide, which has a function of suppressing the permeation of impurities such as water and hydrogen. Furthermore, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. Providing the conductive layers 240a1 and 240b1 can suppress impurities such as water and hydrogen from entering the semiconductor layer 230 through the conductive layers 240a2 and 240b2. Note that the conductive layers 240a2 and 240b2 may be made of the same conductive materials that can be used for the conductive layers 240a and 240b.

[0154] 5B, the upper surfaces of the conductive layers 240a and 240b may be formed to coincide or substantially coincide with the upper surface of the insulating layer 285. As shown in FIG. 6, the lower portion of the conductive layer 240a may be formed to be embedded in the conductive layer 242a. Similarly, the lower portion of the conductive layer 240b may be formed to be embedded in the conductive layer 242b.

[0155] The insulating layers 241a and 241b may be formed using a barrier insulator that can be used for the insulating layer 275, for example. For example, silicon nitride may be used for the insulating layers 241a and 241b. The insulating layers 241a and 241b are provided in contact with the insulating layers 285, 283, 282, 275, 271a, and 271b. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 from entering the semiconductor layer 230 through the conductive layers 240a and 240b. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layers 240a and 240b.

[0156] The conductive layer 260 functions as a gate electrode of the transistor 200. Here, the conductive layer 260 is preferably provided to extend in the channel width direction, as shown in Figures 5A and 5C. With this structure, when a plurality of transistors are provided, the conductive layer 260 functions as a wiring.

[0157] The conductive layer 260 may have a stacked structure. Figure 6 shows an example in which the conductive layer 260 includes a conductive layer 260a located on the side in contact with the insulating layer 250 and a conductive layer 260b thereon. In this case, the conductive layer 260a is preferably made of a conductive material that is resistant to oxidation, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, or a conductive material that has a function of suppressing oxygen diffusion. The conductive layer 260b is preferably made of a low-resistance conductive material, such as tungsten, copper, or aluminum.

[0158] The insulating layer 280 preferably has a low dielectric constant. By using a material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, the insulating layer 280 preferably includes one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide with vacancies. Silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0159] Here, an opening 220 is provided in the insulating layer 201, reaching the substrate 210. In the opening 220, the semiconductor layer 230 and the substrate 210 are in contact with each other.

[0160] 5B and 6 show an example in which the opening 220 is provided in a position overlapping with the conductive layer 240a. More specifically, the conductive layer 240a is provided so as to overlap with a region where the semiconductor layer 230 and the substrate 210 are in contact with each other. By arranging the opening 220 so as to overlap with a part of the transistor 200 in this manner, an increase in the area occupied by the transistor 200 due to the provision of the opening 220 can be prevented, and the transistors 200 can be integrated at approximately the same density as when the opening 220 is not provided.

[0161] In the transistor 200, the opening 220, which is a region where crystal growth of the semiconductor layer 230 starts, is misaligned with the channel formation region. This allows a flat portion of the semiconductor layer 230 to be used as the channel formation region, resulting in a transistor with excellent electrical characteristics and reliability.

[0162] [Modification] The following describes an example in which the configuration is partially different from the above configuration example, and the description of parts that overlap with the above will be omitted.

[0163] 7 shows an example in which a conductive layer 205 functions as a back gate. The structure shown in FIG.

[0164] The conductive layer 205 is provided so as to be embedded in the insulating layer 202. The insulating layer 201 is provided so as to cover the insulating layer 202 and the conductive layer 205.

[0165] The conductive layer 205 functions as a second gate (back gate) of the transistor 200. The conductive layer 205 is provided in a region overlapping with the conductive layer 260 with the semiconductor layer 230 interposed therebetween.

[0166] The conductive layer 205 can be formed using a material that can be used for the conductive layer 260. The conductive layer 205 may have a stacked structure.

[0167] In this case, the insulating layer 201 functions as a second gate insulating layer. In this case, it is preferable that the insulating layer 201 has a stacked structure, and a high-dielectric-constant material such as hafnium oxide, aluminum oxide, or hafnium aluminate is used as a part of the stacked structure.

[0168] A silicon oxide film can be used for the insulating layer 202. Note that it is preferable to provide an insulating film having a barrier property against oxygen, such as silicon nitride or aluminum oxide, between the insulating layer 202 and the conductive layer 205 because oxidation of the conductive layer 205 can be suppressed.

[0169] The opening 220 is provided in the insulating layer 201 and the insulating layer 202. The semiconductor layer 230 has a region in contact with the side surface of the insulating layer 201 and the side surface of the insulating layer 202 near the opening 220. The opening 220 is provided in a region that does not overlap with the conductive layer 205. This can prevent the semiconductor layer 230 and the conductive layer 205 from contacting each other and causing an electrical short circuit.

[0170] 8A to 8D show examples of a transistor 200 that is partially different from the above-described configuration. FIG. 8A is a top view, and FIGS. 8B to 8D are cross-sectional views, respectively. The configurations shown in FIGS. 8A to 8D differ from the above-described configuration mainly in that an insulating layer 255 is included. Furthermore, the insulating layer 250 is in contact with a side surface of the insulating layer 255.

[0171] Here, each of the conductive layers 242a and 242b is shown to have a two-layer structure. The conductive layer 242a has a stacked structure of a conductive layer 242a1 and a conductive layer 242a2 over the conductive layer 242a1. The conductive layer 242b has a stacked structure of a conductive layer 242b1 and a conductive layer 242b2 over the conductive layer 242b1.

[0172] Insulating layer 255 is disposed inside an opening formed in insulating layer 280 or the like, and contacts the side surface of insulating layer 280, the side surface of conductive layer 242a2, the side surface of conductive layer 242b2, the top surface of conductive layer 242a1, the top surface of conductive layer 242b1, and the top surface of insulating layer 201 in the opening. In other words, insulating layer 255 can be said to be formed in a sidewall shape in contact with the side wall of the opening formed in insulating layer 280 or the like. Here, the side wall of the opening corresponds to, for example, the side surface of insulating layer 280 or the like in the opening.

[0173] The insulating layer 255 preferably has a barrier property against oxygen. The insulating layer 255 having a barrier property against oxygen can prevent the side surfaces of the conductive layers 242a and 242b from being oxidized and an oxide film from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200. The insulating layer 255 can be formed using a barrier insulator that can be used for the insulating layer 275, for example. For example, silicon nitride can be used for the insulating layer 255.

[0174] The opening in the insulating layer 280 overlaps the region between the conductive layer 242a2 and the conductive layer 242b2. In a top view, the side surfaces of the insulating layer 280 in the opening coincide or substantially coincide with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2. Furthermore, portions of the conductive layers 242a1 and 242b1 are formed to protrude into the opening. In other words, the portion of the conductive layer 242a1 on which the insulating layer 255 is formed (hereinafter, sometimes referred to as the protruding portion of the conductive layer 242a1) protrudes toward the conductive layer 260 more than the conductive layer 242a2. Similarly, the portion of the conductive layer 242b1 on which the insulating layer 255 is formed (hereinafter, sometimes referred to as the protruding portion of the conductive layer 242b1) protrudes toward the conductive layer 260 more than the conductive layer 242b2.

[0175] Here, a portion of the top surface of the conductive layer 242a1 is in contact with the conductive layer 242a2, and a portion of the top surface of the conductive layer 242b1 is in contact with the conductive layer 242b2. Therefore, inside the opening, the insulating layer 255 is in contact with another portion of the top surface of the conductive layer 242a1, another portion of the top surface of the conductive layer 242b1, a side surface of the conductive layer 242a2, and a side surface of the conductive layer 242b2. Furthermore, the insulating layer 250 is in contact with the top surface of the semiconductor layer 230, the side surface of the conductive layer 242a1, the side surface of the conductive layer 242b1, and the side surface of the insulating layer 255.

[0176] The insulating layer 255 is formed by anisotropic etching to have a sidewall shape in contact with the side wall of the opening provided in the insulating layer 280. The insulating layer 255 is formed in contact with the side surface of the conductive layer 242a2 and the side surface of the conductive layer 242b2 and has a function of protecting the conductive layer 242a2 and the conductive layer 242b2.

[0177] 9A to 9D show examples of the structure of a transistor 200. The structure shown in FIGS. 9A to 9D differs from the above-described modification 2 mainly in that the insulating layer 255 is not provided.

[0178] In a configuration in which the insulating layer 255 is not provided, a part of the insulating layer 250 is arranged to overlap the protruding portions of the conductive layer 242a1 and the protruding portions of the conductive layer 242b1. Also, a part of the conductive layer 260 may be arranged to overlap the protruding portions of the conductive layer 242a1 and the protruding portions of the conductive layer 242b1. Here, the protruding portions of the conductive layer 242a1 and the protruding portions of the conductive layer 242b1 are in contact with the insulating layer 250. Also, the side surface of the insulating layer 250 is in contact with the side surface of the insulating layer 280, the side surface of the insulating layer 275, the side surface of the insulating layer 271a, the side surface of the insulating layer 271b, the side surface of the conductive layer 242a2, and the side surface of the conductive layer 242b2.

[0179] The portions of the insulating layer 250 that are disposed in the openings provided in the insulating layer 280 are formed to reflect the shape of the openings, and therefore the insulating layer 250 is formed to reflect the shapes of the conductive layers 242a1 and 242b1 that protrude into the openings.

[0180] 9B , in a cross-sectional view of the transistor 200 in the channel length direction, the distance between the conductive layer 242a1 and the conductive layer 242b1 is smaller than the distance between the conductive layer 242a2 and the conductive layer 242b2. This configuration allows the distance between the source and the drain to be shortened, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0181] [Modification 4] In the above example, the opening 220 is provided at a position overlapping with the conductive layer 240a. However, below, an example in which the opening 220 does not overlap with the conductive layer 240a will be shown.

[0182] 10A shows an example in which the opening 220 is disposed outside the conductive layer 240a. The semiconductor layer 230 extends outside the conductive layer 240a and has a region that overlaps with the opening 220.

[0183] With this structure, not only the channel formation region of the semiconductor layer 230 but also the source region and drain region can be formed in the flat portion of the semiconductor layer 230, so that a highly reliable transistor can be realized without being affected by steps.

[0184] FIG. 10B shows an example in which the semiconductor layer 230 is not provided in the opening 220 .

[0185] The semiconductor layer 230 is provided only on the insulating layer 201 and does not overlap with the opening 220. In addition, an insulating layer 275 is provided in the opening 220 and its vicinity so as to cover the end portion of the insulating layer 201 and the upper surface of the substrate 210. This makes it possible to prevent impurities contained in the substrate 210 from diffusing into the semiconductor layer 230 even when the impurities are released by heat treatment or the like, thereby realizing a highly reliable transistor.

[0186] [Modification 5] In the above, a configuration in which the gate electrode is buried has been described, but a transistor with a different configuration will be described below.

[0187] 11A shows a cross-sectional view of the transistor 200a in the channel length direction. The transistor 200a includes a semiconductor layer 230, an insulating layer 250, a conductive layer 260, a conductive layer 242a, and a conductive layer 242b. The semiconductor layer 230 is in contact with the substrate 210 through an opening 220 provided in the insulating layer 201.

[0188] An insulating layer 250 is provided to cover the semiconductor layer 230, and a conductive layer 260 is provided on the insulating layer 250 at a position overlapping with the semiconductor layer 230. In addition, an insulating layer 281 and an insulating layer 280 are stacked to cover the insulating layer 250 and the conductive layer 260. A pair of openings reaching the semiconductor layer 230 is provided in each of the insulating layer 281, the insulating layer 280, and the insulating layer 250. The conductive layer 242a and the conductive layer 242b are provided over the insulating layer 280 and are in contact with the semiconductor layer 230 in the openings.

[0189] The insulating layer 281 can be made of an insulator having a barrier property against hydrogen and oxygen, similar to the insulating layer 275. This can prevent impurities contained in the insulating layer 280 from diffusing into the semiconductor layer 230 and prevent oxygen contained in the semiconductor layer 230 from diffusing toward the insulating layer 280.

[0190] A region of the semiconductor layer 230 overlapping with the conductive layer 260 functions as a channel formation region. A pair of regions 230 n sandwiching the channel formation region functions as a source region or a drain region. The region 230 n preferably has lower resistance than the channel formation region.

[0191] For example, the region 230n preferably contains an element that imparts conductivity to the semiconductor layer 230. Examples of such elements include titanium, aluminum, tantalum, tungsten, tin, silicon, germanium, zirconium, hafnium, antimony, magnesium, hydrogen, boron, and phosphorus. The element can be introduced into a portion of the semiconductor layer 230 by a method such as doping, ion implantation, or thermal diffusion. For example, using the conductive layer 260 as a mask, the element can be introduced into a region of the semiconductor layer 230 that does not overlap with the conductive layer 260 via the insulating layer 250 by a doping method or an ion implantation method.

[0192] 11B shows an example in which the insulating layer 250 is located only in the region overlapping with the conductive layer 260, and is not provided on the region 230n of the semiconductor layer 230. In this case, by using a film containing the above-mentioned element for the insulating layer 281 in contact with the region 230n, the element can be introduced into the region 230n during the formation of the insulating layer 281 or by subsequent heat treatment or the like. For example, it is preferable to use silicon nitride containing hydrogen for the insulating layer 281. Alternatively, an oxide of the above-mentioned metal element may be used.

[0193] 11A and 11B show an example in which the contact portion between the conductive layer 242a and the semiconductor layer 230 overlaps with the opening 220, but as shown in Fig. 10A, the opening 220 and the contact portion may not overlap. Also, as shown in Fig. 10B, the opening 220 and the semiconductor layer 230 may not overlap.

[0194] 11C shows an example in which the opening 220 and the semiconductor layer 230 do not overlap. In this case, the insulating layer 250 extends over the opening 220 and is provided in contact with the upper surface of the substrate 210 at the opening 220. This makes it possible to suppress the diffusion of impurities contained in the substrate 210 into the semiconductor layer 230.

[0195] [Modification 6] A vertical transistor in which the source electrode and the drain electrode are located at different heights will be described below.

[0196] 12A is a schematic cross-sectional view of a transistor 200b. The transistor 200b includes a semiconductor layer 230, an insulating layer 250, a conductive layer 260, a conductive layer 245, and a conductive layer 246. The conductive layer 245 serves as one of a source electrode and a drain electrode, and the conductive layer 246 serves as the other electrode.

[0197] A conductive layer 245 is provided over the insulating layer 201, and an insulating layer 211 is provided to cover the conductive layer 245. A conductive layer 246 is provided over the insulating layer 211. Openings reaching the conductive layer 245 are provided in the conductive layer 246 and the insulating layer 211. The semiconductor layer 230 is provided in contact with a top surface of the conductive layer 246, side surfaces of the conductive layer 246 in the openings, side surfaces of the insulating layer 211, and a top surface of the conductive layer 245. The insulating layer 250 is provided to cover the semiconductor layer 230 inside the openings, and the conductive layer 260 is provided to cover the insulating layer 250.

[0198] In the transistor 200b, the source electrode and the drain electrode are located at different heights, and a current flows in the height direction of the semiconductor layer. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor 200b can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like. Since the transistor 200b can have two or more of the source electrode, the semiconductor, and the drain electrode stacked, it can occupy a significantly smaller area than a so-called planar transistor (which can also be called a lateral transistor, LFET (Lateral FET), or the like) in which the semiconductor is arranged on a plane.

[0199] Furthermore, the channel length of the transistor 200b can be precisely controlled by the thickness of the insulating layer 211, which functions as a spacer. This significantly reduces the variation in the channel length compared to planar transistors. Furthermore, by thinning the insulating layer 211, a transistor with an extremely short channel length can be manufactured. For example, a transistor with a channel length of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more can be manufactured. Therefore, a transistor with an extremely short channel length that could not be realized using a mass-production exposure tool can be realized. Furthermore, a transistor with a channel length of less than 10 nm can be manufactured without using an extremely expensive exposure tool used in cutting-edge LSI technology.

[0200] Furthermore, an opening 220 reaching the substrate 210 is provided in the conductive layer 246 , the insulating layer 211 , and the insulating layer 201 , and the semiconductor layer 230 and the substrate 210 are in contact with each other in the opening 220 .

[0201] 12B , a configuration may be adopted in which the semiconductor layer 230 is not provided in the opening 220. In this case, it is preferable that the insulating layer 250 is provided in contact with the upper surface of the substrate 210 in the opening 220, and the surface of the substrate 210 is not exposed.

[0202] In the transistor 200b, the opening provided in the insulating layer 211 can have various shapes.

[0203] FIG. 12C shows a perspective view of the insulating layer 211 and the semiconductor layer 230. Here, an example is shown in which a cylindrical opening 290o is provided in the insulating layer 211. In this case, the semiconductor layer 230 has a cylindrical portion along the sidewall of the opening 290o and flat portions at the bottom and top that are parallel to the substrate surface. In the configuration shown in FIG. 12C, the channel width of the transistor roughly corresponds to the circumferential length of the cylindrical portion. Therefore, in the configuration shown in FIG. 12C, it is easy to reduce the channel length and increase the channel width, thereby realizing a transistor that can pass an extremely large current.

[0204] 12D shows an example in which a slit-shaped opening 290s is provided in the insulating layer 211. As shown in Fig. 12D, a plurality of semiconductor layers 230 can be arranged in the opening 290s, which is suitable for arranging transistors at a high density. Although not shown here, a conductive layer 260 functioning as a gate electrode is provided so as to be embedded in the opening 290s and can be used as a wiring extending in the extension direction of the opening 290s.

[0205] The above is a description of the modified example.

[0206] [Manufacturing Method Example] An example of a manufacturing method of a transistor of one embodiment of the present invention will be described below, taking the transistor 200 illustrated in FIG. 10B as an example.

[0207] 13A1, 13B1, 13C1, 13D1, 14A1, 14B1, and 14C1 are cross-sectional schematic views at various stages of the exemplary fabrication method described below, and FIGS. 13A2, 13B2, 13C2, 13D2, 14A2, 14B2, and 14C2 are perspective views. Note that the perspective views are partially cut away. In addition, in the perspective views, only the outlines of some components (such as insulating layers) are shown by dashed lines.

[0208] First, an insulating layer 201 is formed over a substrate 210, an opening 220 reaching the substrate 210 is formed in the insulating layer 201, and then a semiconductor film 230f is formed. For the substrate 210, the insulating layer 201, the opening 220, and the semiconductor film 230f, the methods for manufacturing the substrate 11, the insulating layer 12, the opening 20, and the semiconductor film 21f in Embodiment 1 can be referred to, respectively.

[0209] It is preferable to perform heat treatment on the semiconductor film 230f. For example, the heat treatment can be performed at 450° C. for one hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. The heat treatment can improve the crystallinity of the semiconductor film 230f. Furthermore, the heat treatment can supply oxygen into the semiconductor film 230f and reduce oxygen vacancies in the semiconductor film 230f. This can improve the reliability of the transistor 200. The heat treatment can also remove hydrogen from the semiconductor film 230f.

[0210] Next, a conductive film 242f is formed on the semiconductor film 230f (FIGS. 13A1 and 13A2). After the semiconductor film 230f is formed, the conductive film 242f is formed on and in contact with the semiconductor film 230f without an etching process or the like. This makes it possible to protect the top surface of the semiconductor film 230f with the conductive film 242f. This makes it possible to suppress diffusion of impurities into the semiconductor layer 230 that constitutes the transistor, thereby improving the electrical characteristics and reliability of the semiconductor device.

[0211] The conductive film 242f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0212] In this embodiment, tantalum nitride is deposited as the conductive film 242f by sputtering. Note that heat treatment may be performed before the deposition of the conductive film 242f. The heat treatment may be performed under reduced pressure, and the conductive film 242f may be deposited successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the semiconductor film 230f can be removed, and the moisture and hydrogen concentrations in the semiconductor film 230f can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0213] Next, the semiconductor film 230f and the conductive film 242f are processed into island shapes by lithography to form the semiconductor layer 230 and the conductive layer 242 (FIG. 13B1 and FIG. 13B2).

[0214] Here, an example is shown in which the region of the semiconductor film 230f that overlaps with the opening 220 is removed by etching. At this time, the upper surface of the substrate 210 is exposed at the opening 220 as shown in FIG.

[0215] The above processing can be performed by dry etching or wet etching. Dry etching is suitable for fine processing. The semiconductor film 230f and the conductive film 242f may be processed under different conditions.

[0216] Further, a layer functioning as a hard mask may be formed over the conductive film 242f. The use of a hard mask is preferable because it improves processability and makes it easier to process the conductive film 242f into a desired shape.

[0217] Here, the semiconductor layer 230 and the conductive layer 242 are preferably processed together into an island shape. At this time, it is preferable that the side edge of the conductive layer 242 coincides or substantially coincides with the side edge of the semiconductor layer 230. With such a structure, the number of steps for manufacturing a semiconductor device according to one embodiment of the present invention can be reduced. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0218] 13B1 , the side surfaces of the semiconductor layer 230 and the conductive layer 242 may be tapered. The taper angle of the side surfaces of the semiconductor layer 230 and the conductive layer 242 may be, for example, 60° or more and less than 90°. By tapering the side surfaces in this manner, the coverage of the insulating layer 275 and the like can be improved in subsequent steps, and defects such as voids can be reduced.

[0219] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left behind using a developer to form a resist mask. Next, an etching process is performed through the resist mask, allowing a conductor, semiconductor, or insulator to be processed into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Alternatively, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask may not be required.

[0220] The resist mask that is no longer needed after processing can be removed by performing a dry etching treatment such as ashing using oxygen plasma (hereinafter, sometimes referred to as oxygen plasma treatment), a wet etching treatment, a dry etching treatment followed by a wet etching treatment, or a wet etching treatment followed by a dry etching treatment.

[0221] Furthermore, a hard mask made of an insulator or conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as the hard mask material is formed on the conductive film 242f, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. For example, tungsten may be used as the hard mask material. Etching of the conductive film 242f and the like may be performed after removing the resist mask or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching of the semiconductor film 230f and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0222] Alternatively, a spin-on-carbon (SOC) film and a spin-on-glass (SOG) film may be formed between the workpiece and the resist mask. Using the SOC film and the SOG film as a mask can improve adhesion with the resist mask and improve the durability of the mask pattern. For example, a lithography method can be performed by forming an SOC film, an SOG film, and a resist mask in this order on the workpiece.

[0223] Next, an insulating layer 275 is formed to cover the semiconductor layer 230 and the conductive layer 242, and an insulating layer 280 is further formed on the insulating layer 275 (FIGS. 13C1 and 13C2).

[0224] At this time, the insulating layer 275 is provided so as to cover the upper surface of the substrate 210 in the opening 220 .

[0225] As the insulating layer 280, it is preferable to form an insulator having a flat upper surface by forming an insulating film that will become the insulating layer 280 and performing CMP treatment on the insulating film. Note that it is also possible to form a silicon nitride film on the insulating layer 280 by, for example, a sputtering method and perform CMP treatment on the silicon nitride until it reaches the insulating layer 280.

[0226] The insulating layer 275 and the insulating layer 280 can each be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0227] The insulating layer 275 is preferably an insulator having a function of suppressing oxygen permeation. For example, it is preferable to form a silicon nitride film by a PEALD method as the insulating layer 275. Alternatively, the insulating layer 275 may be formed by forming an aluminum oxide film by a sputtering method and then forming a silicon nitride film thereon by a PEALD method. The insulating layer 275 having the above structure can improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0228] Furthermore, it is preferable to form the insulating layer 280 using silicon oxide by a sputtering method. The insulating layer 280 containing excess oxygen can be formed by forming the insulating layer 280 by a sputtering method in an oxygen-containing atmosphere. Furthermore, the hydrogen concentration in the insulating layer 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. Heat treatment may be performed before the formation of the insulating layer. The heat treatment may be performed under reduced pressure, and the insulating layer may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulating layer 275 can be removed. The heat treatment conditions described above can be used for the heat treatment.

[0229] Next, the conductive layer 242, the insulating layer 275, and the insulating layer 280 are processed by lithography to form openings (also referred to as grooves) that reach the semiconductor layer 230 and the insulating layer 201 ( FIGS. 13D1 and 13D2 ). Here, the conductive layer 242 is divided to form conductive layers 242a and 242b. The openings formed in the insulating layer 280 and the insulating layer 275 overlap with the semiconductor layer 230.

[0230] Next, the insulating layer 250 is formed so as to cover the openings formed in the insulating layer 280 and the like. Here, the insulating layer 250 is formed along the openings of the insulating layer 280. The insulating layer 250 is in contact with the insulating layer 280, the conductive layer 242a, the conductive layer 242b, the insulating layer 201, and the semiconductor layer 230.

[0231] The insulating layer 250 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Since the insulating layer 250 is preferably formed to have a thin film thickness, it is preferable to form the insulating layer 250 by an ALD method, which has excellent coverage and is easy to control the film thickness.

[0232] When the insulating layer 250 is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２By using HCl, etc. as an oxidizing agent, hydrogen diffusing into the semiconductor layer 230 can be reduced.

[0233] It is preferable to perform microwave treatment before, after, or during the formation of the insulating layer 250 .

[0234] More specifically, microwave treatment is preferably performed in an oxygen-containing atmosphere. Here, microwave treatment refers to treatment using, for example, a device having a power source that generates high-density plasma using microwaves. In this specification and the like, microwave refers to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0235] In the microwave treatment, it is preferable to use a microwave treatment device having a power supply that generates high-density plasma using microwaves, for example. The frequency of the microwave treatment device can be typically 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves in the microwave treatment device is preferably 1000 W or more and 10,000 W or less, and preferably 2000 W or more and 5,000 W or less. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the semiconductor layer 230.

[0236] The microwave treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or higher and 1000 Pa or lower, and more preferably being 300 Pa or higher and 700 Pa or lower. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. The heat treatment temperature is, for example, preferably 100°C or higher and 750°C or lower, and more preferably 300°C or higher and 500°C or lower.

[0237] Next, a conductive film to be the conductive layer 260 is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method. For example, a titanium nitride film and a tungsten film may be stacked by a CVD method.

[0238] Next, the conductive film that will become the insulating layer 250 and the conductive layer 260 is polished by CMP until the insulating layer 280 is exposed. That is, the insulating layer 250 and the portions of the conductive film that are exposed in the openings are removed. This forms the insulating layer 250 and the conductive layer 260 in the openings that reach the semiconductor layer 230 (FIGS. 14A1 and 14A2).

[0239] As a result, the insulating layer 250 is provided in the opening in contact with the conductive layer 242a, the conductive layer 242b, the semiconductor layer 230, and the insulating layer 201. The conductive layer 260 is also arranged to fill the opening with the insulating layer 250 interposed therebetween. In this manner, the transistor 200 is formed.

[0240] Next, an insulating layer 282 is formed over the insulating layer 250, the conductive layer 260, and the insulating layer 280. The insulating layer 282 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulating layer 282 is preferably formed by a sputtering method. The hydrogen concentration in the insulating layer 282 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas.

[0241] Here, by depositing the insulating layer 282 in an atmosphere containing oxygen by a sputtering method, oxygen can be added to the insulating layer 280 during deposition. Thus, the insulating layer 280 can contain excess oxygen.

[0242] Next, an insulating layer 285 is formed over the insulating layer 282 (FIGS. 14B1 and 14B2). The insulating layer 285 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulating layer 285 is preferably formed by a sputtering method. The hydrogen concentration in the insulating layer 285 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas.

[0243] Next, openings reaching the conductive layers 242a and 242b are formed in the insulating layer 275, the insulating layer 280, the insulating layer 282, and the insulating layer 285, respectively. The openings may be formed by lithography. The openings are preferably formed by processing the workpiece by dry etching. The shape of the openings in top view can be a circle, a substantially circle such as an ellipse, a polygon such as a rectangle, or a polygon with rounded corners such as a rectangle.

[0244] Next, after the openings are formed, heat treatment can be performed. The temperature for the heat treatment is 100° C. or higher and 600° C. or lower, preferably 250° C. or higher and 550° C. or lower, more preferably 350° C. or higher and 450° C. or lower. Note that the heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. Furthermore, since the heat treatment is performed in a state in which the conductive layers 242a and 242b are exposed, the heat treatment is preferably performed in an atmosphere that does not contain an oxidizing gas or oxygen gas. For example, the heat treatment is preferably performed in a nitrogen gas atmosphere at 400° C. for one hour. Note that the heat treatment may be performed under reduced pressure. By the heat treatment, oxygen contained in the insulating layer 280 can be supplied to the semiconductor layer 230 through the insulating layer 250. Furthermore, by performing the heat treatment after the openings are formed in the insulating layer 280, part of the oxygen contained in the insulating layer 280 can be released, and the amount of oxygen contained in the insulating layer 280 can be adjusted. This prevents reliability from being impaired by excess oxygen.

[0245] Next, insulating films to become the insulating layers 241a and 241b are formed along the shapes of the openings. The insulating films can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating films to become the insulating layers 241a and 241b are preferably formed by an ALD method because they are formed in openings with a large aspect ratio. Furthermore, it is preferable to use an insulating film that has a function of suppressing oxygen permeation as the insulating film to become the insulating layers 241a and 241b. For example, it is preferable to form a silicon nitride film by a PEALD method. Silicon nitride is preferable because it has a high barrier property against hydrogen.

[0246] Next, the insulating film is anisotropically etched to form insulating layers 241a and 241b. Here, the insulating layer 241a is formed to cover the sidewalls of the openings over the conductive layer 242a, and the insulating layer 241b is formed to cover the sidewalls of the openings over the conductive layer 242b. Dry etching or the like may be used for anisotropically etching the insulating films that will become the insulating layers 241a and 241b. For example, reactive ion etching is preferably performed. Providing the insulating layers 241a and 241b on the sidewalls of the openings can suppress oxygen permeation from the outside and prevent oxidation of the conductive layers 240a and 240b to be formed next. Furthermore, impurities such as water and hydrogen contained in the insulating layer 280 can be prevented from diffusing into the conductive layers 240a and 240b. Note that the anisotropic etching may form recesses in parts of the top surfaces of the conductive layers 242a and 242b.

[0247] Next, conductive films to be the conductive layers 240a and 240b are formed. The conductive films preferably have a stacked structure including a conductor that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, the conductive films can be stacked layers of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive films to be the conductive layers 240a and 240b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0248] Next, CMP treatment is performed to remove parts of the conductive film that will become the conductive layers 240a and 240b, thereby exposing the top surface of the insulating layer 285 (FIGS. 14C1 and 14C2). As a result, the conductive film remains only in the openings, and the conductive layers 240a and 240b can be formed with flat top surfaces. Note that the CMP treatment may remove part of the top surface of the insulating layer 285.

[0249] After the conductive layers 240a and 240b are formed, heat treatment may be further performed. The heat treatment may be performed under the same conditions as those of the above-described heat treatment. By performing the heat treatment, the amount of oxygen supplied to the semiconductor layer 230 can be adjusted. This can improve the electrical characteristics and reliability of the transistor 200.

[0250] Through the above steps, the transistor 200 illustrated in FIG. 10B can be manufactured.

[0251] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0252] Embodiment 3 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor according to one embodiment of the present invention will be described.

[0253] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0254] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0255] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 15A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ) and FIG. 15B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0256] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 15B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 15A (see Non-Patent Document 3). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 15A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 15A.

[0257] 15A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0258] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0259] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0260] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0261] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 15A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0262] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0263] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 15B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei is finally achieved, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the transistor may no longer function. On the other hand, in indium oxide, as shown in FIG. 15A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei is finally achieved, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0264] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0265] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0266] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0267] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0268] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0269] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0270] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0271] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0272] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0273] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0274] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0275] In addition, the indium oxide film in this specification and the like has a high film density. ２ O ３ The film densities of the films are shown in Table 2.

[0276]

[0277] As shown in Table 2, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 2, Condition 1 is the condition of the base of the indium oxide film, Samples 1 to 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition of the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the formation of the indium oxide film, with Sample 1, Sample 4, and Sample 5 being no heat treatment (as-deposited), Sample 2 being baked at 350°C in a CDA atmosphere, Sample 3 being baked at 650°C in a CDA atmosphere, and Sample 6 being baked at 250°C in a vacuum atmosphere.

[0278] In Table 2, CDA stands for clean dry air. It is preferable that the atmosphere used in the heat treatment (condition 3) after the formation of the indium oxide film contains as little hydrogen and water as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower, as the atmosphere.

[0279] As shown in Table 2, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment removes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) from the film, thereby increasing the purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. ３ The theoretical film density of an indium oxide film is 7.18 g / cm ３ In this specification, the range of the film density of the indium oxide film is 6.70 g / cm ３ 7.18g / cm or more ３ Preferably, it is 6.90 g / cm or less. ３ 7.18g / cm or more ３ More preferably, it is 7.00 g / cm or less. ３ 7.18g / cm or more ３ The following is the result.

[0280] The film density can be evaluated by, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated by cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image.

[0281] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0282] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 15C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0283] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0284] Furthermore, as shown in FIG. 15C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the film and is released as water molecules. The oxygen and hydrogen diffuse in the indium oxide film by heat treatment. The temperature of the heat treatment is 200° C. or higher and 700° C. or lower, preferably 350° C. or higher and 650° C. or lower, and more preferably 400° C. or higher and 500° C. or lower.

[0285] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0286] Table 3 shows the results of single crystal indium oxide (here, In ２ O ３) and single-crystal silicon (Si). As shown in Table 3, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 3, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0287]

[0288] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0289] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0290] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0291] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0292] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0293] Here, a comparison is made among a transistor having a crystalline indium oxide film, a transistor having an IGZO (a compound oxide of In, Ga, and Zn) film, and a transistor having a silicon (Si) film. The comparison is shown in Table 4.

[0294]

[0295] In Table 4, transistors having a crystalline indium oxide film are intended for use in LSIs and are clearly indicated as crystalline IO (LSI). Hereinafter, this may be simply referred to as crystalline IO. Transistors having an IGZO film are intended for use in displays and are clearly indicated as IGZO (Display). Hereinafter, this may be simply referred to as IGZO. Transistors having a Si film are also clearly indicated as Si. In Table 4, ◎ represents +2 points, ○ represents +1 point, △ represents 0 points, and × represents −1 point, respectively. Total is the total value of the ◎, ○, △, and × points shown in Table 4. A higher score indicates better characteristics than a lower score.

[0296] In Table 4, the first comparison item is extremely small off-state current, with crystalline IO and IGZO being superior to Si. The second comparison item is on-state current (Ion) characteristics, with crystalline IO and Si being superior to IGZO. The third comparison item is reliability, with crystalline IO and Si being superior to IGZO. The fourth comparison item is miniaturization of channel length, with crystalline IO and IGZO being superior to Si. In the section on miniaturization of channel length, VFET represents a vertical transistor, UFET represents a transistor with a U-shape structure, and 3D structure represents a three-dimensional structure. The fifth comparison item is cutoff frequency, with the characteristics increasing in the order of crystalline IO, Si, and IGZO. The sixth comparison item is improvement in integration, with Si being superior to crystalline IO and IGZO. The seventh comparison item is threshold voltage controllability (Vth controllability), in which Si is superior to crystalline IO and IGZO. The eighth comparison item is radiation resistance, in which crystalline IO and IGZO are superior to Si. The ninth comparison item is 3D (multi-level) integrated structure, in which crystalline IO and IGZO are superior to Si. The tenth comparison item is the possibility of self-heating, in which crystalline IO and IGZO are superior to Si.

[0297] As shown in Table 4, the total score for crystalline IO (LSI) is 9 points, for IGZO (Display) is 4 points, and for Si is 3 points. As described above, the semiconductor device of one embodiment of the present invention, in particular the semiconductor device including a crystalline indium oxide film, has the potential to replace a semiconductor device using Si.

[0298] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0299] 16 to 19. In this embodiment, a configuration example of a memory device in which a layer having memory cells is stacked over a layer in which a driver circuit including a sense amplifier is provided will be described.

[0300] The transistor in which a channel is formed in a single crystal oxide semiconductor (referred to as an OS transistor) described in Embodiment 2 can be used as a transistor included in a memory cell described below.

[0301] 16 is a block diagram illustrating a configuration example of a memory device 480 according to one embodiment of the present invention. The memory device 480 illustrated in FIG. 16 includes a layer 420 and a stacked layer 470.

[0302] The layer 420 is a layer including a Si transistor. The layer 470 includes stacked element layers 430[1] to 430[m] (m is an integer of 2 or more). The element layers 430[1] to 430[m] include OS transistors. The layer 470 including stacked layers including OS transistors can be provided over the layer 420.

[0303] 16 illustrates an example in which the element layers 430[1] to 430[m] each include a plurality of memory cells 432 arranged in a matrix of m rows and n columns (n ​​is an integer of 2 or greater).

[0304] In FIG. 16 , the memory cell 432 in the first row and first column is indicated as memory cell 432[1,1], and the memory cell 432 in the mth row and nth column is indicated as memory cell 432[m,n]. In addition, in this embodiment and the like, an arbitrary row may be referred to as row i. In addition, an arbitrary column may be referred to as column j. Therefore, i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to n. In addition, in this embodiment and the like, the memory cell 432 in the ith row and jth column is indicated as memory cell 432[i,j]. In addition, in this embodiment and the like, when "i+α" (α is a positive or negative integer) is used, "i+α" is not less than 1 or more than m. Similarly, when "j+α" is used, "j+α" is not less than 1 or more than n.

[0305] 16 illustrates, as an example, m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment and the like, the first wiring WL (first row) is referred to as wiring WL[1], and the mth wiring WL (mth row) is referred to as wiring WL[m]. Similarly, the first wiring PL (first row) is referred to as wiring PL[1], and the mth wiring PL (mth row) is referred to as wiring PL[m]. Similarly, the first wiring BL (first column) is referred to as wiring BL[1], and the nth wiring BL (nth column) is referred to as wiring BL[n]. Note that the number of element layers 430[1] to 430[m] does not have to be the same as the number of wirings WL (and wirings PL).

[0306] The memory cells 432 in the i-th row are electrically connected to the wiring WL in the i-th row (wiring WL[i]) and the wiring PL in the i-th row (wiring PL[i]). The memory cells 432 in the j-th column are electrically connected to the wiring BL in the j-th column (wiring BL[j]).

[0307] The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on / off (conducting state or non-conducting state) of an access transistor that functions as a switch. The wiring PL functions as a constant potential line connected to a capacitor. Note that a wiring for transmitting a back gate potential can be provided separately.

[0308] The memory cells 432 included in each of the element layers 430[1] to 430[m] are connected to a sense amplifier 446 (sense amplifier) ​​via a wiring BL. The wiring BL can be arranged in a direction parallel to or perpendicular to the surface of the substrate on which the layer 420 is provided. The wiring BL extending from the memory cells 432 included in the element layers 430[1] to 430[m] can be configured as wirings arranged vertically in addition to wirings arranged horizontally on the surface of the substrate, thereby shortening the length of the wiring between the element layer 430 and the sense amplifier 446. The signal propagation distance between the memory cell and the sense amplifier can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thereby reducing power consumption and signal delay. This can reduce the power consumption and signal delay of the memory device 480. Furthermore, the memory cell 432 can operate even if the capacitance of the capacitor included in the memory cell 432 is reduced. This can reduce the size of the memory device 480.

[0309] The layer 420 includes a PSW 471 (power switch), a PSW 472, and a peripheral circuit 422. The peripheral circuit 422 includes a drive circuit 440, a control circuit 473, and a voltage generation circuit 474. Each circuit included in the layer 420 includes a Si transistor.

[0310] In the memory device 480, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0311] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 473.

[0312] The control circuit 473 is a logic circuit having the function of controlling the overall operation of the memory device 480. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 480. Alternatively, the control circuit 473 generates a control signal for the drive circuit 440 so that this operation mode is executed.

[0313] The voltage generation circuit 474 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 474. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 474, and the voltage generation circuit 474 generates a negative voltage.

[0314] The driver circuit 440 is a circuit for writing and reading data to and from the memory cells 432. The driver circuit 440 includes a row decoder 442, a column decoder 444, a row driver 443, a column driver 445, an input circuit 447, an output circuit 448, and the sense amplifier 446 described above.

[0315] The row decoder 442 and the column decoder 444 have a function of decoding the signal ADDR. The row decoder 442 is a circuit for specifying a row to be accessed, and the column decoder 444 is a circuit for specifying a column to be accessed. The row driver 443 has a function of selecting a wiring WL specified by the row decoder 442. The column driver 445 has a function of writing data to the memory cell 432, a function of reading data from the memory cell 432, a function of holding the read data, and the like.

[0316] The input circuit 447 has a function of holding a signal WDA. The data held by the input circuit 447 is output to the column driver 445. The output data of the input circuit 447 is data (Din) to be written to the memory cell 432. The data (Dout) read from the memory cell 432 by the column driver 445 is output to the output circuit 448. The output circuit 448 has a function of holding Dout. In addition, the output circuit 448 has a function of outputting Dout to the outside of the memory device 480. The data output from the output circuit 448 is a signal RDA.

[0317] The PSW 471 has a function of controlling the supply of VDD to the peripheral circuit 422. The PSW 472 has a function of controlling the supply of VHM to the row driver 443. In this example, the high power supply voltage of the memory device 480 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 471 is controlled by a signal PON1, and the on / off of the PSW 472 is controlled by a signal PON2. In FIG. 16, the number of power domains to which VDD is supplied in the peripheral circuit 422 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0318] The element layers 430[1] to 430[m] can be stacked on the layer 420. Figure 17A is a perspective view of a memory device 480 showing five (m = 5) element layers 430[1] to 430[5] stacked on the layer 420.

[0319] 17A, the element layer 430 provided in the first layer is shown as element layer 430[1], the element layer 430 provided in the second layer is shown as element layer 430[2], and the element layer 430 provided in the fifth layer is shown as element layer 430[5]. Also shown in FIG. 17A are wirings WL and PL extending in the X direction, and wirings BL and BLB extending in the Y direction and Z direction (directions perpendicular to the surface of the substrate on which the driver circuit is provided). The wiring BLB is an inverted bit line. Note that, to make the drawing easier to understand, the wirings WL and PL included in each element layer 430 are partially omitted.

[0320] 17B is a schematic diagram illustrating a configuration example of the sense amplifier 446 connected to the wiring BL and the wiring BLB shown in FIG. 17A and the memory cells 432 included in the element layers 430[1] to 430[5] connected to the wiring BL and the wiring BLB. Note that a configuration in which a plurality of memory cells (memory cells 432) are electrically connected to one wiring BL and one wiring BLB is also referred to as a "memory string."

[0321] 17B illustrates an example of the circuit configuration of the memory cell 432 connected to the wiring BLB. The memory cell 432 includes a transistor 437 and a capacitor 438. The transistor 437, the capacitor 438, and the wirings (BL, WL, etc.) may also be referred to as wirings BL and WL, instead of wirings BL[1] and WL[1].

[0322] In the memory cell 432, one of the source and the drain of the transistor 437 is connected to a wiring BL. The other of the source and the drain of the transistor 437 is connected to one electrode of a capacitor 438. The other electrode of the capacitor 438 is connected to a wiring PL. The gate of the transistor 437 is connected to a wiring WL.

[0323] The wiring PL is a wiring that applies a constant potential for maintaining the potential of the capacitor 438. The number of wirings can be reduced by connecting a plurality of wirings PL to each other and using them as one wiring.

[0324] In one embodiment of the present invention, OS transistors are stacked, and a wiring functioning as a bit line is arranged perpendicular to the surface of the substrate on which the layer 420 is provided. Additionally, the transistor 437 and the capacitor 438 included in the memory cell 432 are arranged side by side in the perpendicular direction to the surface of the substrate on which the layer 420 is provided. By providing each element and each wiring perpendicular to the surface of the substrate, the length of the wiring between element layers can be shortened and the density of elements provided per unit area can be increased. Therefore, a memory device with excellent storage capacity and reduced power consumption can be obtained.

[0325] 18A and 18B show circuit diagrams corresponding to the memory cell 432 described above and circuit block diagrams corresponding to the circuit diagrams. As shown in FIGS. 18A and 18B, the memory cell 432 may be represented as a block in the drawings. Note that the wiring BL shown in FIGS. 18A and 18B can be similarly represented when replaced with wiring BLB.

[0326] 18C and 18D show a circuit diagram corresponding to the sense amplifier 446 and a circuit block diagram corresponding to the circuit diagram. The sense amplifier 446 includes a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplifier circuit 485. The wirings BL and BLB, as well as wirings SA_OUT and SA_OUTB for outputting signals to be read out, are also shown.

[0327] 18C, the switch circuit 482 includes, for example, N-channel transistors 482_1 and 482_2. The transistors 482_1 and 482_2 switch the conduction state between the wiring pair of the wiring SA_OUT and the wiring SA_OUTB and the wiring pair of the wiring BL and the wiring BLB in response to the signal CSEL.

[0328] 18C, the precharge circuit 483 is formed of N-channel transistors 483_1 to 483_3. The precharge circuit 483 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to a potential VDD / 2 in response to a signal EQ.

[0329] 18C, the precharge circuit 484 is configured with P-channel transistors 484_1 to 484_3. The precharge circuit 484 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to a potential VDD / 2 in response to a signal EQB.

[0330] 18C , the amplifier circuit 485 includes P-channel transistors 485_1 and 485_2 and N-channel transistors 485_3 and 485_4 connected to a wiring SAP or a wiring SAN. The wiring SAP or the wiring SAN has a function of supplying VDD or VSS. The transistors 485_1 to 485_4 are transistors that form an inverter loop.

[0331] Moreover, Fig. 18D shows a circuit block diagram corresponding to the sense amplifier 446 described in Fig. 18C etc. As shown in Fig. 18D, the sense amplifier 446 may be represented as a block in the drawings etc.

[0332] Fig. 19 is a circuit diagram of the memory device 480 of Fig. 16. Fig. 19 illustrates the circuit blocks described in Fig. 18A to Fig. 18D.

[0333] 19, the layer 470 including the element layer 430[m] includes a memory cell 432. The memory cell 432 illustrated in FIG. 19 is connected to a pair of wirings BL[1] and BLB[1] or wirings BL[2] and BLB[2], for example. The memory cell 432 connected to the wiring BL is a memory cell to which data is written or read.

[0334] The wiring BL[1] and the wiring BLB[1] are connected to a sense amplifier 446[1], and the wiring BL[2] and the wiring BLB[2] are connected to a sense amplifier 446[2]. The sense amplifier 446[1] and the sense amplifier 446[2] can read data in response to various signals described with reference to FIG.

[0335] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0336] Embodiment 5 In this embodiment, a structural example of a display device to which a transistor of one embodiment of the present invention can be applied will be described.

[0337] Since the transistor of one embodiment of the present invention can be made extremely small, a display device using the transistor of one embodiment of the present invention can have extremely high resolution. For example, the display device of one embodiment of the present invention can be used in a display portion of a wristwatch-type or bracelet-type information terminal (wearable device), a VR device such as a head-mounted display, and a head-mounted display (HMD), such as a glasses-type AR device.

[0338] In a display device according to one embodiment of the present invention, a driver circuit and a pixel circuit can be provided so as to overlap with each other. In this case, the transistor in which a channel is formed in a single-crystal oxide semiconductor, which is described in Embodiment 2 as an example, can be used as a transistor included in the pixel.

[0339] 20A shows a perspective view of a display module 580. The display module 580 has a display device 500A and an FPC 590.

[0340] The display module 580 has a substrate 591 and a substrate 592. The display module 580 has a display unit 581. The display unit 581 is an area for displaying an image.

[0341] 20B is a perspective view schematically illustrating the configuration on the substrate 591 side. A circuit portion 582, a pixel circuit portion 583 on the circuit portion 582, and a pixel portion 584 on the pixel circuit portion 583 are stacked on the substrate 591. A terminal portion 585 for connecting to the FPC 590 is provided in a portion of the substrate 591 that does not overlap with the pixel portion 584. The terminal portion 585 and the circuit portion 582 are electrically connected by a wiring portion 586 composed of a plurality of wirings.

[0342] The pixel section 584 has a plurality of periodically arranged pixels 584a. An enlarged view of one pixel 584a is shown on the right side of Fig. 20B. The pixel 584a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0343] The pixel circuit portion 583 has a plurality of pixel circuits 583a arranged periodically. Each pixel circuit 583a is a circuit that controls the light emission of three light-emitting devices included in one pixel 584a. One pixel circuit 583a may be configured to have three circuits that control the light emission of one light-emitting device. For example, the pixel circuit 583a may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting device. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.

[0344] The circuit portion 582 includes a circuit for driving each pixel circuit 583a of the pixel circuit portion 583. For example, it preferably includes one or both of a gate line driver circuit and a source line driver circuit. In addition, the circuit portion 582 may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Furthermore, a transistor provided in the circuit portion 582 may constitute a part of the pixel circuit 583a. That is, the pixel circuit 583a may be composed of a transistor included in the pixel circuit portion 583 and a transistor included in the circuit portion 582.

[0345] The FPC 590 functions as wiring for supplying a video signal, a power supply potential, and the like from the outside to the circuit portion 582. An IC may be mounted on the FPC 590.

[0346] The display module 580 can be configured such that one or both of the pixel circuit portion 583 and the circuit portion 582 are provided overlapping below the pixel portion 584, thereby enabling the aperture ratio (effective display area ratio) of the display portion 581 to be extremely high. For example, the aperture ratio of the display portion 581 can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 584a can be arranged at extremely high density, enabling the resolution of the display portion 581 to be extremely high. For example, the pixels 584a are preferably arranged in the display portion 581 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20,000 ppi or less, or 30,000 ppi or less.

[0347] Because such a display module 580 has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays, or eyeglass-type AR devices. For example, even in a configuration in which the display unit of the display module 580 is viewed through lenses, the display module 580 has an extremely high-resolution display unit 581, so even when the display unit is enlarged with lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 580 is not limited to this, and can be suitably used in electronic devices with relatively small display units. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0348] [Display Device 500A] A display device 500A shown in FIG. 21 includes a substrate 301, a light emitting element 110R, a light emitting element 110G, a light emitting element 110B, a capacitor 540, a transistor 310, and a transistor 320.

[0349] The transistor 310 is a transistor whose channel is formed in a single crystal substrate. The transistor 320 can be the transistor whose channel is formed in a single crystal oxide semiconductor, which is described in Embodiment 2 as an example.

[0350] The transistor 310 has a channel formation region in a substrate 301. The substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as one of a source and a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311.

[0351] An element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0352] The transistor 320 includes a semiconductor layer 351 , an insulating layer 353 , a conductive layer 354 , a pair of conductive layers 355 , an insulating layer 356 , and a conductive layer 357 .

[0353] An insulating layer 352 is provided over the layer where the transistor 310 is provided, with a wiring layer 316 and an interlayer insulating layer interposed therebetween. The insulating layer 352 functions as a barrier layer that prevents impurities from diffusing from the substrate 301 side to the transistor 320 and prevents oxygen from being released from the semiconductor layer 351 toward the insulating layer 352. The insulating layer 352 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0354] A conductive layer 357 is provided over the insulating layer 352, and an insulating layer 356 is provided to cover the conductive layer 357. The conductive layer 357 functions as a second gate electrode of the transistor 320, and part of the insulating layer 356 functions as a second gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 356 that is in contact with the semiconductor layer 351. The top surface of the insulating layer 356 is preferably planarized.

[0355] The semiconductor layer 351 is provided over the insulating layer 356. The semiconductor layer 351 preferably includes a metal oxide (also referred to as an oxide semiconductor) film exhibiting semiconductor characteristics. A pair of conductive layers 355 is provided over and in contact with the semiconductor layer 351 and functions as a source electrode and a drain electrode.

[0356] An insulating layer 358 and an insulating layer 350 are provided to cover top surfaces and side surfaces of the pair of conductive layers 355 and side surfaces of the semiconductor layer 351. The insulating layer 358 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 351 and prevents oxygen from being released from the semiconductor layer 351. The insulating layer 358 can be formed using an insulating film similar to the insulating layer 352.

[0357] An opening reaching the semiconductor layer 351 is provided in the insulating layer 358 and the insulating layer 350. An insulating layer 353 in contact with a top surface of the semiconductor layer 351 and a conductive layer 354 are buried in the opening. The conductive layer 354 functions as a first gate electrode, and the insulating layer 353 functions as a first gate insulating layer.

[0358] The top surfaces of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are planarized so that their heights are the same or approximately the same, and an insulating layer 359 is provided to cover them. The insulating layer 359 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the transistor 320. The insulating layer 359 can be formed using an insulating film similar to the insulating layer 352.

[0359] The transistor 320 has a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and the transistor may be driven by supplying the same signal to them. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0360] An insulating layer 564 is provided over the insulating layer 359. The insulating layer 564 functions as an interlayer insulating layer.

[0361] A plug 574 electrically connected to one side of the conductive layer 355 is provided to be embedded in the insulating layer 564, the insulating layer 359, the insulating layer 350, and the insulating layer 358. Here, the plug 574 preferably has a conductive layer 574a covering the side surfaces of the opening of the insulating layer 564 etc. and part of the top surface of the conductive layer 355, and a conductive layer 574b in contact with the top surface of the conductive layer 574a. In this case, the conductive layer 574a is preferably made of a conductive material through which oxygen does not easily diffuse.

[0362] Furthermore, a capacitor 540 is provided on the insulating layer 564. The capacitor 540 includes a conductive layer 541, a conductive layer 545, and an insulating layer 543 located therebetween. The conductive layer 541 functions as one electrode of the capacitor 540, the conductive layer 545 functions as the other electrode of the capacitor 540, and the insulating layer 543 functions as a dielectric of the capacitor 540.

[0363] The conductive layer 541 is embedded in an insulating layer 554 provided over the insulating layer 564. The conductive layer 541 is electrically connected to a conductive layer 355 of the transistor 320 by a plug 574. An insulating layer 543 is provided to cover the conductive layer 541. The conductive layer 545 is provided in a region overlapping with the conductive layer 541 with the insulating layer 543 interposed therebetween.

[0364] An insulating layer 555a is provided to cover the capacitor 540, an insulating layer 555b is provided over the insulating layer 555a, and an insulating layer 555c is provided over the insulating layer 555b.

[0365] An inorganic insulating film can be preferably used for each of the insulating layers 555a, 555b, and 555c. For example, it is preferable to use a silicon oxide film for the insulating layer 555a and the insulating layer 555c, and a silicon nitride film for the insulating layer 555b. This allows the insulating layer 555b to function as an etching protection film. In this embodiment, an example is shown in which part of the insulating layer 555c is etched to form a recess, but the insulating layer 555c does not necessarily have to have a recess.

[0366] The light emitting elements 110R, 110G, and 110B are provided on the insulating layer 555c.

[0367] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B.

[0368] The organic layer 112R of the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G of the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B of the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. The organic layer 112R, the organic layer 112G, and the organic layer 112B can also be called EL layers, and each contains at least a layer (light-emitting layer) that contains a light-emitting organic compound.

[0369] The display device 500A has a separate light-emitting device for each emitted color, so there is little change in chromaticity between light emitted at low and high luminance. Furthermore, because the organic layers 112R, 112G, and 112B are spaced apart from one another, crosstalk between adjacent subpixels can be suppressed even in a high-resolution display panel. This makes it possible to realize a high-resolution, high-quality display panel.

[0370] In the region between adjacent light emitting elements, an insulating layer 125, a resin layer 126, and a layer 128 are provided.

[0371] The pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B of the light-emitting element are electrically connected to the conductive layer 355 of the transistor 320 by a plug 556 embedded in the insulating layers 555a, 555b, and 555c, a conductive layer 541 embedded in the insulating layer 554, and a plug 574. The height of the top surface of the insulating layer 555c and the height of the top surface of the plug 556 are the same or approximately the same. Various conductive materials can be used for the plug.

[0372] A protective layer 121 is provided on the light emitting elements 110R, 110G, and 110B. A substrate 170 is attached to the protective layer 121 with an adhesive layer 171.

[0373] There is no insulating layer covering the upper end of each pixel electrode 111 between two adjacent pixel electrodes 111. This allows the distance between adjacent light-emitting elements to be extremely narrow, resulting in a high-definition or high-resolution display device.

[0374] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0375] Embodiment 6 In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

[0376] The electronic devices of this embodiment include a display panel (display device) in which the transistor of one embodiment of the present invention is used in a display portion. The display device of one embodiment of the present invention can easily achieve high definition and high resolution and can also achieve high display quality. Therefore, the display device of one embodiment of the present invention can be used in the display portion of various electronic devices.

[0377] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0378] In particular, the display panel of one embodiment of the present invention can have high resolution and thus can be suitably used in electronic devices having a relatively small display area. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.

[0379] The display panel of one embodiment of the present invention preferably has extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display panel of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display panel having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. Furthermore, there is no particular limitation on the screen ratio (aspect ratio) of the display panel of one embodiment of the present invention. For example, the display panel can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0380] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0381] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

[0382] 22A to 22D , examples of wearable devices that can be worn on the head are described. These wearable devices have one or both of a function for displaying AR content and a function for displaying VR content. Note that these wearable devices may also have a function for displaying SR or MR content in addition to AR and VR. By having an electronic device have a function for displaying at least one of AR, VR, SR, and MR content, it is possible to enhance the user's sense of immersion.

[0383] The electronic device 700A shown in FIG. 22A and the electronic device 700B shown in FIG. 22B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0384] A display panel of one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying images with extremely high resolution can be provided.

[0385] The electronic device 700A and the electronic device 700B can each project an image displayed on the display panel 751 onto a display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each electronic devices capable of AR display.

[0386] Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image in front of them as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.

[0387] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0388] Furthermore, the electronic device 700A and the electronic device 700B are provided with batteries, which can be charged wirelessly and / or by wire.

[0389] The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 721. The touch sensor module can detect a tap operation or a slide operation by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 721 can expand the range of operations.

[0390] Various touch sensors can be used as the touch sensor module. For example, various types of touch sensors can be used, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, and an optical type. In particular, it is preferable to use a capacitance type or an optical type sensor in the touch sensor module.

[0391] When an optical touch sensor is used, a photoelectric conversion device (also called a photoelectric conversion element) can be used as the light receiving device (also called a light receiving element). The active layer of the photoelectric conversion device can be made of either or both of an inorganic semiconductor and an organic semiconductor.

[0392] The electronic device 800A shown in Figure 22C and the electronic device 800B shown in Figure 22D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0393] A display panel of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high definition can be provided, which allows a user to feel a high sense of immersion.

[0394] The display unit 820 is provided inside the housing 821 at a position that can be viewed through the lens 832. In addition, by displaying different images on the pair of display units 820, it is possible to perform three-dimensional display using parallax.

[0395] The electronic device 800A and the electronic device 800B can be said to be electronic devices for VR. A user wearing the electronic device 800A or the electronic device 800B can view an image displayed on the display unit 820 through the lens 832.

[0396] It is preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the left and right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.

[0397] The mounting unit 823 allows the user to mount the electronic device 800A or the electronic device 800B on the head. Note that, in Fig. 22C and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited to this. The mounting unit 823 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0398] The imaging unit 825 has a function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide-angle.

[0399] Although an example including the imaging unit 825 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 825 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0400] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This allows a user to enjoy video and audio simply by wearing the electronic device 800A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0401] The electronic device 800A and the electronic device 800B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device.

[0402] The electronic device of one embodiment of the present invention may have a function of wireless communication with an earphone 750. The earphone 750 includes a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, the electronic device 700A shown in FIG. 22A has a function of transmitting information to the earphone 750 through the wireless communication function. Furthermore, for example, the electronic device 800A shown in FIG. 22C has a function of transmitting information to the earphone 750 through the wireless communication function.

[0403] The electronic device may also have an earphone unit. Electronic device 700B shown in Fig. 22B has earphone unit 727. For example, earphone unit 727 and the control unit may be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or attachment unit 723.

[0404] 22D includes an earphone unit 827. For example, the earphone unit 827 and the control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting the earphone unit 827 and the control unit 824 may be disposed inside the housing 821 or the attachment unit 823. The earphone unit 827 and the attachment unit 823 may also have magnets. This allows the earphone unit 827 to be fixed to the attachment unit 823 by magnetic force, which is preferable as it makes storage easier.

[0405] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0406] As described above, as electronic devices of one embodiment of the present invention, both glasses-type devices (such as the electronic devices 700A and 700B) and goggle-type devices (such as the electronic devices 800A and 800B) are suitable.

[0407] The electronic device 6500 shown in FIG. 23A is a portable information terminal that can be used as a smartphone.

[0408] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. The display portion 6502 has a touch panel function. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like. The use of the semiconductor device of one embodiment of the present invention for the control device 6509 is preferable because power consumption can be reduced.

[0409] The display panel of one embodiment of the present invention can be applied to the display portion 6502 .

[0410] FIG. 23B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0411] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0412] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0413] In a region outside the display portion 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0414] The display device of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0415] 23C shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0416] 23C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0417] The television device 7100 is configured to include a receiver, a modem, and the like. Ordinary television broadcasts can be received using the receiver. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0418] 23D shows an example of a laptop personal computer. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, and the like. A display portion 7000 is incorporated in the housing 7211. The control device 7216 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 7000, the control device 7216, and the like. The use of the semiconductor device of one embodiment of the present invention for the control device 7216 is preferable because power consumption can be reduced.

[0419] 23E and 23F show an example of digital signage.

[0420] 23E includes a housing 7301, a display portion 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0421] 23F shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0422] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it will attract people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0423] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

[0424] 23E and 23F , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. By operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0425] Furthermore, the digital signage 7300 or the digital signage 7400 can be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0426] 23C to 23F, a display panel of one embodiment of the present invention can be applied to the display portion 7000.

[0427] The electronic device shown in Figures 24A to 24G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including the function of detecting, detecting, or measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 9008, etc.

[0428] The electronic devices shown in Figures 24A to 24G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they may have various other functions. The electronic devices may have multiple display units. Furthermore, the electronic devices may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on the display unit, etc.

[0429] Details of the electronic device shown in Figures 24A to 24G will be described below.

[0430] FIG. 24A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on multiple surfaces. FIG. 24A shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and radio wave intensity. Alternatively, an icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0431] 24B is a perspective view showing the mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is placed in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0432] 24C is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, document browsing and creation, music playback, internet communication, and computer games, for example. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of a housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.

[0433] FIG. 24D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0434] 24E to 24G are perspective views showing a foldable mobile information terminal 9201. Also, FIG. 24E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 24G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 24F is a perspective view of a state in the process of changing from one of FIGS. 24E and 24G to the other. The mobile information terminal 9201 has excellent portability in a folded state, and excellent display visibility due to a seamless, wide display area in an unfolded state. The display portion 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display portion 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0435] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0436] Embodiment 7 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0437] An electronic component or the like to which the semiconductor device of one embodiment of the present invention is applied can be applied to the electronic devices exemplified in Embodiment 6.

[0438] [Electronic Component] FIG. 25A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 25A has semiconductor device 710 inside mold 711. FIG. 25A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0439] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0440] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0441] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0442] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0443] 25B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0444] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0445] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0446] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0447] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0448] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0449] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0450] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0451] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 25B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0452] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0453] 26A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0454] 26B shows a perspective view of an example of a computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 is provided with a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0455] Fig. 26C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on the board 5622. Note that Fig. 26C illustrates components other than electronic components 5626, 5627, and 5628.

[0456] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0457] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0458] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0459] The electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0460] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for learning and inference in artificial intelligence, for example.

[0461] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0462] 11: substrate, 12: insulating layer, 20: opening, 21: semiconductor layer, 21a: region, 21c: region, 21f: semiconductor film, 110B: light-emitting element, 110G: light-emitting element, 110R: light-emitting element, 111: pixel electrode, 111B: pixel electrode, 111G: pixel electrode, 111R: pixel electrode, 112B: organic layer, 112G: organic layer, 112R: organic layer, 113: common electrode, 114: common layer, 121: protective layer, 125: insulating layer, 126: resin layer, 128: layer, 170: substrate, 171: adhesive layer, 200: transistor, 200a: transistor, 200b: transistor, 201: insulating Edge layer, 202: insulating layer, 205: conductive layer, 210: substrate, 211: insulating layer, 220: opening, 230: semiconductor layer, 230f: semiconductor film, 230n: region, 240a: conductive layer, 240b: conductive layer, 241a: insulating layer, 241b: insulating layer, 242: conductive layer, 242a: conductive layer, 242b: conductive layer, 242f: conductive film, 245: conductive layer, 246: conductive layer, 250: insulating layer, 255: insulating layer, 260: conductive layer, 260a: conductive layer, 260b: conductive layer, 271a: insulating layer, 271b: insulating layer, 275: insulating layer, 280: insulating layer, 281: insulating layer, 282: insulating layer, 28 3: insulating layer, 285: insulating layer, 290o: opening, 290s: opening, 301: substrate, 310: transistor, 311: conductive layer, 312: low resistance region, 313: insulating layer, 314: insulating layer, 315: element isolation layer, 316: wiring layer, 320: transistor, 350: insulating layer, 351: semiconductor layer, 352: insulating layer, 353: insulating layer, 354: conductive layer, 355: conductive layer, 356: insulating layer, 357: conductive layer, 358: insulating layer, 359: insulating layer, 420: layer, 422: peripheral circuit, 430[1]: element layer, 430[2]: element layer, 430[5]: element layer, 430[m]: element Child layer, 430[m]m: element layer, 430: element layer, 432[1,1]: memory cell, 432[i,j]: memory cell, 432[m,n]: memory cell, 432: memory cell, 437: transistor, 438: capacitance element, 440: drive circuit, 442: row decoder, 443: row driver, 444: column decoder, 445: column driver, 446[1]: sense amplifier, 446[2]: sense amplifier, 446: sense amplifier, 447: input circuit, 448: output circuit, 470: layer, 471: PSW, 472: PSW, 473: control circuit, 474: voltage generation circuit,480: memory device, 482: switch circuit, 482_1: transistor, 482_2: transistor, 483: precharge circuit, 483_1: transistor, 483_3: transistor, 484: precharge circuit, 484_1: transistor, 484_3: transistor, 485: amplifier circuit, 485_1: transistor, 485_2: transistor, 485_3: transistor, 485_4: transistor, 500A: display device, 540: capacitor, 541: conductive layer, 543: insulating layer, 545: conductive layer, 554: insulating layer, 555a: insulating layer, 555b: insulating Edge layer, 555c: insulating layer, 556: plug, 564: insulating layer, 574: plug, 574a: conductive layer, 574b: conductive layer, 580: display module, 581: display section, 582: circuit section, 583: pixel circuit section, 583a: pixel circuit, 584: pixel section, 584a: pixel, 585: terminal section, 586: wiring section, 590: FPC, 591: substrate, 592: substrate, 700: electronic component, 700A: electronic device, 700B: electronic device, 702: printed circuit board, 704: mounting board, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire , 715: drive circuit layer, 716: memory layer, 721: housing, 723: wearing portion, 727: earphone portion, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 750: earphone, 751: display panel, 753: optical member, 756: display area, 757: frame, 758: nose pad, 800A: electronic device, 800B: electronic device, 820: display portion, 821: housing, 822: communication portion, 823: wearing portion, 824: control portion, 825: imaging portion, 827: earphone portion, 832: lens, 5600: mainframe computer, 5610 : Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Electronic component, 5627: Electronic component, 5628: Electronic component, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6500: Electronic device, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6509: Control device, 6510: Protective member, 6511: Display panel, 6512: Optical member,6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7000: Display unit, 7100: Television device, 7101: Housing, 7103: Stand, 7111: Remote control device, 7200: Notebook personal computer, 7211: Housing, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7216: Control device, 7300: Digital signage, 7301: Housing, 7303: Speaker, 7311: Information Information terminal, 7400: digital signage, 7401: pillar, 7411: information terminal, 9000: housing, 9001: display unit, 9002: camera, 9003: speaker, 9005: operation keys, 9006: connection terminal, 9007: sensor, 9008: microphone, 9050: icon, 9051: information, 9052: information, 9053: information, 9054: information, 9055: hinge, 9101: mobile information terminal, 9102: mobile information terminal, 9103: tablet terminal, 9200: mobile information terminal, 9201: mobile information terminal,

Claims

a substrate, a first insulating layer, and a transistor; the first insulating layer is provided on the substrate and has an opening that reaches the substrate; the transistor has a semiconductor layer; the semiconductor layer has a portion in contact with the upper surface of the first insulating layer and a portion in contact with the upper surface of the substrate in the opening, the substrate has a single crystal structure; the first insulating layer has an amorphous structure, The semiconductor layer includes a metal oxide and has a single crystal structure. Semiconductor device. 　 a substrate, a first insulating layer, a second insulating layer, and a transistor; the first insulating layer is provided on the substrate and has an opening that reaches the substrate; the transistor has a semiconductor layer; the semiconductor layer has a portion in contact with an upper surface of the first insulating layer, the second insulating layer has a portion that covers a part of the transistor and a portion that contacts the upper surface of the substrate in the opening, the substrate has a single crystal structure; the first insulating layer has an amorphous structure, The semiconductor layer includes a metal oxide and has a single crystal structure. Semiconductor device. 　 a substrate, a first insulating layer, and a transistor; the first insulating layer is provided on the substrate and has an opening that reaches the substrate; the transistor has a semiconductor layer and a gate insulating layer; the semiconductor layer has a portion in contact with an upper surface of the first insulating layer, the gate insulating layer has a portion overlapping the semiconductor layer and a portion in contact with the upper surface of the substrate in the opening, the substrate has a single crystal structure; the first insulating layer has an amorphous structure, The semiconductor layer includes a metal oxide and has a single crystal structure. Semiconductor device. 　 In any one of claims 1 to 3, the substrate has a cubic crystal structure; The semiconductor layer has a cubic crystal structure. Semiconductor device. 　 In any one of claims 1 to 3, the substrate comprises an oxide comprising zirconium and yttrium; the semiconductor layer includes indium oxide; the first insulating layer includes silicon oxide; Semiconductor device. 　 In any one of claims 1 to 3, the substrate has a hexagonal crystal structure; The semiconductor layer has a cubic crystal structure. Semiconductor device. 　 In any one of claims 1 to 3, the substrate comprises aluminum oxide; Semiconductor device. 　 In claim 7, the semiconductor layer includes indium oxide; the first insulating layer includes silicon oxide; Semiconductor device. 　 forming a first insulating layer on a substrate having a single crystal structure; forming an opening in the first insulating layer that reaches an upper surface of the substrate; forming a semiconductor film that is in contact with an upper surface of the first insulating layer and an upper surface of the substrate in the opening, has a single crystal region, and contains a metal oxide; removing a portion of the semiconductor film to form a semiconductor layer having a portion in contact with the upper surface of the first insulating layer and a portion in contact with the upper surface of the substrate; A method for manufacturing a semiconductor device. forming a first insulating layer on a substrate having a single crystal structure; forming an opening on the first insulating layer that reaches an upper surface of the substrate; forming a semiconductor film that is in contact with an upper surface of the first insulating layer and an upper surface of the substrate in the opening, has a single crystal region, and contains a metal oxide; removing a portion of the semiconductor film to form a semiconductor layer in contact with an upper surface of the first insulating layer and exposing an upper surface of the substrate in the opening; forming a second insulating layer in contact with the upper surface of the substrate in the opening; A method for manufacturing a semiconductor device. 　 In claim 9 or claim 10, The semiconductor layer is formed to contain indium oxide, The first insulating layer is formed to contain silicon oxide. A method for manufacturing a semiconductor device. 　 In claim 9 or claim 10, A substrate containing an oxide containing zirconium and yttrium is used as the substrate. A method for manufacturing a semiconductor device. 　 In claim 9 or claim 10, A substrate containing aluminum oxide is used as the substrate. A method for manufacturing a semiconductor device.

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