Electronic device

Abstract

An electronic device (10) comprises: a chip (20) having a characteristic impedance Z1; a chip (30) having a second characteristic impedance smaller than the characteristic impedance; and a substrate (40) which has the chips (20, 30) mounted thereon and which has formed therein a transmission path (49) which allows transmission therethrough of an electrical signal from one of the chips (20, 30) to the other. The transmission path (49) includes: a dielectric layer (41) that is the body of the substrate (40); a conductor line (42) that is formed on the dielectric layer (41), is connected to the chips (20, 30), and allows propagation therethrough of the electrical signal; and a ground plane (43) that is formed on the dielectric layer (41) and is a conductor connected to the ground. A characteristic impedance Zt of the transmission path (49) is smaller than the characteristic impedance Z1 and larger than a characteristic impedance Z2.

Description

Electronic Devices

[0001] The present invention relates to electronic devices.

[0002] An electronic device is known that has a plurality of chips and a substrate on which the plurality of chips are mounted, and the substrate is provided with a transmission path for electrical signals exchanged between the chips. Also, Non-Patent Document 1 discloses a technique for performing impedance matching for a plurality of devices with different characteristic impedances.

[0003] David M Pozar, Translated by Tadao Nagatsuma and two others, “Microwave Engineering, 4th Edition”, Morikita Publishing, January 18, 2021, pp.289-336

[0004] In the electronic device described above, the characteristic impedance of each of the multiple chips mounted on the substrate is set to a common value (e.g., 50 Ω), and the characteristic impedance of the transmission path provided on the substrate is also set to this value. However, during research and development, the inventors of the present application discovered that, due to factors such as chip miniaturization, there are cases where the characteristic impedance values ​​of some chips must be set to different values. If the characteristic impedances are not consistent, there will be significant reflection of electrical signals between chips.

[0005] As mentioned above, Non-Patent Document 1 discloses an impedance matching technique, but in conventional electronic devices, the characteristic impedance is a common value as described above. For this reason, the impedance matching technique of Non-Patent Document 1 cannot be applied to conventional electronic devices. Furthermore, the technique described in Non-Patent Document 1 is not intended for impedance matching of transmission paths between chips mounted on a substrate. From this perspective, too, the impedance matching technique of Non-Patent Document 1 cannot be applied to conventional electronic devices.

[0006] An object of the present invention is to reduce reflection of an electrical signal transmitted between two chips having different characteristic impedances.

[0007] An electronic device according to the present invention comprises: a first chip having a first characteristic impedance; a second chip having a second characteristic impedance smaller than the first characteristic impedance; and a substrate on which the first chip and the second chip are mounted, the substrate having a transmission line formed thereon for transmitting an electrical signal transmitted from one of the first chip and the second chip to the other, the transmission line including: a dielectric layer which is the main body of the substrate; a conductor line formed in the dielectric layer, the conductor line having a first end connected to the first chip and a second end connected to the second chip, the conductor line through which the electrical signal propagates; and a ground plane which is formed in the dielectric layer and is a conductor connected to ground, the characteristic impedance of the transmission line being smaller than the first characteristic impedance and larger than the second characteristic impedance.

[0008] According to the above configuration, reflection of an electrical signal (especially an electrical signal in a high frequency band) transmitted between two chips having different characteristic impedances is reduced.

[0009] FIG. 1 is a front view of a main part of an electronic device according to an embodiment of the present invention, with a portion thereof shown in cross section. FIG. 2 is a plan view of the main part of the electronic device of FIG. 1. FIG. 3 is a graph showing frequency characteristics in the embodiment and frequency characteristics in a comparative example. FIG. 4 is a plan view of the main part of an electronic device according to a modified example. FIG. 5 is a plan view of the main part of an electronic device according to a modified example. FIG. 6 is a plan view of the main part of an electronic device according to a modified example. FIG. 7 is a plan view of the main part of an electronic device according to a modified example. FIG. 8 is a plan view of the main part of an electronic device according to a modified example. FIG. 9 is a plan view of the main part of an electronic device according to a modified example.

[0010] Hereinafter, electronic devices according to embodiments and modifications of the present invention will be described with reference to the drawings. In the following description, the thickness direction of the substrate is referred to as the up-down direction, and two directions that are perpendicular to the up-down direction and perpendicular to each other are referred to as the left-right direction and the front-rear direction. These directions are not intended to indicate the installation direction of the electronic device. For example, the up-down direction does not have to coincide with the top-to-bottom direction. Furthermore, corresponding elements between the embodiments and modifications are denoted by the same reference numerals, and duplicate explanations will be omitted.

[0011] 1 and 2, an electronic device 10 according to this embodiment includes a chip 20, a chip 30, and a substrate 40. In the electronic device 10 of this embodiment, the chips 20 and 30 are enclosed in the same package together with the substrate 40, and a package configuration known as HB-CDM is used, which shortens the distance between the chips and reduces reflection and loss of electrical signals transmitted between them. This enables ultra-high-speed, wide-band electrical signal transmission between the chips.

[0012] Chips 20 and 30 are, for example, chipped electronic components that output electrical signals after predetermined processing or operate based on input electrical signals. Examples of such chipped electronic components include IC chips that include various circuits such as driver circuits, amplifier circuits, and arithmetic circuits, and chipped optical modulators that include optical circuits but operate based on electrical signals. Chip 30 can be an InP Mach-Zehnder optical modulator. Chip 20 can be a driver circuit that drives chip 30 by supplying an electrical signal as a drive signal to chip 30.

[0013] The chips 20 and 30 are mounted on the substrate 40. A transmission path 49 is formed on the substrate 40 to transmit an electrical signal transmitted from one of the chips 20 and 30 to the other. The transmission path 49 may also transmit an electrical signal transmitted from the other to one of the chips.

[0014] The transmission path 49 comprises a plate-shaped dielectric layer 41 which forms the main body of the substrate 40, a conductor line 42 formed on the upper surface, which is the first main surface, of the dielectric layer 41, and a ground plane 43 formed on the lower surface, which is the second main surface, of the dielectric layer 41.

[0015] The dielectric layer 41 is an insulating substrate made of any dielectric material such as glass, ceramic, resin, quartz, etc. The conductor line 42 and the ground plane 43 may be made of any conductor, such as a metal such as copper, or an appropriate conductive material such as a conductive resin.

[0016] The conductor line 42 extends linearly in the left-right direction. The left end of the conductor line 42 is electrically connected to the terminal 21 of the chip 20 via a connecting conductor 91. The right end of the conductor line 42 is electrically connected to the terminal 31 of the chip 30 via a connecting conductor 92. The connecting conductors 91 and 92 may be made of any conductor, but are preferably made of a material with low parasitic capacitance and inductance, such as a gold stud bump, a solder bump, or a Cu pillar. The electrical signal transmitted by the transmission path 49 propagates through the conductor line 42. For example, if the electrical signal is a drive signal for driving the chip 20, the drive signal is input from the terminal 31 of the chip 30 via the connecting conductor 92 to the right end of the conductor line 42. The input drive signal propagates through the conductor line 42 and is output from the left end of the conductor line 42 to the terminal 21 via the connecting conductor 91.

[0017] The ground plane 43 is formed solidly on the entire or part of the lower surface of the dielectric layer 41. The ground plane 43 is connected to the ground, and a return current flows through the ground plane 43 in response to the electrical signal propagating through the conductor line 42. The ground includes the earth. In other words, the ground plane 43 may be earthed.

[0018] The transmission line 49 is configured as a microstrip line by the above elements 41 to 43.

[0019] The length L of the transmission path 49 satisfies the relationship L≧c / (4*f), where f is the upper limit frequency of the frequency band of the electrical signal transmitted from the chip 20 or 30, and c is the speed of light. This reduces loss and reflection of the electrical signal propagating through the transmission path 49.

[0020] The length L of the transmission line 49 is basically the length of the conductor line 42. However, if the conductor line 42 is longer than the distance between the connecting conductors 91 and 92 (i.e., the distance between the terminals 21 and 32), the length L of the transmission line 49 may be the distance from the first connection point of the conductor line 42, where the connecting conductor 91 is connected, to the second connection point of the conductor line 42, where the connecting conductor 92 is connected (the length including the lengths of the respective connection points). In such a case, the region from the first connection point to the second connection point of the conductor line 42 may be considered to be the conductor line 42 that constitutes the transmission line 49. In this case, the first connection point and the second connection point are both ends of the conductor line 42 that constitutes the transmission line 49.

[0021] The characteristic impedance Z1 of the chip 20 is 50 Ω. The characteristic impedance Z2 of the chip 30 is 35 Ω. The transmission line 49 is configured so that its characteristic impedance Zt satisfies the relationship Z1 > Zt > Z2. The characteristic impedance Zt is adjusted by the dielectric constant of the dielectric layer 41 (i.e., the type of dielectric material), the thickness of the dielectric layer 41, the width of the conductor line 42, and the like. Note that the transmission line 49 may be configured so that its characteristic impedance Zt satisfies the equation Zt = √(Z1 * Z2), like a quarter-wave transformer used for impedance matching. The characteristic impedance can be measured by any method, such as TDR (Time Domain Reflectometry).

[0022] Conventionally, the chips 20 and 30 and the transmission line 49 have been designed to have a characteristic impedance of 50 Ω. However, if the chip 30 is an InP Mach-Zehnder optical modulator or the like, it becomes difficult to design the chip 30 with a characteristic impedance of 50 Ω as the chip 30 is miniaturized. For example, the characteristic impedance of the chip 30 becomes approximately 35 Ω, which is lower than 50 Ω. This results in a situation where the characteristic impedance of the chip 30 is lower than the characteristic impedance of the chip 20, as in the present embodiment. Therefore, in the present embodiment, as described above, the characteristic impedance Zt of the transmission line 49 is set to be smaller than the characteristic impedance Z1 and larger than the characteristic impedance Z2. As a result, compared to when the characteristic impedances of the chip 20 and the transmission line 49 are the same, 50 Ω, and the characteristic impedance of the chip 30 is 35 Ω, the difference in characteristic impedance is divided into the difference between the characteristic impedances of the chip 20 and the transmission line 49 and the difference between the characteristic impedances of the chip 30 and the transmission line 49. This suppresses reflection of electrical signals (deterioration of reflection characteristics) caused by impedance mismatch between the chips 20 and 30. As a result, an electronic device 10 having a chip connection structure that supports a wide frequency band of electrical signals is realized.

[0023] FIG. 3 shows the simulation results (frequency characteristics of propagation loss of electrical signals due to reflection) of the structure of this embodiment. In structure A according to the comparative example, the characteristic impedances were Z1 = Zt = 50Ω and Z2 = 35Ω. In structure B according to this embodiment, Z1 = 50Ω, Z2 = 35Ω, and Zt = √(Z1 * Z2) = √(50 * 35)Ω. As shown in FIG. 3, the loss due to reflection in structure A (comparative example) is greater than -10 dB (more reflection) in the range of 110 GHz or higher, while the reflection characteristics of structure B (this embodiment) are maintained at approximately -10 dB or less (less reflection) up to 150 GHz. Therefore, the frequency band with low reflection characteristics is wider in structure B.

[0024] As a countermeasure against the mismatch in characteristic impedance, it is possible to shorten the transmission path 49 to shorten the distance between the chips 20 and 30, that is, to shorten the transmission path 49. However, since the chips 20 and 30 are also heating elements that generate heat when current is applied, a certain distance must be ensured. In this embodiment, even if the distance is ensured, reflection of the electrical signal (deterioration of the reflection characteristics) due to the mismatch in characteristic impedance is suppressed.

[0025] (Modifications) Modifications of the above embodiment will be described below. In the following description, elements that are the same as elements of the above embodiment and elements that have similar functions will be assigned the same reference numerals, and redundant description will be omitted as appropriate.

[0026] (Variation 1) As shown in Figure 4, an electronic device 110 according to Variation 1 includes a conductor line 142 instead of the conductor line 42. The width (length in the front-to-rear direction) of the conductor line 142 increases in a stepped manner from the left end to the right end. In other words, the conductor line 142 has regions 142A to 142C with different widths. The widths of the regions 142A to 142C increase as they move to the right. A transmission line 149 including such a conductor line 142 has a stepped impedance structure with a plurality of characteristic impedances.

[0027] If the characteristic impedance of portion 149A of transmission line 149 including region 142A is Zt1, the characteristic impedance of portion 149B including region 142B is Zt2, and the characteristic impedance of portion 149C including region 142C is Zt3, the magnitude relationship of each characteristic impedance is Z1 > Zt1 > Zt2 > Zt3 > Z2.

[0028] In this way, the transmission line 149 satisfying Z1 > Zt > Z2 includes N portions (where N is an integer greater than or equal to 2) lined up in a row from the left end to the right end, and it is preferable that the characteristic impedance of the i+1th portion (where i is an integer ranging from 2 to N) counting from the left end of these N portions is smaller than the characteristic impedance of the i-th portion counting from the left end. As a result, the characteristic impedance of each portion decreases as it moves further to the right. Here, the characteristic impedance of each portion is adjusted by the width of the conductor line, but the characteristic impedance may also be adjusted by varying the thickness or material of the dielectric layer 41 at each portion.

[0029] According to this modification, even if the difference between the characteristic impedances of the chips 20 and 30 is large, it is possible to achieve wide-band impedance matching, reduce reflection and loss, and obtain wide-band frequency characteristics.

[0030] 5, an electronic device 210 according to Modification 2 includes a conductor line 242 instead of the conductor line 42. The conductor line 242 includes a tapered portion 242A that gradually widens from the left end to the right end. Note that the entire conductor line 242 may be a tapered portion.

[0031] The transmission line 249 including the conductor line 242 can include a portion in which the characteristic impedance continuously changes toward the right, thereby further suppressing reflection and achieving good frequency characteristics over a wide bandwidth with respect to reflection. The tapered portion 242A may have an exponential taper in which the characteristic impedance changes exponentially. Alternatively, the tapered portion 242A may have a triangular taper or a Kloppenstein taper.

[0032] (Variation 3) As shown in FIG. 6 , an electronic device 310 according to Variation 3 includes a substrate 340 instead of the substrate 40. The substrate 340 has a structure in which a ground plane 344 including a pair of ground planes 344A and 344B is added to the substrate 40. The ground plane 344 is formed on the upper surface of the dielectric layer 41. Each of the ground planes 344A and 344B is formed in a rectangular shape. The pair of ground planes 344A and 344B are disposed on both sides of the conductor line 42 in the front-to-rear direction with a gap therebetween, thereby sandwiching the conductor line 42 in the front-to-rear direction. The ground planes 344 (each of the ground planes 344A and 344B) are also formed of the same material as the ground plane 43 and are connected to the ground.

[0033] Transmission line 349 formed on substrate 340 also includes ground plane 344. Therefore, transmission line 349 is configured as a coplanar line (here, a grounded coplanar line) by dielectric layer 41, conductor line 42, ground plane 43 ( FIG. 1 ), and ground plane 344. A coplanar line is also called a coplanar waveguide.

[0034] This modification allows a return current to flow to the ground plane 344 close to the conductor line 42, thereby reducing transmission loss of the electrical signal.

[0035] The ground plane 43 (FIG. 1) may be omitted. Furthermore, as shown in FIG. 7, the ground plane 344 may be formed in a shape that surrounds the conductor line 42 360 degrees in a plan view. Transmission lines with these configurations are also coplanar lines. This also applies to the coplanar lines in the other modified examples.

[0036] 8 , an electronic device 410 according to Modification 4 includes a conductor line 442 instead of the conductor line 42. In this modification, the electrical signal transmitted from one of the chips 20 and 30 to the other is a differential electrical signal. Therefore, the chip 20 includes a pair of terminals 421A and 421B through which the differential electrical signal is input and output. The chip 30 includes a pair of terminals 431A and 431B through which the differential electrical signal is input and output.

[0037] The conductor line 442 includes a pair of differential conductor lines 442A and 442B extending linearly in the left-right direction. The pair of differential conductor lines 442A and 442B each transmit a pair of differential electrical signals. The left end of the differential conductor line 442A is electrically connected to a terminal 421A of the chip 20 via a connecting conductor 491A. The right end of the differential conductor line 442A is electrically connected to a terminal 431A of the chip 30 via a connecting conductor 492A. The left end of the differential conductor line 442B is electrically connected to a terminal 421B of the chip 20 via a connecting conductor 491B. The right end of the differential conductor line 442B is electrically connected to a terminal 431B of the chip 30 via a connecting conductor 492B. Each connecting conductor is similar to the connecting conductors in the above embodiment. The transmission line 449, which includes the conductor line 442 instead of the conductor line 42, is a microstrip line (more specifically, a differential microstrip line).

[0038] In this fourth modification, the characteristic impedance Zt of the transmission path 449 including the conductor line 442 satisfies the relationship Z1 (characteristic impedance of the chip 20) > Zt > Z2 (characteristic impedance of the chip 20). The other explanations are the same as those of the above embodiment. The differential electrical signal improves noise resistance.

[0039] 9 , an electronic device 510 according to Modification 5 includes a substrate 540 instead of the substrate 40 of Modification 4. The substrate 540 has a structure in which a ground plane 344 including the pair of ground planes 344A and 344B of Modification 3 is added to the substrate 40 of Modification 4. As a result, the substrate 540 forms a transmission line 549 as a coplanar line (more specifically, a differential coplanar line). A return current can be passed through the ground plane 344 close to the conductor line 42, thereby reducing transmission loss of the electrical signal.

[0040] (Scope of the present invention) The present invention is not limited to the above-described embodiments and modifications. For example, the present invention includes various modifications to the above-described embodiments and modifications that can be understood by a person skilled in the art within the scope of the technical concept of the present invention. The configurations listed in the above-described embodiments and modifications can be combined as appropriate within a range that does not contradict. In addition, any of the above-described configurations can be deleted.

[0041] (Supplementary Notes) Configurations that are examples of the above-described embodiments and modified examples are shown below. Only any partial configuration of the above-described embodiments and modified examples may be applied to each supplementary note. Also, parts of each supplementary note may be combined. (Supplementary Note 1) An electronic device comprising: a first chip having a first characteristic impedance; a second chip having a second characteristic impedance smaller than the first characteristic impedance; and a substrate on which the first chip and the second chip are mounted, the substrate having a transmission path formed thereon for transmitting an electrical signal transmitted from one of the first chip and the second chip to the other, the transmission path including: a dielectric layer that is a main body of the substrate; a conductor line formed on the dielectric layer, the conductor line having a first end connected to the first chip and a second end connected to the second chip, the conductor line through which the electrical signal propagates; and a ground plane that is formed on the dielectric layer and connected to ground, the characteristic impedance of the transmission path being smaller than the first characteristic impedance and larger than the second characteristic impedance. (Supplementary Note 2) The electronic device according to Supplementary Note 1, wherein the length L of the transmission line satisfies the relationship L≧c / (4*f), where f is an upper limit frequency of the frequency band of the electrical signal and c is the speed of light. (Supplementary Note 3) The electronic device according to Supplementary Note 1 or 2, wherein the transmission line includes N (N is an integer of 2 or greater) portions lined up in a row from the first end to the second end, and wherein the characteristic impedance of an i+1th portion (i is an integer ranging from 2 to N) of the N portions, counting from the first end, is smaller than the characteristic impedance of an i-th portion, counting from the first end. (Supplementary Note 4) The electronic device according to Supplementary Note 3, wherein the width of the conductor line constituting the i+1th portion is wider than the width of the conductor line constituting the i-th portion. (Supplementary Note 5) The electronic device according to Supplementary Note 1 or 2, wherein the conductor line includes a tapered portion that gradually becomes wider from the first end to the second end.(Supplementary Note 6) The electronic device according to any one of Supplements 1 to 5, wherein the conductor line is formed on a first main surface of the dielectric layer, the ground plane is formed on a second main surface of the dielectric layer opposite to the first main surface, and the transmission line is configured as a microstrip line by the dielectric layer, the conductor line, and the ground plane. (Supplementary Note 7) The electronic device according to any one of Supplements 1 to 5, wherein the conductor line is formed on the main surface of the dielectric layer, the ground plane is formed on the main surface of the dielectric layer, and the transmission line is configured as a coplanar line by the dielectric layer, the conductor line, and the ground plane. (Supplementary Note 8) The electronic device according to any one of Supplements 1 to 7, wherein the electrical signal is a differential electrical signal, and the conductor line includes a pair of differential conductor lines that transmit the differential electrical signal.

[0042] 10...electronic device, 20...chip, 21...terminal, 30...chip, 31...terminal, 40...substrate, 41...dielectric layer, 42...conductor line, 43...ground plane, 49...transmission line, 91, 92...connecting conductor, 110...electronic device, 142...conductor line, 142A to 142C...region, 149...transmission line, 149A to 149C...part, 210...electronic device, 242...conductor line, 242A...tapered portion, 249...transmission line, 310...electronic device 340...substrate, 344...ground plane, 344A, 344B...ground plane, 349...transmission line, 410...electronic device, 421A, 421B...terminal, 431A, 431B...terminal, 442...conductor line, 442A, 442B...differential conductor line, 449...transmission line, 491A, 491B, 492A, 492B...connecting conductor, 510...electronic device, 540...substrate, 549...transmission line, A...structure of comparative example, B...structure of embodiment.

Claims

1. An electronic device comprising: a first chip having a first characteristic impedance; a second chip having a second characteristic impedance smaller than the first characteristic impedance; and a substrate on which the first chip and the second chip are mounted, the substrate having a transmission line formed thereon for transmitting an electrical signal transmitted from one of the first chip and the second chip to the other, the transmission line including: a dielectric layer which is the main body of the substrate; a conductor line formed on the dielectric layer, the conductor line having a first end connected to the first chip and a second end connected to the second chip, the conductor line through which the electrical signal propagates; and a ground plane which is formed on the dielectric layer and is a conductor connected to ground, wherein the characteristic impedance of the transmission line is smaller than the first characteristic impedance and greater than the second characteristic impedance.

2. The electronic device according to claim 1, wherein the length L of the transmission path satisfies the relationship L≧c / (4*f), where f is the upper limit frequency of the frequency band of the electrical signal and c is the speed of light.

3. The electronic device according to claim 1, wherein the transmission line includes N parts (where N is an integer of 2 or more) lined up in a row from the first end to the second end, and the characteristic impedance of the i+1th part (where i is an integer ranging from 2 to N) counting from the first end among the N parts is smaller than the characteristic impedance of the i-th part counting from the first end.

4. The electronic device according to claim 3, wherein the width of the conductor line constituting the (i+1)th portion is wider than the width of the conductor line constituting the i-th portion.

5. The electronic device according to claim 1, wherein the conductor line includes a tapered portion that gradually widens from the first end toward the second end.

6. The electronic device according to claim 1, wherein the conductor line is formed on a first main surface of the dielectric layer, the ground plane is formed on a second main surface of the dielectric layer opposite the first main surface, and the transmission line is configured as a microstrip line by the dielectric layer, the conductor line, and the ground plane.

7. The electronic device according to claim 1, wherein the conductor line is formed on a principal surface of the dielectric layer, the ground plane is formed on the principal surface of the dielectric layer, and the transmission line is configured as a coplanar line by the dielectric layer, the conductor line, and the ground plane.

8. The electronic device according to claim 1, wherein the electrical signal is a differential electrical signal, and the conductor line includes a pair of differential conductor lines that transmit the differential electrical signal.

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