Semiconductor device and method for fabricating semiconductor device

Abstract

This semiconductor device comprises a semiconductor substrate, a first semiconductor layer of a first conductivity type, a plurality of trenches, a plurality of protrusions, a first sub-trench, and a second sub-trench. A second semiconductor layer of a second conductivity type is provided inside the plurality of trenches, the first sub-trench, and the second sub-trench. A plurality of first pillars of the first conductivity type and a plurality of second pillars of the second conductivity type, such pillars constituted by the plurality of protrusions, form a super junction structure.

Description

Semiconductor device and method for manufacturing the same

[0001] This disclosure relates to a semiconductor device having a superjunction structure and a method for manufacturing the semiconductor device. This application claims priority to Japanese Patent Application No. 2024-145719, filed on August 27, 2024, the contents of which are incorporated herein by reference.

[0002] Power devices are key components in power conversion circuits such as inverters, and there is a growing demand for higher voltage resistance and lower loss in order to expand the range of applications and reduce power consumption. Power device semiconductors for such applications employ vertical power devices, such as IGBTs, MOSFETs, and diodes, with the main current path running in the thickness direction of the semiconductor substrate.

[0003] A semiconductor layer called a drift layer is used in the breakdown voltage maintenance structure of vertical power devices. Increasing the thickness of the drift layer and decreasing the impurity concentration improves the breakdown voltage, but there is a trade-off limit in that resistance also increases. The trade-off limit is determined by the dielectric breakdown strength of the semiconductor material of the drift layer, so the trade-off limit can be improved by using wide-gap semiconductors (such as SiC and GaN) that have a greater dielectric breakdown strength than silicon.

[0004] On the other hand, in addition to changing the semiconductor material, it is also possible to improve the aforementioned trade-off limit by changing the device structure. One solution is to replace the drift layer with a simple single semiconductor layer (bulk drift layer) and adopt a superjunction structure. Commonly known methods for manufacturing a superjunction structure are the multi-epitaxial method and the trench backfilling method.

[0005] The multi-epi method involves repeated crystal growth of a relatively thin semiconductor layer and selective ion implantation, which results in poor manufacturing throughput and increases costs.In contrast, the trench backfill method forms a superjunction structure by forming a deep trench in a relatively thick layer and backfilling the trench.

[0006] For example, Patent Document 1 describes a method for manufacturing a superjunction structure of a semiconductor device using a substrate made of SiC single crystal by a trench backfilling method. This semiconductor device has a superjunction structure composed of a p-type column region made of a semiconductor layer buried inside a trench of a predetermined length with closed ends, and an n-type column region made of a part of the n-type substrate between adjacent trenches.

[0007] Furthermore, for example, Patent Document 2 describes a method for manufacturing a SiC semiconductor device with a superjunction structure using a buried epitaxial method. In Patent Document 2, a plurality of convex pillars of SiC semiconductor are formed in a striped shape in a planar view of a semiconductor wafer. In this case, a scribe area that divides a chip region is formed as a recess, and the plurality of convex pillars are provided isolated within the chip region. The semiconductor wafer with the plurality of pillars formed therein is backfilled with a SiC semiconductor layer of the opposite conductivity type to form a superjunction structure.

[0008] International Publication No. 2019 / 160086 International Publication No. 2021 / 260851

[0009] SY Ji, et al., “Fast-filling of 4H-SiC trenches at 10 μm / h by enhancing partial pressures of source species in chemical vapor deposition processes”, J. Cryst. Growth, 546, 125809 (2020).

[0010] The technology described in Patent Document 1 is capable of filling the central portion of the stripe-shaped trench with SiC crystals well, but it has been reported that voids (vacancies) occur at both ends of the trench, creating invalid regions. Furthermore, in a semiconductor device such as that described in Patent Document 2, which aims to make it difficult for voids to form at the trench ends, unfilled portions (concave portions) occur in the scribe area of ​​the chip, preventing the flatness of the entire wafer from being maintained. This can hinder lithography and other processes in the wafer process.

[0011] The present invention has been made in consideration of the above-mentioned circumstances, and aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress the generation of voids inside the trenches that constitute a superjunction structure and maintain surface flatness.

[0012] In order to solve the above problems, the semiconductor device and the method for manufacturing the semiconductor device according to one embodiment of the present invention propose the following means. a plurality of protruding portions that are part of the first semiconductor layer and are formed by remaining portions of the plurality of trenches; a first sub-trench that is formed within the first semiconductor layer, extends in a second direction perpendicular to the first direction, and is connected to one end of the plurality of trenches, the first sub-trench having the first depth; and a second sub-trench that is formed within the first semiconductor layer, extends in the second direction, and is connected to the other end of the plurality of trenches, the second sub-trench having the first depth. A second semiconductor layer of a second conductivity type is provided within the plurality of trenches, the first sub-trench, and the second sub-trench. A superjunction structure is formed within the plurality of trenches, the first sub-trench, and the second sub-trench.

[0013] (2) A method for manufacturing a semiconductor device according to a second aspect of the present disclosure is a method for manufacturing a semiconductor device having a superjunction structure in which a plurality of first pillars of a first conductivity type and a plurality of second pillars of a second conductivity type are alternately provided, the method including: a first step of forming a first semiconductor layer of a first conductivity type on a first main surface of a semiconductor wafer; a second step of setting a plurality of chip regions repeatedly arranged in a first direction and a second direction on the first main surface of the semiconductor wafer, and dicing lines that are boundaries between the adjacent chip regions; and a second step of setting a plurality of first pillars extending in the first direction at a first depth within each of the chip regions. and a third step of forming, in the first semiconductor layer, a plurality of trenches for forming the second pillars, first sub-trenches extending in the second direction at the first depth and connected to one ends of the plurality of trenches, and second sub-trenches extending in the second direction at the first depth and connected to the other ends of the plurality of trenches; a fourth step of filling the plurality of trenches, the first sub-trenches, and the second sub-trenches with a second semiconductor layer of the second conductivity type that is thicker than the first depth; and a fifth step of planarizing the surface of the second semiconductor layer to form the super junction structure.

[0014] According to the present disclosure, it is possible to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress the generation of voids inside the trenches that form the superjunction structure and maintain surface flatness.

[0015] 1 is a schematic configuration diagram showing a semiconductor device according to an embodiment of the present disclosure; FIG. 2 is a top view of the semiconductor device of FIG. 1 when viewed from above; FIG. 3 is a cross-sectional view taken along lines A1-A1' and A2-A2' in FIG. 2; FIG. 4 is a cross-sectional view taken along line BB' in FIG. 2; FIG. 5 is a schematic diagram showing the layout of the semiconductor device on a semiconductor wafer; FIG. 6 is a schematic diagram explaining dicing lines; FIG. 7 is an explanatory diagram showing a manufacturing method for the semiconductor device according to the present embodiment in stages; FIG. 8 is an explanatory diagram showing a manufacturing method for the semiconductor device according to the present embodiment in stages; FIG. 9 is an explanatory diagram showing cross-sectional observation positions in Verification Example 1 and Verification Example 2; FIG. 10 is a SEM photograph showing the results of Verification Example 1; FIG. 11 is a SEM photograph showing the results of Verification Example 1; FIG. 12 is a SEM photograph showing the results of Verification Example 2; FIG. 13 is a SEM photograph showing the results of Verification Example 2.

[0016] Hereinafter, a semiconductor device and a method for manufacturing a semiconductor device according to an embodiment of the present disclosure will be described with reference to the drawings. Note that the embodiment described below is specifically described to provide a better understanding of the gist of the present disclosure, and does not limit the present disclosure unless otherwise specified. Furthermore, the drawings used in the following description may show essential parts enlarged for convenience in order to make the features of the present disclosure easier to understand, and the dimensional ratios of each component may not necessarily be the same as those in reality.

[0017] [Semiconductor Device] Fig. 1 is a perspective view schematically showing the configuration of a semiconductor device according to an embodiment of the present disclosure. Fig. 2 is a top view of the semiconductor device as viewed from above. Fig. 3(a) is a cross-sectional view taken along line A1-A1' in Fig. 2, and Fig. 3(b) is a cross-sectional view taken along line A2-A2' in Fig. 2. Fig. 4 is a cross-sectional view taken along line BB' in Fig. 2.

[0018] The semiconductor device 10 of this embodiment is a vertical power device using a silicon carbide (SiC) wafer. In order to clearly show the main parts, detailed components of the vertical power device (such as source and drain electrodes) are omitted in Figures 1 to 4.

[0019] As shown in Fig. 1, a semiconductor device 10 includes an epitaxial layer (first semiconductor layer) 12 made of SiC formed on a semiconductor substrate 11. The semiconductor substrate 11 is made of n-type SiC. As will be described later with reference to Fig. 5, the semiconductor substrate 11 is sometimes called a semiconductor wafer 11 in the manufacturing process before being separated into individual semiconductor devices 10. The semiconductor substrate 11 is typically doped with a high concentration of n-type impurities on the order of 18 to 19 times the normal concentration per unit volume to provide low resistance, and an n-type electrode (not shown), such as a drain electrode, is formed over the entire back surface of the semiconductor substrate.

[0020] The epitaxial layer 12 is a layer formed by epitaxially growing SiC, and is made of first conductivity type SiC. In the following description, an example will be described in which the first conductivity type is p-type and the second conductivity type, which is the opposite conductivity type to the first conductivity type, is n-type.

[0021] 1 and 2, the semiconductor device (semiconductor chip) 10 has a rectangular shape in plan view from the top surface. The semiconductor device 10 has an active region 13, a termination region 14, and a peripheral region 15 on an epitaxial layer 12.

[0022] The active region (device active region) 13 is disposed in the central portion of the substantially rectangular semiconductor device 10, and power device structures such as MOSFETs, Schottky barrier diodes (SBDs), and PiN diodes are formed in the active region 13. The termination region 14 is disposed so as to surround the outside of the active region 13, and includes a JTE (Junction Termination Extension) structure and a guard ring structure for terminating the PN junction on the chip surface and alleviating electric field concentration when a reverse bias is applied. The peripheral region 15 is disposed so as to surround the termination region 14, and a channel stopper region 16 is formed at the edge of the peripheral region 15.

[0023] That is, a rectangular annular channel stopper region 16 is provided along the edge of the peripheral region 15. Such a rectangular annular channel stopper region 16 has an inner wall and an outer wall, and the outer wall is located at the edge of the semiconductor device (semiconductor chip) 10. The channel stopper region 16 may be provided continuously up to the chip edge, or may be provided inside and spaced a small distance from the chip edge.

[0024] 1 and 2 , a plurality of linear first pillars (protrusions) 21 made of first conductivity type SiC and a plurality of linear second pillars (second semiconductor layers) 22 made of second conductivity type SiC are formed inside the epitaxial layer (first semiconductor layer) 12 in the active region 13, the termination region 14, and the peripheral region 15. Furthermore, two subpillars (second semiconductor layers) 23 a, 23 b made of second conductivity type SiC are formed and connected to one end and the other end of the first pillars 21 and second pillars 22, respectively. The two subpillars can be separately referred to as the first subpillar 23 a and the second subpillar 23 b, but will be collectively referred to simply as subpillars.

[0025] Additionally, a first conductivity type frame region 17 is formed as part of the epitaxial layer 12 along the four edges of the semiconductor device. In the X direction in the figure, the frame region 17 is the region from the side surfaces of the sub-pillars 23a and 23b to the edge of the semiconductor chip 10. In the Y direction, the frame region 17 is the region from the side surface of the second pillar 22 located at the extreme edge to the edge of the semiconductor chip 10. In FIGS. 1 and 2, the first pillar 21, the second pillar 22, and the like are shown as perspective views from above. As can be seen from the cross-sectional views in FIGS. 3 and 4, a device structure layer 19 is formed on the top layer, and the first pillar 21, the second pillar 22, and the like are internal structures that are not directly visible from the outside of the completed semiconductor chip.

[0026] The second pillar (second semiconductor layer) 22 is formed by filling with second conductivity type SiC the interiors of multiple trenches 24 that extend in the X direction (first direction) from one surface 12a of the epitaxial layer 12 in the depth direction (Z direction) to a first depth (Z1). The second pillar 22 and the trenches 24 have a complementary relationship, and because their locations substantially overlap in Figures 1 to 4, they are denoted by the reference numerals 22 (24). The X direction (first direction) in which the multiple trenches 24 extend is typically set to the <11-20> direction, which is the off-direction of the semiconductor wafer 11.

[0027] The first pillars (protrusions) 21 are the remaining portions of the epitaxial layer 12 between the plurality of trenches 24 described above, and are formed from the semiconductor type of the epitaxial layer 12, i.e., first conductivity type SiC.

[0028] Such a structure in which wall-like first pillars 21 and second pillars 22 are alternately and periodically arranged along the Y direction is called a superjunction structure SJ. Such a superjunction structure SJ is also called a superjunction structure, and may be abbreviated to an SJ structure in this specification. A power device (vertical MOSFET) is formed in the active region 13 of such an SJ structure.

[0029] In this type of SJ structure, a depletion layer extends in the Y direction from the pn junction extending in the Z direction, ensuring a high breakdown voltage with higher p and n carrier concentrations than in a case where this structure is not used. Therefore, the product Np·Wp of the carrier concentration Np of the p-type pillar and its width Wp is designed to be approximately equal to or slightly different from the product Nn·Wn of the carrier concentration Nn of the n-type pillar and its width Wn. An SJ structure formed throughout the entire depth direction of the epitaxial layer 12, as in this embodiment, is sometimes referred to as a full superjunction structure (full SJ structure).

[0030] 1 and 2, the number of first pillars 21 and second pillars 22 are shown as a few, but this is because the number is reduced from the actual number in order to clearly show the SJ structure. The width of each of the first pillars 21 and second pillars 22 is typically about 1 to 10 μm. For example, if a 3 mm square chip is formed with the width of each of the first pillars 21 and second pillars 22 being 2.5 μm, the total number of first pillars 21 and second pillars 22 will be 1,200.

[0031] The subpillars (second semiconductor layers) 23a and 23b are formed by filling the insides of first sub-trenches 25a and second sub-trenches 25b, which have a first depth (Z1) and extend in the Y direction, with second conductivity type SiC. The first and second sub-pillars 23a and 23b and the first and second sub-trenches 25a and 25b have a complementary relationship, and their locations substantially overlap in Figures 1 to 4, so they are denoted by the reference symbols 23a (25a) and 23b (25b).

[0032] The first sub-trench 25a is connected to one end of the plurality of trenches 24 at right angles to each other. The second sub-trench 25b is connected to the other end of the plurality of trenches 24 at right angles to each other. As a result, the first sub-trench 25a is formed at one end of the first pillar 21 and the second pillar 22 that constitute the SJ structure so as to be perpendicular to each other, and the second sub-trench 25b is formed at the other end of the first pillar 21 and the second pillar 22 so as to be perpendicular to each other.

[0033] In a method for manufacturing a semiconductor device described later, when trench 24 is filled to form second pillar 22, first sub-trench 25a and second sub-trench 25b leave both ends of trench 24 open rather than closed, thereby preventing voids from occurring inside trench 24 at both ends. This makes it possible to prevent degradation of the characteristics of the SJ structure due to voids.

[0034] The width (X2) of each of the first sub-trench 25 a and the second sub-trench 25 b along the X direction, i.e., the width (X2) of each of the sub-pillars 23 a and 23 b along the X direction, is formed to be equal to or greater than the first depth (Z1) of the trench 24 and equal to or less than twice the first depth (Z1). Because the larger the width (X2), the more chip area is occupied, it is preferable that the width (X2) be equal to or less than 1.5 times the first depth (Z1) of the trench 24, and more preferably equal to or less than 1.1 times. For example, the width (X2) of each of the first sub-trench 25 a and the second sub-trench 25 b along the X direction may be formed to be less than 50 μm.

[0035] The semiconductor device 10 of this embodiment is an individual piece cut from the semiconductor wafer 11 shown in FIG. 5. FIG. 6 is an enlarged view of a portion of FIG. 5 showing the vicinity of four chip regions. Dicing lines DLa, DLb, and DLc are sequentially arranged in the X direction, and dicing lines DL1, DL2, and DL3 are sequentially arranged in the Y direction. Focusing on one chip region, it has four chip edges arranged to define a quadrilateral chip. Two first chip edges 31 parallel to the Y direction are formed by two dicing lines DL1 and DL2 in the Y direction. On the other hand, two second chip edges 32 parallel to the X direction are formed by two dicing lines DLa and DLb in the X direction. The channel stopper region 16 shown in FIGS. 1 to 4 is omitted in FIG. 6.

[0036] Note that, while the above-mentioned FIG. 5 shows an example in which 24 semiconductor devices (semiconductor chips) 10 are formed on one semiconductor wafer 11, the semiconductor devices 10 formed on one semiconductor wafer 11 may be formed in an optimized arrangement depending on the size of the semiconductor wafer 11 and the size of each individual semiconductor device 10, and the number of semiconductor devices 10 arranged is not limited.

[0037] [Method for Manufacturing Semiconductor Device] Next, an example of a method for manufacturing the semiconductor device according to the above-described embodiment will be described. Figures 7 and 8 are explanatory diagrams showing the steps of the method for manufacturing the semiconductor device according to this embodiment for one chip region. First, a SiC wafer is prepared as the semiconductor wafer 11. The SiC wafer is made of n-type SiC doped with n-type impurities such as nitrogen (N).

[0038] Such SiC wafers may be substrates with an off-axis angle. For example, SiC wafers may be used that have a main surface with a (0001) plane tilted 4 degrees in the <11-20> direction. Furthermore, 4H polytype SiC wafers (4H-SiC) may also be used as hexagonal SiC wafers.

[0039] Next, an epitaxial layer (first semiconductor layer) 12 is formed on the first main surface 11a of the semiconductor wafer 11 (FIG. 7(a): first step). The epitaxial layer 12 is made of SiC of a first conductivity type. When the first conductivity type is p-type, the epitaxial layer 12 is formed by epitaxially growing p-type SiC doped with p-type impurities such as boron (B) or aluminum (Al) in a CVD apparatus.

[0040] The thickness of the epitaxial layer 12 can be designed based on the required device breakdown voltage and the first depth (Z1) of the trench that constitutes the SJ structure, and is typically about 5 to 100 μm. １５ ~9.0 x 10 １７ cm －３ It's fine as long as it's to a certain extent.

[0041] Next, as shown in FIGS. 5 and 6, a plurality of chip regions (areas where individual semiconductor devices 10 are formed) are repeatedly arranged in the X and Y directions on the first main surface 11a of the semiconductor wafer 11, and two dicing lines DLa and DLb in the X direction and two dicing lines DL1 and DL2 in the Y direction that serve as boundaries between adjacent chip regions are set (second step).

[0042] Next, in each chip region partitioned by the two dicing lines DLa, DLb in the X direction and the two dicing lines DL1, DL2 in the Y direction described in FIG. 6 , a plurality of trenches 24 extending in the X direction to a first depth (Z1), a first sub-trench 25 a extending in the Y direction to the first depth and connected across one ends of the plurality of trenches 24, and a second sub-trench 25 b extending in the Y direction to the first depth and connected across the other ends of the plurality of trenches 24 are formed from the surface to the interior of the epitaxial layer (first semiconductor layer) 12 ( FIG. 7( b ): third step).

[0043] This third step may be performed by a semiconductor pattern formation process such as photolithography and etching. For example, a hard mask having openings corresponding to the top surface shapes of the second pillars 22 and the sub-pillars 23 a and 23 b connected thereto is formed in the epitaxial layer 12, and the epitaxial layer (first semiconductor layer) 12 is etched using this hard mask as an etching mask.

[0044] By this third step, the epitaxial layer 12 is etched to match the opening shape of the hard mask, and a rectangular parallelepiped trench 24 and a first sub-trench 25a and a second sub-trench 25b connected to one end and the other end of the trench 24 are formed along the depth direction Z. In addition, a plurality of protrusions (first pillars 21) are formed in the remaining portion of the first semiconductor layer 12 in which the trenches have been formed. After this, the hard mask may be removed.

[0045] The width (X2) of the first sub-trench 25 a and the second sub-trench 25 b formed in the third step along the X direction may be equal to or greater than the first depth (Z1) and equal to or less than twice the first depth (Z1). The width (X2) is preferably equal to or less than 1.5 times the first depth (Z1) of the trench 24, and more preferably equal to or less than 1.1 times the first depth (Z1). For example, the width (X2) of the first sub-trench 25 a and the second sub-trench 25 b along the X direction is formed to be less than 50 μm.

[0046] In this third step, the first sub-trench 25 a and the second sub-trench 25 b may be provided in a chip region spaced apart by a first width (X1) (see FIG. 6 ) along the X direction from the two dicing lines DL1 and DL2 in the Y direction, thereby forming frame regions 17 on the four sides of the chip region.

[0047] Next, the multiple trenches 24, first sub-trench 25a, and second sub-trench 25b formed in the third step and extending parallel to one another are filled with a backfill layer 18, which is a second semiconductor layer made of SiC of the second conductivity type and formed so as to have a thickness greater than the first depth (Z1) (FIG. 8(a): fourth step).

[0048] In this fourth step, the trench 24, the first sub-trench 25 a, and the second sub-trench 25 b are filled with the second conductivity type SiC by epitaxially growing the backfilling layer 18 made of second conductivity type SiC. The backfilling layer 18 is formed over the entire main surface of the semiconductor wafer, and an epitaxial layer is also formed on the top surfaces of multiple convex portions (first pillars) formed as remaining portions of the trench 24 and on the top surface of the frame region 17 on the four sides of the chip region. After the epitaxial growth of the backfilling layer 18 is completed, the main surface of the semiconductor wafer is not flat due to the influence of the deep unevenness formed before the growth.

[0049] In the fourth step, a first sub-trench 25 a and a second sub-trench 25 b that communicate with the trench 24 are formed at one end and the other end of the trench 24, respectively, so as to extend in a direction perpendicular to the extension direction of the trench 24. This prevents the upper side of the sidewall of the trench 24 from becoming overhanging during the regrowth process inside the trench 24. This makes it possible to prevent voids (cavities) from being formed at one end and the other end of the second pillar (second semiconductor layer) 22 that is formed by filling the trench 24. In other words, the important configuration of this embodiment is that the ends of the trench 24 are open ends due to the sub-trench rather than closed ends.

[0050] Next, the surface of the backfill layer 18 formed in the fourth step is planarized by grinding or the like, and further grinding is carried out to form a flat surface that exposes the first pillar 21, the second pillar 22, the sub-pillars 23a and 23b, and the frame region 17 (FIG. 8(b): fifth step).

[0051] The fifth step may be performed by, for example, CMP (Chemical Mechanical Polishing), etc. It is preferable that the fifth step be performed so that the difference between the maximum and minimum values ​​of the unevenness on the surfaces of the chip region and dicing lines is 0.1 μm or less.

[0052] Through the above steps, an SJ structure can be formed inside the epitaxial layer (first semiconductor layer) 12. Thereafter, a device structure layer 19 is formed on the semiconductor wafer, the entire surface of which is planarized and includes the SJ structure. A known active region 13, termination region 14, peripheral region 15, and channel stopper region 16 are formed in the device structure layer 19. When a vertical MOSFET structure is formed in the active region, a source electrode and a gate electrode are formed on the surface of the device structure layer 19. A drain electrode of the vertical MOSFET is formed on the back surface of the semiconductor wafer 11. The semiconductor device 10 of this embodiment can then be manufactured by cutting out individual semiconductor devices 10 along dicing lines DLa, DLb, and dicing lines DL1, DL2 of the semiconductor wafer.

[0053] In the fifth step, the main surface (front surface) of the semiconductor wafer on which the SJ structure is formed is planarized, so that the device structure layer 19 formed on that surface also maintains planarization. In the subsequent device formation process, photolithography, ion implantation, formation of an insulating film, formation of an electrode film, etc. are performed, and the precision of device fabrication is guaranteed because the semiconductor wafer has guaranteed flatness.

[0054] In contrast, when the technology described in Patent Document 2 is adopted, a semiconductor wafer having concave portions in both the vertical and horizontal directions of the scribe line is used, so the photoresist cannot be applied uniformly and the precision of the photolithography cannot be maintained. Furthermore, with a semiconductor wafer having concave portions, the alignment marks for photography are easily lost, and the alignment precision may not be guaranteed.

[0055] The above-described embodiment can be modified as follows: <Modification 1> In the semiconductor device 10 of the above-described embodiment, p-type SiC is used as the first conductivity type of the epitaxial layer 12 formed on the n-type semiconductor substrate 11, and n-type SiC is used as the second conductivity type of the backfilled layer 18 that backfills the trench 24. In contrast, Modification 1 differs in that the first conductivity type is n-type and the second conductivity type is p-type.

[0056] In the first modification, n-type SiC is used as the first conductivity type of the epitaxial layer 12 formed on the n-type semiconductor substrate 11, and p-type SiC is used as the second conductivity type of the backfilled layer 18 of the trench 24. In the first modification and the embodiment described above, the semiconductor substrate 11 is commonly n-type, but the conductivity types of the epitaxial layer 12 and the backfilled layer 18 are opposite to each other.

[0057] <Modification 2> The semiconductor device 10 of the above-described embodiment has been described using a full superjunction (full SJ) structure as an example. However, instead of the full SJ structure, a semi-superjunction (semi-SJ) structure may be used (Modification 2). In this Modification 2, similar to the semiconductor device 10 of the above-described embodiment, the first conductivity type is p-type and the second conductivity type is n-type. In the semi-SJ structure of Modification 2, a bulk drift layer is further inserted between the n-type semiconductor substrate 11 and the epitaxial layer 12 in the cross section of the semiconductor device 10 of the above-described embodiment shown in FIGS. 2 to 4. This bulk drift layer is of the same conductivity type as the n-type semiconductor substrate 11. The trench 24 penetrates the epitaxial layer 12 to a depth sufficient to reach this bulk drift layer.

[0058] The manufacturing process for the semi-SJ structure simply requires successively forming a two-layer structure of an n-type SiC layer (bulk drift layer) 12a and a second conductivity type (p-type) SiC layer 12b on an n-type semiconductor substrate 11. Although not particularly limited, if the carrier concentration of the n-type semiconductor substrate 11 is N1, the carrier concentration of the n-type bulk drift layer is N2, and the carrier concentration of the second conductivity type second pillar (n-type pillar) is N3, then they are typically designed to have the relationship N1 > N3 > N2.

[0059] In such a semi-SJ structure, the reverse recovery current tends to have a soft recovery waveform with a trailing tail, which suppresses voltage spikes due to parasitic inductance in the circuit and prevents element damage and ringing due to overvoltage.

[0060] <Variation 3> In Variation 3, the semiconductor device of Variation 1 described above has a semi-SJ structure, and similarly to Variation 1, the first conductivity type is n-type and the second conductivity type is p-type. In the semi-SJ structure of Variation 3, a bulk drift layer is inserted between the n-type semiconductor substrate 11 and the first conductivity type epitaxial layer 12 in the semiconductor device 10 of Variation 1. In Variation 3, the epitaxial layer 12 has the first conductivity type, that is, n-type, and the bulk drift layer has the same conductivity type as the n-type semiconductor substrate 11, that is, n-type. In the manufacturing process of this semi-SJ structure, a two-layer structure of an n-type SiC layer (bulk drift layer) 12a and a second conductivity type (n-type) SiC layer 12b may be successively formed on the n-type semiconductor substrate 11.

[0061] Although several embodiments of the present disclosure have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as defined in the claims.

[0062] For example, in the above-described embodiment, assuming a relatively complicated MOSFET structure, the device structure layer 19 is defined as a separate layer on the SJ structure (epitaxial layer 12) in Figures 2 and 3, but this layer is not essential. For devices such as diodes with simple structures, the element structure may be formed directly on the surface of the SJ structure by ion implantation or the like.

[0063] Furthermore, in the individualized semiconductor device 10 shown in FIGS. 1 to 4 of the above-described embodiment, a frame region 17 is provided surrounding the edge of the quadrilateral chip. This frame region 17 is essential for defining the sub-trenches in the manufacturing process shown in FIGS. 7 and 8 . However, during individualization, the frame region 17 may be broken and eliminated by the dicing device. In other words, if the total width of the frame regions on both sides of the dicing line is set to be equal to or less than the dicing width of the dicing device, the frame region will disappear at the edge of the semiconductor device 10. In other words, the frame region is not an essential component of the individualized semiconductor device 10.

[0064] 7A shows an example in which the first semiconductor layer 12 is provided in contact with the main surface of the semiconductor substrate 11. However, in this specification, when B is "provided over A," it means both a case in which A and B are in direct contact with each other and a case in which another layer is interposed between A and B.

[0065] In fact, a variation in which a bulk drift layer is inserted is available in the semi-SJ shown in Modification 2. When epitaxially growing first semiconductor layer 12 on highly doped semiconductor substrate 11, it is also common to first grow a buffer layer having an impurity concentration similar to that of semiconductor substrate 11, and then epitaxially growing the first semiconductor layer.

[0066] The effects of the present disclosure were verified by an experiment in which backfill crystal growth was performed on patterns including sub-trenches and trenches of various dimensions formed on a SiC substrate. (Verification Example 1) First, n-type silicon nitride (nCd) with an off-angle of 4 degrees in the <11-20> direction relative to the (0001) plane (Si-plane) was grown. ＋ A molded 4H-SiC substrate (4-degree off-axis substrate) was prepared, a mask was formed on its main surface using photolithography, and trenches and sub-trenches with a target depth of approximately 10 μm were formed by dry etching. The trench mask design values ​​were a pitch of 5 μm and a trench width varying from 0.75 to 4 μm.

[0067] The mask design values ​​for the width (X2) along the X direction of the sub-trench connecting the ends of the trenches were varied to 2.5 μm, 5 μm, 7.5 μm, 10 μm, and 12.5 μm. The mask was then removed, and crystal growth was performed to backfill the SJ trenches and sub-trench with SiC crystal. The target film thickness for the backfill crystal growth was approximately 20 μm. A CVD device was used for the SiC backfill crystal growth, and silane (SiH) was used as the growth gas. ４ ), propane (C ３ H ８ ), hydrogen (H ２ The detailed conditions for backfilling crystal growth are as described in Non-Patent Document 1.

[0068]

[0069] In the optical microscope observation (OM Test) in Table 1, visible light was transmitted through the backfilled sample to observe a contrast image from above. In Table 1, the observation result of the upstream sub-trench is designated A, and the observation result of the downstream sub-trench is designated B. The trenches were provided to extend in the <11-20> direction, which is the off-direction of the SiC substrate. The upstream side refers to the first sub-trench located on the starting side of the <11-20> direction, which is the off-direction, and the downstream side refers to the second sub-trench located on the end side of the <11-20> direction.

[0070] The optical microscope observations (OM Test) shown in Table 1 are summarized as follows. When contrast due to voids was clearly observed in the backfilled region, it was judged as "Void." Furthermore, because the backfilled crystal growth grows a crystal layer that is significantly thicker than the trench depth, a step in the backfilled growth layer occurs near the sub-trench. When it was difficult to determine whether or not a void had occurred due to the contrast of the step, it was judged as "Line." When there was no influence from the step and no contrast due to voids was observed, it was judged as "None." The optical microscope observations (OM Test) in Table 1 confirmed that void occurrence was prevented at least at the design value X2 = 12.5 μm or more. Note that, except for the trench ends, the trench was well filled and no voids were observed for any trench width variation from 0.75 to 4 μm.

[0071] Furthermore, for the SEM observations (SEM Test) in Table 1, a FIB-SEM hybrid device was used to create cross-sectional observation samples using a focused ion beam (FIB) from a sample with the width of the subtrench before and after the voids disappeared. Detailed cross-sectional observations (SEM Tests) were then performed using a scanning electron microscope. Figure 9 shows an example of the upstream cross-sectional area observed. Cross-section (1) is a cross-section connecting the frame region, the buried first subtrench, and the buried trench (second pillar). Cross-section (2) is a cross-section connecting the frame region, the buried first subtrench, and the protrusion (first pillar) formed by the remaining portion of the trench. SEM observations (SEM Tests) were performed on both the upstream side (A) and downstream side (B), but the results were similar. Therefore, photographs of the upstream side (A) are shown in Figures 10 and 11.

[0072] The measured sub-trench width of the sample in Figure 10 was 7.53 μm, and the trench depth was 11.41 μm. In Figure 10, a dotted auxiliary line has been visually inserted to show the boundary between the trench and the backfilled layer, but it has been slightly shifted from the exact boundary for ease of viewing. The same applies to the dotted lines in the other SEM observation results below. In this sample, the sub-trench width was 0.66 times the trench depth, which is less than 1, and a void has occurred at the position indicated by the white arrow in the figure.

[0073] The measured sub-trench width and trench depth of the sample in Fig. 11 were 10.12 µm and 10.99 µm, respectively. In this sample, the sub-trench width was 0.92 times the trench depth, which is close to 1, and it was confirmed that void formation was prevented.

[0074] (Verification Example 2) In Verification Example 2, a sample was prepared using the same procedure as in Verification Example 1, and similar observations were performed. In Verification Example 2, the trench depth was approximately twice that of Verification Example 1, and trenches and sub-trenches with a target depth of approximately 20 μm were formed by dry etching. The trench mask design values ​​were a pitch of 5 μm, and trench widths varied from 0.75 to 4 μm.

[0075] The mask design values ​​for the width (X2) of the sub-trench along the X direction were varied to 10 μm, 15 μm, 17.5 μm, 20 μm, and 25 μm. The target film thickness for the backfilling crystal growth in the trench was approximately 35 μm. The results of Verification Example 2 are shown in Table 2.

[0076]

[0077] As shown in Table 2, optical microscope observation showed a tendency for obvious voids to disappear as X2 increased, but when X2 was 15 μm or more, the linear contrast (lines) due to the steps of backfilled crystal growth was significant, making it difficult to accurately determine whether voids had disappeared. Similar to Verification Example 1, the trench was well filled except for the edges, and no voids were observed.

[0078] Therefore, SEM observation (SEM Test) was performed on samples with X2 = 17.5 μm and 25 μm (design value) in the same manner as in Verification Example 1. The results are shown in Figures 12 and 13. In the observations in Figures 12 and 13, the surface of the backfilled layer was polished after backfilling growth to the extent that the substrate surface before backfilling was exposed, in order to facilitate FIB processing of the sample for cross-sectional observation using an FIB-SEM composite device.

[0079] The measured sub-trench width and trench depth of the sample in Figure 12 were 16.08 µm and 19.83 µm, respectively. In this sample, the sub-trench width was 0.81 times the trench depth, which is smaller than 1, and voids were generated at the positions indicated by the white arrows in the figure.

[0080] The measured sub-trench width was 23.48 μm and the trench depth was 18.70 μm for the sample in Fig. 13. In this sample, the sub-trench width was 1.26 times the trench depth, and it was confirmed that void formation was prevented.

[0081] The key points that can be understood from the above disclosure are as follows: a plurality of trenches provided in the first semiconductor layer, the plurality of trenches being spaced apart from each other and extending parallel to a first direction, and each having a first depth; a plurality of protruding portions that are part of the first semiconductor layer and are formed by remaining portions of the plurality of trenches; a first sub-trench that is provided within the first semiconductor layer, extends in a second direction perpendicular to the first direction, and is connected to one ends of the plurality of trenches, the first sub-trench having the first depth; and a second sub-trench that is provided within the first semiconductor layer, extends in the second direction, and is connected to the other ends of the plurality of trenches, the second sub-trench having the first depth; [Structure 2] The semiconductor device according to Structure 1, further comprising a frame region provided in the first semiconductor layer along an edge of a quadrangle of the semiconductor substrate, wherein the first sub-trench and the second sub-trench are provided between the frame region along the edge in the second direction and edges of the plurality of trenches. [Structure 3] The method for manufacturing a semiconductor device according to Structure 1 or 2, wherein a width (X2) of the first sub-trench and the second sub-trench in the first direction is equal to or greater than the first depth and is equal to or less than twice the first depth.[Configuration 4] A method for manufacturing a semiconductor device having a superjunction structure in which a plurality of first pillars of a first conductivity type and a plurality of second pillars of a second conductivity type are alternately provided, the method comprising: a first step of forming a first semiconductor layer of a first conductivity type on a first main surface of a semiconductor wafer; a second step of setting a plurality of chip regions repeatedly arranged in a first direction and a second direction on the first main surface of the semiconductor wafer, and dicing lines that serve as boundaries between the chip regions adjacent to each other; and a third step of forming, in the first semiconductor layer, a plurality of trenches that extend to a first depth in the first direction and are used to form the first pillars and the second pillars, first sub-trenches that extend to the first depth in the second direction and are connected to one ends of the plurality of trenches, and second sub-trenches that extend to the first depth in the second direction and are connected to the other ends of the plurality of trenches, within each of the chip regions. A method for manufacturing a semiconductor device, the method comprising the steps of: a fourth step of filling the plurality of trenches, the first sub-trench, and the second sub-trench with a second semiconductor layer of the second conductivity type, the second semiconductor layer having a thickness greater than the first depth; and a fifth step of planarizing the surface of the second semiconductor layer to form the super junction structure. [Structure 5] The method for manufacturing a semiconductor device according to Structure 4, wherein in the third step, the first sub-trench and the second sub-trench are provided in the chip region spaced a first width (X1) from the dicing line along the first direction. [Structure 6] The method for manufacturing a semiconductor device according to Structure 4 or 5, wherein in the third step, the width (X2) of the first sub-trench and the second sub-trench along the first direction is formed to be equal to or greater than the first depth and not greater than twice the first depth. [Structure 7] The method for manufacturing a semiconductor device according to any one of Structures 4 to 6, wherein in the third step, the width (X2) of the first sub-trench and the second sub-trench along the first direction is formed to be less than 50 μm. [Configuration 8] The method for manufacturing a semiconductor device according to any one of Configurations 4 to 7, wherein in the fifth step, the difference between the maximum and minimum values ​​of the unevenness on the surfaces of the chip region and the dicing line is set to 0.1 μm or less.[Configuration 9] The method for manufacturing a semiconductor device according to any one of Configurations 4 to 8, wherein the semiconductor wafer, the first semiconductor layer, and the second semiconductor layer contain silicon carbide.

[0082] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure can suppress the generation of voids inside the trenches that form the superjunction structure and maintain the flatness of the surface. Therefore, the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure have industrial applicability.

[0083] DESCRIPTION OF SYMBOLS 10...Semiconductor device 11...Semiconductor substrate (semiconductor wafer) 12...Epitaxial layer (first semiconductor layer) 13...Active region 14...Termination region 15...Peripheral region 16...Channel stopper region 17...Frame region 18...Backfilled layer (second semiconductor layer) 19...Device structure layer 21...First pillar 22...Second pillar (second semiconductor layer) 23a...First sub-pillar (second semiconductor layer) 23b...Second sub-pillar (second semiconductor layer) 24...Trench 25a...First sub-trench 25b...Second sub-trench 31...First chip end 32...Second chip end SJ...Super junction structure (SJ structure)

Claims

a first semiconductor layer of a first conductivity type provided on the semiconductor substrate; a plurality of trenches provided in the first semiconductor layer, spaced apart from each other, extending parallel to a first direction and having a first depth; a plurality of protruding portions that are part of the first semiconductor layer and are formed by remaining portions of the plurality of trenches; a first sub-trench provided within the first semiconductor layer, extending in a second direction perpendicular to the first direction, connected to one ends of the plurality of trenches, the first sub-trench having the first depth; a second sub-trench provided within the first semiconductor layer, extending in the second direction, and connected to the other ends of the plurality of trenches, the second sub-trench having the first depth; 2. The semiconductor device according to claim 1, further comprising a frame region provided in the first semiconductor layer along an edge of the quadrangle of the semiconductor substrate, and the first sub-trench and the second sub-trench are provided between the frame region along the edge in the second direction and the edges of the plurality of trenches.

3. The semiconductor device according to claim 1 or 2, wherein the width (X2) of the first sub-trench and the second sub-trench along the first direction is equal to or greater than the first depth and equal to or less than twice the first depth.

4. A method for manufacturing a semiconductor device having a superjunction structure in which a plurality of first pillars of a first conductivity type and a plurality of second pillars of a second conductivity type are alternately arranged, comprising: a first step of forming a first semiconductor layer of a first conductivity type on a first main surface of a semiconductor wafer; a second step of setting a plurality of chip regions repeatedly arranged in a first direction and a second direction on the first main surface of the semiconductor wafer, and dicing lines that form boundaries between adjacent chip regions; and a third step of forming, in the first semiconductor layer, a plurality of trenches that extend to a first depth in the first direction and are used to form the first pillars and the second pillars, first sub-trenches that extend to the first depth in the second direction and are connected to one ends of the plurality of trenches, and second sub-trenches that extend to the first depth in the second direction and are connected to the other ends of the plurality of trenches, within each of the chip regions. A method for manufacturing a semiconductor device, comprising: a fourth step of filling the plurality of trenches, the first sub-trench, and the second sub-trench with a second semiconductor layer of the second conductivity type, the second semiconductor layer having a thickness greater than the first depth; and a fifth step of planarizing a surface of the second semiconductor layer to form the super junction structure.

5. A method for manufacturing a semiconductor device as described in claim 4, wherein in the third step, the first sub-trench and the second sub-trench are provided within the chip region spaced apart from the dicing line by a first width (X1) along the first direction.

6. A method for manufacturing a semiconductor device according to claim 4 or 5, wherein in the third step, the width (X2) of the first sub-trench and the second sub-trench along the first direction is formed to be equal to or greater than the first depth and equal to or less than twice the first depth.

7. The method for manufacturing a semiconductor device according to claim 6, wherein in the third step, the width (X2) of the first sub-trench and the second sub-trench along the first direction is formed to be less than 50 μm.

8. A method for manufacturing a semiconductor device according to claim 4 or 5, wherein in the fifth step, the difference between the maximum and minimum values ​​of the unevenness on the surfaces of the chip region and the dicing line is set to 0.1 μm or less.

9. The method for manufacturing a semiconductor device according to claim 4 or 5, wherein the semiconductor wafer, the first semiconductor layer, and the second semiconductor layer contain silicon carbide.

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