Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device comprises a first semiconductor element. The semiconductor device includes a first object, a second object, and a bonding layer interposed between the first object and the second object. The bonding layer includes a first surface layer bonded to the first object, a second surface layer bonded to the second object, and a base layer positioned between the first surface layer and the second surface layer. The first surface layer is bonded to the first object by solid-phase diffusion bonding, and includes a plurality of first crystal grains having a median diameter of 0.001 μm to 1.0 μm, inclusive.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] An example of a conventional semiconductor device is disclosed in Patent Document 1. The semiconductor device disclosed in this document uses solid-phase diffusion bonding to bond components together.

[0003] JP 2024-056982 A

[0004] [Summary] In solid-phase diffusion bonding, it is preferable that bonding be performed in a better state.

[0005] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device that enable solid-phase diffusion bonding to be performed in a better state.

[0006] A first aspect of the present disclosure provides a semiconductor device including a first semiconductor element. The semiconductor element includes a first object, a second object, and a bonding layer interposed between the first object and the second object. The bonding layer includes a first surface layer bonded to the first object, a second surface layer bonded to the second object, and a base layer located between the first surface layer and the second surface layer. The first surface layer is bonded to the first object by solid-state diffusion bonding and includes a plurality of first crystal grains having a median diameter of 0.001 μm or more and 1.0 μm or less.

[0007] A vehicle provided by a second aspect of the present disclosure includes the semiconductor device provided by the first aspect of the present disclosure.

[0008] A third aspect of the present disclosure provides a method for manufacturing a semiconductor device, including the steps of preparing a first object, a second object, and a bonding layer, and bonding the first object and the bonding layer by solid-state diffusion bonding. The bonding layer includes a first surface layer, a second surface layer, and a base layer located between the first surface layer and the second surface layer. The first surface layer includes a plurality of first crystal grains having a median diameter of 0.001 μm or more and 1.0 μm or less. In the step of bonding the first object and the bonding layer by solid-state diffusion bonding, the first surface layer and the first object are bonded by solid-state diffusion bonding.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0010] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a partial perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a partial perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 4 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 5 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 6 is a partial side view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 7 is a partial enlarged plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 8 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 9 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 10 is a side view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 11 is a bottom view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 5. FIG. 13 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 14 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 15 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 16 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 17 is a partially enlarged cross-sectional view showing the semiconductor device according to the first embodiment of the present disclosure. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 5. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 5. FIG. 20 is a partially enlarged plan view showing the semiconductor device according to the first embodiment of the present disclosure. FIG. 21 is a partially enlarged plan view showing the semiconductor device according to the first embodiment of the present disclosure. FIG. 22 is a configuration diagram showing a vehicle according to the first embodiment of the present disclosure. FIG. 23 is a flow diagram showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 24 is an exploded perspective view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 25 is a partially enlarged cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 26 is a cross-sectional view conceptually showing another example of the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 27 is a partially enlarged cross-sectional view showing a second modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 28 is a partially enlarged cross-sectional view showing a third modified example of the semiconductor device according to the first embodiment of the present disclosure.FIG. 29 is a partially enlarged cross-sectional view showing a fourth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 30 is a partially enlarged cross-sectional view showing a fifth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 31 is a partially enlarged cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 32 is a partially enlarged cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 33 is a partially enlarged cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 34 is a partially enlarged cross-sectional view showing a semiconductor device according to the third embodiment of the present disclosure. FIG. 35 is a partially enlarged cross-sectional view showing a semiconductor device according to the third embodiment of the present disclosure. FIG. 36 is a partially enlarged cross-sectional view showing a semiconductor device according to the third embodiment of the present disclosure. FIG. 37 is a partially enlarged cross-sectional view showing a first modified example of the semiconductor device according to the third embodiment of the present disclosure. FIG. 38 is a partially enlarged cross-sectional view showing a first modified example of the semiconductor device according to the third embodiment of the present disclosure. FIG. 39 is a perspective view of a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 40 is a plan view of a semiconductor device according to the fourth embodiment of the present disclosure. FIG. 41 is a plan view corresponding to FIG. 40 , seen through the sealing resin. FIG. 42 is a bottom view of the semiconductor device shown in FIG. 40 . FIG. 43 is a right side view of the semiconductor device shown in FIG. 40. FIG. 44 is a cross-sectional view taken along line XLIV-XLIV in FIG. 41. FIG. 45 is a cross-sectional view taken along line XLV-XLV in FIG. 41. FIG. 46 is a partially enlarged view of FIG. 44, showing a first semiconductor element and its vicinity. FIG. 47 is a partially enlarged view of FIG. 44, showing a second semiconductor element and its vicinity. FIG. 48 is a perspective view showing an exciter module according to a fifth embodiment of the present disclosure. FIG. 49 is a plan view of the exciter module shown in FIG. 48. FIG. 50 is a plan view corresponding to FIG. 49, showing the resin member through the view. FIG. 51 is a right side view of the exciter module shown in FIG. 48. FIG. 52 is a bottom view of the exciter module shown in FIG. 48. FIG. 53 is a cross-sectional view taken along line LIII-LIII in FIG. 50. FIG. 54 is a cross-sectional view taken along line LIV-LIV in FIG. 50. Fig. 55 is a cross-sectional view taken along line LV-LV in Fig. 50. Fig. 56 is a circuit diagram showing the circuit configuration of the exciter module shown in Fig. 48. Fig. 57 is a block diagram for explaining an example of use of the exciter module shown in Fig. 48.

[0011] DETAILED DESCRIPTION Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0012] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0013] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0014] 1 to 22 show a semiconductor device according to a first embodiment of the present disclosure. A semiconductor device B1 of this embodiment includes a semiconductor module A1 and a heat dissipation member 70.

[0015] The semiconductor module A1 may include a plurality of first semiconductor elements 10A, a plurality of second semiconductor elements 10B, a main substrate 3, a first terminal 41, a plurality of second terminals 42, a third terminal 43, a plurality of control terminals 45, a first conductive member 5, a second conductive member 6, and a sealing resin 8.

[0016] FIG. 1 is a perspective view showing a semiconductor device B1. FIG. 2 is a partial perspective view showing the semiconductor device B1. FIG. 3 is a partial perspective view showing the semiconductor device B1. FIG. 4 is a plan view showing the semiconductor device B1. FIG. 5 is a partial plan view showing the semiconductor device B1. FIG. 6 is a partial side view showing the semiconductor device B1. FIG. 7 is a partial enlarged plan view showing the semiconductor device B1. FIG. 8 is a partial plan view showing the semiconductor device B1. FIG. 9 is a partial plan view showing the semiconductor device B1. FIG. 10 is a side view showing the semiconductor device B1. FIG. 11 is a bottom view showing the semiconductor device B1. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 5. FIG. 13 is a partial enlarged cross-sectional view showing the semiconductor device B1. FIG. 14 is a partial enlarged cross-sectional view showing the semiconductor device B1. FIG. 15 is a partial enlarged cross-sectional view showing the semiconductor device B1. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 5. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 5. FIG. 20 is a partial enlarged plan view showing the semiconductor device B1. Fig. 21 is a partially enlarged plan view showing the semiconductor device B1. Fig. 22 is a configuration diagram showing a vehicle according to the first embodiment of the present disclosure. For ease of understanding, the heat dissipation member 70 is omitted from Figs. 2, 3, 5 to 9, 11, 20, and 21. For ease of understanding, the sealing resin 8 is omitted from Figs. 2, 3, 5 to 9, and 20 to 21.

[0017] In these figures, for example, the thickness direction z is an example of a thickness direction in the present disclosure. Also, for example, the first direction x is an example of a direction perpendicular to the thickness direction z. Also, for example, the second direction y is an example of a direction perpendicular to the thickness direction z and the first direction x. Also, for example, one side of the first direction x is referred to as the x1 side of the first direction x, and the other side of the first direction x is referred to as the x2 side of the first direction x. Also, for example, one side of the second direction y is referred to as the y1 side of the second direction y, and the other side of the second direction y is referred to as the y2 side of the second direction y. Also, for example, one side of the thickness direction z is referred to as the z1 side of the thickness direction z, and the other side of the thickness direction z is referred to as the z2 side of the thickness direction z.

[0018] The multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are electronic components that are central to the functionality of the semiconductor module A1. The constituent material of each of the first semiconductor elements 10A and each of the second semiconductor elements 10B is, for example, a semiconductor material primarily composed of silicon carbide (SiC). This semiconductor material is not limited to silicon carbide (SiC) and may be silicon (Si), gallium nitride (GaN), diamond (C), or the like. Each of the first semiconductor elements 10A and each of the second semiconductor elements 10B may be, for example, a power semiconductor chip with switching function, such as a metal oxide semiconductor field effect transistor (MOSFET). While this embodiment illustrates a case in which the first semiconductor elements 10A and the second semiconductor elements 10B are MOSFETs, the present invention is not limited thereto and may be other transistors, such as an insulated gate bipolar transistor (IGBT).

[0019] The first semiconductor elements 10A and the second semiconductor elements 10B may have different configurations or may have the same configuration. In the following description, the first semiconductor elements 10A and the second semiconductor elements 10B are all the same element. Each of the first semiconductor elements 10A and the second semiconductor elements 10B is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.

[0020] 13 and 14 , the first semiconductor element 10A and the second semiconductor element 10B each have an element main surface 101 and an element back surface 102. In each of the first semiconductor elements 10A and the second semiconductor elements 10B, the element main surface 101 and the element back surface 102 are spaced apart in the thickness direction z. The element main surface 101 faces the z1 side in the thickness direction z, and the element back surface 102 faces the z2 side in the thickness direction z.

[0021] The number of first semiconductor elements 10A and the number of second semiconductor elements 10B are changed as appropriate depending on the required performance, such as the current capacity handled by the semiconductor module A1. In this embodiment, as shown in Figures 8 and 9, four first semiconductor elements 10A and four second semiconductor elements 10B are arranged. The number of first semiconductor elements 10A and four second semiconductor elements 10B may be two or three, or five or more. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B may be equal to or different from each other.

[0022] The semiconductor module A1 is configured, for example, as a half-bridge switching circuit. In this case, a plurality of first semiconductor elements 10A form an upper arm circuit of the semiconductor module A1, and a plurality of second semiconductor elements 10B form a lower arm circuit. In the upper arm circuit, the plurality of first semiconductor elements 10A are connected in parallel with each other, and in the lower arm circuit, the plurality of second semiconductor elements 10B are connected in parallel with each other. The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are connected in series to form a bridge layer.

[0023] As shown in Figures 8, 9, and 19, each of the multiple first semiconductor elements 10A is mounted on a first conductive portion 32A of the main substrate 3, which will be described later. In the example shown in Figures 8 and 9, the multiple first semiconductor elements 10A are lined up, for example, in the second direction y and spaced apart from one another. Each first semiconductor element 10A is conductively bonded to the first conductive portion 32A via a first conductive bonding material 19A. The element back surface 102 faces the first conductive portion 32A.

[0024] As shown in Figures 8, 9, and 18, each of the multiple second semiconductor elements 10B is mounted on a second conductive portion 32B of the main substrate 3 (described later). In the example shown in Figures 8 and 9, the multiple second semiconductor elements 10B are aligned, for example, in the second direction y and spaced apart from one another. Each second semiconductor element 10B is conductively bonded to the second conductive portion 32B via a second conductive bonding material 19B. The element back surface 102 faces the second conductive portion 32B. As can be seen from Figure 9, the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap when viewed in the first direction x, but they do not necessarily have to overlap.

[0025] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B each have a first principal surface electrode 11, a second principal surface electrode 12, a third principal surface electrode 131, and a back surface electrode 15. The configurations of the first principal surface electrode 11, the second principal surface electrode 12, the third principal surface electrode 131, and the back surface electrode 15 described below are common to each of the first semiconductor elements 10A and each of the second semiconductor elements 10B. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 131 are provided on the element main surface 101. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 131 are insulated by an insulating film (not shown). The back surface electrode 15 is provided on the element back surface 102.

[0026] The first principal surface electrode 11 is, for example, a gate electrode, to which a drive signal (for example, a gate voltage) for driving the first semiconductor element 10A (second semiconductor element 10B) is input. In the first semiconductor element 10A (second semiconductor element 10B), the second principal surface electrode 12 is, for example, a source electrode, through which a source current flows. The third principal surface electrode 131 is, for example, a source sense electrode, through which a source current flows. The back surface electrode 15 is, for example, a drain electrode, through which a drain current flows. The back surface electrode 15 covers substantially the entire area of ​​the element back surface 102. The back surface electrode 15 is, for example, formed by Ag (silver) plating.

[0027] When a drive signal (gate voltage) is input to the first principal surface electrode 11 (gate electrode), each first semiconductor element 10A (each second semiconductor element 10B) switches between a conductive state and a non-conductive state in response to the drive signal. In the conductive state, current flows from the back surface electrode 15 (drain electrode) to the second principal surface electrode 12 (source electrode), and in the non-conductive state, current does not flow. In other words, each first semiconductor element 10A (each second semiconductor element 10B) performs a switching operation. The semiconductor module A1 converts a DC voltage input between one third terminal 43 and two first terminals 41 into, for example, an AC voltage, and outputs the AC voltage from two second terminals 42, using the switching functions of the multiple first semiconductor elements 10A and multiple second semiconductor elements 10B.

[0028] In addition to the main board 3, the semiconductor module A1 of this embodiment may include a first sub-board 48A and a second sub-board 48B.

[0029] The main substrate 3 supports a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B. The specific configuration of the main substrate 3 is not limited, and may be, for example, a direct bonded copper (DBC) substrate or an active metal brazing (AMB) substrate. The main substrate 3 includes a main insulating layer 31, a first main metal layer 32, and a second main metal layer 33. The first main metal layer 32 includes a first conductive portion 32A and a second conductive portion 32B. The dimension of the main substrate 3 in the thickness direction z is not limited, and may be, for example, 0.4 mm or more and 3.0 mm or less. In the illustrated example, the first main metal layer 32 does not include a plating layer or the like and may be a single layer, or may be a multi-layer structure including a plating layer of Ni or the like.

[0030] The constituent material of the main insulating layer 31 includes, for example, ceramics with excellent thermal conductivity. Examples of such ceramics include SiN (silicon nitride). The constituent material of the main insulating layer 31 is not limited to ceramics and may be an insulating resin sheet or the like. The main insulating layer 31 has, for example, a rectangular shape in a plan view. The dimension of the main insulating layer 31 in the thickness direction z is not limited in any way and is, for example, 0.05 mm or more and 1.0 mm or less.

[0031] As shown in FIGS. 8, 9, and 12, the first conductive portion 32A supports a plurality of first semiconductor elements 10A, and the second conductive portion 32B supports a plurality of second semiconductor elements 10B. The first conductive portion 32A and the second conductive portion 32B are formed on the upper surface (the surface facing the z1 side in the thickness direction z) of the main insulating layer 31. The constituent material of the first conductive portion 32A and the second conductive portion 32B includes, for example, Cu (copper). The constituent material may include, for example, Al (aluminum) other than Cu (copper). The first conductive portion 32A and the second conductive portion 32B are spaced apart in the first direction x. The first conductive portion 32A is located on the x1 side of the second conductive portion 32B in the first direction x. The first conductive portion 32A and the second conductive portion 32B each have, for example, a rectangular shape in a plan view. The first conductive portion 32A and the second conductive portion 32B, together with the first conductive member 5 and the second conductive member 6, constitute a path of the main circuit current switched by the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B.

[0032] The first conductive portion 32A has a first main surface 301A. The first main surface 301A is a flat surface facing the z1 side in the thickness direction z. A plurality of first semiconductor elements 10A are bonded to the first main surface 301A of the first conductive portion 32A via first conductive bonding materials 19A. The second conductive portion 32B has a second main surface 301B. The second main surface 301B is a flat surface facing the z1 side in the thickness direction z. A plurality of second semiconductor elements 10B are bonded to the second main surface 301B of the second conductive portion 32B via second conductive bonding materials 19B. The constituent materials of the first conductive bonding material 19A and the second conductive bonding material 19B are not particularly limited and may be, for example, solder, a metal paste material containing a metal such as Ag (silver), or a sintered metal containing a metal such as Ag (silver). The dimensions of first conductive portion 32A and second conductive portion 32B in thickness direction z are not limited in any way and may be, for example, 0.1 mm or more and 1.5 mm or less.

[0033] The second main metal layer 33 is formed on the lower surface (surface facing the z2 side in the thickness direction z) of the main insulating layer 31. The constituent material of the second main metal layer 33 is, for example, the same as the constituent material of the first main metal layer 32. The second main metal layer 33 has a back surface 302. The back surface 302 is a flat surface facing the z2 side in the thickness direction z. In the example shown in FIG. 11 , the back surface 302 is, for example, exposed from the sealing resin 8. In a plan view, the second main metal layer 33 overlaps both the first conductive portion 32A and the second conductive portion 32B.

[0034] The specific configurations of the first terminals 41, the second terminals 42, and the third terminal 43 are not limited in any way, and in this embodiment, they are made of a plate-shaped metal plate. This metal plate contains, for example, Cu (copper) or a Cu (copper) alloy. In the examples shown in Figures 1 to 6, 8, 9, and 11, the semiconductor module A1 includes two first terminals 41 and two third terminals 43, and two second terminals 42, but the number of each terminal is not limited in any way.

[0035] A DC voltage to be converted into power is input to the first terminal 41 and the third terminal 43. For example, the third terminal 43 is a positive electrode (P terminal), and the first terminal 41 is a negative electrode (N terminal). An AC voltage converted into power by the first semiconductor element 10A and the second semiconductor element 10B is output from the plurality of second terminals 42. Each of the plurality of first terminals 41, the plurality of second terminals 42, and the third terminal 43 includes a portion covered with the sealing resin 8 and a portion exposed from the sealing resin 8.

[0036] As shown in FIG. 12 , the third terminal 43 is conductively bonded to the first conductive portion 32A. The conductive bonding method is not limited, and methods such as ultrasonic bonding, laser bonding, and welding, or methods using solder, metal paste, silver sintered body, etc., may be appropriately adopted. The third terminal 43 may be integrally formed with the first conductive portion 32A. As shown in FIGS. 8 and 9 , the third terminal 43 is located on the x1 side in the first direction x with respect to the multiple first semiconductor elements 10A and the first conductive portions 32A. The third terminal 43 is conductively connected to the first conductive portion 32A and, via the first conductive portion 32A, to the back surface electrode 15 (drain electrode) of each first semiconductor element 10A.

[0037] As shown in FIG. 5 , the multiple first terminals 41 are conductively joined to the second conductive member 6. The conductive joining method is not limited, and methods such as ultrasonic bonding, laser bonding, and welding, or methods using solder, metal paste, silver sintered body, etc., may be appropriately adopted. The first terminals 41 may be integrally formed with the second conductive member 6. As shown in FIGS. 5 and 8 , the first terminals 41 are located on the x1 side of the multiple first semiconductor elements 10A and the first conductive portions 32A in the first direction x. The first terminals 41 are conductively connected to the second conductive member 6 and, via the second conductive member 6, to the second principal surface electrodes 12 (source electrodes) of each second semiconductor element 10B.

[0038] As shown in FIGS. 1 to 5 and 11 , in the semiconductor module A1, two first terminals 41 and two third terminals 43 each protrude from the sealing resin 8 toward the x1 side in the first direction x. The two first terminals 41 and two third terminals 43 are spaced apart from each other. The two first terminals 41 are located on opposite sides of the third terminal 43 in the second direction y. One first terminal 41 is located on the y1 side of the third terminal 43 in the second direction y, and the other first terminal 41 is located on the y2 side of the third terminal 43 in the second direction y. The two first terminals 41 and two third terminals 43 overlap each other when viewed in the second direction y.

[0039] As can be seen from FIGS. 8 , 9 , and 12 , the two second terminals 42 are each conductively bonded to the second conductive portion 32B. The conductive bonding method is not limited to any particular method, and methods such as ultrasonic bonding, laser bonding, and welding, or methods using solder, metal paste, silver sintered body, etc., may be appropriately employed. As shown in FIG. 8 and other figures, the two second terminals 42 are each located on the x2 side of the second semiconductor elements 10B and the second conductive portions 32B in the first direction x. Each second terminal 42 is conductively connected to the second conductive portion 32B and, via the second conductive portion 32B, to the back electrode 15 (drain electrode) of each second semiconductor element 10B. The number of second terminals 42 is not limited to two and may be, for example, one or three or more. For example, when there is one second terminal 42, it is preferably connected to the center portion of the second conductive portion 32B in the second direction y.

[0040] The first sub-substrate 48A and the second sub-substrate 48B support a plurality of control terminals 45. The first sub-substrate 48A and the second sub-substrate 48B are interposed between the first main surface 301A and the second main surface 301B and the plurality of control terminals 45 in the thickness direction z. The first sub-substrate 48A and the second sub-substrate 48B may have different configurations or may have a common configuration. The first sub-substrate 48A is disposed on the first conductive portion 32A. The second sub-substrate 48B is disposed on the second conductive portion 32B. In this embodiment, the first sub-substrate 48A and the second sub-substrate 48B have a common configuration and are rotated 180 degrees relative to each other when viewed in the thickness direction z.

[0041] The specific configuration of the first sub-substrate 48A and the second sub-substrate 48B is not limited in any way. Specific examples of the first sub-substrate 48A and the second sub-substrate 48B include an IMS (Insulated Metal Substrate) substrate, a glass epoxy resin substrate, a metal substrate, etc. In this embodiment, the first sub-substrate 48A and the second sub-substrate 48B are IMS substrates. As shown in FIG. 12 , the first sub-substrate 48A and the second sub-substrate 48B have a sub-insulation layer 481, a first sub-metal layer 482, and a second sub-metal layer 483 stacked on top of each other.

[0042] The sub-insulating layer 481 is made of, for example, ceramics. The sub-insulating layer 481 has, for example, a rectangular shape in plan view. The thickness of the sub-insulating layer 481 is not particularly limited and is, for example, 0.05 mm to 1.0 mm.

[0043] The first sub-metal layer 482 is formed on the upper surface (surface facing the z1 side in the thickness direction z) of the sub-insulating layer 481. The first sub-metal layer 482 includes, for example, Cu (copper) or a Cu (copper) alloy. The specific configuration of the first sub-metal layer 482 is not limited in any way. The thickness of the first sub-metal layer 482 is not limited in any way and is, for example, 0.035 mm or more and 2.0 mm or less.

[0044] 20 and 21, the first sub-metal layer 482 includes a plurality of regions 482A, 482B, 482C, 482D, 482E, and 482F. The plurality of regions 482A, 482B, 482C, 482D, 482E, and 482F are separated and insulated from one another.

[0045] The region 482A includes a connection portion 4821A and a terminal portion 4822A. In the first sub-substrate 48A, the connection portion 4821A is located on the x2 side in the first direction x, and the terminal portion 4822A is located on the x1 side in the first direction x. In the second sub-substrate 48B, the connection portion 4821A is located on the x1 side in the first direction x, and the terminal portion 4822A is located on the x2 side in the first direction x. The connection portion 4821A has a shape that extends elongatedly in the second direction y. The terminal portion 4822A has a substantially circular shape.

[0046] A plurality of wires 401 are joined to the connecting portion 4821A. In this embodiment, the wires 401 are joined to the connecting portion 4821A. The constituent material of the wires 401 is not limited in any way and includes, for example, Al (aluminum) or an Al (aluminum) alloy. The region 482A is electrically connected to the first main surface electrodes 11 (gate electrodes) of the plurality of first semiconductor elements 10A (the plurality of second semiconductor elements 10B) via the plurality of wires 401.

[0047] The region 482B includes a connection portion 4821B and a terminal portion 4822B. In the first sub-substrate 48A, the connection portion 4821B is located on the x2 side in the first direction x, and the terminal portion 4822B is located on the x1 side in the first direction x. In the second sub-substrate 48B, the connection portion 4821B is located on the x1 side in the first direction x, and the terminal portion 4822B is located on the x2 side in the first direction x. In the first sub-substrate 48A, the region 482B is located on the x1 side in the first direction x of the connection portion 4821A. In the second sub-substrate 48B, the region 482B is located on the x2 side in the first direction x of the connection portion 4821A. The connection portion 4821B has a shape that extends elongated in the second direction y. The terminal portion 4822B has a substantially semicircular shape. On the first sub-substrate 48A, the terminal portion 4822B is located on the y2 side of the terminal portion 4822A in the second direction y. On the second sub-substrate 48B, the terminal portion 4822B is located on the y1 side of the terminal portion 4822A in the second direction y.

[0048] A plurality of wires 402 are joined to the connection portion 4821B. In this embodiment, the wires 402 are joined to the connection portion 4821B. The constituent material of the wires 402 is not limited in any way and includes, for example, Al (aluminum) or an Al (aluminum) alloy. The region 482B is electrically connected to the third principal surface electrodes 131 (source sense electrodes) of the plurality of first semiconductor elements 10A (the plurality of second semiconductor elements 10B) via the plurality of wires 402.

[0049] The region 482C includes a connection portion 4821C and a terminal portion 4822C. In the first sub-substrate 48A, the connection portion 4821C is located on the y2 side in the second direction y, and the terminal portion 4822C is located on the y1 side in the second direction y. In the second sub-substrate 48B, the connection portion 4821C is located on the y1 side in the second direction y, and the terminal portion 4822C is located on the y2 side in the second direction y. The connection portion 4821C has a bent shape extending in the second direction y. The terminal portion 4822C has a substantially circular shape. In the first sub-substrate 48A, the terminal portion 4822C is located on the x1 side in the first direction x of the connection portion 4821A, and on the y2 side in the second direction y of the terminal portion 4822B. On the second sub-substrate 48B, the connecting portion 4821A is located on the x2 side in the first direction x, and the terminal portion 4822C is located on the y1 side in the second direction y of the terminal portion 4822B.

[0050] The region 482D includes a connection portion 4821D and a terminal portion 4822D. In the first sub-substrate 48A, the connection portion 4821D is located on the y2 side in the second direction y, and the terminal portion 4822D is located on the y1 side in the second direction y. The connection portion 4821D is, for example, rectangular, and the terminal portion 4822D is, for example, approximately circular. In the first sub-substrate 48A, the connection portion 4821D is located on the x1 side in the first direction x of the connection portion 4821C. In the second sub-substrate 48B, the connection portion 4821D is located on the x2 side in the first direction x of the connection portion 4821C. In the first sub-substrate 48A, the terminal portion 4822D is located on the y2 side in the second direction y of the terminal portion 4822C. In the second sub-substrate 48B, the terminal portion 4822D is located on the y1 side in the second direction y of the terminal portion 4822C.

[0051] In the first sub-substrate 48A, the region 482E is located on the y2 side in the second direction y of the connecting portion 4821A, and on the x2 side in the first direction x of the connecting portion 4821C. In the second sub-substrate 48B, the region 482E is located on the y1 side in the second direction y of the connecting portion 4821A, and on the x1 side in the first direction x of the connecting portion 4821C. The region 482E has a shape that extends in the second direction y.

[0052] The multiple regions 482F are arranged alternately in the second direction y, with the terminal portion 4822A, the terminal portion 4822B, the terminal portion 4822C, and the terminal portion 4822D. The shape of the multiple regions 482F is not limited in any way and may be rectangular, circular, or the like, and is rectangular in the illustrated example.

[0053] 12 , the second sub-metal layer 483 is formed on the lower surface (the surface on the z2 side in the thickness direction z) of the sub-insulating layer 481. The constituent material of the second sub-metal layer 483 includes, for example, Cu (copper) or a Cu (copper) alloy. The thickness of the second sub-metal layer 483 is not particularly limited and is, for example, 0.035 mm to 3.0 mm.

[0054] The second sub-metal layer 483 of the first sub-substrate 48A is conductively bonded to the first conductive portion 32A. The second sub-metal layer 483 of the second sub-substrate 48B is conductively bonded to the second conductive portion 32B. The method for conductively bonding the second sub-metal layer 483 to the first conductive portion 32A or the second conductive portion 32B is not limited in any way. Examples of conductive bonding methods include a method using a conductive bonding material, a laser bonding method, an ultrasonic bonding method, and a solid-state bonding method. In this embodiment, the second sub-metal layers 483 of the first sub-substrate 48A and the second sub-substrate 48B are conductively bonded to the first conductive portion 32A and the second conductive portion 32B via a conductive bonding material 49, as shown in FIG. 12 . The conductive bonding material 49 is, for example, solder.

[0055] 20 , in the first sub-substrate 48A, a wire 403 is connected to the connecting portion 4821D and the first conductive portion 32A. The material of the wire 403 is not limited in any way and includes, for example, Al (aluminum) or an Al (aluminum) alloy. This provides electrical continuity between the region 482D and the first conductive portion 32A.

[0056] 21 , on the second sub-board 48B, a thermistor 17 is connected to the connection portion 4821C and the connection portion 4821D. The thermistor 17 is used as a temperature detection sensor. Note that in addition to the thermistor 17, a configuration may be provided that includes, for example, a temperature-sensitive diode, or a configuration that does not include the thermistor 17.

[0057] The wire 401, the wire 402, and the wire 403 are not connected to the first main metal layer 32. In other words, the first main metal layer 32 is separated from the plurality of wires 401, 402, and 403.

[0058] The plurality of control terminals 45 are terminals for controlling each of the first semiconductor elements 10A and each of the second semiconductor elements 10B. The plurality of control terminals 45 include a plurality of first control terminals 46A, 46B, 46E and a plurality of second control terminals 47A to 47D. The plurality of first control terminals 46A, 46B, 46E are used to control each of the first semiconductor elements 10A, etc. The plurality of second control terminals 47A to 47D are used to control each of the second semiconductor elements 10B, etc. The plurality of first control terminals 46A, 46B, 46E are supported by a first sub-substrate 48A. The plurality of second control terminals 47A to 47D are supported by a second sub-substrate 48B.

[0059] The multiple first control terminals 46A, 46B, 46E are arranged at intervals in the second direction y. The multiple first control terminals 46A, 46B, 46E are supported by the first conductive portion 32A via the first sub-substrate 48A, as shown in Figures 2, 3, 5, 6, 8, 20, etc. The multiple first control terminals 46A, 46B, 46E are located in the first direction x between the multiple first semiconductor elements 10A and the two first terminals 41 and the third terminal 43, as shown in Figure 5.

[0060] 20 , the first control terminal 46A is disposed on the terminal portion 4822A. The first control terminal 46A is a terminal (gate terminal) for inputting drive signals to the plurality of first semiconductor elements 10A. A drive signal for driving the plurality of first semiconductor elements 10A is input to the first control terminal 46A (for example, a gate voltage is applied).

[0061] The first control terminal 46B is disposed on the terminal portion 4822B. The first control terminal 46B is a terminal (source sense terminal) for detecting source signals of the multiple first semiconductor elements 10A. The first control terminal 46B detects a voltage (a voltage corresponding to a source current) applied to each second main surface electrode 12 (source electrode) of the multiple first semiconductor elements 10A.

[0062] The first control terminal 46E is disposed on the terminal portion 4822D. The first control terminal 46E is a terminal (drain sense terminal) for detecting drain signals of the multiple first semiconductor elements 10A. The first control terminal 46E detects the voltage (voltage corresponding to the drain current) applied to each back electrode 15 (drain electrode) of the multiple first semiconductor elements 10A. The first control terminal 46E corresponds to the "first control terminal" in this disclosure.

[0063] The second control terminals 47A to 47D are arranged at intervals in the second direction y. As shown in Figures 2, 3, 5, 6, 8, 21, etc., the second control terminals 47A to 47D are supported by the second conductive portion 32B via the second sub-substrate 48B. As shown in Figure 5, the second control terminals 47A to 47D are located between the second semiconductor elements 10B and the second terminals 42 in the first direction x.

[0064] 21 , the second control terminal 47A is disposed on the terminal portion 4822A. The second control terminal 47A is a terminal (gate terminal) for inputting drive signals for the plurality of second semiconductor elements 10B. A drive signal for driving the plurality of second semiconductor elements 10B is input to the second control terminal 47A (for example, a gate voltage is applied).

[0065] The second control terminal 47B is disposed on the terminal portion 4822B. The second control terminal 47B is a terminal (source sense terminal) for detecting source signals of the plurality of second semiconductor elements 10B. The second control terminal 47B detects a voltage (a voltage corresponding to a source current) applied to each second main surface electrode 12 (source electrode) of the plurality of second semiconductor elements 10B.

[0066] The second control terminal 47C is disposed on the terminal portion 4822C. The second control terminal 47D is disposed on the terminal portion 4822D. The second control terminals 47C and 47D are terminals that are electrically connected to the thermistor 17.

[0067] As shown in FIGS. 12 and 20 to 21, each of the plurality of control terminals 45 (the plurality of first control terminals 46A, 46B, 46E and the plurality of second control terminals 47A to 47D) includes a holder 451 and a pin 452.

[0068] The holder 451 is made of a conductive material and may be bonded to the first sub-metal layer 482 by, for example, ultrasonic bonding, laser bonding, solid-state diffusion bonding, or the like.

[0069] The pin 452 is a rod-shaped member extending in the thickness direction z. The pin 452 is supported, for example, by being press-fitted into the holder 451. The pin 452 is electrically connected to the first sub-metal layer 482 at least via the holder 451. As shown in FIGS. 1 and 12 , the pin 452 protrudes from the sealing resin 8 toward the z1 side in the thickness direction z. In the illustrated example, the pin 452 includes a thick-diameter portion 4521. The thick-diameter portion 4521 is provided near the end of the pin 452 on the z1 side in the thickness direction z. The thick-diameter portion 4521 has a larger dimension in a direction perpendicular to the thickness direction z than other portions of the holder 451. The thick-diameter portion 4521 may be press-fitted into a through-hole provided in a control board (not shown) external to the semiconductor module A1 when the pin 452 is connected to the control board.

[0070] The first conductive member 5 and the second conductive member 6, together with the first conductive portion 32A and the second conductive portion 32B, form a path for a main circuit current switched by the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B. The first conductive member 5 and the second conductive member 6 are spaced apart from the first main surface 301A and the second main surface 301B on the z1 side in the thickness direction z and overlap the first main surface 301A and the second main surface 301B in a plan view. In this embodiment, the first conductive member 5 and the second conductive member 6 are each made of a metal plate material. The metal includes, for example, Cu (copper) or a Cu (copper) alloy. Specifically, the first conductive member 5 and the second conductive member 6 are made of an appropriately bent metal plate material.

[0071] The first conductive member 5 is connected to the second principal surface electrode 12 (source electrode) of each first semiconductor element 10A and the second conductive portion 32B, thereby electrically connecting the second principal surface electrode 12 of each first semiconductor element 10A and the second conductive portion 32B. The first conductive member 5 forms a path for a main circuit current switched by the multiple first semiconductor elements 10A. As shown in FIGS. 7 and 8 , the first conductive member 5 includes a main portion 51, multiple first bonding portions 52, and multiple second bonding portions 53.

[0072] The main portion 51 is located between the plurality of first semiconductor elements 10A and the second conductive portion 32B in the first direction x and is a strip-shaped portion extending in the second direction y in a plan view. The main portion 51 overlaps both the first conductive portion 32A and the second conductive portion 32B in a plan view and is spaced apart in the thickness direction z from the first main surface 301A and the second main surface 301B on the z1 side in the thickness direction z. As shown in FIG. 19 and other figures, the main portion 51 is located on the z2 side in the thickness direction z with respect to a third path portion 66 and a fourth path portion 67 of the second conductive member 6 described later and is closer to the first main surface 301A and the second main surface 301B than the third path portion 66 and the fourth path portion 67.

[0073] In this embodiment, the main portion 51 is disposed parallel to the first main surface 301A and the second main surface 301B.

[0074] As shown in FIG. 8 and other figures, the main portion 51 extends continuously in the second direction y to correspond to the region in which the multiple first semiconductor elements 10A are arranged. In this embodiment, as shown in FIGS. 7 , 8 , 12 , and other figures, multiple first openings 514 are formed in the main portion 51. Each of the multiple first openings 514 is, for example, a through hole penetrating in the thickness direction z (the plate thickness direction of the main portion 51). The multiple first openings 514 are arranged at intervals in the second direction y. The multiple first openings 514 are provided corresponding to each of the multiple first semiconductor elements 10A. In this embodiment, four first openings 514 are provided in the main portion 51, and these first openings 514 and the multiple (four) first semiconductor elements 10A are positioned at the same position in the second direction y.

[0075] 8, 12, etc., in the present embodiment, each first opening 514 overlaps with a gap between the first conductive portion 32A and the second conductive portion 32B in a plan view. The multiple first openings 514 are formed to facilitate the flow of the resin material between the upper side (the z1 side in the thickness direction z) and the lower side (the z2 side in the thickness direction z) near the main portion 51 (first conductive member 5) when injecting the flowable resin material to form the sealing resin 8.

[0076] As shown in FIG. 8 and other figures, the multiple first bonding portions 52 and the multiple second bonding portions 53 are connected to the main portion 51 and are arranged corresponding to the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B. Specifically, each first bonding portion 52 is located on the x1 side of the main portion 51 in the first direction x. Each second bonding portion 53 is located on the x2 side of the main portion 51 in the first direction x. As shown in FIG. 13 , the multiple first bonding portions 52 are individually bonded to the second principal surface electrodes 12 of the multiple first semiconductor elements 10A via conductive bonding materials 59. The multiple second bonding portions 53 and the second conductive portion 32B are bonded to each other via the conductive bonding material 59. The material of the conductive bonding material 59 is not particularly limited and may be, for example, solder, a metal paste material, or a sintered metal. In this embodiment, the first bonding portion 52 has two portions spaced apart in the second direction y.

[0077] The second conductive member 6 electrically connects the second main surface electrode 12 (source electrode) of each second semiconductor element 10B to the two first terminals 41. The second conductive member 6 is formed integrally with the two first terminals 41. The second conductive member 6 constitutes a path for a main circuit current that is switched by the plurality of second semiconductor elements 10B. As shown in FIGS. 2 and 5 to 7 , the second conductive member 6 includes a plurality of third joint portions 61, a first path portion 64, a second path portion 65, a plurality of third path portions 66, and a fourth path portion 67.

[0078] The multiple third bonding portions 61 are portions that are individually bonded to the multiple second semiconductor elements 10B. Each third bonding portion 61 and the second main surface electrode 12 of each second semiconductor element 10B are bonded via a conductive bonding material 69. The material of the conductive bonding material 69 is not particularly limited and may be, for example, solder, a metal paste material, or a sintered metal. In this embodiment, the third bonding portion 61 has two flat portions 611 and two first inclined portions 612.

[0079] The two flat portions 611 are aligned in the second direction y. The two flat portions 611 are spaced apart from each other in the second direction y. The shape of the flat portions 611 is not limited in any way, and in the illustrated example, they are rectangular. The two flat portions are joined to the second principal surface electrode 12 on both sides in the second direction y.

[0080] The two first inclined portions 612 are connected to the outside of the two flat portions 611 in the second direction y. That is, the first inclined portion 612 located on the y1 side in the second direction y is connected to the y1 side in the second direction y of the flat portion 611 located on the y1 side in the second direction y. Furthermore, the first inclined portion 612 located on the y2 side in the second direction y is connected to the y2 side in the second direction y of the flat portion 611 located on the y2 side in the second direction y. The first inclined portion 612 is inclined so that the farther it is from the flat portion 611 in the second direction y, the closer it is to the z1 side in the thickness direction z.

[0081] The first path portion 64 is interposed between the plurality of third joint portions 61 and the first terminal 41. In the illustrated example, the first path portion 64 is connected to the first terminal 41 via a first step portion 602. The first path portion 64 overlaps the first conductive portion 32A in a plan view. The first path portion 64 has a shape that extends as a whole in the first direction x.

[0082] The first path portion 64 includes a first band portion 641 and a first extending portion 643. The first band portion 641 is located on the x2 side in the first direction x with respect to the first terminal 41, and is substantially parallel to the first main surface 301A. The first band portion 641 has a shape that extends in the first direction x as a whole.

[0083] The first extending portion 643 extends from the side end of the first strip portion 641 on the y1 side in the second direction y to the z2 side in the thickness direction z. The first extending portion 643 is spaced apart from the first conductive portion 32A. In the illustrated example, the first extending portion 643 has a shape that follows the thickness direction z and is an elongated rectangle with the first direction x as its longitudinal direction. Note that the first path portion 64 may not have the first extending portion 643.

[0084] The second path portion 65 is interposed between the plurality of third joint portions 61 and the first terminal 41. In the illustrated example, the second path portion 65 is connected to the first terminal 41 via the second step portion 603. The second path portion 65 overlaps the first conductive portion 32A in a plan view. The second path portion 65 has a shape that extends as a whole in the first direction x.

[0085] The second path portion 65 includes a second band portion 651 and a second extending portion 653. The second band portion 651 is located on the x2 side in the first direction x with respect to the first terminal 41 and is substantially parallel to the first main surface 301A. The second band portion 651 has a shape that extends in the first direction x as a whole.

[0086] The second extending portion 653 extends from the side end of the second strip portion 651 on the y2 side in the second direction y to the z2 side in the thickness direction z. The second extending portion 653 is spaced apart from the first conductive portion 32A. In the example shown, the second extending portion 653 is shaped along the thickness direction z and has an elongated rectangular shape with the first direction x as the longitudinal direction. Note that the second path portion 65 may not have the second extending portion 653.

[0087] The multiple third path portions 66 are individually connected to the multiple third joint portions 61. Each third path portion 66 has a shape extending in the first direction x and is arranged at a distance from one another in the second direction y. There is no limitation on the number of multiple third path portions 66, and in the example shown, five third path portions 66 are arranged. Each third path portion 66 is arranged so as to be located between the multiple second semiconductor elements 10B in the second direction y or to be located outward of the multiple second semiconductor elements 10B in the second direction y.

[0088] In the present embodiment, one third joint 61 is disposed between two third path portions 66 adjacent to each other in the second direction y. In one third joint 61, the first inclined portion 612 located on the y1 side in the second direction y is connected to the third path portion 66 located on the y1 side in the second direction y, of the two third path portions 66 adjacent to each other in the second direction y. In one third joint 61, the first inclined portion 612 located on the y2 side in the second direction y is connected to the third path portion 66 located on the y2 side in the second direction y, of the two third path portions 66 adjacent to each other in the second direction y.

[0089] The fourth path portion 67 is connected to the ends of the plurality of third path portions 66 on the x1 side in the first direction x. The fourth path portion 67 has a shape that extends elongatedly in the second direction y. The fourth path portion 67 is connected to the ends of the first band portion 641 of the first path portion 64 and the second band portion 651 of the second path portion 65 on the x2 side in the first direction x. In the example shown, the first path portion 64 is connected to the end of the fourth path portion 67 on the y1 side in the second direction y. Furthermore, the second path portion 65 is connected to the end of the fourth path portion 67 on the y2 side in the second direction y.

[0090] The sealing resin 8 covers the multiple first semiconductor elements 10A, the multiple second semiconductor elements 10B, the main substrate 3 (excluding the back surface 302), portions of the multiple first terminals 41, the multiple second terminals 42, and the multiple third terminals 43, portions of the multiple control terminals 45, the first sub-substrate 48A and the second sub-substrate 48B, the first conductive member 5, the second conductive member 6, and the multiple wires 401 to 403. The sealing resin 8 is made of, for example, black epoxy resin. The sealing resin 8 is formed, for example, by molding. The size of the sealing resin 8 is not limited in any way, and may be, for example, approximately 35 mm to 60 mm in the first direction x, approximately 35 mm to 50 mm in the second direction y, and approximately 4 mm to 15 mm in the thickness direction z. These dimensions are the sizes of the largest portions along each direction. The sealing resin 8 has a resin main surface 81 and a resin back surface 82.

[0091] As shown in Figures 10, 12, and 18, the resin main surface 81 and the resin back surface 82 are spaced apart in the thickness direction z. The resin main surface 81 faces the z1 side in the thickness direction z, and the resin back surface 82 faces the z2 side in the thickness direction z. A plurality of control terminals 45 (a plurality of first control terminals 46A, 46B, and 46E and a plurality of second control terminals 47A to 47D) protrude from the resin main surface 81. As shown in Figure 11, the resin back surface 82 has a frame shape that surrounds the back surface 302 (the lower surface of the second main metal layer 33) of the main substrate 3 in a plan view. The back surface 302 of the main substrate 3 is exposed from the resin back surface 82 and is, for example, flush with the resin back surface 82.

[0092] The heat dissipation member 70 is used to cool the semiconductor module A1. The heat dissipation member 70 contains a metal. The heat dissipation member 70 may contain, for example, aluminum (Al).

[0093] The heat dissipation member 70 has a main surface 700. The heat dissipation member 70 may have a base portion 71, a heat dissipation portion 72, and a protrusion 73.

[0094] The main surface 700 faces the first side z1 in the thickness direction z. The main surface 700 may be a flat surface. The main surface 700 is bonded to the back surface 302 via a bonding layer 39.

[0095] The base 71 has a flat plate shape. In this example, the base 71 includes a main surface 700.

[0096] The heat dissipation portion 72 is connected to the base 71. The heat dissipation portion 72 protrudes from the base 71 to the second side z2 in the thickness direction z. The specific hole configuration of the heat dissipation portion 72 is not limited in any way, and in the example shown, the heat dissipation portion 72 may be a plurality of fins. The plurality of fins may each extend in the second direction y and may be arranged at equal intervals in the first direction x. A heat dissipation member 70 configured in this manner may be used in a state where it is attached to another box-shaped member (not shown). The box-shaped member and the heat dissipation member 70 may form a flow path through which a cooling medium can flow, for example.

[0097] The bonding layer 39 is interposed between the main surface 700 of the heat dissipation member 70 and the back surface 302 of the main substrate 3. The main surface 700 and the back surface 302 may be bonded by solid-state diffusion bonding with the bonding layer 39 sandwiched between them. In this embodiment, the heat dissipation member 70 corresponds to a first object of the present disclosure, and the main substrate 3 corresponds to a second object of the present disclosure.

[0098] There are no particular limitations on the specific configuration of bonding layer 39. The material constituting the surface of bonding layer 39 may be the same as or different from the materials constituting main surface 700 and back surface 302. When the material constituting the surface of bonding layer 39 and the material constituting main surface 700 and back surface 302 are the same, these surfaces may be made of, for example, Ag (silver).

[0099] 15 shows a specific example of the bonding layer 39, the second main metal layer 33, and the heat dissipation member 70. In this example, the bonding layer 39 may include a base layer 390, a second surface layer 392, a first surface layer 391, a first intermediate layer 3911, a second intermediate layer 3921, a third intermediate layer 3912, and a fourth intermediate layer 3922.

[0100] Base layer 390 is a layer that serves as a base for bonding layer 39. The material of base layer 390 may be softer than the material of first surface layer 391. Base layer 390 may contain, for example, Al (aluminum). First surface layer 391 is a surface layer located on second side z2 in thickness direction z and is a layer that is solid-state diffusion bonded to main surface 700. The material of first surface layer 391 is not limited in any way and may contain, for example, Ag (silver). Second surface layer 392 is a surface layer located on first side z1 in thickness direction z and is a layer that is solid-state diffusion bonded to back surface 302. The material of second surface layer 392 is not limited in any way and may contain, for example, Ag (silver).

[0101] 16 , the first surface layer 391 includes a plurality of first crystal grains 3910. The median diameter of the plurality of first crystal grains 3910 is 0.001 μm or more and 1.0 μm or less. The median diameter of the plurality of first crystal grains 3910 may be 0.001 μm or more and 0.2 μm or less. Furthermore, the median diameter of the plurality of first crystal grains 3910 may be 0.001 μm or more and 0.1 μm or less.

[0102] The heat dissipation member 70 may have a metal layer 709. The metal layer 709 contains, for example, Ag (silver) and constitutes the main surface 700. The metal layer 709 includes a plurality of crystal grains 7090. The median diameter of the plurality of crystal grains 7090 may be 0.001 μm or more and 1.0 μm or less. The median diameter of the plurality of crystal grains 7090 may be 0.001 μm or more and 0.2 μm or less. Furthermore, the median diameter of the plurality of crystal grains 7090 may be 0.001 μm or more and 0.1 μm or less.

[0103] 17 , the second surface layer 392 includes a plurality of second crystal grains 3920. The median diameter of the plurality of second crystal grains 3920 may be 0.001 μm or more and 1.0 μm or less. The median diameter of the plurality of second crystal grains 3920 may be 0.001 μm or more and 0.2 μm or less. Furthermore, the median diameter of the plurality of second crystal grains 3920 may be 0.001 μm or more and 0.1 μm or less.

[0104] The main substrate 3 may have a metal layer 309. The metal layer 309 contains, for example, Ag (silver) and constitutes the back surface 302. The metal layer 309 includes a plurality of crystal grains 3090. The median diameter of the plurality of crystal grains 3090 is 0.001 μm or more and 1.0 μm or less. The median diameter of the plurality of crystal grains 3090 may be 0.001 μm or more and 0.2 μm or less. Furthermore, the median diameter of the plurality of crystal grains 3090 may be 0.001 μm or more and 0.1 μm or less.

[0105] 15 , first intermediate layer 3911 is located between base layer 390 and first surface layer 391 and may include, for example, Ni (nickel). Second intermediate layer 3921 is located between base layer 390 and second surface layer 392 and may include, for example, Ni (nickel).

[0106] The third intermediate layer 3912 is located between the first intermediate layer 3911 and the first surface layer 391 and may contain, for example, Cu (copper). The fourth intermediate layer 3922 is located between the second intermediate layer 3921 and the second surface layer 392 and may contain, for example, Cu (copper).

[0107] Next, a vehicle C1 equipped with the semiconductor device B1 will be described with reference to Fig. 22. The vehicle C1 is, for example, an electric vehicle (EV).

[0108] As shown in Fig. 22, vehicle C1 includes an on-board charger 91, a storage battery 92, and a drive system 93. Power is supplied to on-board charger 91 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to on-board charger 91 via a wired connection. The on-board charger 91 is configured with a step-up DC-DC converter. The voltage of the power supplied to on-board charger 91 is stepped up by the converter and then supplied to storage battery 92. The stepped-up voltage is, for example, 600 V.

[0109] The drive system 93 drives the vehicle C1. The drive system 93 has an inverter 931 and a drive source 932. The semiconductor device B1 constitutes part of the inverter 931. Power stored in the storage battery 92 is supplied to the inverter 931. The power supplied from the storage battery 92 to the inverter 931 is DC power. Alternatively, unlike the power system shown in FIG. 22 , a step-up DC-DC converter may be further provided between the storage battery 92 and the inverter 931. The inverter 931 converts DC power into AC power. The inverter 931 including the semiconductor device B1 is electrically connected to the drive source 932.

[0110] The drive source 932 includes an AC motor and a transmission. When AC power converted by the inverter 931 is supplied to the drive source 932, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and then rotates the drive shaft of the vehicle C1. This drives the vehicle C1. To drive the vehicle C1, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. The semiconductor device B1 in the inverter 931 is required to output AC power whose frequency has been appropriately changed to correspond to the required rotation speed of the AC motor.

[0111] Next, a method for manufacturing the semiconductor device B1 will be described below with reference to FIGS.

[0112] 23 , the manufacturing method of semiconductor device B1 includes a step of preparing a first object, a second object, and a bonding layer 39, and a step of bonding the first object, the second object, and the bonding layer 39 by solid-state diffusion bonding. That is, in this embodiment, the manufacturing method includes a step of preparing a heat dissipation member 70, a main substrate 30, and the bonding layer 39, and a step of bonding the heat dissipation member 70, the main substrate 30, and the bonding layer 39 by solid-state diffusion bonding.

[0113] In the process of preparing heat dissipation member 70, main substrate 3, and bonding layer 39, the median diameter of multiple first crystal grains 3910 in first surface layer 391 and the median diameter of multiple second crystal grains 3920 in second surface layer 392 are set to the above-mentioned numerical ranges. Furthermore, the median diameter of multiple crystal grains 7090 in metal layer 709 and the median diameter of multiple crystal grains 3090 in metal layer 309 may also be set to the above-mentioned numerical ranges. First surface layer 391, second surface layer 392, metal layer 709, and metal layer 309 may be formed by, for example, a plating process. The above-mentioned median diameters can be adjusted, for example, by appropriately setting the plating process conditions.

[0114] Next, as shown in FIG. 24 , the semiconductor module A1 and the heat dissipation member 70 are bonded by solid-state diffusion bonding the back surface 302 and the main surface 700 via the bonding layer 39. As a result, as shown in FIG. 16 , the first surface 391 and the metal layer 709 are bonded by solid-state diffusion bonding. The bonded interface formed by solid-state diffusion bonding may have an unclear interface shape. In the figure, the main surface 700 is indicated by an imaginary line (two-dot chain line), and it may be difficult to clearly recognize the main surface 700 after bonding. Furthermore, as shown in FIG. 17 , the second surface 392 and the metal layer 309 are bonded by solid-state diffusion bonding. The bonded interface formed by solid-state diffusion bonding may have an unclear interface shape. In the figure, the back surface 302 is indicated by an imaginary line (two-dot chain line), and it may be difficult to clearly recognize the back surface 302 after bonding.

[0115] If the plurality of control terminals 45 interfere with each other during solid-phase diffusion bonding, the plurality of control terminals 45 may be attached to the semiconductor module A1 after the semiconductor module A1 and the heat dissipation member 70 are bonded together.

[0116] After this, for example, a plurality of control terminals 45 are attached, and then the semiconductor device B1 is obtained.

[0117] Next, the operation of the semiconductor device B1 and the method for manufacturing the semiconductor device B1 will be described.

[0118] According to this embodiment, as shown in FIG. 16 , the first surface layer 391 and the metal layer 709 of the heat dissipation member 70, which is the first object, are bonded by solid-state diffusion bonding. The median diameter of the plurality of first crystal grains 3910 is 0.001 μm or more and 1.0 μm or less. This allows the first surface layer 391 and the heat dissipation member 70 to be solid-state diffusion bonded in a better state. Solid-state diffusion bonding in a better state means, for example, that a stronger bond strength can be expected when the processing temperature in solid-state diffusion bonding is the same, or that a lower processing temperature can be used to achieve the same level of bond strength as in the past.

[0119] The state of solid-state diffusion bonding can be further improved when the median diameter of the plurality of first crystal grains 3910 is 0.001 μm or more and 0.2 μm or less. Furthermore, the state of solid-state diffusion bonding is favorable when the median diameter of the plurality of first crystal grains 3910 is 0.001 μm or more and 0.1 μm or less.

[0120] Metal layer 709 includes a plurality of crystal grains 7090. The median diameter of crystal grains 7090 is not less than 0.001 μm and not more than 1.0 μm. This allows first surface layer 391 and metal layer 709 to be solid-phase diffusion bonded in a better state.

[0121] The state of solid-state diffusion bonding can be further improved when the median diameter of the plurality of crystal grains 7090 is 0.001 μm or more and 0.2 μm or less. Furthermore, the state of solid-state diffusion bonding is preferably improved when the median diameter of the plurality of crystal grains 7090 is 0.001 μm or more and 0.1 μm or less.

[0122] 17 , second surface layer 392 and metal layer 309 of main substrate 3, which is the second object, are bonded by solid-state diffusion bonding. The median diameter of the plurality of second crystal grains 3920 is 0.001 μm or more and 1.0 μm or less. This allows second surface layer 392 and main substrate 3 to be solid-state diffusion bonded in a better state.

[0123] The state of solid-state diffusion bonding can be further improved when the median diameter of the second crystal grains 3920 is 0.001 μm or more and 0.2 μm or less. Furthermore, the state of solid-state diffusion bonding is favorable when the median diameter of the second crystal grains 3920 is 0.001 μm or more and 0.1 μm or less.

[0124] Metal layer 309 includes a plurality of crystal grains 3090. The median diameter of crystal grains 3090 is not less than 0.001 μm and not more than 1.0 μm. This allows second surface layer 392 and metal layer 709 to be solid-phase diffusion bonded in a better state.

[0125] The state of solid-state diffusion bonding can be further improved when the median diameter of the plurality of crystal grains 3090 is 0.001 μm or more and 0.2 μm or less. Furthermore, the state of solid-state diffusion bonding is preferably improved when the median diameter of the plurality of crystal grains 3090 is 0.001 μm or more and 0.1 μm or less.

[0126] 26 to 57 show modified examples and other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals. Furthermore, the configurations of the various parts in each modified example and each embodiment can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0127] 26 shows another example of the method for manufacturing the semiconductor device B1. This example includes a step of temporarily fixing the bonding layer 39 to the heat dissipation member 70 before the step of bonding the main substrate 30 and the main surface 700 by solid-state diffusion bonding.

[0128] In the illustrated example, the bonding layer 39 is placed on the main surface 700 of the heat dissipation member 70. The bonding layer 39 is temporarily fixed to the main surface 700 by performing a temporary fixing process on the bonding layer 39. The temporary fixing process is not limited to any particular process, and examples thereof include ultrasonic bonding and laser bonding. In the illustrated example, ultrasonic bonding is performed using an ultrasonic bonding tool Us. The portion of the bonding layer 39 that protrudes from the back surface 302 is preferably temporarily fixed using the ultrasonic bonding tool Us.

[0129] This embodiment also allows solid-phase diffusion bonding to be performed in a better state. As can be seen from this embodiment, solid-phase diffusion bonding may be performed after the bonding layer 39 is temporarily fixed. In this case, displacement of the bonding layer 39 is suppressed, which is preferable for solid-phase diffusion bonding.

[0130] 27 shows a second modified example of semiconductor device B1. In this modified semiconductor device B12, bonding layer 39 includes base layer 390, first surface layer 391, second surface layer 392, first intermediate layer 3911, and second intermediate layer 3921. First surface layer 391 and second surface layer 392 include, for example, Cu (copper). In this case, back surface 302 may be made of Cu (copper). Heat dissipation member 70 may have a metal layer (not shown) including Cu (copper) that forms main surface 700.

[0131] This modification allows solid-state diffusion bonding to be performed in a better state. As can be seen from this modification, there are no limitations on the materials that make up the surfaces that are solid-state diffusion bonded.

[0132] 28 shows a third modification of the semiconductor device B1. In the semiconductor device B13 of this modification, the heat dissipation member 70 has a plurality of flow paths 721.

[0133] The plurality of flow paths 721 extend, for example, in the second direction y. A cooling medium such as cooling water flows through the plurality of flow paths 721.

[0134] This modification allows solid-phase diffusion bonding to be performed in a better state. As can be seen from this modification, the specific configuration of the heat dissipation member 70 is not limited in any way.

[0135] 29 shows a fourth modified example of the semiconductor device B1. The semiconductor device B14 of this modified example includes three semiconductor modules A1. The three semiconductor modules A1 are arranged, for example, in the second direction y. Each semiconductor module A1 is bonded to a heat dissipation member 70, similar to the semiconductor device B1.

[0136] This modification allows solid-phase diffusion bonding to be performed in a better state. As can be seen from this modification, the number and arrangement of the semiconductor modules A1 are not limited in any way.

[0137] 30 shows a fifth modification of the semiconductor device B1. In the semiconductor device B15 of this modification, the arrangement of the plurality of control terminals 45 of the semiconductor module A15 differs from that of the semiconductor module A1 and the like.

[0138] In this modification, all the control terminals 45 are located on the side (second side x2) where the second terminals 42 are located with respect to the center of the sealing resin 8 in the first direction x.

[0139] This modification allows solid-phase diffusion bonding to be performed in a better state. As can be seen from this modification, the arrangement of the control terminals 45 is not limited in any way.

[0140] 31 to 33, a semiconductor device B2 according to a second embodiment of the present disclosure will be described. The semiconductor device B2 includes a semiconductor module A2 and a heat dissipation member 70. The main substrate 3 and the heat dissipation member 70 of the semiconductor module A2 may be bonded via a bonding layer 39, similar to the semiconductor device B1.

[0141] In the semiconductor module A2, the main substrate 3 and the first semiconductor element 10A are bonded via a bonding layer 39A. With respect to the bonding layer 39A, the main substrate 3 corresponds to the first object of the present disclosure, and the first semiconductor element 10A corresponds to the second object of the present disclosure.

[0142] Bonding layer 39A may have the same configuration as bonding layer 39, and may include a base layer 390, a first surface layer 391, and a second surface layer 392. Bonding layer 39A may include a first intermediate layer 3911, a second intermediate layer 3921, a third intermediate layer 3912, and a fourth intermediate layer 3922.

[0143] 32 , the first surface layer 391 includes a plurality of first crystal grains 3910. The median diameter of the plurality of first crystal grains 3910 is 0.001 μm or more and 1.0 μm or less. The median diameter of the plurality of first crystal grains 3910 may be 0.001 μm or more and 0.2 μm or less. Furthermore, the median diameter of the plurality of first crystal grains 3910 may be 0.001 μm or more and 0.1 μm or less.

[0144] The main substrate 3 may have a metal layer 309A. The metal layer 309A contains, for example, Ag (silver) and constitutes the first main surface 301A. The metal layer 309A includes a plurality of crystal grains 3090. The median diameter of the plurality of crystal grains 3090 may be 0.001 μm or more and 1.0 μm or less. The median diameter of the plurality of crystal grains 3090 may be 0.001 μm or more and 0.2 μm or less. Furthermore, the median diameter of the plurality of crystal grains 3090 may be 0.001 μm or more and 0.1 μm or less.

[0145] First surface layer 391 and metal layer 309A are bonded by solid-state diffusion bonding.

[0146] 33 , the second surface layer 392 includes a plurality of second crystal grains 3920. The median diameter of the plurality of second crystal grains 3920 may be 0.001 μm or more and 1.0 μm or less. The median diameter of the plurality of second crystal grains 3920 may be 0.001 μm or more and 0.2 μm or less. Furthermore, the median diameter of the plurality of second crystal grains 3920 may be 0.001 μm or more and 0.1 μm or less.

[0147] The first semiconductor element 10A may have a metal layer 159. The metal layer 159 contains, for example, Ag (silver) and is formed on the back electrode 15. The metal layer 159 includes a plurality of crystal grains 1590. The median diameter of the plurality of crystal grains 1590 is not less than 0.001 μm and not more than 1.0 μm. The median diameter of the plurality of crystal grains 1590 may be not less than 0.001 μm and not more than 0.2 μm. Furthermore, the median diameter of the plurality of crystal grains 1590 may be not less than 0.001 μm and not more than 0.1 μm.

[0148] Second surface layer 392 and metal layer 159 are bonded by solid-state diffusion bonding.

[0149] The second semiconductor element 10B may be bonded to the main substrate 3 by solid-state diffusion bonding via a bonding layer 39A, similar to the first semiconductor element 10A.

[0150] According to this embodiment, solid-state diffusion bonding can be performed in a better state. As can be understood from this embodiment, the bonding layer, the first object, and the second object in the present disclosure are not limited in any way and can be applied to various locations in various semiconductor devices.

[0151] 34 to 36, a semiconductor device B3 according to a third embodiment of the present disclosure will be described. The semiconductor device B3 includes a semiconductor module A3 and a heat dissipation member 70. The main substrate 3 and heat dissipation member 70 of the semiconductor module A3 may be bonded via a bonding layer 39, similar to the semiconductor devices B1 and B2. The main substrate 3 and first semiconductor element 10A may be bonded via a bonding layer 39A, similar to the semiconductor device B2.

[0152] In the semiconductor module A3, the first semiconductor element 10A and the first conductive member 5 are bonded via a bonding layer 39B. With respect to the bonding layer 39B, the first semiconductor element 10A corresponds to the first object of the present disclosure, and the first conductive member 5 corresponds to the second object of the present disclosure.

[0153] Bonding layer 39B may have the same configuration as bonding layer 39 and bonding layer 39A, and may include a base layer 390, a first surface layer 391, and a second surface layer 392. Bonding layer 39B may include a first intermediate layer 3911, a second intermediate layer 3921, a third intermediate layer 3912, and a fourth intermediate layer 3922.

[0154] 35 , the first surface layer 391 includes a plurality of first crystal grains 3910. The median diameter of the plurality of first crystal grains 3910 is 0.001 μm or more and 1.0 μm or less. The median diameter of the plurality of first crystal grains 3910 may be 0.001 μm or more and 0.2 μm or less. Furthermore, the median diameter of the plurality of first crystal grains 3910 may be 0.001 μm or more and 0.1 μm or less.

[0155] The first semiconductor element 10A may have a metal layer 129. The metal layer 129 includes, for example, Ag (silver) and is formed on the second principal surface electrode 12. The metal layer 129 includes a plurality of crystal grains 1290. The median diameter of the plurality of crystal grains 1290 is 0.001 μm or more and 1.0 μm or less. The median diameter of the plurality of crystal grains 1290 may be 0.001 μm or more and 0.2 μm or less. Furthermore, the median diameter of the plurality of crystal grains 1290 may be 0.001 μm or more and 0.1 μm or less.

[0156] First surface layer 391 and metal layer 129 are bonded by solid-state diffusion bonding.

[0157] 36 , the second surface layer 392 includes a plurality of second crystal grains 3920. The median diameter of the plurality of second crystal grains 3920 may be 0.001 μm or more and 1.0 μm or less. The median diameter of the plurality of second crystal grains 3920 may be 0.001 μm or more and 0.2 μm or less. Furthermore, the median diameter of the plurality of second crystal grains 3920 may be 0.001 μm or more and 0.1 μm or less.

[0158] The first conductive member 5 may have a metal layer 58. The metal layer 58 includes, for example, Ag (silver) and is formed on the first bonding portion 52. The metal layer 58 includes a plurality of crystal grains 580. The median diameter of the plurality of crystal grains 580 is 0.001 μm or more and 1.0 μm or less. The median diameter of the plurality of crystal grains 580 may be 0.001 μm or more and 0.2 μm or less. Furthermore, the median diameter of the plurality of crystal grains 580 may be 0.001 μm or more and 0.1 μm or less.

[0159] Second surface layer 392 and metal layer 58 are bonded by solid-state diffusion bonding.

[0160] The second semiconductor element 10B may be bonded to the second conductive member 6 via a bonding layer 39B by solid-state diffusion bonding, similar to the first semiconductor element 10A.

[0161] According to this embodiment, solid-state diffusion bonding can be performed in a better state. As can be understood from this embodiment, the bonding layer, the first object, and the second object in the present disclosure are not limited in any way and can be applied to various locations in various semiconductor devices.

[0162] A semiconductor device B31 according to a first modified example of the third embodiment of the present disclosure will be described with reference to FIGS.

[0163] The semiconductor device B31 includes a semiconductor module A31 and a heat dissipation member 70. The semiconductor module A31 and the heat dissipation member 70 may be bonded by solid-state diffusion bonding via a bonding layer 39. The main substrate 3 and the first semiconductor element 10A may be bonded by solid-state diffusion bonding via a bonding layer 39A.

[0164] The semiconductor module A31 includes a first conductive member 5A. The first conductive member 5A forms a conductive path similar to that of the first conductive member 5 in the above example. The first conductive member 5A may be a wire containing a metal such as aluminum (Al) or copper (Cu) or an alloy thereof. The first semiconductor element 10A and the first conductive member 5A are bonded via a bonding layer 39B. With respect to the bonding layer 39B, the first semiconductor element 10A corresponds to the first object of the present disclosure, and the first conductive member 5A corresponds to the second object.

[0165] The bonding layer 39B may have the same configuration as the bonding layer 39B in the semiconductor device B3. The first surface layer 391 and the metal layer 129 are bonded by solid-phase diffusion bonding.

[0166] 38 , the first conductive member 5A is bonded to the second surface layer 392. The bonding method for the first conductive member 5A and the second surface layer 392 may be a method other than solid-state diffusion bonding, such as wedge bonding. In this case, the median diameter of the multiple crystal grains 500 of the first conductive member 5A may be greater than, for example, the above-mentioned 1.0 μm.

[0167] According to the present embodiment, solid-state diffusion bonding can be performed in a better state. As can be understood from the present embodiment, the bonding method of the bonding layer and the second object in the present disclosure is not limited to solid-state diffusion bonding, and various bonding methods can be applied.

[0168] 39 to 47, a semiconductor device B4 according to a fourth embodiment of the present disclosure will be described. The semiconductor device B4 includes a semiconductor module A4 and a heat dissipation member 70. The joining method and joining form of the semiconductor module A4 and the heat dissipation member 70 may be the same as those of the semiconductor device B1 described above. Furthermore, the joining using the joining layers 39A and 39B in the semiconductor modules A2 and A3 described above may be appropriately adopted. A description of these joining methods will be omitted.

[0169] The semiconductor module A4 is generally used in power conversion circuits such as inverters. The semiconductor module A4 includes a main insulating layer 31, a first conductive portion 32A, a second main metal layer 33, a second conductive portion 32B, a first semiconductor element 10A, a second semiconductor element 10B, a first terminal 41, a second terminal 42, a first control terminal 46A, a first control terminal 46B, and a sealing resin 8. The semiconductor module A4 also includes wires 401, 402, and 403. For ease of understanding, FIG. 41 shows the sealing resin 8 in a perspective view. In FIG. 41, the transparent sealing resin 8 is indicated by an imaginary line (double-dashed line).

[0170] 44, the sealing resin 8 covers the first semiconductor element 10A and the second semiconductor element 10B. The sealing resin 8 is an insulator and is made of a material containing, for example, black epoxy resin.

[0171] 43 , the sealing resin 8 has a resin main surface 81 and a resin back surface 82. As shown in FIGS. 44 and 45 , the resin main surface 81 faces the same side as a first main surface 301A of a first conductive part 32A (described later) in the thickness direction z. The resin back surface 82 faces the opposite side to the resin main surface 81 in the thickness direction z.

[0172] As shown in Figures 44 and 45, the main insulating layer 31 is covered with a sealing resin 8. The main insulating layer 31 is made of a material with relatively high thermal conductivity. For example, the main insulating layer 31 is made of ceramics containing either silicon nitride (Si3N4) or aluminum nitride (AlN). Alternatively, the main insulating layer 31 may be made of a material containing resin.

[0173] As shown in Figures 44 and 45 , the first conductive portion 32A is joined to one side of the main insulating layer 31 in the thickness direction z. The first semiconductor element 10A and the second semiconductor element 10B are mounted on the first conductive portion 32A. The first conductive portion 32A is covered with sealing resin 8. The first conductive portion 32A contains copper (Cu). The dimension of the first conductive portion 32A in the thickness direction z is larger than the dimension of the main insulating layer 31 in the thickness direction z.

[0174] 41 and 44, the first conductive part 32A has a first main surface 301A. The first main surface 301A faces one side in the thickness direction z. The first semiconductor element 10A and the second semiconductor element 10B face the first main surface 301A.

[0175] As shown in FIGS. 44 and 45 , the second main metal layer 33 is located on the opposite side of the main insulating layer 31 from the first conductive portion 32A and is bonded to the main insulating layer 31. As shown in FIG. 42 , the second main metal layer 33 is exposed to the outside from the resin back surface 82 of the sealing resin 8. The second main metal layer 33 contains copper. In the semiconductor module A4, the dimension of the second main metal layer 33 in the thickness direction z is larger than the dimension of the main insulating layer 31 in the thickness direction z and is equal to the dimension of the first conductive portion 32A in the thickness direction z. The relationship of the dimension of the second main metal layer 33 in the thickness direction z to the dimensions of the main insulating layer 31 and the first conductive portion 32A in the thickness direction z may be variously determined.

[0176] As shown in Figures 41 and 45, the second conductive portion 32B is located on the same side as the first conductive portion 32A with respect to the main insulating layer 31, and is joined to the main insulating layer 31. The second conductive portion 32B is located adjacent to the first conductive portion 32A in the first direction x. The second conductive portion 32B extends in the second direction y. The second conductive portion 32B is covered with sealing resin 8. The second conductive portion 32B contains copper. The dimension of the second conductive portion 32B in the thickness direction z is larger than the dimension of the main insulating layer 31 in the thickness direction z.

[0177] As shown in FIGS. 44 and 45 , the first semiconductor element 10A is bonded to the first main surface 301A of the first conductive portion 32A. The first semiconductor element 10A is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). Alternatively, the first semiconductor element 10A may be a field-effect transistor including a metal-insulator-semiconductor field-effect transistor (MISFET) or a bipolar transistor such as an insulated gate bipolar transistor (IGBT). In the description of the semiconductor module A4, the first semiconductor element 10A is an n-channel MOSFET with a vertical structure. The first semiconductor element 10A includes a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC).

[0178] As shown in FIG. 46, the first semiconductor element 10A has a back surface electrode 15, two second principal surface electrodes 12, and a first principal surface electrode 11.

[0179] As shown in FIG. 46 , the back electrode 15 is located on one side in the thickness direction z. The back electrode 15 faces the first main surface 301A of the first conductive portion 32A. The back electrode 15 is conductively bonded to the first main surface 301A via a first conductive bonding material 19A. This allows the back electrode 15 to be electrically connected to the first conductive portion 32A. The first conductive bonding material 19A is, for example, solder. Alternatively, the first conductive bonding material 19A may be a sintered metal containing silver or the like. A current corresponding to the power before conversion by the first semiconductor element 10A flows through the back electrode 15. In other words, the back electrode 15 corresponds to the drain of the first semiconductor element 10A.

[0180] As shown in Fig. 46 , the two second principal surface electrodes 12 are located on the opposite side of the back surface electrode 15 in the thickness direction z. As shown in Fig. 41 , the two second principal surface electrodes 12 are spaced apart from each other in the first direction x. A current corresponding to the power converted by the first semiconductor element 10A flows through each of the two second principal surface electrodes 12. That is, the two second principal surface electrodes 12 correspond to the sources of the first semiconductor element 10A.

[0181] 41 and 46 , the first principal surface electrode 11 is located on the same side as the two second principal surface electrodes 12 in the thickness direction z. A gate voltage for driving the first semiconductor element 10A is applied to the first principal surface electrode 11. The first principal surface electrode 11 is electrically connected to the second conductive portion 32B. As shown in FIG. 41 , the area of ​​the first principal surface electrode 11 is smaller than the area of ​​each of the two second principal surface electrodes 12 when viewed in the thickness direction z.

[0182] As shown in FIG. 44 , the second semiconductor element 10B is bonded to the first main surface 301A of the first conductive portion 32A. The second semiconductor element 10B is the same element as the first semiconductor element 10A. Therefore, the second semiconductor element 10B is an n-channel MOSFET with a vertical structure. The second semiconductor element 10B is located adjacent to the first semiconductor element 10A in the second direction y.

[0183] As shown in FIG. 47, the second semiconductor element 10B has a back surface electrode 15, two second principal surface electrodes 12, and a first principal surface electrode 11.

[0184] As shown in Fig. 47, the back electrode 15 is located on one side in the thickness direction z. The back electrode 15 faces the first main surface 301A of the first conductive portion 32A. The back electrode 15 is conductively bonded to the first main surface 301A via a first conductive bonding material 19A. This allows the back electrode 15 to be electrically connected to the first conductive portion 32A. A current corresponding to the power before being converted by the second semiconductor element 10B flows through the back electrode 15. In other words, the back electrode 15 corresponds to the drain of the second semiconductor element 10B.

[0185] 47 , the two second principal surface electrodes 12 are located on the opposite side of the back surface electrode 15 in the thickness direction z. As shown in FIG. 41 , the two second principal surface electrodes 12 are spaced apart from each other in the first direction x. A current corresponding to the power converted by the second semiconductor element 10B flows through each of the two second principal surface electrodes 12. That is, the two second principal surface electrodes 12 correspond to the sources of the second semiconductor element 10B.

[0186] 41 and 47 , the first principal surface electrode 11 is located on the same side as the two second principal surface electrodes 12 in the thickness direction z. A gate voltage for driving the second semiconductor element 10B is applied to the first principal surface electrode 11. The first principal surface electrode 11 is electrically connected to the second conductive portion 32B. As shown in FIG. 41 , the area of ​​the first principal surface electrode 11 is smaller than the area of ​​each of the two second principal surface electrodes 12 when viewed in the thickness direction z.

[0187] 41 , the first terminal 41 is located on one side of the first semiconductor element 10A and the second semiconductor element 10B in the first direction x. The first terminal 41 is electrically connected to the back electrode 15 of the first semiconductor element 10A and the back electrode 15 of the second semiconductor element 10B. Therefore, the first terminal 41 corresponds to the drain terminal of the semiconductor module A4. The first terminal 41 contains copper.

[0188] As shown in FIGS. 41 and 45 , the first terminal 41 has a first base portion 416 and a plurality of first bonding portions 417. As viewed in the thickness direction z, the first base portion 416 is spaced from the first main surface 301A of the first conductive portion 32A. As shown in FIG. 40 , the first base portion 416 includes a portion covered with the sealing resin 8 and a portion exposed to the outside from the sealing resin 8. As viewed in the thickness direction z, the plurality of first bonding portions 417 extend from the first base portion 416 in the first direction x toward the side where the first semiconductor element 10A and the second semiconductor element 10B are located. The plurality of first bonding portions 417 are arranged along the second direction y. Each of the plurality of first bonding portions 417 is covered with the sealing resin 8.

[0189] 41 and 44, the second terminal 42 is conductively bonded to the two second main surface electrodes 12 of the first semiconductor element 10A and the two second main surface electrodes 12 of the second semiconductor element 10B. As a result, the second terminal 42 is electrically connected to each of the two second main surface electrodes 12. Therefore, the second terminal 42 corresponds to the source terminal of the semiconductor module A4. The second terminal 42 contains copper.

[0190] As shown in FIGS. 41 and 44 , the second terminal 42 has a second base portion 421, a plurality of second bonding portions 422, and a plurality of third bonding portions 423. When viewed in the thickness direction z, the second base portion 421 overlaps the first main surface 301A of the first conductive portion 32A. As shown in FIG. 40 , the second base portion 421 includes a portion covered with the sealing resin 8 and a portion exposed to the outside from the sealing resin 8. Each of the plurality of second bonding portions 422 is connected to the second base portion 421 and is covered with the sealing resin 8. As shown in FIG. 45 , each of the plurality of second bonding portions 422 protrudes from the second base portion 421 toward the first semiconductor element 10A. Each of the plurality of second bonding portions 422 is conductively bonded to one of the two second main surface electrodes 12 of the first semiconductor element 10A via a first conductive bonding material 19A. Each of the plurality of third bonding portions 423 is connected to the second base portion 421 and is covered with the sealing resin 8. Each of the plurality of third bonding portions 423 protrudes from the second base portion 421 toward the second semiconductor element 10B. Each of the plurality of third bonding portions 423 is conductively bonded to one of the two second principal surface electrodes 12 of the second semiconductor element 10B via the first conductive bonding material 19A.

[0191] As shown in FIG. 40 , the first control terminal 46A includes a portion covered by the sealing resin 8 and a portion exposed from the sealing resin 8. The first control terminal 46A is located on one side of the second base portion 421 of the second terminal 42 in the second direction y. The first control terminal 46A is electrically connected to the second conductive portion 32B. Therefore, the first control terminal 46A is electrically connected to the first principal surface electrode 11 of the first semiconductor element 10A and the first principal surface electrode 11 of the second semiconductor element 10B. In other words, the first control terminal 46A corresponds to the gate terminal of the semiconductor module A4. The first control terminal 46A includes copper. As shown in FIG. 43 , the portion of the first control terminal 46A exposed from the sealing resin 8 includes a portion extending along the thickness direction z.

[0192] As shown in FIG. 40 , the first control terminal 46B includes a portion covered with the sealing resin 8 and a portion exposed from the sealing resin 8. The first control terminal 46B is located between the first control terminal 46A and the second base portion 421 of the second terminal 42 in the second direction y. In the semiconductor module A4, the first control terminal 46B is connected to the second base portion 421. Therefore, the first control terminal 46B is electrically connected to each of the two second principal-surface electrodes 12. A voltage having the same potential as the voltages applied to each of the two second principal-surface electrodes 12 is applied to the first control terminal 46B. The first control terminal 46B includes copper. Like the first control terminal 46A, the portion of the first control terminal 46B exposed from the sealing resin 8 includes a portion extending along the thickness direction z.

[0193] 41 , the wire 401 is conductively bonded to the first principal surface electrode 11 of the first semiconductor element 10A and the second conductive portion 32B. This allows the second conductive portion 32B to be electrically connected to the first principal surface electrode 11. The wire 401 is covered with the sealing resin 8. The wire 401 is a wire containing, for example, either aluminum (Al) or gold (Au).

[0194] 41 , the wire 402 is conductively bonded to the first principal surface electrode 11 of the second semiconductor element 10B and the second conductive portion 32B. This allows the second conductive portion 32B to be electrically connected to the first principal surface electrode 11. The wire 402 is covered with the sealing resin 8. The wire 402 is a wire containing, for example, either aluminum or gold.

[0195] 41 , the wire 403 is conductively joined to the second conductive portion 32B and the first control terminal 46A. This allows the second conductive portion 32B to be electrically connected to the first control terminal 46A. The wire 403 is covered with the sealing resin 8. The wire 403 is, for example, a wire containing either aluminum or gold. In the semiconductor module A4, the wire 403 is connected to the wire 402.

[0196] According to this embodiment, solid-state diffusion bonding can be performed under better conditions. The semiconductor module A4 further includes a main insulating layer 31 to which the first conductive portion 32A is bonded, and a second main metal layer 33 located on the opposite side of the main insulating layer 31 from the first conductive portion 32A and bonded to the main insulating layer 31. The main insulating layer 31 and the first conductive portion 32A are covered with a sealing resin 8. The second main metal layer 33 is exposed to the outside from the sealing resin 8. This configuration can improve the heat dissipation of the semiconductor module A4 while suppressing a decrease in the dielectric strength voltage of the semiconductor module A4.

[0197] Fifth Embodiment: A semiconductor device B5 according to a fifth embodiment of the present disclosure will be described with reference to Figures 48 to 57. The semiconductor device B5 includes a semiconductor module A5 and a heat dissipation member 70. The joining method and joining form of the semiconductor module A5 and the heat dissipation member 70 may be the same as those of the semiconductor device B1 described above. Furthermore, the joining using the joining layers 39A and 39B in the semiconductor modules A2 and A3 described above may be appropriately adopted. A description of these joining methods will be omitted.

[0198] The semiconductor module A5 includes two first semiconductor elements 10A, a second semiconductor element 10B, four third to fifth semiconductor elements 10C to 10E, a seventh semiconductor element 10G, a main substrate 3, a first terminal 41, a second terminal 42, a third terminal 43, a fourth terminal 44, first control terminals 46A, 46B, and 46C, second control terminals 47A, 47B, and 47C, a plurality of wires 400, and a sealing resin 8. The first semiconductor element 10A, the second semiconductor element 10B, and the third to fifth semiconductor elements 10C to 10E may be referred to as semiconductor elements 10A to 10E, respectively.

[0199] FIG. 48 is a perspective view showing the semiconductor module A5. FIG. 49 is a plan view of the semiconductor module A5. FIG. 50 is a plan view corresponding to FIG. 49, and for ease of understanding, the outline of the sealing resin 8 is shown by an imaginary line (two-dot chain line) through the sealing resin 8. FIG. 51 is a right side view showing the semiconductor module A5. FIG. 52 is a bottom view showing the semiconductor module A5. FIG. 53 is a cross-sectional view taken along line LIII-LIII in FIG. 50. FIG. 54 is a cross-sectional view taken along line LIV-LIV in FIG. 50. FIG. 55 is a cross-sectional view taken along line LV-LV in FIG. 50. FIG. 56 is a circuit diagram showing the circuit configuration of the semiconductor module A5. FIG. 57 is a block diagram for explaining an example of use of the exciter module shown in FIG. 48.

[0200] The shape of the portion of the semiconductor module A5 covered with the sealing resin 8 when viewed in the thickness direction is rectangular. For convenience of explanation, the thickness direction (direction in a plan view) of the semiconductor module A5 is referred to as the thickness direction z, the direction in which the first terminals 41 and the second terminals 42 of the semiconductor module A5 protrude, which is perpendicular to the thickness direction z (the up-down direction in FIG. 49 ), is referred to as the first direction x, and the direction perpendicular to the thickness direction z and the first direction x (the left-right direction in FIG. 49 ) is referred to as the second direction y. Furthermore, one side of the thickness direction z (the right side in FIG. 51 ) is referred to as the first side z1, and the other side (the left side in FIG. 51 ) is referred to as the second side z2. One side of the first direction x (the upper side in FIGS. 49 and 50 ) is referred to as the first side x1, and the other side (the lower side in FIGS. 49 and 50 ) is referred to as the second side x2. One side in the second direction y (the right side in FIGS. 49 and 50) is referred to as the first side y1, and the other side (the left side in FIGS. 49 and 50) is referred to as the second side y2. The shape and dimensions of the semiconductor module A5 are not limited.

[0201] The semiconductor module A5 is a module for exciting the rotor's field winding by passing a DC current through it in a wound-field synchronous motor. As shown in FIG. 57 , the wound-field synchronous motor M includes a stator M1 and a rotor M2. The wound-field synchronous motor M generates a rotating magnetic field by passing three-phase AC current supplied from a three-phase inverter module E through a winding (not shown) of the stator M1. The wound-field synchronous motor M also generates magnetic flux by passing DC current supplied from the semiconductor module A5 through a field winding (not shown) of the rotor M2. The semiconductor module A5 controls the magnetic flux generated in the rotor M2 by controlling the DC current (excitation current) it outputs in response to a drive signal input from a drive circuit (not shown). The three-phase inverter module E and the semiconductor module A5 receive DC power from a battery D, which is converted to an appropriate voltage by a transformer (not shown) and then input.

[0202] The multiple semiconductor elements 10A-10E are elements that perform the electrical functions of the semiconductor module A5. Each of the semiconductor elements 10A-10E is constructed using a semiconductor material primarily composed of, for example, silicon (Si). Note that the semiconductor material is not limited to Si and may be silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or the like. The multiple semiconductor elements 10A-10E are bonded to a first main metal layer 32 (described below) of the main substrate 3 with a conductive bonding material (not shown). The conductive bonding material may be, for example, solder, silver paste, or sintered metal.

[0203] In this embodiment, the first semiconductor element 10A and the second semiconductor element 10B are IGBTs (Insulated Gate Bipolar Transistors). However, the first semiconductor element 10A and the second semiconductor element 10B are not limited to IGBTs and may be field effect transistors such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and MISFETs (Metal-Insulator-Semiconductor FETs).

[0204] The first semiconductor element 10A has an element main surface 101A and an element back surface 102A. The element main surface 101A and the element back surface 102A face in opposite directions in the thickness direction z. The element main surface 101A faces the second side z2. The element back surface 102A faces the first side z1. The element back surface 102A faces the main substrate 3.

[0205] The first semiconductor element 10A also has a second principal surface electrode 12, a first principal surface electrode 11, and a back surface electrode 15. The second principal surface electrode 12 and the first principal surface electrode 11 are disposed on the element principal surface 101A. The second principal surface electrode 12 is larger than the first principal surface electrode 11 in a plan view. The back surface electrode 15 is disposed on the element back surface 102A. The back surface electrode 15 covers substantially the entire element back surface 102A. In the first semiconductor element 10A, which is an IGBT, the second principal surface electrode 12 is an emitter electrode from which current is output, the first principal surface electrode 11 is a gate electrode to which a drive signal is input, and the back surface electrode 15 is a collector electrode to which current is input. The back surface electrode 15 is conductively joined to a portion of the first main metal layer 32 of the main substrate 3 (a first conductive portion 32A described below) via a conductive bonding material.

[0206] The second semiconductor element 10B has an element main surface 101B and an element back surface 102B. The element main surface 101B and the element back surface 102B face in opposite directions in the thickness direction z. The element main surface 101B faces the second side z2. The element back surface 102B faces the first side z1. The element back surface 102B faces the main substrate 3.

[0207] The second semiconductor element 10B also has a second principal surface electrode 12, a first principal surface electrode 11, and a back surface electrode 15. The second principal surface electrode 12 and the first principal surface electrode 11 are disposed on the element principal surface 101B. The second principal surface electrode 12 is larger than the first principal surface electrode 11 in a plan view. The back surface electrode 15 is disposed on the element back surface 102B. The back surface electrode 15 covers substantially the entire element back surface 102B. In the second semiconductor element 10B, which is an IGBT, the second principal surface electrode 12 is an emitter electrode, the first principal surface electrode 11 is a gate electrode, and the back surface electrode 15 is a collector electrode. The back surface electrode 15 is conductively joined to a portion of the first main metal layer 32 of the main substrate 3 (a fourth conductive portion 32D described later) via a conductive bonding material.

[0208] The third semiconductor element 10C to the sixth semiconductor element 10F are diodes. The third semiconductor element 10C and the fourth semiconductor element 10D are connected in series in the reverse direction to the first semiconductor element 10A and the second semiconductor element 10B, respectively. The third semiconductor element 10C and the fourth semiconductor element 10D are freewheel diodes for circulating current due to a flyback voltage generated in the coil of a motor, which is a load, when the first semiconductor element 10A and the second semiconductor element 10B are turned off. The fifth semiconductor element 10E and the sixth semiconductor element 10F are connected in antiparallel to the first semiconductor element 10A and the second semiconductor element 10B, respectively. The fifth semiconductor element 10E and the sixth semiconductor element 10F are freewheel diodes for preventing reverse voltage from being applied to the first semiconductor element 10A and the second semiconductor element 10B when the first semiconductor element 10A and the second semiconductor element 10B are turned off.

[0209] The third semiconductor element 10C has an element main surface 101C and an element back surface 102C. The element main surface 101C and the element back surface 102C face opposite each other in the thickness direction z. The element main surface 101C faces the second side z2. The element back surface 102C faces the first side z1. The element back surface 102C faces the main substrate 3. The third semiconductor element 10C has an anode electrode 13 to which a current is input and a cathode electrode 14 to which a current is output. The anode electrode 13 is disposed on the element main surface 101C. The cathode electrode 14 is disposed on the element back surface 102C. The cathode electrode 14 is conductively bonded to a portion of the first main metal layer 32 of the main substrate 3 (a third conductive portion 32C described later) via a conductive bonding material.

[0210] The fourth semiconductor element 10D has an element main surface 101D and an element back surface 102D. The element main surface 101D and the element back surface 102D face opposite each other in the thickness direction z. The element main surface 101D faces the second side z2. The element back surface 102D faces the first side z1. The element back surface 102D faces the main substrate 3. The fourth semiconductor element 10D has an anode electrode 13 and a cathode electrode 14. The anode electrode 13 is disposed on the element main surface 101D. The cathode electrode 14 is disposed on the element back surface 102D. The cathode electrode 14 is conductively bonded to a portion of the first main metal layer 32 of the main substrate 3 (a first conductive portion 32A described later) via a conductive bonding material.

[0211] The fifth semiconductor element 10E has an element main surface 101E and an element back surface 102FE. The element main surface 101E and the element back surface 102FE face opposite each other in the thickness direction z. The element main surface 101E faces the second side z2. The element back surface 102FE faces the first side z1. The element back surface 102FE faces the main substrate 3. The fifth semiconductor element 10E has an anode electrode 13 and a cathode electrode 14. The anode electrode 13 is disposed on the element main surface 101E. The cathode electrode 14 is disposed on the element back surface 102FE. The cathode electrode 14 is conductively bonded to a portion of the first main metal layer 32 of the main substrate 3 (a first conductive portion 32A described later) via a conductive bonding material.

[0212] The sixth semiconductor element 10F has an element main surface 101F and an element back surface 102F. The element main surface 101F and the element back surface 102F face opposite each other in the thickness direction z. The element main surface 101F faces the second side z2. The element back surface 102F faces the first side z1. The element back surface 102F faces the main substrate 3. The sixth semiconductor element 10F has an anode electrode 13 and a cathode electrode 14. The anode electrode 13 is disposed on the element main surface 101F. The cathode electrode 14 is disposed on the element back surface 102F. The cathode electrode 14 is conductively bonded to a portion of the first main metal layer 32 of the main substrate 3 (a fourth conductive portion 32D described later) via a conductive bonding material.

[0213] The seventh semiconductor element 10G is disposed at the center of the main substrate 3 as viewed in the thickness direction z, and is used as a temperature detection sensor for the semiconductor module A5. One electrode of the seventh semiconductor element 10G is conductively joined to a portion of the first main metal layer 32 of the main substrate 3 (a ninth conductive portion 32J described later) via a conductive bonding material, and the other electrode is conductively joined to a portion of the first main metal layer 32 of the main substrate 3 (a tenth conductive portion 32K described later) via a conductive bonding material. Note that the semiconductor module A5 does not necessarily have to include the seventh semiconductor element 10G.

[0214] The main substrate 3 is a member that supports the multiple semiconductor elements 10A-10F and also forms conductive paths between each of the semiconductor elements 10A-10F and the first terminal 41, second terminal 42, third terminal 43, fourth terminal 44, first control terminals 46A, 46B, 46C, and second control terminals 47A, 47B, 47C. In this embodiment, the main substrate 3 is made of a direct bonded copper (DBC) substrate. The main substrate 3 includes a main insulating layer 31, a first main metal layer 32, and a second main metal layer 33.

[0215] The main insulating layer 31 is, for example, flat and electrically insulating. The constituent material of the main insulating layer 31 is, for example, a ceramic with excellent thermal conductivity, and in this embodiment, is Al2O3 (aluminum oxide). The constituent material of the main insulating layer 31 is not limited and may be other ceramics such as AlN (aluminum nitride) or SiN (silicon nitride). The constituent material of the main insulating layer 31 is also not limited to ceramics and may be Si or a synthetic resin. The constituent material of the main insulating layer 31 may be any material that is insulating and can withstand the heat generated by the semiconductor elements 10A-10F.

[0216] The main insulating layer 31 has an insulating layer main surface 311 and an insulating layer rear surface 312. The insulating layer main surface 311 and the insulating layer rear surface 312 face opposite each other in the thickness direction z. The insulating layer main surface 311 faces the second side z2. The insulating layer rear surface 312 faces the first side z1.

[0217] The first main metal layer 32 is disposed on the insulating layer main surface 311 of the main insulating layer 31. The constituent material of the first main metal layer 32 is, for example, a metal containing Cu. However, the constituent material is not limited thereto. The first main metal layer 32 does not protrude from the main insulating layer 31 as viewed in the thickness direction z, but is contained within the main insulating layer 31 as viewed in the thickness direction z. Furthermore, the first main metal layer 32 is entirely covered with the sealing resin 8 and is not exposed from the sealing resin 8.

[0218] The first main metal layer 32 includes a first conductive portion 32A to a tenth conductive portion 32K. As shown in Fig. 50, the first conductive portion 32A to the tenth conductive portion 32K are arranged spaced apart from one another. Note that in Fig. 50, the first main metal layer 32 is hatched for ease of understanding.

[0219] The first conductive portion 32A is disposed on the insulating layer main surface 311 of the main insulating layer 31 from a first side x1 in the first direction x to a second side y2 in the second direction y, and extends in the first direction x. The first semiconductor element 10A, the fourth semiconductor element 10D, and the fifth semiconductor element 10E are bonded to the first conductive portion 32A, and a portion of the first terminal 41 is also bonded to the first conductive portion 32A. The first conductive portion 32A has a recess recessed from the second side y2 in the second direction y to the first side y1. As shown in FIG. 53 , the first conductive portion 32A is electrically connected to the back surface electrode 15 (collector electrode) of the first semiconductor element 10A, the cathode electrode 14 of the fourth semiconductor element 10D, and the cathode electrode 14 of the fifth semiconductor element 10E. That is, the back surface electrode 15 (collector electrode) of the first semiconductor element 10A, the cathode electrode 14 of the fourth semiconductor element 10D, and the cathode electrode 14 of the fifth semiconductor element 10E are electrically connected via the first conductive portion 32A.

[0220] The second conductive portion 32B is disposed on a first side x1 in the first direction x and a first side y1 in the second direction y on the insulating layer main surface 311 of the main insulating layer 31. A part of the third terminal 43 is joined to the second conductive portion 32B.

[0221] The third conductive portion 32C is arranged on the insulating layer main surface 311 of the main insulating layer 31 at a second side x2 in the first direction x and a second side y2 in the second direction y. The third semiconductor element 10C is joined to the third conductive portion 32C, and a part of the second terminal 42 is joined to the third conductive portion 32C. As shown in FIG. 54 , the third conductive portion 32C is electrically connected to the cathode electrode 14 of the third semiconductor element 10C.

[0222] The fourth conductive portion 32D is disposed on the insulating layer main surface 311 of the main insulating layer 31 on a first side y1 in the second direction y and a second side x2 in the first direction x, and extends in the first direction x. The second semiconductor element 10B and the sixth semiconductor element 10F are bonded to the fourth conductive portion 32D, and a portion of the fourth terminal 44 is also bonded to the fourth conductive portion 32D. The fourth conductive portion 32D has a recess recessed from the first side y1 to the second side y2 in the second direction y. As shown in FIGS. 54 and 55 , the fourth conductive portion 32D is electrically connected to the back electrode 15 (collector electrode) of the second semiconductor element 10B and the cathode electrode 14 of the sixth semiconductor element 10F. In other words, the back electrode 15 (collector electrode) of the second semiconductor element 10B and the cathode electrode 14 of the sixth semiconductor element 10F are electrically connected via the fourth conductive portion 32D.

[0223] The fifth conductive portions 32E, 225b are arranged side by side in the first direction x in the recess of the first conductive portion 32A on the insulating layer main surface 311 of the main insulating layer 31. A first control terminal 46A is joined to the fifth conductive portion 32E. A first control terminal 46B is joined to the sixth conductive portion 32F.

[0224] The seventh conductive portions 32G, 226b are arranged side by side in the first direction x in the recess of the fourth conductive portion 32D on the insulating layer main surface 311 of the main insulating layer 31. A second control terminal 47B is joined to the seventh conductive portion 32G. A second control terminal 47A is joined to the eighth conductive portion 32H.

[0225] The ninth conductive portions 32J and 227b are arranged side by side in the first direction x, surrounded by the first conductive portions 32A, 223, and 224, approximately at the center of the insulating layer main surface 311 of the main insulating layer 31. A first control terminal 46C is joined to the ninth conductive portion 32J. A second control terminal 47C is joined to the tenth conductive portion 32K. Different electrodes of the seventh semiconductor element 10G are joined to the ninth conductive portion 32J and the tenth conductive portion 32K, respectively. In other words, the seventh semiconductor element 10G is arranged across the ninth conductive portion 32J and the tenth conductive portion 32K.

[0226] The arrangement and shape of each of the first to tenth conductive portions 32A to 32K are not limited to those described above.

[0227] The second main metal layer 33 is disposed on the insulating layer back surface 312 of the main insulating layer 31. The constituent material of the second main metal layer 33 is, for example, a metal containing Cu. However, the constituent material is not limited thereto. The second main metal layer 33 does not protrude from the main insulating layer 31 as viewed in the thickness direction z, but is contained within the main insulating layer 31 as viewed in the thickness direction z. As shown in FIGS. 52 to 54 , the surface of the second main metal layer 33 facing the first side z1 in the thickness direction z is exposed from the sealing resin 8.

[0228] The main substrate 3 is not limited to being made of a DBC substrate, and there are no limitations on the method for forming the main substrate 3. The main substrate 3 may be formed by forming a first main metal layer 32 and a second main metal layer 33 on a main insulating layer 31 by, for example, plating.

[0229] The first terminal 41, the second terminal 42, the third terminal 43, the fourth terminal 44, the first control terminals 46A, 46B, 46C, and the second control terminals 47A, 47B, 47C are each bonded to the first main metal layer 32 inside the sealing resin 8. The first terminal 41, the second terminal 42, the third terminal 43, the fourth terminal 44, the first control terminals 46A, 46B, 46C, and the second control terminals 47A, 47B, 47C are each partially exposed from the sealing resin 8. The first terminal 41, the second terminal 42, the third terminal 43, the fourth terminal 44, the first control terminals 46A, 46B, 46C, and the second control terminals 47A, 47B, 47C form conduction paths for input / output currents or input / output signals of the semiconductor module A5.

[0230] The first terminal 41 and the second terminal 42 each protrude from the main insulating layer 31 when viewed in the thickness direction z and protrude from the sealing resin 8 in the first direction x. The first terminal 41 and the second terminal 42 are each a plate-shaped member and are formed from the same lead frame. The lead frame is made of metal, preferably either Cu or Ni, or an alloy thereof or a 42 alloy. The first terminal 41 and the third terminal 43 are terminals for applying a DC voltage to the semiconductor module A5. The second terminal 42 and the fourth terminal 44 are terminals for outputting a DC voltage from the semiconductor module A5.

[0231] The first terminal 41 is one terminal for applying a DC voltage and is a positive terminal. The first terminal 41 is conductively joined to the first conductive portion 32A via a conductive bonding material. The joining method is not limited, and may be laser bonding, ultrasonic bonding, or the like. The first terminal 41 is conductively connected to the back electrode 15 (collector electrode) of the first semiconductor element 10A, the cathode electrode 14 of the fourth semiconductor element 10D, and the cathode electrode 14 of the fifth semiconductor element 10E via the first conductive portion 32A. The first terminal 41 is partially covered by the sealing resin 8, and partially protrudes from the sealing resin 8 toward a first side x1 in the first direction x and extends in the first direction x.

[0232] The third terminal 43 is the other terminal for applying a DC voltage and is a negative terminal. The third terminal 43 is conductively joined to the second conductive portion 32B via a conductive bonding material. The joining method is not limited. The third terminal 43 is conductively connected to the second principal surface electrode 12 (emitter electrode) of the second semiconductor element 10B via the second conductive portion 32B and a wire 400 (wire 408 described later). The third terminal 43 is partially covered by the sealing resin 8 and partially protrudes from the sealing resin 8 toward a first side x1 in the first direction x, extending in the first direction x.

[0233] The second terminal 42 is one terminal for outputting an excitation current and is a positive terminal. The second terminal 42 is conductively joined to the third conductive portion 32C via a conductive bonding material. The joining method is not limited. The second terminal 42 is conductively connected to the cathode electrode 14 of the third semiconductor element 10C via the third conductive portion 32C. The second terminal 42 is partially covered by the sealing resin 8, and partially protrudes from the sealing resin 8 toward the second side x2 in the first direction x, extending in the first direction x.

[0234] The fourth terminal 44 is the other terminal for outputting the excitation current and is a negative terminal. The fourth terminal 44 is conductively joined to the fourth conductive portion 32D via a conductive bonding material. The joining method is not limited. The fourth terminal 44 is conductively connected to the back electrode 15 (collector electrode) of the second semiconductor element 10B and the cathode electrode 14 of the sixth semiconductor element 10F via the fourth conductive portion 32D. The fourth terminal 44 is partially covered by the sealing resin 8 and partially protrudes from the sealing resin 8 toward the second side x2 in the first direction x, extending in the first direction x.

[0235] The first control terminals 46A, 46B, 46C and the second control terminals 47A, 47B, 47C are all press-fit terminals that protrude from the sealing resin 8 toward the second side z2 in the thickness direction z. As shown in FIG. 55 , the first control terminals 46A, 46B, 46C and the second control terminals 47A, 47B, 47C each include a holder 451 and a pin 452. The holder 451 is made of a conductive material and has a cylindrical shape extending in the thickness direction z. The holder 451 is bonded to the first main metal layer 32 via a conductive bonding material. Note that the bonding method is not limited. The pin 452 is made of a conductive material and is a rod-shaped member extending in the thickness direction z. The pin 452 is press-fitted and supported along the inner circumferential surface of the holder 451. The pin 452 is electrically connected to the first main metal layer 32 via the holder 451 and the conductive bonding material.

[0236] The first control terminal 46A is a terminal to which a drive signal for driving the first semiconductor element 10A is input. The first control terminal 46A is electrically connected to the first principal surface electrode 11 (gate electrode) of the first semiconductor element 10A via the fifth conductive portion 32E and a wire 400 (wire 401 described below). A drive signal for controlling the on / off of the first semiconductor element 10A is input to the first control terminal 46A. For example, a drive circuit is connected to the first control terminal 46A. The drive circuit generates a drive signal for controlling the switching operation of the first semiconductor element 10A. The drive signal is input to the first control terminal 46A from the drive circuit.

[0237] The second control terminal 47A is a terminal to which a drive signal for driving the second semiconductor element 10B is input. The second control terminal 47A is electrically connected to the first principal surface electrode 11 (gate electrode) of the second semiconductor element 10B via the eighth conductive portion 32H and the wire 400 (wire 402 described below). A drive signal for controlling the on / off of the second semiconductor element 10B is input to the second control terminal 47A. For example, a drive circuit is connected to the second control terminal 47A. The drive circuit generates a drive signal that controls the switching operation of the second semiconductor element 10B. The drive signal is input to the second control terminal 47A from the drive circuit. The drive signal input to the second control terminal 47A may be the same (or substantially the same) as the drive signal input to the first control terminal 46A, or may be different. For example, drive signals with different phases may be input to the first control terminal 46A and the second control terminal 47A.

[0238] The first control terminal 46B is an emitter sense terminal of the first semiconductor element 10A. The first control terminal 46B is electrically connected to the second principal surface electrode 12 (emitter electrode) of the first semiconductor element 10A via the sixth conductive portion 32F and a wire 400 (a wire 403 described later). A drive circuit, for example, is connected to the first control terminal 46B. The voltage applied to the first control terminal 46B is input to the drive circuit as a feedback signal.

[0239] The second control terminal 47B is an emitter sense terminal of the second semiconductor element 10B. The second control terminal 47B is electrically connected to the second principal surface electrode 12 (emitter electrode) of the second semiconductor element 10B via the seventh conductive portion 32G and a wire 400 (a wire 404 described later). A drive circuit, for example, is connected to the second control terminal 47B. The voltage applied to the second control terminal 47B is input to the drive circuit as a feedback signal.

[0240] The first control terminals 46C and 35b are temperature detection terminals of the semiconductor module A5. The first control terminal 46C is electrically connected to one electrode of the seventh semiconductor element 10G via the ninth conductive part 32J. The second control terminal 47C is electrically connected to the other electrode of the seventh semiconductor element 10G via the tenth conductive part 32K. A drive circuit, for example, is connected to the first control terminals 46C and 35b. The drive circuit detects overheating abnormalities based on the potential difference between the first control terminal 46C and the second control terminal 47C, i.e., the potential difference between the two electrodes of the seventh semiconductor element 10G, which corresponds to the ambient temperature of the seventh semiconductor element 10G. When the detected potential difference exceeds the potential difference corresponding to the threshold temperature, the drive circuit stops outputting a drive signal, thereby stopping operation of the semiconductor module A5.

[0241] The first control terminal 46A and the first control terminal 46B are arranged side by side in the first direction x. The second control terminal 47A and the second control terminal 47B are arranged side by side in the first direction x. The first control terminals 46C and 46b are arranged side by side in the first direction x. The arrangement of the first control terminals 46A, 46B, and 46C and the second control terminals 47A, 47B, and 47C is not limited.

[0242] Each of the plurality of wires 400 provides electrical continuity between two spaced apart portions. Each wire 400 is a so-called bonding wire. The constituent material of each wire 400 is, for example, Al, Au, Cu, or an alloy containing any of these. The plurality of wires 400 includes wires 401 to 410.

[0243] One end of the wire 401 is joined to the first principal surface electrode 11 (gate electrode) of the first semiconductor element 10A, and the other end is joined to the fifth conductive portion 32E. The wire 401 provides electrical continuity between the first principal surface electrode 11 and the fifth conductive portion 32E. The wire 402 has one end joined to the first principal surface electrode 11 (gate electrode) of the second semiconductor element 10B, and the other end joined to the eighth conductive portion 32H. The wire 402 provides electrical continuity between the first principal surface electrode 11 and the eighth conductive portion 32H.

[0244] One end of the wire 403 is joined to the second principal surface electrode 12 (emitter electrode) of the first semiconductor element 10A, and the other end is joined to the sixth conductive portion 32F. The wire 403 provides electrical continuity between the second principal surface electrode 12 and the sixth conductive portion 32F. The wire 404 has one end joined to the second principal surface electrode 12 (emitter electrode) of the second semiconductor element 10B, and the other end joined to the seventh conductive portion 32G. The wire 404 provides electrical continuity between the second principal surface electrode 12 and the seventh conductive portion 32G.

[0245] One end of the wire 405 is joined to the second principal surface electrode 12 (emitter electrode) of the first semiconductor element 10A, and the other end is joined to the anode electrode 13 of the fifth semiconductor element 10E. The wire 405 provides electrical continuity between the second principal surface electrode 12 and the anode electrode 13. The wire 406 has one end joined to the second principal surface electrode 12 (emitter electrode) of the second semiconductor element 10B, and the other end joined to the anode electrode 13 of the sixth semiconductor element 10F. The wire 406 provides electrical continuity between the second principal surface electrode 12 and the anode electrode 13.

[0246] One end of the wire 407 is joined to the second principal surface electrode 12 (emitter electrode) of the first semiconductor element 10A, and the other end is joined to the third conductive portion 32C. The wire 407 electrically connects the second principal surface electrode 12 and the third conductive portion 32C.

[0247] One end of the wire 408 is joined to the second principal surface electrode 12 (emitter electrode) of the second semiconductor element 10B, and the other end is joined to the second conductive portion 32B. The wire 408 electrically connects the second principal surface electrode 12 and the second conductive portion 32B.

[0248] One end of the wire 409 is joined to the second principal surface electrode 12 (emitter electrode) of the second semiconductor element 10B, and the other end is joined to the anode electrode 13 of the third semiconductor element 10C. The wire 409 electrically connects the second principal surface electrode 12 and the anode electrode 13.

[0249] One end of the wire 410 is joined to the anode electrode 13 of the fourth semiconductor element 10D, and the other end is joined to the fourth conductive portion 32D. The wire 410 electrically connects the anode electrode 13 and the fourth conductive portion 32D.

[0250] The sealing resin 8 is an electrically insulating semiconductor sealing material. The sealing resin 8 covers the entire semiconductor elements 10A to 10F, the main insulating layer 31, the first main metal layer 32, and the plurality of wires 400, as well as a portion of each of the first terminal 41, the second terminal 42, the third terminal 43, the fourth terminal 44, the first control terminals 46A, 46B, and 46C, and the second control terminals 47A, 47B, and 47C. The material of the sealing resin 8 is, for example, epoxy resin. However, there is no limitation on the material of the sealing resin 8. The sealing resin 8 is formed, for example, by transfer molding using a mold. However, there is no limitation on the method of forming the sealing resin 8. The sealing resin 8 has a resin main surface 81 and a resin back surface 82.

[0251] The resin main surface 81 and the resin back surface 82 face opposite each other in the thickness direction z. The resin main surface 81 faces the second side z2, and the resin back surface 82 faces the first side z1. The second main metal layer 33 is exposed from the resin back surface 82, and the resin back surface 82 and the surface of the second main metal layer 33 facing the first side z1 in the thickness direction z are flush with each other.

[0252] The circuit configuration of the semiconductor module A5 is as shown in the circuit diagram of FIG.

[0253] The second principal surface electrode 12 (emitter electrode) of the first semiconductor element 10A and the cathode electrode 14 of the third semiconductor element 10C are electrically connected via a wire 407 and a second conductive portion 32B. The back surface electrode 15 (collector electrode) of the second semiconductor element 10B and the anode electrode 13 of the fourth semiconductor element 10D are electrically connected via a fourth conductive portion 32D and a wire 410. The back surface electrode 15 (collector electrode) of the first semiconductor element 10A and the cathode electrode 14 of the fourth semiconductor element 10D are electrically connected via a first conductive portion 32A. The anode electrode 13 of the third semiconductor element 10C and the second principal surface electrode 12 (emitter electrode) of the second semiconductor element 10B are electrically connected via a wire 409. The fifth semiconductor element 10E is connected in anti-parallel to the first semiconductor element 10A via a wire 405 and a first conductive portion 32A. The sixth semiconductor element 10F is connected in anti-parallel to the second semiconductor element 10B by the wire 406 and the fourth conductive portion 32D.

[0254] A first terminal 41 is bonded to a first conductive portion 32A that electrically connects the back surface electrode 15 (collector electrode) of the first semiconductor element 10A to the cathode electrode 14 of the fourth semiconductor element 10D. The second main surface electrode 12 (emitter electrode) of the second semiconductor element 10B, which is electrically connected to the anode electrode 13 of the third semiconductor element 10C, is electrically connected to the second conductive portion 32B via a wire 408, and a third terminal 43 is bonded to the second conductive portion 32B. A second terminal 42 is bonded to a third conductive portion 32C that electrically connects the second main surface electrode 12 (emitter electrode) of the first semiconductor element 10A to the cathode electrode 14 of the third semiconductor element 10C. A fourth terminal 44 is bonded to a fourth conductive portion 32D that electrically connects the back surface electrode 15 (collector electrode) of the second semiconductor element 10B to the anode electrode 13 of the fourth semiconductor element 10D.

[0255] The first principal surface electrode 11 (gate electrode) of the first semiconductor element 10A is conductively connected to the first control terminal 46A via a wire 401 and a fifth conductive portion 32E. The first principal surface electrode 11 (gate electrode) of the second semiconductor element 10B is conductively connected to the second control terminal 47A via a wire 402 and an eighth conductive portion 32H. The second principal surface electrode 12 (emitter electrode) of the first semiconductor element 10A is conductively connected to the first control terminal 46B via a wire 403 and a sixth conductive portion 32F. The second principal surface electrode 12 (emitter electrode) of the second semiconductor element 10B is conductively connected to the second control terminal 47B via a wire 404 and a seventh conductive portion 32G.

[0256] In the semiconductor module A5, an external DC voltage is applied between the first terminal 41 and the third terminal 43, and a voltage is output between the second terminal 42 and the fourth terminal 44. The drive circuit receives a feedback signal from the first control terminals 46B and 34b, and outputs a drive signal to the first control terminals 46A and 33b. The semiconductor module A5 outputs a DC current controlled in accordance with the drive signal input from the drive circuit as an excitation current to the field winding of the rotor M2 of the wound magnetic field type synchronous motor M, which is connected between the second terminal 42 and the fourth terminal 44.

[0257] One electrode of the seventh semiconductor element 10G is conductively connected to the first control terminal 46C via the ninth conductive portion 32J. The other electrode of the seventh semiconductor element 10G is conductively connected to the second control terminal 47C via the tenth conductive portion 32K. The drive circuit detects an overheating abnormality based on the potential difference between the first control terminal 46C and the second control terminal 47C.

[0258] Next, the effects of the semiconductor module A5 will be described.

[0259] According to this embodiment, solid-state diffusion bonding can be performed in a better state. The semiconductor module A5 constitutes an exciter circuit connected as shown in the circuit diagram of Fig. 56. The semiconductor module A5 is a modularized exciter, and is smaller than conventional exciters.

[0260] In this embodiment, the first terminal 41, the second terminal 42, the third terminal 43, and the fourth terminal 44 are plate-shaped members made of lead frames, and therefore, the first terminal 41, the second terminal 42, the third terminal 43, and the fourth terminal 44 can carry a larger current than when they are made of press-fit terminals whose cross-sectional area is smaller than that of the lead frames.

[0261] Furthermore, in this embodiment, the surface of the second main metal layer 33 of the main substrate 3 facing the first side z1 in the thickness direction z is exposed from the sealing resin 8. This allows the semiconductor module A5 to improve its heat dissipation efficiency. Furthermore, the semiconductor module A5 can further improve its heat dissipation effect by attaching a heat dissipation member or cooler to the exposed surface of the second main metal layer 33.

[0262] In the present embodiment, the case where all of the wires 400 are bonding wires has been described, but this is not limiting. Instead of any of the wires 400, a connecting member other than a bonding wire (for example, a metal plate member or a metal ribbon) may be used.

[0263] In addition, in the present embodiment, the first terminal 41, the second terminal 42, the third terminal 43, and the fourth terminal 44 are all bonded to the first main metal layer 32, but this is not limiting. Any of the first terminal 41, the second terminal 42, the third terminal 43, and the fourth terminal 44 may be bonded to the main insulating layer 31 at a distance from the first main metal layer 32. In this case, the terminal is electrically connected to the first main metal layer 32 by a connecting member such as a bonding wire.

[0264] In addition, in the present embodiment, the first control terminals 46A, 46B, 46C and the second control terminals 47A, 47B, 47C are all press-fit terminals, but this is not limiting. Any of the first control terminals 46A, 46B, 46C and the second control terminals 47A, 47B, 47C may be formed from the same lead frame as the first terminal 41, the second terminal 42, the third terminal 43, and the fourth terminal 44.

[0265] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiments. The specific configurations of the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure can be freely modified in various ways. The present disclosure includes the embodiments described in the following appendices.

[0266] Supplementary Note 1. A semiconductor device (B1) comprising a first semiconductor element (10A), including a first object, a second object, and a bonding layer (39) interposed between the first object and the second object, wherein the bonding layer (39) includes a first surface layer (391) bonded to the first object and a second surface layer (392) bonded to the second object, and a base layer (390) located between the first surface layer (391) and the second surface layer (392), wherein the first surface layer (391) is bonded to the first object by solid-state diffusion bonding and includes a plurality of first crystal grains (3910) having a median diameter of 0.001 μm or more and 1.0 μm or less. Supplementary Note 2. The semiconductor device (B1) according to Supplementary Note 1, wherein the material of the base layer (390) is softer than the material of the first surface layer (391). Supplementary Note 3. The semiconductor device (B1) according to Appendix 2, wherein the first surface layer (391) contains Ag. Appendix 4. The semiconductor device (B1) according to Appendix 2 or 3, wherein the base layer (390) contains Al. Appendix 5. The semiconductor device (B1) according to any one of Appendixes 1 to 4, wherein the second surface layer (392) is bonded to the second object by solid-state diffusion bonding and includes a plurality of second crystal grains (3920) having a median diameter of 0.001 μm or more and 1.0 μm or less. Appendix 5-1. The semiconductor device (B1) according to Appendix 5, wherein the second surface layer (392) contains Ag. Appendix 6. The semiconductor device (B1) according to Appendix 5, comprising: a semiconductor module (A1) having the first semiconductor element (10A), a main substrate (3) on which the first semiconductor element (10A) is mounted, and a sealing resin (8) covering the first semiconductor element (10A) and a portion of the main substrate (3), and a heat dissipation member (70) bonded to the semiconductor module (A1), wherein the heat dissipation member (70) is the first object, and the main substrate (3) is the second object. Appendix 7. The semiconductor device (B1) according to Appendix 6, wherein the heat dissipation member (70) has a metal layer (709) bonded to the first surface layer (391) by solid-state diffusion bonding, and the metal layer (709) includes a plurality of crystal grains (7090) having a median diameter of 0.001 μm or more and 1.0 μm or less.Appendix 8. The semiconductor device (B2) according to Appendix 7, wherein the main substrate (3) has a metal layer (309) bonded to the second surface layer (392) by solid-state diffusion bonding, and the metal layer (309) includes a plurality of crystal grains (3090) having a median diameter of 0.001 μm or more and 1.0 μm or less. Appendix 9. The semiconductor device (B2) according to Appendix 5, comprising: a semiconductor module (A1) having the first semiconductor element (10A), a main substrate (3) on which the first semiconductor element (10A) is mounted, and a sealing resin (8) covering the first semiconductor element (10A) and a portion of the main substrate (3), wherein the main substrate (3) is the first object, and the first semiconductor element (10A) is the second object. Appendix 9-1. The semiconductor device (B2) according to Appendix 9, wherein the main substrate (30) has a metal layer (309A) bonded to the first surface layer (391) by solid-state diffusion bonding, the metal layer (309A) including a plurality of crystal grains (3090) having a median diameter of 0.001 μm or more and 1.0 μm or less, and the first semiconductor element (10A) has a metal layer (159) bonded to the second surface layer (392) by solid-state diffusion bonding, the metal layer (159) including a plurality of crystal grains (1590) having a median diameter of 0.001 μm or more and 1.0 μm or less. Appendix 9-2. The semiconductor device (B1) according to any one of Supplementary Notes 6 to 9, wherein the main substrate (3) includes a main insulating layer (31) and a first main metal layer (32) and a second main metal layer (33) positioned on either side of the main insulating layer (31), the first main metal layer (32) includes a first conductive portion (32A) and a second conductive portion (32B) spaced apart from each other, the first semiconductor element (10A) is mounted on the first conductive portion (32A), and the semiconductor module (A1) includes a second semiconductor element (10B) mounted on the second conductive portion (32B). Supplementary Note 9-3. The semiconductor device (B1) according to Supplementary Note 9-2, wherein the semiconductor device (B1) includes a first conductive member (5) forming a conductive path between the second terminal (42) and the second semiconductor element (10B). Supplementary Note 9-4. The semiconductor device (B1) according to appendix 9-3, further comprising a second conductive member (6) that forms a conductive path between the first terminal (41) and the second semiconductor element (10B).Supplementary Note 10. The semiconductor device (B3) according to any one of Supplementary Notes 1 to 4, comprising a semiconductor module (A3) having the first semiconductor element (10A), a main substrate (3) on which the first semiconductor element (10A) is mounted, a first conductive member (5) conductively joined to the first semiconductor element (10A), and a sealing resin (8) covering the first semiconductor element (10A) and a portion of the main substrate (3), wherein the first semiconductor element (10A) is the first object, and the first conductive member (5) is the second object. Supplementary Note 11. The semiconductor device (B4) according to any one of Supplementary Notes 6 to 10, wherein the semiconductor module (A4) comprises: a first terminal (41), a second terminal (42), and a third terminal (43) protruding from the sealing resin (8) in a direction intersecting the thickness direction (z) of the main substrate (3); and a plurality of control terminals (45) protruding from the sealing resin (8) in the thickness direction (z). Supplementary Note 11-1. The semiconductor device (B4) according to Supplementary Note 11, wherein the semiconductor module (A4) comprises a first sub-substrate (48A) and a second sub-substrate (48B) mounted on the first main metal layer (32). Supplementary Note 11-2. The semiconductor device (B4) according to Supplementary Note 12-1, wherein the plurality of control terminals (45) are mounted on the first sub-substrate (48A) and the second sub-substrate (48B). Supplementary Note 12. The semiconductor device (B4) according to any one of Supplementary Notes 6 to 10, wherein the semiconductor module (A4) comprises: a first terminal (41) and a second terminal (42) protruding from the sealing resin (8) in a direction intersecting the thickness direction (z) of the main substrate (3); and a plurality of control terminals (46A, 46B). Supplementary Note 12-1. The semiconductor device (B4) according to Supplementary Note 12, wherein the semiconductor module (A1) comprises a second semiconductor element (10B), and the first terminal (41) is electrically connected to the first semiconductor element (10A) and the second semiconductor element (10B). Supplementary Note 12-2. The semiconductor device (B4) according to Supplementary Note 12-1, wherein the second terminal (42) is electrically connected to the first semiconductor element (10A) and the second semiconductor element (10B). Supplementary Note 12-3. The semiconductor device (B4) according to Appendix 12-2, wherein the first control terminal (46B) is integrally configured with the second terminal (42).Supplementary Note 13. The semiconductor device (B5) according to any one of Supplementary Notes 6 to 10, wherein the semiconductor module (A5) is configured as an exciter that passes an excitation current through a field winding of a rotor of a wound-field-type synchronous motor. Supplementary Note 13-1. The semiconductor device (B5) according to Supplementary Note 13, wherein the semiconductor module (A5) includes a third semiconductor element (10C), a fourth semiconductor element (10D), a fifth semiconductor element (10E), and a sixth semiconductor element (10F), which are diodes. Supplementary Note 14. A method for manufacturing a semiconductor device (B1), comprising: a step of preparing a first object, a second object, and a bonding layer (39); and a step of bonding the first object and the bonding layer (39) by solid-state diffusion bonding, wherein the bonding layer (39) includes a first surface layer (391) and a second surface layer (392), and a base layer (390) located between the first surface layer (391) and the second surface layer (392), and the first surface layer (391) includes a plurality of first crystal grains (3910) having a median diameter of 0.001 μm or more and 1.0 μm or less, and in the step of bonding the first object and the bonding layer (39) by solid-state diffusion bonding, the first surface layer (391) and the first object are bonded by solid-state diffusion bonding. Appendix 15. A method for manufacturing a semiconductor device (B1) according to Appendix 14, comprising a step of bonding the second object and the bonding layer (39) by solid-state diffusion bonding, wherein the second surface layer (392) includes a plurality of second crystal grains (3920) having a median diameter of 0.001 μm or more and 1.0 μm or less, and in the step of bonding the second object and the bonding layer (39) by solid-state diffusion bonding, the second surface layer (392) and the second object are bonded by solid-state diffusion bonding.

[0267] A1, A12, A15, A2, A3, A31, A4, A5: semiconductor modules, B1, B12, B13, B14, B15, B2, B3, B31, B4, B5: semiconductor device C1: vehicle, 3: main board, 5, 5A: first conductive member, 6: second conductive member, 8: sealing resin, 10A: first semiconductor element, 10B: second semiconductor element, 10C: third semiconductor element, 10D: fourth semiconductor element, 10E: fifth semiconductor element, 10F: sixth semiconductor element, 10G: seventh semiconductor element, 11: first main surface electrode, 12: second main surface electrode, 13: anode electrode, 14: cathode electrode, 1 5: rear surface electrode, 17: thermistor, 19A: first conductive bonding material, 19B: second conductive bonding material, 30: main substrate, 31: main insulating layer, 31b: first terminal, 32: first main metal layer, 32A: first conductive portion, 32B: second conductive portion, 32C: third conductive portion, 32D: fourth conductive portion, 32E: fifth conductive portion, 32F: sixth conductive portion, 32G: seventh conductive portion, 32H: eighth conductive portion, 32J: ninth conductive portion, 32K: tenth conductive portion, 32b: second terminal, 33: second main metal layer, 33b: first control terminal, 34b: first control terminal , 35b: first control terminal, 39, 39A, 39B: bonding layer, 41: first terminal, 42: second terminal, 43: third terminal, 44: fourth terminal, 45: control terminal, 46A: first control terminal, 46B: first control terminal, 46C: first control terminal, 46E: first control terminal, 47A: second control terminal, 47B: second control terminal, 47C: second control terminal, 47D: second control terminal, 48A: first sub-substrate, 48B: second sub-substrate, 49: conductive bonding material, 51: main portion, 52: first bonding portion, 53: second bonding portion, 59: conductive bonding material, 61: third bonding portion, 64: first path portion, 65: second path portion, 66: third path portion, 67: fourth path portion, 69: conductive bonding material, 70: heat dissipation member, 71: base portion, 72: heat dissipation portion, 73: protrusion, 81: resin main surface, 82: resin back surface, 91: on-board charger, 92: storage battery, 93: drive system, 101, 101A, 101B, 101C, 101D, 101E, 101F: element main surface, 102, 102A, 102B, 102C, 102D, 102E, 102F: element back surface, 131: third principal surface electrode, 129,159: metal layer, 223: first conductive portion, 224: first conductive portion, 225b: fifth conductive portion, 226b: seventh conductive portion, 227b: ninth conductive portion, 301A: first main surface, 301B: second main surface, 302: back surface, 309: metal layer, 311: insulating layer main surface, 312: insulating layer back surface, 390: base layer, 391: first surface layer, 392: second surface layer, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410: wire, 416: first base portion, 417: first bonding portion, 421: second base portion, 422: second bonding portion, 423: third bonding portion, 451: holder, 452: pin, 481: sub-insulating layer, 482: first sub-metal layer, 482A, 482B, 482C, 482D, 482E, 482F: region, 483: second sub-metal layer, 514: first opening, 602: first step portion, 603: second step portion, 611: flat portion, 612: first inclined portion, 641: first strip portion, 643: first extension portion, 651: second strip portion, 653: second extension portion, 700: main surface, 709: metal layer, 721: flow path, 931: inverter, 932: driving source, 1290, 1590, 7090: crystal grains, 3 910: first crystal grain, 3911: first intermediate layer, 3912: third intermediate layer, 3920: second crystal grain, 3921: second intermediate layer, 3922: fourth intermediate layer, 4521: thick diameter portion, 4821A, 4821B, 4821C, 4821D: connection portion, 4822A, 4822B, 4822C, 4822D: terminal portion, 4829: surface metal layer, Ct: grinding tool, D: battery, E: three-phase inverter module, M: wound magnetic field type synchronous motor, M1: stator, M2: rotor, Us: ultrasonic joining tool, t2a, t2b, t30, t31, t32: thickness, x: first direction, y: second direction, z: thickness direction,

Claims

1. A semiconductor device comprising a first semiconductor element, a first object, a second object, and a bonding layer interposed between the first object and the second object, wherein the bonding layer includes a first surface layer bonded to the first object and a second surface layer bonded to the second object, and a base layer located between the first surface layer and the second surface layer, wherein the first surface layer is bonded to the first object by solid-state diffusion bonding, and includes a plurality of first crystal grains having a median diameter of 0.001 μm or more and 1.0 μm or less.

2. The semiconductor device according to claim 1, wherein the material of said base layer is softer than the material of said first surface layer.

3. The semiconductor device according to claim 2, wherein the first surface layer contains Ag.

4. The semiconductor device according to claim 2 or 3, wherein the base layer contains Al.

5. A semiconductor device according to any one of claims 1 to 4, wherein the second surface layer is bonded to the second object by solid-state diffusion bonding and includes a plurality of second crystal grains having a median diameter of 0.001 μm or more and 1.0 μm or less.

6. A semiconductor device according to claim 5, comprising: a semiconductor module having the first semiconductor element, a main substrate on which the first semiconductor element is mounted, and a sealing resin covering the first semiconductor element and a portion of the main substrate; and a heat dissipation member bonded to the semiconductor module, wherein the heat dissipation member is the first object and the main substrate is the second object.

7. The semiconductor device according to claim 6, wherein the heat dissipation member has a metal layer bonded to the first surface layer by solid-state diffusion bonding, and the metal layer includes a plurality of crystal grains having a median diameter of 0.001 μm or more and 1.0 μm or less.

8. The semiconductor device according to claim 7, wherein the main substrate has a metal layer bonded to the second surface layer by solid-state diffusion bonding, and the metal layer includes a plurality of crystal grains having a median diameter of 0.001 μm or more and 1.0 μm or less.

9. The semiconductor device according to claim 5, comprising: a semiconductor module having: the first semiconductor element; a main substrate on which the first semiconductor element is mounted; and a sealing resin covering the first semiconductor element and a portion of the main substrate, wherein the main substrate is the first object, and the first semiconductor element is the second object.

10. A semiconductor device according to any one of claims 1 to 4, comprising a semiconductor module having: the first semiconductor element; a main substrate on which the first semiconductor element is mounted; a first conductive member conductively joined to the first semiconductor element; and a sealing resin covering the first semiconductor element and a portion of the main substrate, wherein the first semiconductor element is the first object, and the first conductive member is the second object.

11. A semiconductor device according to any one of claims 6 to 10, wherein the semiconductor module comprises: a first terminal, a second terminal, and a third terminal protruding from the sealing resin in a direction intersecting the thickness direction of the main substrate; and a plurality of control terminals protruding from the sealing resin in the thickness direction.

12. The semiconductor device according to claim 6, wherein the semiconductor module comprises: a first terminal and a second terminal protruding from the sealing resin in a direction intersecting the thickness direction of the main substrate; and a plurality of control terminals.

13. The semiconductor device according to any one of claims 6 to 10, wherein the semiconductor module is configured as an exciter that passes an excitation current through a field winding of a rotor of a wound magnetic field type synchronous motor.

14. A method for manufacturing a semiconductor device, comprising: a step of preparing a first object, a second object, and a bonding layer; and a step of bonding the first object and the bonding layer by solid-state diffusion bonding, wherein the bonding layer includes a first surface layer and a second surface layer, and a base layer located between the first surface layer and the second surface layer, and the first surface layer includes a plurality of first crystal grains having a median diameter of 0.001 μm or more and 1.0 μm or less, and in the step of bonding the first object and the bonding layer by solid-state diffusion bonding, the first surface layer and the first object are bonded by solid-state diffusion bonding.

15. A method for manufacturing a semiconductor device as described in claim 14, further comprising a step of bonding the second object and the bonding layer by solid-state diffusion bonding, wherein the second surface layer includes a plurality of second crystal grains having a median diameter of 0.001 μm or more and 1.0 μm or less, and wherein in the step of bonding the second object and the bonding layer by solid-state diffusion bonding, the second surface layer and the second object are bonded by solid-state diffusion bonding.

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