Semiconductor device

Abstract

A semiconductor substrate (12) has a configuration including: a plurality of second-conductivity-type deep layers (36) disposed apart from a body layer (34), arranged at predetermined intervals along the longitudinal direction of gate trenches (14), connected to second-conductivity-type trench underlayers (35), and connected to contact layers (32), the plurality of second-conductivity-type deep layers (36) extending in the surface direction of the semiconductor substrate (12), which is an intersecting direction intersecting the longitudinal direction; and first-conductivity-type deep layers (37) disposed between second-conductivity-type deep layers adjacent to each other in the longitudinal direction and having portions extending in the intersecting direction. The first-conductivity-type deep layers (37) have portions that are disposed between the second-conductivity-type deep layers (36) and the body layer (34), are located closer to the opposite surface than the body layer (34), and are in contact with gate insulating films (16) on side surfaces of the gate trenches (14). The distance d6 between the body layer (34) and the second-conductivity-type deep layers 36 is set to be greater than or equal to 0.14 μm.

Description

Semiconductor Devices CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Patent Application No. 2024-147660, filed on August 29, 2024, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device.

[0003] Conventionally, semiconductor devices have been proposed in which a MOSFET (short for metal oxide semiconductor field effect transistor) having a trench gate structure is formed on a semiconductor substrate made of silicon carbide or the like (see, for example, Patent Document 1). Specifically, in this semiconductor device, the trench gate structure is formed so as to penetrate a p-type body layer formed in a surface layer portion of the semiconductor substrate, with one direction in the surface direction of the semiconductor substrate as the longitudinal direction. Note that the trench gate structure is configured such that a gate insulating film is disposed in a gate trench and a gate electrode is disposed on the gate insulating film.

[0004] The semiconductor substrate has a p-type trench lower layer formed therein, extending in the longitudinal direction of the gate trench so as to face the lower surface of the gate trench. The semiconductor substrate also has a plurality of p-type deep layers formed therein, extending in one direction in the surface direction of the semiconductor substrate, a direction intersecting the longitudinal direction of the gate trench, and connected to the body layer. The p-type deep layers have a higher impurity concentration than the body layer, are spaced apart from each other in the longitudinal direction of the gate trench, and are formed so as to intersect with and connect to the p-type trench lower layer. This electrically connects the p-type trench lower layer to the body layer via the p-type deep layer. The semiconductor substrate also has an n-type deep layer disposed between adjacent p-type deep layers in the longitudinal direction.

[0005] In such a semiconductor device, when a potential equal to or greater than the gate threshold is applied to the gate electrode, a channel is formed in the body layer adjacent to the trench gate structure, and current flows through the channel, thereby turning the device into an ON state. When the potential applied to the gate electrode is reduced from a value equal to or greater than the gate threshold to a value less than the gate threshold, the channel disappears, and no current flows, turning the device into an OFF state. Furthermore, in such a semiconductor device, a depletion layer formed in the lower layer of the p-type trench and between the p-type deep layer and the n-type deep layer alleviates electric field concentration near the bottom surface of the gate trench, thereby improving breakdown voltage.

[0006] Japanese Patent Application Laid-Open No. 2022-140217

[0007] However, in the semiconductor device described above, the saturation current is large, which may make the device more susceptible to breakdown in the event of a short circuit or the like.

[0008] An object of the present disclosure is to provide a semiconductor device that can reduce the saturation current.

[0009] According to one aspect of the present disclosure, a semiconductor device includes a semiconductor substrate having one surface and another surface opposite to the one surface, with a gate trench formed on the one surface side, a gate insulating film covering an inner surface of the gate trench, and a gate electrode disposed in the gate trench and insulated from the semiconductor substrate by the gate insulating film, wherein the semiconductor substrate includes: a first impurity layer of a first conductivity type formed on the one surface side of the semiconductor substrate and in contact with the gate insulating film on a side surface of the gate trench; a body layer of a second conductivity type in contact with the gate insulating film on a side surface of the gate trench located on the other surface side of the first impurity layer; a contact layer of the second conductivity type disposed on the body layer on the opposite side to the gate trench with the first impurity layer interposed therebetween and having a portion with a higher impurity concentration than the body layer; a second conductivity type trench lower layer disposed so as to face a lower part of the gate trench and extending along the longitudinal direction of the gate trench; a first conductivity type deep layer disposed between adjacent deep layers of the second conductivity type in the longitudinal direction and having a portion extending in the intersecting direction; a first conductivity type drift layer disposed on the other side of the first conductivity type deep layer; a second impurity layer of the first conductivity type or the second conductivity type disposed on the other side of the drift layer; a first electrode electrically connected to the body layer and the first impurity layer; and a second electrode electrically connected to the second impurity layer. The first conductivity type deep layer is disposed between the deep layer of the second conductivity type and the body layer, and has a portion located on the other side of the body layer that contacts the gate insulating film on the side of the gate trench. The distance between the body layer and the deep layer of the second conductivity type is 0.14 μm or more.

[0010] According to this, the second-conductivity-type deep layer is formed away from the body layer, and the gate trench has a portion between the body layer and the second-conductivity-type deep layer that contacts the n-type deep layer. Therefore, compared to when the second-conductivity-type deep layer is formed so as to contact the body layer, the current path is wider in the on-state, thereby reducing the on-state voltage. Furthermore, the distance between the body layer and the second-conductivity-type deep layer is set to 0.14 μm or more. This allows the saturation current to be reduced while reducing the on-state voltage.

[0011] 1 is a perspective cross-sectional view of a semiconductor device according to a first embodiment; FIG. 2 is a perspective cross-sectional view of a semiconductor device of a portion different from FIG. 1; FIG. 3 is a perspective cross-sectional view of a semiconductor device of a portion different from FIG. 1 and FIG. 2; FIG. 4 is a perspective cross-sectional view of a semiconductor device according to a comparative example; FIG. 5 is a diagram showing saturation current, DS breakdown voltage, and on-voltage in the semiconductor device according to the first embodiment and the semiconductor device according to the comparative example; FIG. 6 is a perspective cross-sectional view of a semiconductor device according to a second embodiment; FIG. 7 is a diagram showing saturation current, DS breakdown voltage, and on-voltage in the semiconductor device according to the second embodiment and the semiconductor device according to the comparative example; FIG. 8 is a perspective cross-sectional view of a semiconductor device according to a modified example of the second embodiment; FIG. 9 is a cross-sectional view of a semiconductor device according to a third embodiment; FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth embodiment; FIG. 11 is a perspective cross-sectional view of a semiconductor device according to a fifth embodiment; FIG. 12 is a diagram showing saturation current, DS breakdown voltage, and on-voltage in the semiconductor device according to the fifth embodiment; and FIG. 13 is a diagram showing the relationship between the distance between the body layer and the p-type deep layer and the on-voltage in the semiconductor device according to the fifth embodiment.

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0013] First Embodiment A semiconductor device 10 according to a first embodiment will be described with reference to the drawings. In this embodiment, a semiconductor device 10 including a MOSFET will be described.

[0014] As shown in FIGS. 1 to 3 , the semiconductor device 10 includes a semiconductor substrate 12 having a first surface 12 a and a second surface 12 b. In the following description, the depth (i.e., thickness) direction of the semiconductor substrate 12 is referred to as the z-axis direction, a direction parallel to the first surface 12 a of the semiconductor substrate 12 (i.e., a direction perpendicular to the z-axis direction) is referred to as the x-axis direction, and a direction perpendicular to the x-axis and z-axis directions is referred to as the y-axis direction. In the following description, the length in the z-axis direction from the first surface 12 a to the second surface 12 b of the semiconductor substrate 12 is also referred to simply as the depth. FIG. 1 shows a perspective cross-sectional view of an n-type deep layer 37 (described later) in an x-z ​​cross section, FIG. 2 shows a perspective cross-sectional view of a first p-type deep layer 36 a (described later) in an x-z ​​cross section, and FIG. 3 shows a perspective cross-sectional view of a second p-type deep layer 36 b (described later) in an x-z ​​cross section. In the following description, the portion of each part located on the second surface 12 b of the semiconductor substrate 12 is also referred to as the bottom surface or lower part.

[0015] In this embodiment, the semiconductor substrate 12 is made of silicon carbide, but may be made of other semiconductors such as gallium nitride or gallium oxide.

[0016] A plurality of gate trenches 14 are formed in the semiconductor substrate 12 from the one surface 12a side. The gate trenches 14 are formed with their longitudinal direction in the y-axis direction and are arranged at equal intervals in the x-axis direction to form a stripe pattern. In the gate trenches 14 of this embodiment, opposing side surfaces are substantially parallel to the z-axis direction, and the bottom portions have a curvature (i.e., roundness). However, the gate trenches 14 may also be formed such that their bottom portions are substantially parallel to the other surface 12b of the semiconductor substrate 12, and the side surfaces and the bottom portions form a substantially right angle. Furthermore, the gate trenches 14 of this embodiment are formed so that their bottom portions are located within an n-type deep layer 37, which will be described later.

[0017] The inner surface (i.e., the side surface and bottom surface) of each gate trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed on the gate insulating film 16 in each gate trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of each gate electrode 18 is covered with an interlayer insulating film 20.

[0018] A source electrode 22 serving as a first electrode is provided on the one surface 12a of the semiconductor substrate 12. The source electrode 22 is disposed so as to cover each interlayer insulating film 20, and is insulated from the gate electrode 18 by the interlayer insulating film 20. The source electrode 22 contacts the one surface 12a of the semiconductor substrate 12 through a contact hole 20a formed in the interlayer insulating film 20. A drain electrode 24 serving as a second electrode is disposed on the other surface 12b of the semiconductor substrate 12. The drain electrode 24 is disposed so as to contact the entire other surface 12b of the semiconductor substrate 12.

[0019] The semiconductor substrate 12 includes a source layer 30, a contact layer 32, a body layer 34, a p-type trench lower layer 35, a first p-type deep layer 36a, a second p-type deep layer 36b, an n-type deep layer 37, a drift layer 38, and a drain layer 40. In this embodiment, the source layer 30 corresponds to a first impurity layer, and the drain layer 40 corresponds to a second impurity layer.

[0020] The source layer 30 has a high n-type impurity concentration. ＋A plurality of source layers 30 are formed. Each source layer 30 is disposed in an area that partially includes one surface 12a of the semiconductor substrate 12 and is in ohmic contact with the source electrode 22. Each source layer 30 is in contact with the gate insulating film 16 at the top of the side surface of the gate trench 14 and faces the gate electrode 18 via the gate insulating film 16. Each source layer 30 extends longitudinally in the y-axis direction along the side surface of the gate trench 14. That is, when the semiconductor substrate 12 is viewed from the one surface 12a side, each source layer 30 extends parallel to the longitudinal direction of the gate trench 14, extending from one end to the other end in the longitudinal direction of the gate trench 14. Note that the view from the one surface 12a side can also be referred to as the view from the z-axis direction or in the z-axis direction.

[0021] The contact layer 32 has a portion with a high p-type impurity concentration. ＋ The contact layers 32 are mold layers, and a plurality of them are formed. Each contact layer 32 is arranged in an area that partially includes one surface 12a of the semiconductor substrate 12. More specifically, each contact layer 32 is arranged between two corresponding source layers 30. In other words, each contact layer 32 is arranged on the opposite side of the source layer 30 from the gate trench 14. Each contact layer 32 is in ohmic contact with the source electrode 22. Each contact layer 32 extends elongately in the y-axis direction. That is, when the semiconductor substrate 12 is viewed from the one surface 12a side, each contact layer 32 extends parallel to the longitudinal direction of the gate trench 14, and extends from one end to the other end in the longitudinal direction of the gate trench 14.

[0022] The body layer 34 is a p-type layer having a lower p-type impurity concentration than the contact layer 32. The body layer 34 is disposed below each of the source layers 30 and each of the contact layers 32, and is in contact with each of the source layers 30 and each of the contact layers 32 from their lower surfaces. In other words, each of the source layers 30 and each of the contact layers 32 is formed in a surface layer portion of the body layer 34. The body layer 34 is in contact with the gate insulating film 16 on the side surface of the gate trench 14 located below the source layer 30, and faces the gate electrode 18 via the gate insulating film 16.

[0023] The p-type trench lower layer 35 is a p-type layer disposed below each gate trench 14. In other words, the p-type trench lower layer 35 is a p-type layer disposed so as to face the lower part of each gate trench 14. In this embodiment, each p-type trench lower layer 35 is disposed so as to be in contact with the gate insulating film 16 that covers the lower part of each gate trench 14. However, each p-type trench lower layer 35 may be formed slightly away from the lower part of the corresponding gate trench 14.

[0024] When the semiconductor substrate 12 is viewed from the one surface 12a side, each p-type trench lower layer 35 extends elongately along the longitudinal direction (i.e., the y-axis direction) of the corresponding gate trench 14, and extends continuously from one longitudinal end to the other longitudinal end of the gate trench 14. Note that in this embodiment, an example will be described in which each p-type trench lower layer 35 extends continuously from one longitudinal end to the other longitudinal end of the gate trench 14, but each p-type trench lower layer 35 may be arranged so as to have a divided portion between one longitudinal end and the other longitudinal end of the gate trench 14. Furthermore, although the p-type trench lower layer 35 is shown in FIGS. 1 to 3 as having a lower portion substantially parallel to the other surface 12b, the lower portion may have a shape that follows the lower portion of the gate trench 14.

[0025] The first p-type deep layer 36a and the second p-type deep layer 36b are p-type layers whose p-type impurity concentration is higher than the p-type impurity concentration of the body layer 34. In this embodiment, the first p-type deep layer 36a and the second p-type deep layer 36b have the same p-type impurity concentration, and the p-type impurity concentration is 1.0×10 １７ ~1.0 x 10 １９ / cm ３ However, the first p-type deep layer 36a and the second p-type deep layer 36b may have different p-type impurity concentrations.

[0026] The first p-type deep layer 36a protrudes from the lower surface of the body layer 34 in the z-axis direction and is formed deeper than the bottom of the gate trench 14. The first p-type deep layer 36a is formed to extend longitudinally in the x-axis direction. That is, the first p-type deep layer 36a is formed to intersect (i.e., perpendicular to) the longitudinal direction of the gate trench 14 (i.e., the y-axis direction). The first p-type deep layer 36a is electrically connected to the p-type trench lower layer 35. A plurality of first p-type deep layers 36a are arranged at intervals in the y-axis direction.

[0027] The second p-type deep layer 36b is formed away from the lower surface of the body layer 34. In this embodiment, the second p-type deep layer 36b is formed closer to the other surface 12b than the lower portion of the gate trench 14. The second p-type deep layer 36b is formed to extend elongatedly in the x-axis direction. That is, the second p-type deep layer 36b is formed to intersect (i.e., perpendicular to) the longitudinal direction of the gate trench 14 (i.e., the y-axis direction). In this embodiment, the first p-type deep layer 36a and the second p-type deep layer 36b are formed to be approximately parallel when viewed from the z-axis direction. The second p-type deep layer 36b is electrically connected to the p-type trench lower layer 35. As a result, the second p-type deep layer 36b is electrically connected to the body layer 34 via the p-type trench lower layer 35 and the first p-type deep layer 36a. A plurality of second p-type deep layers 36b are arranged at predetermined intervals in the y-axis direction. Specifically, the second p-type deep layers 36b are disposed between the first p-type deep layers 36a adjacent to each other in the y-axis direction, i.e., the first p-type deep layers 36a and the second p-type deep layers 36b are disposed alternately in the y-axis direction.

[0028] The n-type deep layer 37 is an n-type layer having a higher n-type impurity concentration than the drift layer 38 described later. In this embodiment, the n-type impurity concentration is 5.0×10 １６ ~1.0 x 10 １９ / cm ３Alternatively, the n-type deep layer 37 may have the same n-type impurity concentration as the drift layer 38. The n-type impurity concentration of the n-type deep layer 37 may be lower than the p-type impurity concentrations of the first p-type deep layer 36a and the second p-type deep layer 36b. The n-type deep layer 37 is formed to cover the p-type trench lower layer 35, the first p-type deep layer 36a, and the second p-type deep layer 36b while contacting a portion of the lower surface of the body layer 34 that is different from the portion contacted by the first p-type deep layer 36a. The n-type deep layer 37 of this embodiment is formed so that its lower surface is located closer to the other surface 12b than the lower surface of the second p-type deep layer 36b. In other words, the lower surface of the second p-type deep layer 36b is located within the n-type deep layer 37. The lower surface of the second p-type deep layer 36b refers to the surface of the second p-type deep layer 36b facing the other surface 12b, and the lower surface of the n-type deep layer 37 refers to the surface of the n-type deep layer 37 facing the other surface 12b.

[0029] Here, the thickness of the first p-type deep layer 36a, which is the length in the z-axis direction, is defined as the first p-type thickness d1, the thickness of the second p-type deep layer 36b, which is the length in the z-axis direction, is defined as the second p-type thickness d2, and the thickness of the n-type deep layer 37, which is the length in the z-axis direction, is defined as the n-type thickness d3. In this embodiment, if the sum of the first p-type thickness d1 and the second p-type thickness d2 is defined as the p-type deep layer thickness (i.e., d1 + d2), the first p-type deep layer 36a, the second p-type deep layer 36b, and the n-type deep layer 37 are formed so that the p-type deep layer thickness is thinner than the n-type thickness d3.

[0030] The drift layer 38 is an n-type layer having a lower n-type impurity concentration than the n-type deep layer 37. The drift layer 38 is disposed below the n-type deep layer 37. The drift layer 38 is in contact with the n-type deep layer 37 from below.

[0031] The drain layer 40 is an n-type layer having a higher n-type impurity concentration than the drift layer 38 and the n-type deep layer 37. The drain layer 40 is in contact with the drift layer 38 from below. The drain layer 40 is disposed in an area including the other surface 12b of the semiconductor substrate 12. The drain layer 40 is in ohmic contact with the drain electrode 24.

[0032] The above is the configuration of the semiconductor device 10 in this embodiment. In this embodiment, n-type corresponds to the first conductivity type, and p-type corresponds to the second conductivity type. Next, the operation of the semiconductor device 10 will be explained, and the configuration will be explained in more detail.

[0033] The semiconductor device 10 described above is used with a higher potential applied to the drain electrode 24 than to the source electrode 22. When a potential equal to or greater than the gate threshold is applied to each gate electrode 18, a channel is formed in the body layer 34 near the gate insulating film 16, and the source layer 30 and the n-type deep layer 37 are connected by the channel. As a result, electrons flow from the source layer 30 to the drain layer 40 via the channel, the n-type deep layer 37, and the drift layer 38, resulting in an ON state in which current flows. When the potential of the gate electrode 18 is reduced from a value equal to or greater than the gate threshold to a value less than the gate threshold, the channel disappears, the flow of electrons stops, and the semiconductor device 10 enters an OFF state in which no current flows.

[0034] When the semiconductor device 10 is in an off state, a reverse voltage is applied to the pn junction at the interface between the body layer 34 and the n-type deep layer 37. Therefore, a depletion layer spreads from the body layer 34 to the n-type deep layer 37. Furthermore, the p-type trench lower layer 35, the first p-type deep layer 36a, and the second p-type deep layer 36b are electrically connected to the body layer 34 and have substantially the same potential as the body layer 34. Therefore, when the channel disappears, a reverse voltage is also applied to the pn junction at the interface between the p-type trench lower layer 35, the first p-type deep layer 36a, the second p-type deep layer 36b, and the n-type deep layer 37. Therefore, a depletion layer also spreads from the p-type trench lower layer 35, the first p-type deep layer 36a, and the second p-type deep layer 36b to the n-type deep layer 37. In this way, the n-type deep layer 37 is quickly depleted by the depletion layer spreading from the body layer 34, the p-type trench lower layer 35, the first p-type deep layer 36 a, and the second p-type deep layer 36 b. This significantly reduces the electric field concentration near the bottom of the gate trench 14. This improves the DS breakdown voltage between the drain and source.

[0035] The inventors conducted extensive research into the characteristics of the semiconductor device 10 of this embodiment and obtained the results shown in Fig. 5. In Fig. 5, a comparative semiconductor device J10 is defined as a semiconductor device in which, instead of the first p-type deep layer 36a and the second p-type deep layer 36b in the semiconductor device 10 of this embodiment, a p-type deep layer 36 is formed from the lower surface of the body layer 34 to approximately the same depth as the lower surface of the p-type trench lower layer 35, as shown in Fig. 4, and the other configuration is the same as that of the semiconductor device 10 of this embodiment. In other words, the comparative semiconductor device J10 is defined as a semiconductor device in which the second p-type deep layer 36b is not formed in the semiconductor device 10 of this embodiment, and the lower surface of the first p-type deep layer 36a is positioned approximately the same depth as the lower surface of the p-type trench lower layer 35 to form the p-type deep layer 36, and the other configuration is the same as that of the semiconductor device 10 of this embodiment. 1 to 3, the distance L along the longitudinal direction (i.e., the y-axis direction) of the gate trench 14 between the first p-type deep layer 36a and the second p-type deep layer 36b is referred to as the p-to-pp distance L. Hereinafter, the ratio (%) of the p-to-pp distance L to the p-type deep layer thickness (i.e., d1 + d2), which is the sum of the first p-type thickness d1 and the second p-type thickness d2, is also simply referred to as the p-to-pp ratio. FIG. 5 shows the results when the p-type deep layer thickness (i.e., d1 + d2) is 0.7 μm.

[0036] As shown in FIG. 5 , the shorter the pp distance L, the smaller the n-type deep layer 37, narrowing the current path and thereby reducing the saturation current. Furthermore, the shorter the pp distance L, the larger the depletion layer due to the first p-type deep layer 36 a and the second p-type deep layer 36 b, thereby increasing the DS breakdown voltage. On the other hand, the shorter the pp distance L, the narrower the current path and therefore the higher the on-state voltage. However, it was also confirmed that shortening the pp distance L results in a greater decrease in saturation current and an increase in DS breakdown voltage than the increase in on-state voltage. Therefore, the semiconductor device 10 of this embodiment can reduce the saturation current and further improve the DS breakdown voltage without significantly increasing the on-state voltage. In this case, by setting the pp ratio to 50% or less, the saturation current can be reduced by 6.2% or more compared to the semiconductor device J10 of the comparative example, confirming that the saturation current can be sufficiently reduced.

[0037] Furthermore, in this embodiment, the second p-type deep layer 36b is formed so that its lower surface is located within the n-type deep layer 37. Therefore, compared to when the second p-type deep layer 36b is formed so that its lower surface is located within the drift layer 38, which has a lower n-type impurity concentration than the n-type deep layer 37, excessive extension of the depletion layer caused by the second p-type deep layer 36b in the on state can be suppressed, and an increase in on-state voltage can be suppressed.

[0038] Furthermore, in this embodiment, the thickness of the p-type deep layer (i.e., d1+d2) is set thinner than the n-type thickness d3 of the n-type deep layer 37. This prevents the p-type layer region from increasing too much, and prevents an increase in on-state voltage.

[0039] According to the present embodiment described above, the first p-type deep layer 36 a and the second p-type deep layer 36 b are provided, which allows the current path to be narrowed and the saturation current to be reduced, compared to a semiconductor device that does not have the second p-type deep layer 36 b, for example.

[0040] (1) In this embodiment, the pp ratio is set to 50% or less, so that the saturation current can be sufficiently reduced.

[0041] (2) In this embodiment, the second p-type deep layer 36b is formed so that its lower surface is located within the n-type deep layer 37. Therefore, an increase in on-state voltage can be suppressed compared to when the second p-type deep layer 36b is formed so that its lower surface is located within the drift layer 38, which has a lower n-type impurity concentration than the n-type deep layer 37.

[0042] (3) In this embodiment, the thickness of the p-type deep layer (i.e., d1+d2) is set thinner than the n-type thickness d3 of the n-type deep layer 37. This prevents the p-type layer region from increasing too much, thereby preventing an increase in on-state voltage.

[0043] (Modification of First Embodiment) A modification of the first embodiment will be described. In the first embodiment, the second p-type deep layer 36b may be formed so that its lower surface is located within the drift layer 38. Also, in the first embodiment, the thickness of the p-type deep layer (i.e., d1+d2) may be greater than the n-type thickness d3.

[0044] Second Embodiment A second embodiment will be described. In this embodiment, a wide portion is formed in the p-type deep layer in comparison with the first embodiment. As the other features are the same as those of the first embodiment, a description thereof will be omitted here.

[0045] 6, compared to the semiconductor device 10 of the first embodiment, the semiconductor device 10 of this embodiment includes a p-type deep layer 36 instead of the first p-type deep layer 36a and the second p-type deep layer 36b. Specifically, the p-type deep layer 36 has a p-type impurity concentration higher than the p-type impurity concentration of the body layer 34. In this embodiment, the p-type deep layer 36 has a p-type impurity concentration of 1.0×10 １７ ~1.0 x 10 １９ / cm ３ It is said that...

[0046] The p-type deep layer 36 protrudes from the lower surface of the body layer 34 in the z-axis direction, and is formed so that its lower surface is at approximately the same depth as the lower surface of the p-type trench lower layer 35. The p-type deep layer 36 is also formed so as to extend elongatedly in the x-axis direction. That is, the p-type deep layer 36 is formed so as to intersect (i.e., perpendicular to) the longitudinal direction of the gate trench 14 (i.e., the y-axis direction). The p-type deep layer 36 is electrically connected to the p-type trench lower layer 35. A plurality of p-type deep layers 36 are also arranged at intervals in the y-axis direction. In this embodiment, the p-type deep layer 36 corresponds to a breakdown voltage improvement layer.

[0047] The p-type deep layer 36 of this embodiment has, at a predetermined location, a wide portion 360 whose length (i.e., width) is increased along the longitudinal direction of the gate trench 14 (i.e., the y-axis direction). That is, the p-type deep layer 36 of this embodiment is configured with the wide portion 360 whose width is partially increased and a narrow portion in a portion different from the portion where the wide portion 360 is provided. In this embodiment, the wide portion 360 is formed in a portion of the p-type deep layer 36 that is connected to the body layer 34. The wide portion 360 is formed to extend along the x-axis direction. However, the wide portion 360 may be formed to be divided in the x-axis direction.

[0048] The n-type deep layer 37 is formed to cover the p-type trench lower layer 35 and the p-type deep layer 36, including a portion located between the p-type deep layers 36 adjacent to each other in the y-axis direction.

[0049] The above is the configuration of the semiconductor device 10 of this embodiment. This semiconductor device 10, like the semiconductor device 10 of the first embodiment, is controlled between an ON state in which current flows and an OFF state in which current does not flow. Furthermore, in the semiconductor device 10 of this embodiment, the p-type deep layer 36 has a wide portion 360. Therefore, in the semiconductor device 10 of this embodiment, when the semiconductor device 10 is in the ON state, the current path is narrower and the saturation current can be reduced compared to when the wide portion 360 is not formed. However, as shown in FIG. 6 , if the thickness of the wide portion 360 along the z-axis direction is defined as the wide portion thickness d4, if the wide portion thickness d4 is too long, the current path may become too narrow, resulting in an excessively high ON voltage.

[0050] For this reason, the inventors conducted extensive research into the characteristics of the semiconductor device 10 of this embodiment and obtained the results shown in Fig. 7. In the following, a semiconductor device that does not have the wide portion 360 but has the same other configuration as the semiconductor device 10 of this embodiment (i.e., the above-mentioned Fig. 4) is referred to as a comparative semiconductor device. In the following, as shown in Fig. 6, the thickness of the p-type deep layer 36, which is the length in the z-axis direction, is referred to as the p-type deep layer thickness d5, and the ratio (%) of the wide portion thickness d4 to the p-type deep layer thickness d5 is also simply referred to as the wide portion ratio.

[0051] As shown in FIG. 7 , as the wide portion thickness d4 increases, the n-type deep layer 37 decreases, narrowing the current path and thereby reducing the saturation current. Furthermore, as the wide portion thickness d4 increases, the depletion layer increases, thereby increasing the DS breakdown voltage. On the other hand, as the wide portion thickness d4 increases, the current path narrows and the on-state voltage increases. However, as shown in FIG. 7 , when the wide portion thickness d4 increases, the rate of decrease in saturation current and the rate of increase in DS breakdown voltage are greater than the rate of increase in on-state voltage. Therefore, according to the semiconductor device 10 of this embodiment, the saturation current can be reduced without significantly increasing the on-state voltage, and the DS breakdown voltage can be improved. In this case, according to the inventors' study, by setting the wide portion ratio to 50% or less, the saturation current can be sufficiently reduced while suppressing the increase in on-state voltage to 5% or less, compared to the semiconductor device of the comparative example.

[0052] According to the present embodiment described above, the wide portion 360 is formed in the p-type deep layer 36. Therefore, the saturation current can be reduced compared to when the wide portion 360 is not formed. Furthermore, a large increase in the on-state voltage can be suppressed compared to when the wide portion 360 is not formed.

[0053] (1) In this embodiment, the breakdown voltage improvement layer is configured to include the p-type deep layer 36, and the p-type deep layer 36 is formed to a position deeper than the bottom of the gate trench 14. This makes it easier to alleviate electric field concentration near the bottom of the gate trench 14.

[0054] (2) In this embodiment, by setting the wide portion ratio to 50% or less, it is possible to sufficiently reduce the saturation current while suppressing the increase in on-voltage to 5% or less compared to a semiconductor device in which the wide portion 360 is not formed.

[0055] (Modification of Second Embodiment) A modification of the second embodiment will be described. In the second embodiment, the wide portion 360 may be formed in a position in the p-type deep layer 36 that is farther from the body layer 34. In this case, as shown in FIG. 8, the wide portion 360 may be formed in a position closer to the other surface 12b than the lower portion of the gate trench 14. Although not specifically shown, the wide portion 360 may also be formed in a position farther from the body layer 34 and closer to the one surface 12a than the lower portion of the gate trench 14. In other words, the position in which the wide portion 360 is formed can be changed as appropriate. However, the closer the wide portion 360 is formed to the lower surface of the p-type deep layer 36, the more easily the depletion layer extends toward the other surface 12b, which makes it easier to improve the DS breakdown voltage.

[0056] Third Embodiment A third embodiment will be described. This embodiment differs from the second embodiment in that a breakdown voltage trench is formed separately from the gate trench 14. As the other features are the same as those of the second embodiment, a description thereof will be omitted here.

[0057] As shown in FIG. 9, the semiconductor device 10 of this embodiment has an n-type MOSFET on the drain layer 40. － A p-type drift layer 38 is formed on the n-type body layer 34. A p-type body layer 34 is formed on the n-type drift layer 38. ＋ A mold source layer 30 is formed.

[0058] The gate trench 14 is formed so as to penetrate from the one surface 12a through the source layer 30 and the body layer 34. The gate trench 14 of this embodiment extends with its longitudinal direction in the y-axis direction. Note that while only one gate trench 14 is shown in FIG. 9, in reality, a plurality of gate trenches 14 are formed with their longitudinal direction in the y-axis direction and are arranged at equal intervals in the x-axis direction to form a stripe pattern. Also, in FIG. 9, the angle between the side surface and the bottom of the gate trench 14 is shown as a substantially right angle, but the bottom may have a curvature (i.e., roundness).

[0059] The inner surface of the gate trench 14 is covered with a gate insulating film 16, and a gate electrode 18 is disposed on the gate insulating film 16. Therefore, the gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. In this manner, the trench gate structure of this embodiment is formed.

[0060] Furthermore, the semiconductor substrate 12 is formed with breakdown voltage trenches 50 that extend from the one surface 12a through the body layer 34 and reach the drift layer 38. Similar to the gate trenches 14, the breakdown voltage trenches 50 are extended with their longitudinal direction in the y-axis direction, and a plurality of them are formed in a stripe pattern along the x-axis direction. Furthermore, the breakdown voltage trenches 50 are formed such that the gate trenches 14 are disposed between adjacent breakdown voltage trenches 50 in the x-axis direction.

[0061] The voltage trench 50 of this embodiment is formed so that its lower surface is located closer to the other surface 12b than the lower surface of the gate trench 14. In other words, the voltage trench 50 of this embodiment is formed so that its lower surface is deeper than the lower surface of the gate trench 14. The lower surface of the gate trench 14 refers to the surface of the gate trench 14 facing the other surface 12b, and the lower surface of the voltage trench 50 refers to the surface of the voltage trench 50 facing the other surface 12b. The inner surface of the voltage trench 50 is covered with an insulating film 51 made of an oxide film or the like.

[0062] Furthermore, in this embodiment, the p-type trench lower layer 35 facing the lower surface of the gate trench 14 is not formed, and the p-type trench lower layer 61 is formed so as to face the lower surface of the voltage trench 50. The p-type trench lower layer 61 is formed so as to extend elongate along the longitudinal direction (i.e., the y-axis direction) of the corresponding voltage trench 50 when viewed from the one surface 12a side of the semiconductor substrate 12. However, the p-type trench lower layer 61 may be formed so as to have a divided portion between one end and the other end of the longitudinal direction of the voltage trench 50. Furthermore, although the p-type trench lower layer 61 is formed so as to contact the lower surface of the voltage trench 50 in this embodiment, it may be formed slightly away from the lower surface of the voltage trench 50.

[0063] The semiconductor substrate 12 also has a p-type trench-side layer 62 formed thereon, the p-type trench lower layer 61 being connected to the p-type trench lower layer 61 and extending along the side surface of the breakdown voltage trench 50. The semiconductor substrate 12 also has a contact layer 32 formed thereon, the contact layer 32 being located on the opposite side of the gate trench 14 across the source layer 30 and connected to the p-type trench-side layer 62. The p-type trench-side layer 62 is formed from the lower surface of the contact layer 32 along the side surface of the breakdown voltage trench 50. The detailed shape and location of the contact layer 32 can be changed as appropriate, as long as the p-type trench lower layer 61, the p-type trench-side layer 62, and the body layer 34 are electrically connected to the source electrode 22 and the potential is fixed. For example, the contact layer 32 may be formed to extend elongatedly in the y-axis direction, or may be divided and selectively formed. The contact layer 32 may also be formed above the body layer 34. The lower surface of the contact layer 32 refers to the surface of the contact layer 32 on the other surface 12b side.

[0064] The p-type trench-side layer 62 in this embodiment is selectively formed in the y-axis direction. In the portion where the p-type trench-side layer 62 is not formed, the body layer 34 is in contact with the side surface of the voltage trench 50. However, the p-type trench-side layer 62 may be formed so as to extend long along the longitudinal direction of the gate trench 14 (i.e., the y-axis direction). In this embodiment, the p-type trench-side layer 62 is formed so as to be in contact with the side surface of the voltage trench 50, but may be formed slightly away from the side surface of the voltage trench 50.

[0065] As described above, the breakdown voltage trench 50 is formed so that its lower surface is located closer to the other surface 12b than the lower surface of the gate trench 14. Therefore, it can be said that the p-type trench lower layer 61 is formed closer to the other surface 12b than the lower surface of the gate trench 14 (i.e., at a deeper position). It can also be said that the p-type trench side layer 62 has a portion formed closer to the other surface 12b than the lower surface of the gate trench 14 (i.e., at a deeper position). Therefore, in this embodiment, the breakdown voltage improving layer 63 is configured to include the p-type trench lower layer 61 and the p-type trench side layer 62.

[0066] The breakdown voltage improving layer 63 has a wide portion 360 whose length in the x-axis direction is partially increased. In this embodiment, the wide portion 360 is provided in the p-type trench lower layer 61 of the breakdown voltage improving layer 63. The x-axis direction can also be said to be an intersecting direction that intersects with the longitudinal direction of the gate trench 14.

[0067] An interlayer insulating film 20 is disposed on the one surface 12a of the semiconductor substrate 12 so as to cover the gate electrode 18. In the interlayer insulating film 20 of this embodiment, contact holes 20a are formed to expose the source layer 30, the contact layer 32, and the breakdown voltage trench 50.

[0068] The source electrode 22 disposed on the interlayer insulating film 20 is formed so as to be electrically connected to the source layer 30 and the contact layer 32 through a contact hole 20a formed in the interlayer insulating film 20. The source electrode 22 is also disposed in the voltage-resistant trench 50. However, because the insulating film 51 is disposed in the voltage-resistant trench 50, the source electrode 22 disposed in the voltage-resistant trench 50 is not directly electrically connected to the p-type trench lower layer 61 and the p-type trench-side layer 62. This configuration can prevent breakdown and an increase in drain-source DS leakage. The p-type trench-side layer 62 is electrically connected to the source electrode 22 via the contact layer 32, and the p-type trench lower layer 61 and the body layer 34 are electrically connected to the source electrode 22 via the p-type trench-side layer 62 and the contact layer 32.

[0069] According to the present embodiment described above, since the wide portion 360 is formed in the breakdown voltage improving layer 63, it is possible to obtain the same effects as in the second embodiment.

[0070] (1) In this embodiment, the breakdown voltage improving layer 63 is disposed along the breakdown voltage trench 50, and therefore the breakdown voltage improving layer 63 is likely to be disposed at a position away from the gate trench 14. This makes it easy to ensure a current path, and the on-voltage can be reduced.

[0071] (Modification of Third Embodiment) A modification of the third embodiment will be described. In the third embodiment, the bottom surface of the voltage trench 50 may be the same depth as the bottom surface of the gate trench 14, or may be shallower than the bottom surface of the gate trench 14, as long as at least a portion of the p-type trench lower layer 61 and the p-type trench side layer 62 constituting the voltage resistance improving layer 63 is located closer to the other surface 12b than the bottom surface of the gate trench 14. Furthermore, as long as a portion of the p-type trench side layer 62 is located closer to the other surface 12b than the bottom surface of the gate trench 14, the p-type trench lower layer 61 does not have to be located.

[0072] Furthermore, the wide portion 360 may be provided in the p-trench side layer 62 located in the drift layer 38 , instead of in the p-trench lower layer 61 .

[0073] Fourth Embodiment A fourth embodiment will be described. In this embodiment, the source layer 30 is disposed only on one side of the gate trench 14, as compared to the second embodiment. As the other features are the same as those of the second embodiment, a description thereof will be omitted here.

[0074] As shown in FIG. 10, the semiconductor device 10 of this embodiment has an n-type MOSFET on the drain layer 40. － A p-type drift layer 38 is formed on the n-type body layer 34. A p-type body layer 34 is formed on the surface of the body layer 34. ＋ A mold source layer 30 is formed.

[0075] The gate trench 14 is formed so as to penetrate from the one surface 12a through the source layer 30 and the body layer 34. Note that in FIG. 10 , the angle between the side surface and the bottom of the gate trench 14 is approximately right angles, but the bottom may have a curvature (i.e., roundness). Similar to the first embodiment, the gate trenches 14 are formed so as to extend in the y-axis direction as the longitudinal direction, and are arranged at equal intervals in the x-axis direction to form a stripe pattern. In this embodiment, the source layer 30 and the body layer 34 are formed so as to contact only one of the opposing side surfaces of the gate trench 14.

[0076] The semiconductor substrate 12 also has a p-type silicon nitride film formed in contact with the other side surface of the gate trench 14 and extending from the bottom of the gate trench 14 to the other surface 12b. ＋ 10, the source layer 30 and the body layer 34 are formed so as to contact the side surface of the gate trench 14 on the left side of the page, and the contact layer 32 is formed so as to contact the side surface of the gate trench 14 on the right side of the page. In this embodiment, the contact layer 32 corresponds to a breakdown voltage improving layer.

[0077] A wide portion 360, the length of which in the x-axis direction is partially increased, is formed in the contact layer 32. In this embodiment, the wide portion 360 is formed in a portion of the contact layer 32 located in the drift layer 38 so as to protrude to the opposite side of the gate trench 14 that is in contact with the contact layer 32.

[0078] As in the first embodiment, an interlayer insulating film 20 is disposed on the one surface 12a of the semiconductor substrate 12 so as to cover the gate electrode 18. In addition, a contact hole 20a is formed in the interlayer insulating film 20 to expose the source layer 30 and the contact layer 32.

[0079] A source electrode 22 is disposed on the interlayer insulating film 20. Specifically, the source electrode 22 is formed so as to be electrically connected to the source layer 30 and the contact layer 32 through a contact hole 20a formed in the interlayer insulating film 20. The body layer 34 is electrically connected to the source electrode 22 via the contact layer 32.

[0080] According to the present embodiment described above, the wide portion 360 is formed in the portion of the contact layer 32 located in the drift layer 38, and therefore, the same effects as those of the second embodiment can be obtained.

[0081] (1) As in this embodiment, the source layer 30 and the body layer 34 are formed so as to contact only one of the opposing side surfaces of the gate trench 14, and the contact layer 32 is formed so as to contact only the other side surface. By forming the contact layer 32 deeper than the bottom of the gate trench 14, it is possible to simplify the structure while improving the DS breakdown voltage.

[0082] (Modification of Fourth Embodiment) A modification of the fourth embodiment will be described. In the fourth embodiment, although not particularly shown, the wide portion 360 may be provided so as to extend from the contact layer 32 to the gate trench 14 side with which the contact layer 32 is in contact. Furthermore, the wide portion 360 may be provided so as to extend from the contact layer 32 to the gate trench 14 side with which the contact layer 32 is in contact, and to the side opposite to the gate trench 14 with which the contact layer 32 is in contact.

[0083] Fifth Embodiment A fifth embodiment will be described. In this embodiment, unlike the first embodiment, the p-type deep layer is formed away from the body layer 34. As the other features are the same as those of the first embodiment, a description thereof will be omitted here.

[0084] As shown in FIG. 11 , the semiconductor device 10 of this embodiment differs from the semiconductor device 10 of the first embodiment in that it includes a p-type deep layer 36 instead of the first p-type deep layer 36 a and the second p-type deep layer 36 b. Specifically, the p-type deep layer 36 has a p-type impurity concentration higher than that of the body layer 34. The p-type deep layer 36 is formed away from the lower surface of the body layer 34. The p-type deep layer 36 is formed so that its lower surface is at approximately the same depth as the lower surface of the p-type trench lower layer 35. The p-type deep layer 36 is formed to extend elongately in the x-axis direction. In other words, the p-type deep layer 36 is formed so as to intersect (i.e., perpendicular to) the longitudinal direction of the gate trench 14 (i.e., the y-axis direction). The p-type deep layer 36 is electrically connected to the p-type trench lower layer 35. In addition, in the portion in contact with the side surface of the gate trench 14, an n-type deep layer 37 is disposed between the body layer 34 and the p-type deep layer 36. A plurality of p-type deep layers 36 are disposed at intervals in the y-axis direction.

[0085] In this embodiment, the inner surface of the gate trench 14 extending along the z-axis direction is referred to as the side surface 14a, and the inner surface connected to the side surface 14a and having a curvature is referred to as the lower portion 14b. In this embodiment, if the portion of the p-type deep layer 36 on the one surface 12a side is referred to as the upper surface, the upper surface is formed so as to be located closer to the one surface 12a than the portion of the gate trench 14 located closest to the other surface 12b. In other words, the p-type deep layer 36 is formed so as to be in contact with the gate trench 14. More specifically, the p-type deep layer 36 in this embodiment is formed so that the upper surface is located closer to the one surface 12a than the lower portion 14b. In other words, the p-type deep layer 36 is formed so that the upper surface is in contact with the side surface 14a.

[0086] The contact layer 32 in this embodiment is formed deeper than the source layer 30 so as to penetrate the body layer 34 and be connected to the p-type deep layer 36. As a result, the p-type deep layer 36 is connected to the body layer 34 (i.e., the source electrode 22) via the contact layer 32, and the p-type trench lower layer 35 is connected to the body layer 34 (i.e., the source electrode 22) via the p-type deep layer 36 and the contact layer 32.

[0087] The above is the configuration of the semiconductor device 10 of this embodiment. This semiconductor device 10, like the semiconductor device 10 of the first embodiment, is controlled between an on state in which current flows and an off state in which current does not flow. In the semiconductor device 10 of this embodiment, the p-type deep layer 36 is formed away from the lower surface of the body layer 34, and the side surface 14a of the gate trench 14 has a portion that contacts the n-type deep layer 37 between the body layer 34 and the p-type deep layer 36. Therefore, when the semiconductor device 10 is in the on state, the current path is wider than in a semiconductor device in which the p-type deep layer 36 contacts the lower surface of the body layer 34, thereby reducing the on-state voltage. However, as shown in FIG. 11 , if the distance d6 between the body layer 34 and the p-type deep layer 36 along the z-axis direction is made too long, the on-state voltage can be reduced, but there is a concern that the saturation current may become too large.

[0088] Therefore, the inventors have conducted extensive research into the characteristics of the semiconductor device 10 of this embodiment and obtained the results shown in Fig. 12. Note that, hereinafter, the distance d6 between the body layer 34 and the p-type deep layer 36 may also be simply referred to as the distance d6.

[0089] 12 , it is confirmed that the shorter the distance d6, the narrower the current path, and therefore the saturation current decreases. It is also confirmed that the shorter the distance d6, the larger the depletion layer, and therefore the DS breakdown voltage increases. On the other hand, it is confirmed that the shorter the distance d6, the narrower the current path, and therefore the on-state voltage increases. However, when the distance d6 is shortened, the rate of decrease in saturation current is greater than the rate of increase in on-state voltage. Therefore, when the body layer 34 and the p-type deep layer 36 are separated as in the semiconductor device 10 of this embodiment, shortening the distance d6 can reduce the saturation current without significantly increasing the on-state voltage.

[0090] In this case, as shown in FIG. 13, it was confirmed that when the distance d6 is shorter than 0.14 μm, the on-state voltage increases sharply. Therefore, it is preferable that the distance d6 be 0.14 μm or greater. Furthermore, as shown in FIG. 12, it was confirmed that when the distance d6 is up to approximately 0.23 μm, the saturation current is smaller than that of the semiconductor device of the comparative example described in the first embodiment or the second embodiment, and the current requirements can be fully met. Note that FIG. 13 shows the results when the semiconductor device 10 is turned on at 200° C. and the drain current is 200 A.

[0091] Furthermore, in the semiconductor device of this embodiment, it is also possible to set the distance d6 to 0.14 μm or more by lowering the lower surfaces of the body layer 34 and the p-type deep layer 36 toward the other surface 12b. However, in this configuration, the length of the body layer 34 in contact with the gate trench 14 along the z-axis direction becomes longer, and the channel length becomes longer, which makes it easier for the gate threshold to increase. For this reason, in this embodiment, the p-type deep layer 36 is formed so that its upper surface is located closer to the one surface 12a than the portion of the gate trench 14 closest to the other surface 12b. This prevents the gate threshold from increasing. Furthermore, in this embodiment, the p-type deep layer 36 is formed so that its upper surface is located closer to the one surface 12a than the lower portion 14b. This prevents the body layer 34 from contacting the curved lower portion 14b, thereby preventing fluctuations in the gate threshold.

[0092] According to the present embodiment described above, the p-type deep layer 36 is formed at a position away from the lower surface of the body layer 34, and the gate trench 14 has a portion that contacts the n-type deep layer 37 between the body layer 34 and the p-type deep layer 36. Therefore, compared to a case where the p-type deep layer 36 is formed so as to contact the lower surface of the body layer 34, the current path is wider when the semiconductor device 10 is in the on state, thereby enabling a reduction in on-voltage.

[0093] In the semiconductor device 10 of this embodiment, the distance d6 between the body layer 34 and the p-type deep layer 36 is set to 0.14 μm or more. This allows the saturation current to be reduced while also reducing the on-state voltage. In this case, by setting the distance d6 to 0.23 μm or less, the saturation current can be made sufficient to meet current requirements.

[0094] (1) In this embodiment, the p-type deep layer 36 includes a portion whose upper surface is located closer to the one surface 12a than the portion of the gate trench 14 that is located closest to the other surface 12b. This makes it possible to suppress an increase in the gate threshold value.

[0095] (2) In this embodiment, the upper surface of the p-type deep layer 36 is located closer to the one surface 12a than the lower portion 14b, which has a curvature, of the gate trench 14. This makes it possible to suppress fluctuations in the gate threshold.

[0096] (Modification of Fifth Embodiment) A modification of the fifth embodiment will be described. In the fifth embodiment, the p-type deep layer 36 may be formed so that its upper surface is located closer to the other surface 12 b than the portion of the gate trench 14 that is located closest to the other surface 12 b.

[0097] (Other Embodiments) While the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0098] For example, the semiconductor device 10 of each of the above embodiments has been described as including an n-channel MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type. However, this is merely an example, and a p-channel MOSFET may be formed, for example, in which the conductivity types of the components of the n-channel MOSFET are reversed. Furthermore, the semiconductor device 10 may be configured to include an IGBT having a similar structure in addition to a MOSFET. In the case of an IGBT, the IGBT is the same as the MOSFET described in each of the above embodiments, except that the drain layer 40 in each of the above embodiments is changed to a p-type collector layer.

[0099] Furthermore, in the first embodiment, when viewed from the side of the one surface 12a of the semiconductor substrate 12, the first p-type deep layer 36a, the second p-type deep layer 36b, and the n-type deep layer 37 may be formed so as to diagonally intersect with each gate trench 14. Similarly, in the second and fifth embodiments, when viewed from the side of the one surface 12a of the semiconductor substrate 12, the p-type deep layer 36 and the n-type deep layer 37 may be formed so as to diagonally intersect with each gate trench 14.

[0100] Furthermore, the above embodiments can be combined as appropriate.

Claims

1. A semiconductor device comprising: a semiconductor substrate (12) having one surface (12a) and another surface (12b) opposite to the one surface, with a gate trench (14) formed on the one surface; a gate insulating film (16) covering the inner surface of the gate trench; and a gate electrode (18) disposed in the gate trench and insulated from the semiconductor substrate by the gate insulating film, wherein the semiconductor substrate comprises: a first impurity layer (30) of a first conductivity type formed on the one surface of the semiconductor substrate and in contact with the gate insulating film on a side surface of the gate trench; a body layer (34) of a second conductivity type in contact with the gate insulating film on the side surface of the gate trench located on the other surface side of the first impurity layer; and a contact layer (32) of a second conductivity type disposed on the body layer on the opposite side of the gate trench with the first impurity layer therebetween, and having a portion with a higher impurity concentration than the body layer. a second conductivity type trench lower layer (35) disposed opposite a lower portion of the gate trench and extending along the longitudinal direction of the gate trench; second conductivity type deep layers (36) extending along an intersecting direction in the surface direction of the semiconductor substrate, intersecting the longitudinal direction of the gate trench, the second conductivity type deep layers (36) being spaced apart from the body layer and arranged at predetermined intervals along the longitudinal direction, the second conductivity type trench lower layer (35) being connected to the second conductivity type trench lower layer and the contact layer; a first conductivity type deep layer (37) disposed between adjacent second conductivity type deep layers in the longitudinal direction and having a portion extending in the intersecting direction; a first conductivity type drift layer (38) disposed on the other surface side of the first conductivity type deep layer; a first conductivity type or second conductivity type second impurity layer (40) disposed on the other surface side of the drift layer; a first electrode (22) electrically connected to the body layer and the first impurity layer; and a second electrode (24) electrically connected to the second impurity layer. a first conductivity type deep layer disposed between the second conductivity type deep layer and the body layer, and having a portion located on the other side of the body layer that contacts the gate insulating film on the side of the gate trench, and a distance (d6) between the body layer and the second conductivity type deep layer is 0.14 μm or more.

2. The semiconductor device according to claim 1, wherein the second conductivity type deep layer has a portion of the gate trench that is located closer to the one surface than a portion of the gate trench that is located closest to the other surface.

3. The semiconductor device according to claim 1, wherein the gate trench has a curved lower portion on the other surface side, and the second conductivity type deep layer has a portion located closer to the one surface side than the lower portion.

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