Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device which comprises: a semiconductor substrate containing silicon; and a lifetime adjustment region with a carrier lifetime of 3 μs or less provided on the semiconductor substrate, wherein in a spectrum of emitted light obtained when the lifetime adjustment region is irradiated with an electron beam or a light, the emission intensity ratio obtained by dividing a first emission intensity derived from a CiOi defect by a second emission intensity at the silicon band edge is at least 1 but at most 15.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] A technique for controlling carrier lifetime by irradiating a semiconductor substrate with helium or the like is known (see, for example, Patent Document 1). Problem to be solved

[0003] In semiconductor devices, it is preferable to suppress fluctuations in characteristics. General disclosure

[0004] In order to solve the above problems, a first aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate containing silicon. Any of the above semiconductor devices may include a lifetime adjusting region provided in the semiconductor substrate, the lifetime adjusting region having a carrier lifetime of 3 μs or less. In any of the above semiconductor devices, C ｉ O ｉ An emission intensity ratio obtained by dividing the first emission intensity derived from defects by the second emission intensity at the band edge of silicon may be 1 or more and 15 or less.

[0005] In any of the above semiconductor devices, the emission intensity ratio may be 12 or less.

[0006] In any of the above semiconductor devices, the emission intensity ratio may be greater than two.

[0007] In any of the above semiconductor devices, the lifetime adjusting region may contain helium. In any of the above semiconductor devices, a value obtained by dividing the emission intensity ratio by the dose of helium in the lifetime adjusting region is 6×10 －１１ cm ２ It may be the following:

[0008] In any of the above semiconductor devices, the distribution of the emission intensity ratio in the depth direction of the semiconductor substrate may have a minimum value in the lifetime adjusting region.

[0009] In any of the above semiconductor devices, the emission intensity ratio may exhibit a maximum value at a position deeper than the position where the emission intensity ratio exhibits the minimum value.

[0010] In any of the above semiconductor devices, the carrier concentration measured by the SR method in the lifetime adjusting region may be lower than the phosphorus chemical concentration and the antimony chemical concentration.

[0011] In any of the above semiconductor devices, the distribution of the carrier lifetime in the depth direction of the semiconductor substrate may have a minimum value in the lifetime adjusting region.

[0012] In any of the above semiconductor devices, the semiconductor substrate may have an upper surface and a lower surface. Any of the above semiconductor devices may include a diode section including an anode region provided in a region within the semiconductor substrate that contacts the upper surface, and a cathode region provided in a region within the semiconductor substrate that contacts the lower surface. In any of the above semiconductor devices, at least a portion of the lifetime adjusting region may be provided in the diode section.

[0013] In any one of the above semiconductor devices, the carbon chemical concentration of the semiconductor substrate is 1×10 １４ / cm ３ It may be more than that.

[0014] In any one of the above semiconductor devices, the oxygen chemical concentration of the semiconductor substrate is 1×10 １６ / cm ３ That's it, 1 x 10 １８ / cm ３ It may be the following:

[0015] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device. In the manufacturing method, charged particles may be injected into a semiconductor substrate containing silicon to form a lifetime adjusting region in which the carrier lifetime is reduced. In any of the manufacturing methods, after the injected charged particles, the lifetime adjusting region may be irradiated with light having an energy of 0.7 eV or more and 1.1 eV or less.

[0016] In any of the above manufacturing methods, the lifetime adjusting region may be irradiated with the light for a period of 100 nsec or more and 10 hours or less.

[0017] In any of the above manufacturing methods, the semiconductor substrate may be heated to a first temperature of 100° C. or higher and 400° C. or lower, and the lifetime adjusting region may be irradiated with the light.

[0018] In any of the above manufacturing methods, the semiconductor substrate may be heated for a period of not less than 10 minutes and not more than 10 hours.

[0019] In any of the above manufacturing methods, the semiconductor substrate may be heated to a second temperature higher than the first temperature after the charged particles are injected and before the light is irradiated.

[0020] In any of the above manufacturing methods, the light may be condensed and irradiated to a depth of the lifetime adjusting region.

[0021] In any of the above manufacturing methods, the light may be irradiated by passing through the semiconductor substrate.

[0022] In any of the above manufacturing methods, the charged particles may be electrons, hydrogen ions, or helium ions.

[0023] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also constitute inventions.

[0024] 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention; FIG. 2 is an enlarged view of region D in FIG. 1; FIG. 3 is a diagram showing an example of a cross section taken along the line ee in FIG. 2; and FIG. 4 is a diagram showing an example of voltage-current characteristics of a diode section 80 before and after energization of a semiconductor substrate 10. ２ , and C ｉ O ｉ An example of a defect level is shown. ｉ O ｉ12A is a diagram showing an analysis by simulation of energy changes accompanying structural changes in a lifetime killer 202 including defects and vacancies V. FIG. 12B is a diagram showing an analysis by simulation of energy changes accompanying structural changes in a lifetime killer 202 including vacancies V. FIG. 12C is a diagram showing an example of the spectrum of emitted light obtained when an electron beam or light is irradiated onto a lifetime adjustment region 200 according to a reference example. FIG. 12D is a diagram showing an example of changes in the emission intensity ratio before and after energization of a semiconductor substrate 10. FIG. 12E is a diagram showing a part of a manufacturing process for a semiconductor device 100 according to one embodiment of the present invention. FIG. 12F is a diagram showing another example of a manufacturing process for a semiconductor device 100. FIG. 12G is a diagram showing an example of the characteristics of semiconductor devices according to Examples 1 to 3 of the present invention and a semiconductor device according to a comparative example. For Examples 1 to 3 and Comparative Example 1 in FIG. 12A, the horizontal axis shows the emission intensity ratio, and the vertical axis shows ΔV when energized. Ｆ The helium concentration distribution along the ff line in FIG. ｉ O ｉ 1 is a diagram showing an example of a concentration distribution and a light emission intensity ratio distribution. ｉ O ｉ 10A and 10B are diagrams showing other examples of the concentration distribution and the emission intensity ratio distribution. ｉ O ｉ 10A and 10B are diagrams showing other examples of concentration distribution and emission intensity ratio distribution, and are diagrams showing the relationship between the dose of helium ions and the emission intensity ratio.

[0025] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0026] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0027] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0028] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0029] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0030] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0031] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0032] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is NＤ , acceptor concentration is N Ａ Then, the net doping concentration at any position is N Ｄ -N Ａ In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0033] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, interstitial silicon (Si-i) in a silicon semiconductor is bonded with hydrogen, and interstitial carbon (C ｉ ) and interstitial oxygen (O ｉ ) and hydrogen bonded to C ｉ O ｉ —H functions as a donor that supplies electrons. ｉ O ｉ --H or interstitial Si--H may be referred to as a hydrogen donor.

[0034] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donors are donors due to dopants contained substantially uniformly in the ingot that is the base of the semiconductor substrate when the ingot is manufactured. In this example, the bulk donors are elements other than hydrogen. The dopants of the bulk donors include, but are not limited to, phosphorus, antimony, arsenic, selenium, or sulfur. In this example, the bulk donors are phosphorus. The bulk donors are also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), and the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 １７ ~7 x 10 １７ / cm ３ The oxygen concentration in the substrate manufactured by the FZ method is 1×10 １５ ~5 x 10 １６ / cm ３The higher the oxygen concentration, the more likely it is that hydrogen donors are generated. The bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, or may be a value between 90% and 100% of the chemical concentration. Alternatively, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the non-doped substrate is, for example, 1×10 １０ / cm ３ That's it, 5 x 10 １２ / cm ３ The bulk donor concentration (D0) of the non-doped substrate is preferably 1×10 １１ / cm ３ The bulk donor concentration (D0) of the non-doped substrate is preferably 5×10 １２ / cm ３ The concentrations in the present invention may be values ​​at room temperature, for example, values ​​at 300 K (Kelvin) (approximately 26.9° C.).

[0035] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Furthermore, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0036] In this specification, chemical concentration refers to the atomic density of an impurity measured regardless of its state of electrical activation. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as a value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is sufficiently greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0037] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor, or net doping in that region. In cases where the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in that region may be taken as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. ３ , or / cm ３ This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atoms notation may be omitted.

[0038] The carrier concentration measured by the SR method may be lower than the concentration of donors or acceptors. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects or the like.

[0039] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen.

[0040] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0041] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end edges 162 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 in this example has two pairs of end edges 162 that face each other in a top view. In FIG. 1 , the X-axis and Y-axis are parallel to either of the end edges 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0042] An active portion 160 is provided in the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted from FIG. 1 . The active portion 160 may refer to a region that overlaps with the emitter electrode in a top view. The active portion 160 may also include a region sandwiched between the active portions 160 in a top view.

[0043] The active section 160 is provided with at least one of a transistor section 70 including a transistor element such as an insulated gate bipolar transistor (IGBT) and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 1 , the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (in this example, the X-axis direction) on the top surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT).

[0044] In FIG. 1 , the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1 ). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0045] The diode section 80 has an N+ type cathode region in a region that contacts the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region of the lower surface of the semiconductor substrate 10 other than the cathode region. In this specification, an extension region 81 that extends the diode section 80 in the Y-axis direction to the gate wiring described below may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0046] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. The transistor section 70 also has a gate structure, which has an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the upper surface side of the semiconductor substrate 10.

[0047] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 162. The vicinity of the edge 162 refers to the region between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0048] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with diagonal lines.

[0049] The gate wiring in this example has a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than a base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be the active portion 160.

[0050] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0051] The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, it is possible to reduce variations in wiring length from the gate pad 164 for each region of the semiconductor substrate 10.

[0052] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The peripheral gate wiring 130 and the active side gate wiring 131 are disposed above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

[0053] The active side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active side gate wiring 131 extends in the X axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 that sandwich the active section 160, crossing the active section 160 at approximately the center in the Y axis direction. When the active section 160 is divided by the active side gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X axis direction in each divided region.

[0054] The semiconductor device 100 may include a temperature sensing section (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting section (not shown) which simulates the operation of a transistor section provided in the active section 160.

[0055] In the present example, the semiconductor device 100 includes an edge termination structure 90 between the active section 160 and the edge 162 when viewed from above. The edge termination structure 90 in the present example is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 90 relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding the active section 160.

[0056] 2 is an enlarged view of region D in FIG. 1 . Region D includes a transistor section 70, a diode section 80, and an active-side gate wiring 131. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are each an example of a trench section. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0057] An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is not shown in Fig. 2. In this example, contact holes 54 are provided in the interlayer insulating film so as to penetrate the interlayer insulating film. In Fig. 2, each contact hole 54 is hatched with diagonal lines.

[0058] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 does not need to be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a potential different from the potential of the emitter electrode 52 and the potential of the gate conductive portion.

[0059] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0060] The emitter electrode 52 is made of a material containing metal. FIG. 2 shows the area where the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as a metal alloy such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like below the region made of aluminum or the like. Furthermore, the contact hole may have a plug formed by embedding tungsten or the like so as to contact the barrier metal and aluminum or the like.

[0061] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width into an area where it does not overlap with the active side gate wiring 131. In this example, the well region 11 is provided away from the end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131. The well region 11 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the base region 14 is P- type, and the well region 11 is P+ type.

[0062] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0063] The gate trench portion 40 in this example may have two straight line portions 39 (portions of the trench that are straight along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a tip portion 41 that connects the two straight line portions 39. The extension direction in FIG. 2 is the Y-axis direction.

[0064] At least a portion of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0065] In the transistor section 70, the dummy trench section 30 is provided between each of the linear portions 39 of the gate trench section 40. One or more dummy trench sections 30 may be provided between each of the linear portions 39. The dummy trench section 30 may have a linear shape extending in the extension direction, and may have a linear section 29 and a tip section 31, similar to the gate trench section 40. The semiconductor device 100 shown in FIG. 2 includes both linear dummy trench sections 30 without tip sections 31 and dummy trench sections 30 with tip sections 31.

[0066] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0067] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between the trench portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench. In this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, the mesa portion simply referred to as a mesa portion refers to both the mesa portion 60 and the mesa portion 61.

[0068] A base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active-side gate wiring 131 is referred to as the base region 14-e. While FIG. 2 shows the base region 14-e located at one end of each mesa portion in the extension direction, a base region 14-e is also located at the other end of each mesa portion. In each mesa portion, at least one of a first-conductivity-type emitter region 12 and a second-conductivity-type contact region 15 may be provided in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0069] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0070] The contact regions 15 and the emitter regions 12 in the mesa portion 60 are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion 60 are alternately arranged along the extension direction of the trench portions (the Y-axis direction).

[0071] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extension direction of the trench portion (Y-axis direction). For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0072] The mesa portion 61 of the diode section 80 does not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61, a contact region 15 may be provided in contact with each of the base regions 14-e. In the region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61, a base region 14 may be provided. The base region 14 may be disposed in the entire region sandwiched between the contact regions 15.

[0073] A contact hole 54 is provided above each mesa portion. The contact hole 54 is arranged in a region sandwiched between the base regions 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in regions corresponding to the base region 14-e and the well region 11. The contact hole 54 may be arranged in the center of the arrangement direction (X-axis direction) of the mesa portions 60.

[0074] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2 , the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0075] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby improving the breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0076] Fig. 3 is a diagram showing an example of the e-e cross section in Fig. 2. The e-e cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0077] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact holes 54 described with reference to FIG. 2 .

[0078] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 passes through a contact hole 54 in the interlayer insulating film 38 and contacts the upper surface 21 of the semiconductor substrate 10. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.

[0079] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in each of the transistor section 70 and the diode section 80.

[0080] In the mesa portion 60 of the transistor section 70, an N+ type emitter region 12 and a P- type base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0081] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0082] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0083] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. That is, the accumulation region 16 has a higher donor concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0084] A P-type base region 14 is provided in the mesa portion 61 of the diode section 80 in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An accumulation region 16 may be provided below the base region 14 in the mesa portion 61.

[0085] In each of the transistor section 70 and the diode section 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Furthermore, the doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0086] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be located at the same depth as the chemical concentration peak of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0087] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0088] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as donors and acceptors in each region are not limited to the above-mentioned examples. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0089] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In regions where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these doped regions. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include trenches formed in the order of forming the trenches and then forming the doped regions.

[0090] As described above, the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30. The diode section 80 is provided with the dummy trench section 30, but is not provided with the gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0091] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and further inside than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0092] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0093] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0094] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a downwardly convex curved shape (a curved shape in cross section).

[0095] The semiconductor substrate 10 of this example includes silicon. The semiconductor substrate 10 may be a silicon substrate, or may be a silicon carbide substrate. The semiconductor substrate 10 is provided with a lifetime adjusting region 200. In this example, the lifetime adjusting region 200 is a region where the carrier lifetime is 3 μs or less. A region where the carrier lifetime is 2 μs or less may be the lifetime adjusting region 200, or a region where the carrier lifetime is 1 μs or less may be the lifetime adjusting region 200. The lifetime adjusting region 200 includes lifetime killers 202. The lifetime killers 202 are defects such as vacancies.

[0096] At least a portion of the lifetime adjusting region 200 may be provided in the diode section 80. The diode section 80 includes an anode region (in this example, the base region 14) provided in a region in contact with the upper surface 21 inside the semiconductor substrate 10, and a cathode region 82 provided in a region in contact with the lower surface 23 inside the semiconductor substrate 10.

[0097] 3, the lifetime adjusting region 200 is provided on the upper surface 21 side of the semiconductor substrate 10, over the entire diode section 80 and a portion of the transistor section 70. With this configuration, the reverse recovery time of the diode section 80 can be shortened, thereby reducing switching loss. However, the position and range in which the lifetime adjusting region 200 is provided are not limited to this. The lifetime adjusting region 200 can be provided in a region of the semiconductor substrate 10 where it is desired to adjust the carrier lifetime.

[0098] The lifetime adjusting region 200 may be provided locally in the depth direction of the semiconductor substrate 10. In this case, the distribution of the carrier lifetime in the depth direction of the semiconductor substrate 10 has a minimum value in the lifetime adjusting region 200. The local lifetime adjusting region 200 may be provided on the upper surface 21 side of the semiconductor substrate 10, on the lower surface 23 side, or on both the upper surface 21 side and the lower surface 23 side. The lifetime adjusting region 200 may be provided throughout the entire depth direction of the semiconductor substrate 10. The lifetime adjusting region 200 may be provided throughout the entire transistor section 70, or may be provided in a part of the diode section 80.

[0099] Forming the lifetime adjusting region 200 makes it possible to adjust the characteristics of the semiconductor device 100. On the other hand, when a current is passed through the semiconductor substrate 10 during actual operation of the semiconductor device 100, the concentration of the lifetime killer 202 in the lifetime adjusting region 200 changes over time, which may result in fluctuations in the carrier lifetime.

[0100] FIG. 4 is a diagram showing an example of the voltage-current characteristics of the diode section 80 before and after energizing the semiconductor substrate 10. In this example, energizing the semiconductor substrate 10 refers to passing a current in the depth direction of the semiconductor substrate 10. The horizontal axis in FIG. 4 represents the forward voltage applied to the diode section 80, and the vertical axis represents the current flowing through the diode section 80. When the lifetime adjusting region 200 is formed in the diode section 80, the number of carriers that can contribute to the current when the diode section 80 is on decreases, which increases the on-resistance and energy loss. For this reason, when the lifetime adjusting region 200 is formed, the concentration of the lifetime killer 202 and the on-resistance are controlled.

[0101] On the other hand, it has been confirmed that when a current is passed through the diode section 80, the on-resistance of the diode section 80 changes irreversibly as shown in Fig. 4. This is presumably because the concentration of the lifetime killer 202 changes due to the current passing through the diode section 80.

[0102] 5 is a diagram illustrating an example of the lifetime killer 202. The lifetime killer 202 includes a void V, a sub-void V, and a ２ , and C ｉ O ｉ C ｉ indicates interstitial carbon, and O ｉ indicates interstitial oxygen. ｉ O ｉ The defects are interstitial carbon and interstitial oxygen bonds, and the lifetime killer 202 may include all of these defects.

[0103] In FIG. 5, the void V and the double void V ２ , and C ｉ O ｉ An example of a defect level is shown. Ｃ is the energy of the bottom of the conduction band in the semiconductor substrate 10, and E Ｖ is the energy at the top of the valence band, and E ｉ is the Fermi level. Vacancy V and divacancy V ２ acts as an electron trap, and C ｉ O ｉ The defects act as hole traps.

[0104] Carbon and oxygen penetrate into the semiconductor substrate 10 containing silicon during the growth of the ingot. Also, in the manufacturing process of the semiconductor device 100, oxygen in the atmosphere diffuses into the semiconductor substrate 10 from a main surface such as the upper surface 21. When charged particles such as hydrogen ions, helium ions, or electrons are implanted into such a semiconductor substrate 10, carbon and oxygen are introduced into the semiconductor substrate 10. ｉ O ｉ Defects are easily formed. For example, by implanting hydrogen ions or helium ions into a predetermined depth position in the semiconductor substrate 10, a lifetime adjusting region 200 is formed in the vicinity of that depth position. Also, by passing an electron beam through the semiconductor substrate 10 in the depth direction, the lifetime adjusting region 200 is formed over the entire semiconductor substrate 10. The phenomenon in which the concentration of lifetime killers changes when a current is passed through the semiconductor substrate 10 is called vacancies V, subvacancies V, and the like. ２ , and C ｉ O ｉ This is thought to be caused by a change in the defect concentration.

[0105] The carbon chemical concentration of the semiconductor substrate 10 is 1×10 １４ / cm ３ The carbon chemical concentration of the semiconductor substrate 10 may be 5×10 or more. １４ / cm ３ or more, and may be 1×10 １５ / cm ３ The carbon chemical concentration of the semiconductor substrate 10 may be 1×10 １６ / cm ３ may be less than or equal to 5×10 １５ / cm ３ may be less than or equal to 3×10 １５ / cm ３ may be equal to or less than 2×10 １５ / cm ３ The oxygen chemical concentration of the semiconductor substrate 10 may be 1×10 １６ / cm ３ The oxygen chemical concentration of the semiconductor substrate 10 may be 2×10 １６ / cm ３ or more, and may be 5×10 １６ / cm ３ or more, and may be 1×10 １７ / cm３ or more, and may be 2×10 １７ / cm ３ or more, and may be 3×10 １７ / cm ３ or more, and may be 5×10 １７ / cm ３ or more, and may be 7×10 １７ / cm ３ The oxygen chemical concentration of the semiconductor substrate 10 may be 1×10 １８ / cm ３ may be equal to or less than 7×10 １７ / cm ３ may be less than or equal to 5×10 １７ / cm ３ may be less than or equal to 3×10 １７ / cm ３ It may be the following:

[0106] FIG. 6 shows the C ｉ O ｉ 6 is a diagram showing a first-principles simulation analysis of the change in the energy of the lifetime killer 202 with respect to the change in the structure of the lifetime killer 202 including defects and vacancies V. The horizontal axis in FIG. ｉ O ｉ The graph shows the change in structure due to the positions of defects and vacancies V, and the vertical axis indicates the energy of the lifetime killer 202. The energy of the lifetime killer 202 in the initial state (structure 1) is approximately 4.2 eV. In the initial state, the interstitial carbon C ｉ and interstitial oxygen O ｉ is combined to C ｉ O ｉ It functions as a defect.

[0107] When the structure of the lifetime killer 202 is changed, the interstitial carbon C ｉ The structure in which the position of the atom near the vacancy V changes when interstitial carbon C enters the substitutional position of silicon has the highest energy, with a peak of 0.7 eV (structure 6). ｉ is interstitial oxygen O ｉ and a substitutional carbon C arranged at a substitutional position of silicon. ｓ In the most stable state of the structure, the energy is sufficiently lower than that of the initial state (structure 16).ｉ O ｉ The defect is a substitutional carbon C Ｓ and interstitial oxygen O ｉ The reaction barrier for decomposition into the more stable substituted carbon C is about 0.7 eV. Ｓ and interstitial oxygen O ｉ It can be seen that the reaction of changing the structure progresses. ｉ O ｉ The defect is a substitutional carbon C Ｓ and interstitial oxygen O ｉ It is believed that a decomposition reaction occurs, and the concentration of the lifetime killer 202 decreases.

[0108] FIG. 7 is a diagram showing a simulation analysis of the energy state due to the change in structure when the position of the vacancy V changes in the lifetime killer 202 containing the vacancy V. As a transition state during the change in the position of the vacancy V, an energy increase of 0.26 eV from the energy of the initial state was observed (structure 4). From FIG. 7, it can be seen that the diffusion barrier for the diffusion of the vacancy V is about 0.26 eV. The vacancy V moves easily and C ｉ O ｉ Reacts with defects and C ｉ O ｉ It is presumed that the defects are decomposed. Therefore, when a current is applied to the semiconductor substrate 10, the vacancies V are diffused and the C ｉ O ｉ It is believed that the decomposition of the defects occurs and the concentration of the lifetime killer 202 decreases.

[0109] FIG. 8 is a diagram showing an example of the spectrum of emitted light obtained when an electron beam or light is irradiated onto the lifetime adjusting region 200 according to the reference example. In the reference example of FIG. 8, the spectra before and after energization of the semiconductor substrate 10 are compared. In FIG. 8, the spectrum before energization of the semiconductor substrate 10 is shown by a dashed line, and the spectrum after energization is shown by a solid line. The horizontal axis in FIG. 8 represents the wavelength of the emitted light, and the vertical axis represents the luminescence intensity (spectral intensity) of the emitted light at each wavelength. The spectrum in FIG. 8 was measured by a cross-sectional CL (cathodoluminescence) method. The spectrum of emitted light may also be measured by other methods, such as a PL (photoluminescence) method.

[0110] In the emission spectrum, C ｉ O ｉ The emission intensity due to defects is defined as the first emission intensity, and the emission intensity at the silicon band edge is defined as the second emission intensity. The first emission intensity is the maximum value of the emission intensity in the range of 1560 nm to 1580 nm. The first emission intensity may be a maximum value (peak value) within that range. In the example of FIG. 8 , the first emission intensity before energization is defined as Sa, and the first emission intensity after energization is defined as Sb. The second emission intensity is the maximum value of the emission intensity in the range of 1117 nm to 1137 nm. The second emission intensity may be a maximum value (peak value) within that range. In the example of FIG. 8 , the second emission intensity is defined as S2.

[0111] Since the emission intensity at the band edge of silicon does not change before and after the current is passed through the semiconductor substrate 10, the second emission intensity S2 does not change before and after the current is passed through. On the other hand, the first emission intensity decreases from Sa to Sb before and after the current is passed through. This is because the current passes through C ｉ O ｉ This indicates that defects have been reduced. ｉ O ｉ When the number of defects decreases, the carrier lifetime and the like change, which may cause the characteristics of the semiconductor device 100 to change after the semiconductor device 100 begins to be used in practice.

[0112] 9 is a diagram showing an example of change in the emission intensity ratio before and after the current is passed through the semiconductor substrate 10. The emission intensity ratio is calculated by dividing the C ｉ O ｉThis is a value obtained by dividing the first emission intensity derived from defects by the second emission intensity at the band edge of silicon. For example, in the example of FIG. 8, the emission intensity ratio before energization is Sa / S2, and the emission intensity ratio after energization is Sb / S2. In the example of FIG. 9, the emission intensity ratio was measured by the cross-sectional CL method in a depth range of 10 μm to 50 μm from the top surface 21 of the semiconductor substrate 10. The lifetime adjusting region 200 in this example is provided at a depth of 20 μm from the top surface 21. In FIG. 9, the measured values ​​of the emission intensity ratio before energization are plotted as squares, and the measured values ​​of the emission intensity ratio after energization are plotted as circles.

[0113] The black plots and the white plots in FIG. 9 represent different samples. In both samples, the emission intensity ratio drops significantly when a current is applied. For this reason, the characteristics of the semiconductor device 100 may change significantly after the semiconductor device 100 begins to be used. From the example in FIG. 9, it is clear that the C ｉ O ｉ It can be inferred that defects are reduced.

[0114] In one embodiment of the present invention, C ｉ O ｉ By reducing the number of defects, fluctuations in the characteristics of the semiconductor device 100 over time during actual use can be suppressed. ｉ O ｉ The defect concentration fluctuates significantly in a relatively short period from the start of current application, and the fluctuation becomes more gradual as the time from the start of current application passes. ｉ O ｉ By reducing the number of defects, fluctuations in the characteristics of the semiconductor device 100 can be effectively suppressed.

[0115] 10 is a diagram showing a portion of a manufacturing process for a semiconductor device 100 according to one embodiment of the present invention. The manufacturing process in this example includes a charged particle beam irradiation step S1002, a light irradiation step S1006, and an electrode formation step S1008. Prior to the charged particle beam irradiation step S1002, at least a portion of the internal structure of the semiconductor substrate 10 may be formed. The internal structure refers to, for example, multiple trench portions and doped regions such as the emitter region 12 and the base region 14 formed by implanting dopants.

[0116] In the charged particle beam irradiation step S1002, charged particles are implanted into the semiconductor substrate 10 containing silicon by irradiating the semiconductor substrate 10 with a charged particle beam, thereby forming a lifetime adjusting region 200 in which the carrier lifetime is reduced. As described above, the charged particles are hydrogen ions, helium ions, electrons, or the like. In the charged particle beam irradiation step S1002, the charged particles may be implanted from the upper surface 21 of the semiconductor substrate 10, or may be implanted from the lower surface 23. In the charged particle beam irradiation step S1002, the lifetime adjusting region 200 may be formed locally in a portion of the semiconductor substrate 10 in the depth direction, or the lifetime adjusting region 200 may be formed throughout the entire semiconductor substrate 10 in the depth direction.

[0117] In the light irradiation step S1006, after the charged particles are implanted into the semiconductor substrate 10, the lifetime adjusting region 200 is irradiated with light having an energy of 0.7 eV or more and 1.1 eV or less. In S1006, the light is irradiated onto at least a region overlapping the lifetime adjusting region 200 in the XY plane. In S1006, the light may be irradiated onto the entire upper surface 21 or the entire lower surface 23 of the semiconductor substrate 10. By irradiating the lifetime adjusting region 200 with light having an energy of 0.7 eV or more, as described with reference to FIGS. 6 and 7 , CiOi defects can be reduced in advance during the manufacturing process. This allows CiOi defects, which decrease in a relatively short period after the start of current application, to be reduced in advance during the manufacturing process, thereby suppressing abrupt fluctuations in the characteristics of the semiconductor device 100 after current application. A reduction in CiOi defects increases the carrier lifetime. Therefore, it is preferable to determine the amount of charged particle irradiation in S1002 taking into account the reduction in CiOi defects. The energy of the light irradiated in S1006 may be 0.75 eV or more, 0.8 eV or more, or 0.85 eV or more.

[0118] If the energy of the light is greater than 1.1 eV, the energy will be greater than the band gap of silicon. As a result, at least a portion of the light will be absorbed by the silicon of the semiconductor substrate 10. Therefore, by setting the energy of the light to 1.1 eV or less, it is possible to efficiently reduce C i O i defects. The energy of the light irradiated in S1006 may be 1.05 eV or less, 1.0 eV or less, or 0.95 eV or less.

[0119] The light irradiated in S1006 has a wavelength λ corresponding to the magnitude of its energy. The wavelength λ is defined by the following formula: E is the energy of the light, h is Planck's constant, and c is the speed of light. λ = hc / E As an example, the wavelength of the light is 1.1 μm or more and 1.7 μm or less. The light may be laser light.

[0120] In S1006, the light is irradiated onto a region including the lifetime adjustment region 200. In S1006, the light may be condensed and irradiated at a depth position of the lifetime adjustment region 200. By condensing the light at a depth position of the lifetime adjustment region 200, the light can be selectively irradiated onto a region where many CiOi defects exist, thereby efficiently reducing the CiOi defects. In S1006, the light may be irradiated by passing through the semiconductor substrate 10. This makes it possible to reduce CiOi defects throughout the entire depth direction of the semiconductor substrate 10. In S1006, the light may be irradiated locally and entirely onto the semiconductor substrate 10.

[0121] In S1006, the light may be irradiated onto the region including the lifetime adjustment region 200 for a period of 100 nsec or more and 10 hours or less. When the light is sequentially focused at multiple depth positions, this period is the period during which the light is irradiated onto one depth position. CiOi defects decompose in a relatively short period. Therefore, by irradiating the light for 100 nsec or more, the CiOi defects can be reduced. This period may be 1 minute or more, 30 minutes or more, or even 1 hour or more. The longer this period, the more the fluctuation in the characteristics of the semiconductor device 100 after the semiconductor substrate 10 is energized can be suppressed. On the other hand, as the period is extended, the amount of reduction in CiOi defects tends to saturate. Therefore, by setting the period to 10 hours or less, the CiOi defects can be efficiently reduced while shortening the manufacturing process. This period may be 8 hours or less, or may be 6 hours or less.

[0122] In S1006, the lifetime adjusting region 200 may be irradiated with light while the semiconductor substrate 10 is heated to a first temperature of 100°C or higher and 400°C or lower. Irradiating the semiconductor substrate 10 with light while it is heated can promote the reduction of C1Oi defects. The first temperature may be 200°C or higher, 250°C or higher, or 300°C or higher. The first temperature may be 350°C or lower, or 330°C or lower.

[0123] In S1006, the period during which the semiconductor substrate 10 is heated to the first temperature may be 10 minutes or more and 10 hours or less. The semiconductor substrate 10 is irradiated with light for at least a part of the period or for the entire period. The period during which the semiconductor substrate 10 is heated to the first temperature may be 30 minutes or more, or may be 1 hour or more. The period may be 8 hours or less, or may be 6 hours or less.

[0124] In the electrode formation step S1008, a metal electrode is formed on at least one of the upper surface 21 and the lower surface 23 of the semiconductor substrate 10. This electrode is, for example, the emitter electrode 52 or the collector electrode 24. In steps S1002 and S1006, no metal electrode is formed on at least the surface irradiated with charged particles and the surface irradiated with light. This process allows the manufacture of a semiconductor device 100 in which CiOi defects have been reduced in advance. Furthermore, by reducing CiOi defects through light irradiation, the CiOi defects can be reduced in a shorter time than by applying current. Furthermore, by concentrating light, CiOi defects can also be reduced locally.

[0125] 11 is a diagram showing another example of the manufacturing process of the semiconductor device 100. The manufacturing process of this example differs from the example of FIG. 10 in that it further includes a heat treatment step S1004. The other steps are the same as those of the example of FIG.

[0126] The heat treatment step S1004 is performed after the charged particles are injected in S1002 and before the light irradiation in S1006. The semiconductor substrate 10 is heated to a second temperature higher than the first temperature. The second temperature may be 350°C or higher and 420°C or lower. The second temperature may be 360°C or higher, or 370°C or higher. The second temperature may be 410°C or lower, or 400°C or lower. S1004 can repair excess defects formed in S1002. For example, it can repair defects in a passage region through which the charged particles pass, between the surface irradiated with the charged particles (e.g., the upper surface 21) and the lifetime adjusting region 200.

[0127] By setting the first temperature in S1006 lower than the second temperature, it is possible to prevent the lifetime killer from being excessively reduced and the carrier lifetime from being excessively restored by the process of S1006. On the other hand, by heating the semiconductor substrate 10 to a relatively low temperature in S1006, the movement of vacancies V is promoted, and the decomposition of C1Oi defects is facilitated.

[0128] 12A is a diagram showing an example of the characteristics of semiconductor devices according to Examples 1 to 3 of the present invention and a semiconductor device according to a comparative example. Examples 1 to 3 were manufactured using the manufacturing process described in FIG. 11. However, the light irradiation position and heating temperature in S1006 were different in each example. Furthermore, in the comparative example, the step of S1006 was not performed.

[0129] The conditions of the manufacturing process before S1002 are as follows: The semiconductor substrate is an n-type silicon substrate. The carbon concentration of the silicon substrate is 2×10 １５ / cm ３ , oxygen concentration is 3×10 １７ / cm ３ A vertical PN diode was formed on the semiconductor substrate. Specifically, boron ions were implanted into the top surface and phosphorus ions were implanted into the bottom surface, and the semiconductor substrate was then annealed at 1100°C to activate the dopants.

[0130] In step S1002, helium ions are irradiated from the upper surface of the semiconductor substrate at a dose of 2×10 １１ / cm ２ In step S1004, the semiconductor substrate was annealed at 350° C. for 1 hour.

[0131] In Examples 1 to 3, 0.9 eV light was irradiated in step S1006. In Examples 1 and 3, the light was not focused but passed through the semiconductor substrate 10 in the depth direction. In Example 2, the light was focused at the depth position of the lifetime adjusting region 200 (20 μm in this example). In Examples 1 and 2, the heating temperature in S1006 was set to 300° C., and the light irradiation and heating period was set to 5 hours. In Example 3, heating was not performed in S1006.

[0132] For Examples 1 to 3 and Comparative Example 1, the emission intensity ratio before energization and the change ΔV in the forward voltage of the diode section 80 before and after energization are shown. Ｆ The current flow was measured at 940 A / cm2 for the diode section 80. ２ A current equivalent to 1000 kJ / cm was passed for 50 hours. The luminescence intensity ratio was measured at a depth of 20 μm.

[0133] The emission intensity ratio in Comparative Example 1 is 25, and the forward voltage fluctuation ΔV Ｆ On the other hand, in Example 3 in which the semiconductor substrate was irradiated with light, the emission intensity ratio was 15, and the forward voltage fluctuation ΔV Ｆ By irradiating the semiconductor substrate with light, the C1Oi defects were reduced until the emission intensity ratio reached 15, and as a result, ΔV Ｆ It can be estimated that the difference is smaller than that in Comparative Example 1.

[0134] FIG. 12B shows the emission intensity ratio on the horizontal axis and ΔV when current is applied on the vertical axis for Examples 1 to 3 and Comparative Example 1 in FIG. 12A. Ｆ 1 is a diagram plotting the light-emission intensity ratio. As shown in Examples 1 to 3, the light-emission intensity ratio can be reduced by appropriately combining the light-collection depth, heating temperature, time, etc. The light-emission intensity ratio of the semiconductor device may be 15 or less. This makes it possible to suppress fluctuations in the characteristics of the semiconductor device after energization. The light-emission intensity ratio may be 12 or less, or may be 10 or less. This makes it possible to further suppress fluctuations in the characteristics of the semiconductor device after energization. The light-emission intensity ratio is 1 or more. The light-emission intensity ratio may be 2 or more, or may be greater than 2. The numerical range of the light-emission intensity ratio specified in this specification applies to the light-emission intensity ratio at the depth position of the lifetime adjustment region 200, but the numerical range of the light-emission intensity ratio may be satisfied throughout the entire depth direction of the drift region 18. Furthermore, the numerical range of the light-emission intensity ratio may be satisfied throughout the entire depth direction of the semiconductor substrate.

[0135] When the lifetime adjustment region 200 exhibits a minimum value of the carrier lifetime, the depth position of the minimum value may be taken as the depth position of the lifetime adjustment region 200. When the portion of the lifetime adjustment region 200 exhibiting the minimum value of the carrier lifetime is continuous in the depth direction, the center of the portion in the depth direction may be taken as the depth position of the lifetime adjustment region 200.

[0136] In Example 2, in which the semiconductor substrate was irradiated with light while being heated, the emission intensity ratio was 8, and the forward voltage fluctuation ΔV Ｆ By irradiating the semiconductor substrate with light while it was heated, the number of C1Oi defects was reduced until the emission intensity ratio reached 8, and as a result, ΔV Ｆ It can be estimated that the emission intensity ratio of the semiconductor device may be 8 or less.

[0137] In Example 3, in which the semiconductor substrate was heated and irradiated with concentrated light, the emission intensity ratio was 5, and the forward voltage fluctuation ΔV Ｆ By irradiating the semiconductor substrate with light while it is heated, the number of C1Oi defects is reduced until the emission intensity ratio reaches 5, and as a result, ΔV Ｆ The emission intensity ratio of the semiconductor device may be 5 or less.

[0138] When the emission intensity ratio decreases from 15 to 8, ΔV Ｆ was significantly reduced, whereas when the emission intensity ratio decreased from 8 to 5, ΔV Ｆ The decrease in the emission intensity ratio is relatively small. The emission intensity ratio may be greater than 5, or may be equal to or greater than 6. The emission intensity ratio may be equal to or greater than 6 and equal to or less than 12.

[0139] FIG. 13 shows the helium concentration distribution along the ff line in FIG. 3, C ｉ O ｉ 1 is a diagram showing an example of a concentration distribution and a luminescence intensity ratio distribution. Line ff is a straight line that passes through the lifetime adjusting region 200 and is parallel to the Z axis. ｉ O ｉ The concentration distribution and the luminescence intensity ratio distribution are similar distributions, and are therefore shown in the same graph.ｉ O ｉ The concentration distribution and the emission intensity ratio distribution are shown by dashed lines, and the distribution after irradiation is shown by a solid line.

[0140] In this example, helium ions are implanted into the lifetime adjusting region 200. The helium concentration shows a maximum value at the implantation position Zd of the helium ions. In addition, in the light irradiation step S1006, the semiconductor substrate 10 is irradiated with light over the entire depth direction. As a result, C ｉ O ｉ The concentration and the emission intensity ratio are reduced throughout the semiconductor substrate 10. ｉ O ｉ The concentration distribution and the emission intensity ratio distribution may exhibit a maximum value at the depth position Zd. As described above, the maximum value of the emission intensity ratio may be 15 or less, 12 or less, or 8 or less.

[0141] FIG. 14 shows the helium concentration distribution along the ff line. ｉ O ｉ 13A and 13B are diagrams showing other examples of concentration distribution and luminescence intensity ratio distribution. In this example, in the light irradiation step S1006, light is focused and irradiated at the depth position Zf of the lifetime adjusting region 200. Other conditions are the same as those in the example of FIG. 13. The light focusing position Zf may be the same as the helium ion implantation position Zd. In another example, the focusing position Zf and the implantation position Zd may be spaced apart by 10 μm or less, by 5 μm or less, or by 3 μm or less.

[0142] In this example, the distribution of the emission intensity ratio in the depth direction of the semiconductor substrate 10 has a minimum value Rmin in the lifetime adjustment region 200. The depth position of the minimum value Rmin is the light collection position Zf. Furthermore, the emission intensity ratio may show a maximum value Rmax at a position deeper than the position Zf where the emission intensity ratio shows the minimum value Rmin. A position deeper than the position Zf refers to a position closer to the center of the depth direction of the semiconductor substrate 10 than the position Zf. The helium concentration does not need to have a minimum value at the position Zf. The helium concentration distribution may have an upwardly convex shape in the range including the position Zf, and the emission intensity ratio distribution may have a downwardly convex shape in the range including the position Zf.

[0143] FIG. 15 shows the helium concentration distribution along the ff line. ｉ O ｉ 14A and 14B are diagrams showing other examples of the concentration distribution and the emission intensity ratio distribution. This example differs from the example of FIG. 14 in that the helium concentration distribution has a relatively narrow width. Other conditions are the same as those of the example of FIG. 14. As described above, the focusing position Zf and the injection position Zd may be the same or different.

[0144] 16 is a diagram showing the relationship between the dose of helium ions and the emission intensity ratio. In this example, helium ions are implanted to form the lifetime adjusting region 200. Therefore, the lifetime adjusting region 200 contains helium.

[0145] 16, the characteristic before the light irradiation in S1006 is shown by a thick broken line, and the characteristic after the light irradiation is shown by a thick solid line. As an example, when the dose of helium ions is 2×10 １１ / cm ２ In this case, the emission intensity ratio before light irradiation was 25, and the emission intensity ratio after light irradiation was 12. As described above, the characteristics of the semiconductor device before light irradiation change significantly when a current is applied, whereas the characteristics of the semiconductor device 100 after light irradiation change only slightly even when a current is applied.

[0146] Increasing the helium dose increases the amount of C formed. ｉ O ｉ The defect concentration increases. Therefore, increasing the helium dose increases the emission intensity ratio. The amount of decrease in the emission intensity ratio may be controlled according to the helium dose. The amount of decrease in the emission intensity ratio can be controlled by the amount of light irradiation, irradiation time, heating conditions, etc. in S1006. For example, if the value obtained by dividing the emission intensity ratio by the helium dose in the lifetime adjustment region 200 is 6×10 －１１ cm ２ The helium dose may be determined by the chemical concentration of helium ( / cm ３ ) over the entire depth direction in the region where the carrier lifetime is 3 μm or less. The value obtained by dividing the emission intensity ratio by the helium dose is 4×10 －１１ cm ２ may be equal to or less than 1×10－１１ cm ２ It may be the following:

[0147] In each example herein, the carrier concentration measured by the SR method in the lifetime adjusting region 200 may be lower than the phosphorus chemical concentration or antimony chemical concentration in the lifetime adjusting region 200. In the lifetime adjusting region 200, the carrier lifetime is short, and therefore the resistance value is high. Therefore, the carrier concentration measured by the SR method is lower than the chemical concentration of the dopant (e.g., phosphorus or antimony) in the lifetime adjusting region 200.

[0148] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0149] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0150] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Accumulation region, 18...Drift region, 20...Buffer region, 21...Upper surface, 22...Collector region, 23...Lower surface, 24...Collector electrode, 29...Straight portion, 30...Dummy trench portion, 31...Tip portion, 32...Dummy insulating film, 34...Dummy conductive portion, 38...Interlayer insulating film, 39...Straight portion, 40...Gate trench portion, 41...Tip End, 42...gate insulating film, 44...gate conductive portion, 52...emitter electrode, 54...contact hole, 60, 61...mesa portion, 70...transistor portion, 80...diode portion, 81...extension region, 82...cathode region, 90...edge termination structure portion, 100...semiconductor device, 130...periphery gate wiring, 131...active side gate wiring, 160...active portion, 162...edge, 164...gate pad, 200...lifetime adjustment region, 202...lifetime killer

Claims

1. A semiconductor substrate containing silicon; and a lifetime adjusting region provided in the semiconductor substrate, the lifetime of which is 3 μs or less, wherein the lifetime adjusting region is irradiated with an electron beam or light, and the spectrum of emitted light obtained is C ｉ O ｉ A semiconductor device in which an emission intensity ratio obtained by dividing a first emission intensity derived from defects by a second emission intensity at the band edge of silicon is 1 or more and 15 or less.

2. The semiconductor device according to claim 1, wherein the emission intensity ratio is 12 or less.

3. The semiconductor device according to claim 1, wherein the emission intensity ratio is greater than 2.

4. The lifetime adjusting region contains helium, and a value obtained by dividing the emission intensity ratio by the dose of helium in the lifetime adjusting region is 6×10 －１１ cm ２ 2. The semiconductor device according to claim 1, wherein:

5. The semiconductor device according to claim 1, wherein the distribution of the emission intensity ratio in the depth direction of the semiconductor substrate has a minimum value in the lifetime adjusting region.

6. The semiconductor device according to claim 5, wherein the emission intensity ratio exhibits a maximum value at a position deeper than the position where the emission intensity ratio exhibits the minimum value.

7. The semiconductor device according to claim 1, wherein the carrier concentration measured by the SR method in said lifetime adjusting region is lower than the phosphorus chemical concentration and the antimony chemical concentration.

8. The semiconductor device according to claim 1, wherein the distribution of the carrier lifetime in the depth direction of the semiconductor substrate has a minimum value in the lifetime adjusting region.

9. A semiconductor device according to any one of claims 1 to 8, wherein the semiconductor substrate has an upper surface and a lower surface, and further comprises a diode section including an anode region provided in a region inside the semiconductor substrate that contacts the upper surface, and a cathode region provided in a region inside the semiconductor substrate that contacts the lower surface, and at least a portion of the lifetime adjusting region is provided in the diode section.

10. The carbon chemical concentration of the semiconductor substrate is 1×10 １４ / cm ３ The semiconductor device according to any one of claims 1 to 8.

11. The oxygen chemical concentration of the semiconductor substrate is 1×10 １６ / cm ３ That's it, 1 x 10 １８ / cm ３ 9. The semiconductor device according to claim 1, wherein:

12. A method for manufacturing a semiconductor device, comprising injecting charged particles into a semiconductor substrate containing silicon to form a lifetime adjusting region in which the carrier lifetime is reduced, and after the injection of the charged particles, irradiating the lifetime adjusting region with light having an energy of 0.7 eV or more and 1.1 eV or less.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the light is irradiated onto the lifetime adjusting region for a period of 100 nsec or more and 10 hours or less.

14. The method for manufacturing a semiconductor device according to claim 12, wherein the semiconductor substrate is heated to a first temperature of 100° C. or higher and 400° C. or lower, and the lifetime adjusting region is irradiated with the light.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the semiconductor substrate is heated for a period of not less than 10 minutes and not more than 10 hours.

16. The method for manufacturing a semiconductor device according to claim 14, wherein the semiconductor substrate is heated to a second temperature higher than the first temperature after the charged particles are injected and before the light is irradiated.

17. The method for manufacturing a semiconductor device according to any one of claims 12 to 16, wherein the light is focused and irradiated to the depth of the lifetime adjusting region.

18. The method for manufacturing a semiconductor device according to any one of claims 12 to 16, wherein the light is irradiated by passing through the semiconductor substrate.

19. The method for manufacturing a semiconductor device according to any one of claims 12 to 16, wherein the charged particles are electrons, hydrogen ions, or helium ions.

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