Display panel and display apparatus

Abstract

Disclosed in the present application are a display panel and a display apparatus. By arranging one column of pixel circuit to be correspondingly and electrically connected to two data signal lines, and using the two data signal lines to achieve interleaved writing of data signals to the pixel circuit, the impact of jumping caused by the on / off of each row of pixel circuit on the same data signal line can be reduced, thereby improving circuit stability. In addition, by arranging a first connection line segment and a second connection line segment in an active area, at least part of the data signal lines are electrically connected to fanout wires via the first connection line segment and the second connection line segment in the active area, i.e., wire layout for transmitting data signals to at least part of the data signal lines is implemented in the active area, i.e., part of the fanout wires are arranged in the active area (Fanout in Active Area, FIAA), so as to provide a compression space for a bottom bezel of the display panel, thereby helping to achieve narrow bezels of display panels.

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411256455.X, filed on September 6, 2024, entitled “A display panel and display device”, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of display, and in particular, to a display panel and display device. BACKGROUND

[0004] With the continuous development of display technology, display panels are rapidly developing towards higher resolution, better display effect and narrower frame. In order to achieve a narrower frame, the technology of Fanout in AA (FIAA) is usually used. However, high-resolution display panels usually have high pixel density (PPI), not only the pixel space is reduced, but also the number of data signal lines for FIAA switching increases, therefore, it is very difficult to arrange the fan-out lines in the display area to switch the data signal lines.

[0005] SUMMARY

[0006] To solve the above technical problems, the embodiments of the present application provide a display panel and display device,

[0007] To achieve the above purpose, the embodiments of the present application provide the following technical solutions:

[0008] A display panel, comprising a display area and a non-display area at least partially surrounding the display area;

[0009] The display area comprises an array of pixel circuits, and a column of pixel circuits is electrically connected to two data signal lines, the data signal lines extend along a first direction and are arranged along a second direction, the first direction and the second direction intersect;

[0010] The display area comprises a first display area and a second display area located on at least one side of the first display area along the second direction, and the non-display area comprises a fan-out area located on one side of the display area along the first direction, the fan-out area comprises a plurality of fan-out lines, and the data signal lines are electrically connected to the fan-out lines;

[0011] The display area includes a plurality of first auxiliary wires extending along a first direction and a plurality of second auxiliary wires extending along a second direction, at least part of the first auxiliary wires include first connection line segments, and at least part of the second auxiliary wires include second connection line segments, and the data signal lines in the second display area are electrically connected to the fan-out wires through the first connection line segments and the second connection line segments.

[0012] A display device includes the display panel.

[0013] Compared with the prior art, the technical solution has the following advantages:

[0014] The display panel provided by the embodiment of the application can reduce the influence of the switching of each row of pixel circuits on the same data signal line and improve the stability of the circuit by electrically connecting two data signal lines to one column of pixel circuits and writing data signals into the pixel circuits by the two data signal lines; and the first connection line segments and the second connection line segments are arranged in the display area, so that at least part of the data signal lines are electrically connected to the fan-out wires through the first connection line segments and the second connection line segments in the display area, that is, the wiring of the transmission of data signals to at least part of the data signal lines is performed in the display area, and part of the fan-out wires are arranged in the display area (Fanout in AA, FIAA), so that the compression space of the lower frame of the display panel is provided, and the narrow frame of the display panel is facilitated to be realized. BRIEF DESCRIPTION OF DRAWINGS

[0015] FIG. 1 is a top view of a display panel provided by an embodiment of the application;

[0016] FIG. 2 is a top view of another display panel provided by an embodiment of the application;

[0017] FIG. 3 is a partial structure diagram of a display panel provided by an embodiment of the application;

[0018] FIG. 4 is a top view of another display panel provided by an embodiment of the application;

[0019] FIG. 5 is a partial enlarged top view of a display panel provided by an embodiment of the application;

[0020] FIG. 6 is a partial layout structure diagram of a display panel provided by an embodiment of the application;

[0021] FIG. 7 is a partial layout structure diagram of a data signal line ND, a first auxiliary wire D1 and a second auxiliary wire D2 in the layout structure shown in FIG. 6;

[0022] FIG. 8 is a partial layout structure diagram of a larger range than FIG. 7;

[0023] Fig. 9 is a schematic diagram of a circuit structure of the pixel circuit 10 in the layout structure shown in Fig. 6;

[0024] Fig. 10 is a schematic diagram of a partial cross section of a display panel according to an embodiment of the present application;

[0025] Figs. 11a-11h are schematic diagrams of layout structures of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG, the metal layer M2, the metal layer M3, and the metal layer M4, respectively, in the layout structure shown in Fig. 6;

[0026] Fig. 12a is a schematic diagram of layout structures of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG, and the metal layer M2 in the layout structure shown in Fig. 6;

[0027] Fig. 12b is a schematic diagram of layout structures of the metal layer M3 and the metal layer M4 in the layout structure shown in Fig. 6;

[0028] Fig. 13 is a schematic diagram of a grid of the first reference signal line ref1 and the second reference signal line ref2 in the layout structure shown in Fig. 6;

[0029] Fig. 14 is a schematic diagram of a partial layout structure of a display panel according to an embodiment of the present application;

[0030] Fig. 15 is a schematic diagram of a partial layout structure of the data signal line ND, the first auxiliary trace D1, and the second auxiliary trace D2 in the layout structure shown in Fig. 14;

[0031] Fig. 16 is a schematic diagram of a partial layout structure in a larger range than Fig. 15;

[0032] Fig. 17 is a schematic diagram of a circuit structure of the pixel circuit 10 in the layout structure shown in Fig. 14;

[0033] Figs. 18a-18h are schematic diagrams of layout structures of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG, the metal layer M2, the metal layer M3, and the metal layer M4, respectively, in the layout structure shown in Fig. 14;

[0034] Fig. 19a is a schematic diagram of layout structures of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG, and the metal layer M2 in the layout structure shown in Fig. 14;

[0035] Fig. 19b is a schematic diagram of layout structures of the metal layer M2, the metal layer M3, and the metal layer M4 in the layout structure shown in Fig. 14;

[0036] Fig. 20 is a schematic diagram of a grid of the bias signal line DVH and the second reference signal line ref2 in the layout structure shown in Fig. 14;

[0037] FIG. 21 is a partial layout structure diagram of a display panel according to an embodiment of the present application;

[0038] FIG. 22 is a partial layout structure diagram of data signal lines ND, first auxiliary wires D1 and second auxiliary wires D2 in the layout structure shown in FIG. 21;

[0039] FIG. 23 is a partial layout structure diagram of a larger range than FIG. 22;

[0040] FIGS. 24a-24h are layout structure diagrams of an active layer poly, a metal layer M1, a metal layer MC, an oxide layer IGZO, a metal layer MG, a metal layer M2, a metal layer M3 and a metal layer M4 in the layout structure shown in FIG. 21, respectively;

[0041] FIG. 25a is a layout structure diagram of an active layer poly, a metal layer M1, a metal layer MC, an oxide layer IGZO, a metal layer MG and a metal layer M2 in the layout structure shown in FIG. 21;

[0042] FIG. 25b is a layout structure diagram of a metal layer M2, a metal layer M3 and a metal layer M4 in the layout structure shown in FIG. 21;

[0043] FIG. 26 is a grid diagram of bias signal lines DVH and second reference signal lines ref2 in the layout structure shown in FIG. 21;

[0044] FIG. 27 is an arrangement diagram of data signal lines ND and first auxiliary wires D1 in a display panel according to an embodiment of the present application;

[0045] FIG. 28 is a partial layout structure diagram of a display panel according to an embodiment of the present application;

[0046] FIG. 29 is a partial layout structure diagram of data signal lines ND, first auxiliary wires D1 and second auxiliary wires D2 in the layout structure shown in FIG. 28;

[0047] FIG. 30 is a partial layout structure diagram of a larger range than FIG. 29;

[0048] FIGS. 31a-31h are layout structure diagrams of an active layer poly, a metal layer M1, a metal layer MC, an oxide layer IGZO, a metal layer MG, a metal layer M2, a metal layer M3 and a metal layer M4 in the layout structure shown in FIG. 28, respectively;

[0049] FIG. 32a is a layout structure diagram of an active layer poly, a metal layer M1, a metal layer MC, an oxide layer IGZO, a metal layer MG and a metal layer M2 in the layout structure shown in FIG. 28;

[0050] Fig. 32b is a schematic view of the layout structure of the metal layer M2, the metal layer M3 and the metal layer M4 in the layout structure shown in Fig. 28;

[0051] Fig. 33 is a grid schematic view of the bias signal line DVH, the first reference signal line ref1 and the second reference signal line ref2 in the layout structure shown in Fig. 28;

[0052] Fig. 34 is a schematic view of a partial layout structure of a display panel according to an embodiment of the present application;

[0053] Fig. 35 is a schematic view of a partial layout structure of the data signal line ND, the first auxiliary trace D1 and the second auxiliary trace D2 in the layout structure shown in Fig. 34;

[0054] Fig. 36 is a schematic view of a partial layout structure in a larger range than Fig. 35;

[0055] Figs. 37a-37h are schematic views of the layout structure of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG, the metal layer M2, the metal layer M3 and the metal layer M4 in the layout structure shown in Fig. 34, respectively;

[0056] Fig. 38a is a schematic view of the layout structure of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG and the metal layer M2 in the layout structure shown in Fig. 34;

[0057] Fig. 38b is a schematic view of the layout structure of the metal layer M3 and the metal layer M4 in the layout structure shown in Fig. 34;

[0058] Fig. 39 is a grid schematic view of the bias signal line DVH, the first reference signal line ref1 and the second reference signal line ref2 in the layout structure shown in Fig. 34;

[0059] Fig. 40 is a schematic view of a partial layout structure of a display panel according to an embodiment of the present application;

[0060] Fig. 41a is a schematic view of the layout structure of the metal layer M3 in the layout structure shown in Fig. 40;

[0061] Fig. 41b is a schematic view of the layout structure of the metal layer M4 in the layout structure shown in Fig. 40;

[0062] Fig. 41c is a schematic view of the layout structure of the metal layer M3 and the metal layer M4 in the layout structure shown in Fig. 40;

[0063] Fig. 42 is a schematic view of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0064] With reference to the drawings and embodiments disclosed herein, it will be understood that the application is not limited in scope to the particular embodiments described herein. It will be apparent to those having skill in the relevant art that changes can be made to the embodiments described without departing from the scope of the present application. It will be understood that the application is not limited in scope to the particular embodiments described herein, which are intended as illustrations only. Changes can be made without departing from the spirit or scope of the application. Thus, numerous modifications, as well as numerous implementations, can be made to and from the techniques described above without departing from the scope of the application.

[0065] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the application. Flowever, it will be apparent to one skilled in the art that the application can be practiced without the specific details set forth in this description. In other instances, well-known methods have not been described in detail in order to avoid obscuring the application. Therefore, the specific details set forth hereinafter are by way of example and not intended to limit the scope of the application.

[0066] FIG. 1 shows a top view of a display panel according to an embodiment of the present application. As shown in FIG. 1, the display panel includes a display area AA and a non-display area NA surrounding the display area AA at least partially. The display area AA includes pixel circuits 10 arranged in an array. A column of pixel circuits 10 is electrically connected to two data signal lines ND. The data signal lines ND extend along a first direction X and are arranged along a second direction Y. In other words, the pixel circuits 10 are written with data signals by a double data line (DDL) design crossing. In this way, the influence of the switching of each row of pixel circuits on the same data signal line can be reduced, and the stability of the circuit can be improved. Meanwhile, the design of the double data line can reduce the delay of the data line signal, improve the charging efficiency of the pixel circuit, and achieve high-frequency display. The first direction X and the second direction Y intersect, and optionally, the first direction X and the second direction Y are perpendicular.

[0067] In the present application, a column of pixel circuits 10 is electrically connected to two data signal lines ND. Optionally, as shown in FIG. 1, in a column of pixel circuits 10, the pixel circuits 10 in odd-numbered rows share (i.e., are electrically connected to) one data signal line ND, and the pixel circuits 10 in even-numbered rows share (i.e., are electrically connected to) one data signal line ND. This is because, as shown in FIG. 2, the display panel includes a plurality of light emitting elements 20. As shown in FIGS. 1 and 2, the pixel circuits 10 are electrically connected to the light emitting elements 20 one by one, so that the pixel circuits 10 drive the light emitting elements 20 to display. The light emitting elements 20 electrically connected to the pixel circuits 10 sharing the same data signal line ND have the same display color.

[0068] For example, the light emitting elements 20 include a first color light emitting element 21, a second color light emitting element 22, and a third color light emitting element 23; wherein the first color light emitting element 21 and the second color light emitting element 22 in the same column are respectively electrically connected with the pixel circuit 10 electrically connected with different data signal lines ND, the first color light emitting element 21 in the same column is located in the odd row, and the second color light emitting element 22 in the same column is located in the even row. Alternatively, the first color light emitting element 21 in the same column is located in the even row, and the second color light emitting element 22 in the same column is located in the odd row; and the third color light emitting element 23 in the same column is electrically connected with the pixel circuit 10 in the odd row, and the third color light emitting element 23 in the even row is electrically connected with the pixel circuit 10 in the even row.

[0069] Since the voltage of the data signal required by the light emitting elements of different colors to reach the same display brightness has a difference, the pixel circuits electrically connected with the light emitting elements of the same display color share the data signal line. The pixel circuits electrically connected with the light emitting elements of different display colors are electrically connected with different data signal lines, which can prevent the voltage jump of each pixel circuit sharing the data signal line when writing the data signal, or in other words, the voltage jump difference between the pixel circuits electrically connected with the light emitting elements of the same color is small.

[0070] It should be noted that in this application, one column of pixel circuits 10 is electrically connected with two data signal lines ND, and is not limited to the above-mentioned manner that in one column of pixel circuits 10, the pixel circuits 10 in the odd row share one data signal line ND, and the pixel circuits 10 in the even row share one data signal line ND. In other manners, the double data signal lines can also cross the pixel circuits 10 to write the data signal, reduce the jump influence caused by the switch of each row of pixel circuits on the same data signal line, and improve the stability of the circuit.

[0071] As shown in FIG. 1, the non-display area NA of the display panel includes a fan-out area FA located on one side of the display area AA along the first direction X, and a pin area PA located on the side of the fan-out area FA away from the display area AA. The fan-out area FA includes a plurality of fan-out wires, and the pin area PA is provided with a plurality of pins including data pins and power pins. After the display panel is manufactured, the driver integrated circuit (IC) is bonded and connected with the pins in the pin area PA, such as data pins and power pins. In actual application, the pin area PA will be bent to the back of the display panel.

[0072] It can be understood that the data signal lines ND in the display area AA are electrically connected with the fan-out wires in the fan-out area FA, so that the data signals output by the driver integrated circuit IC are transmitted to the data signal lines ND in the display area AA through the data pins in the pin area PA and the fan-out wires in the fan-out area FA, to drive the pixel circuits 10 in the display area AA to work, and then drive the light emitting elements 20 in the display area AA to display.

[0073] As known from the foregoing, the double data signal line DDL design increases the number of data signal lines, and accordingly, the fan-out wires in the fan-out area FA and the data pins in the pin area PA also increase correspondingly.

[0074] Optionally, FIG. 3 shows a partial structure schematic diagram of a display panel provided by an embodiment of the present application. In combination with FIGS. 2 and 3, the display panel can further include a plurality of demultiplexing circuits Demux, a plurality of data signal terminals Data_in (i.e. data pins) and a plurality of clock signal lines 30, which are located in the non-display area NA. Each demultiplexing circuit Demux includes a plurality of switching units CK. The input ends of the switching units CK of the same demultiplexing circuit Demux are electrically connected with the same data signal terminal Data_in. The control ends of the switching units CK of the same demultiplexing circuit Demux are electrically connected with different clock signal lines 30, so that the clock signals transmitted by the different clock signal lines 30 can control the switching units CK of the same demultiplexing circuit Demux to be turned on at different times. The output ends of the switching units CK of each demultiplexing circuit Demux are electrically connected with the data signal lines ND one by one. In this way, the plurality of data signal lines ND can share the same data signal terminal Data_in, which is conducive to reducing the number of data signal terminals Data_in provided in the lower frame of the display panel.

[0075] It should be noted that each demultiplexing circuit Demux can include a plurality of switching units CK, i.e. two or more switching units CK, and the present application does not limit the number of switching units CK in each demultiplexing circuit Demux. Moreover, FIG. 3 only exemplarily shows that each switching unit CK includes one transistor, but each switching unit CK can include one or more switching devices in the present application.

[0076] Although the demultiplexing circuits and the plurality of clock signal lines are added in the lower frame of the display panel, which can reduce the number of data signal terminals provided in the lower frame of the display panel, the demultiplexing circuits and the plurality of clock signal lines also occupy a certain space, which limits the realization of narrow frame design. Moreover, the increase of the fan-out wires in the fan-out area FA increases the difficulty of realizing narrow frame design.

[0077] Fig. 4 shows a top view of another display panel provided by the embodiments of the present application. As shown in Fig. 4, the display area AA includes a first display area AA1 and a second display area AA2 located at least one side of the first display area AA1 along the second direction Y, and the first display area AA1 and the second display area AA2 each include a plurality of data signal lines ND; and the fanout area FA includes a plurality of fanout wires S1.

[0078] As shown in Fig. 4, the first display area AA1 is located at the central region of the display area AA along the second direction Y, and the data signal lines ND in the first display area AA1 can be directly extended to the position of the fanout area FA and electrically connected with the fanout wires S1 in the fanout area FA.

[0079] The second display area AA2 is located at the left region or the right region of the display area AA along the second direction Y. In some display panels, the fanout wires S1 in the fanout area FA need to be routed in the non-display area of the lower frame of the display panel to be electrically connected with the data signal lines ND in the second display area AA2, but in this way, the fanout wires S1 electrically connected with the data signal lines ND in the second display area AA2 are arranged at the lower left frame or the lower right frame of the display panel, which makes the fanout wires S1 occupy a larger space along the second direction Y, especially, one column of pixel circuits 10 correspondingly electrically connected with two data signal lines ND, which greatly increases the number of data signal lines ND. Then, the fanout wires S1 will occupy a larger space along the second direction Y, which is not conducive to the narrow frame of the display panel.

[0080] In the present application, as shown in Fig. 4, the first connection line segment DV1 and the second connection line segment DH1 are arranged in the display area AA, the first connection line segment DV1 extends along the first direction X, and the second connection line segment DH1 extends along the second direction Y. Thus, the data signal lines ND in the second display area AA2 are electrically connected with the fanout wires S1 through the first connection line segment DV1 and the second connection line segment DH1. For example, the data signal lines ND in the second display area AA2 can be electrically connected with the fanout wires S1 in the fanout area FA through the second connection line segment DH1 extending along the second direction Y and then through the first connection line segment DV1 extending along the first direction X. In this way, the fanout wires S1 do not need to be arranged at the position close to the lower left frame and / or the lower right frame of the display panel, but are routed in the display area AA to transmit data signals to the data signal lines ND in the second display area AA2, and part of the fanout wires are arranged in the display area (Fanout in AA, FIAA), which provides compression space for the lower frame of the display panel and is conducive to the narrow frame of the display panel.

[0081] Figure 5 shows a partial enlarged top view of a display panel according to an embodiment of the present application. As shown in Figure 5, in consideration of the etching uniformity and the uniformity of reflection effect of the display panel, the display area AA further includes a first non-connection line segment DV2, which is insulatively arranged in the same layer as the first connection line segment DV1 and extends along the first direction X. Thus, the first connection line segment DV1 and the first non-connection line segment DV2 constitute a first auxiliary wire D1; or in other words, the first auxiliary wire D1 includes the first connection line segment DV1 and the first non-connection line segment DV2 which are insulatively arranged in the same layer.

[0082] Similarly, the display area AA further includes a second non-connection line segment DH2, which is insulatively arranged in the same layer as the second connection line segment DH1 and extends along the second direction Y. Thus, the second connection line segment DH1 and the second non-connection line segment DH2 constitute a second auxiliary wire D2; or in other words, the second auxiliary wire D2 includes the second connection line segment DH1 and the second non-connection line segment DH2 which are insulatively arranged in the same layer.

[0083] It should be noted that, as shown in Figure 5, in the first auxiliary wire D1, the first non-connection line segment DV2 can include an entire line segment extending along the first direction X which does not transmit data signals to the data signal line ND, or can include a partial line segment of an entire line segment extending along the first direction X which does not transmit data signals to the data signal line ND.

[0084] Similarly, as shown in Figure 5, in the second auxiliary wire D2, the second non-connection line segment DH2 can include an entire line segment extending along the second direction Y which does not transmit data signals to the data signal line ND, or can include a partial line segment of an entire line segment extending along the second direction Y which does not transmit data signals to the data signal line ND.

[0085] It should be noted that part or all of the first non-connection line segment DV2 can be connected to a fixed potential, so as to reduce the resistance of the fixed potential wire and decrease the voltage drop on the fixed potential wire. For example, as shown in Figure 5, at least part of the first non-connection line segment DV1 is electrically connected to the power voltage line PVEE, so as to be connected in parallel with the power voltage line PVEE, thereby reducing the resistance of the power voltage line PVEE and decreasing the voltage drop on the power voltage line PVEE.

[0086] Similarly, part or all of the second non-connection line segment DH2 can be connected to a fixed potential, so as to reduce the resistance of the fixed potential wire and decrease the voltage drop on the fixed potential wire. For example, as shown in Figure 5, at least part of the second non-connection line segment DH2 is electrically connected to the power voltage line PVEE, so as to be connected in parallel with the power voltage line PVEE, thereby reducing the resistance of the power voltage line PVEE and decreasing the voltage drop on the power voltage line PVEE.

[0087] And the first non-connecting line segment DV2 and the second non-connecting line segment DH2 can be electrically connected to form a mesh structure, so as to further reduce the resistance of the fixed potential trace and reduce the voltage drop on the fixed potential trace.

[0088] Therefore, the display panel provided by the embodiment of the present application can reduce the influence of the switching of each row of pixel circuits on the same data signal line, and improve the stability of the circuit, by arranging one column of pixel circuits to correspond to two data signal lines, and using the two data signal lines to cross to write data signals to the pixel circuits. In addition, by arranging the first connecting line segment and the second connecting line segment in the display area, at least part of the data signal lines are electrically connected to the fan-out traces through the first connecting line segment and the second connecting line segment in the display area, that is, the wiring of the data signal transmission to at least part of the data signal lines is performed in the display area, and part of the fan-out traces are arranged in the display area (Fanout in AA, FIAA), so as to provide compression space for the lower frame of the display panel, which is conducive to realizing the narrow frame of the display panel.

[0089] As known from the foregoing, the double data signal line DDL design can greatly increase the number of data signal lines, and a high-resolution display panel usually has a high pixel density (Pixels Per Inch, PPI). Therefore, not only is the pixel space reduced, but the number of data signal lines that need to be connected to the FIAA is also increased, and therefore, it is very difficult to arrange the fan-out traces in the display area to connect the data signal lines.

[0090] FIG. 6 shows a partial layout structure schematic diagram of a display panel provided by an embodiment of the present application. As shown in FIG. 6, along the second direction Y, two data signal lines ND corresponding to one column of pixel circuits 10 are distributed on the opposite sides of the column of pixel circuits 10.

[0091] It should be noted that FIG. 6 shows eight pixel circuits 10, which form a two-row and four-column matrix along the first direction X and the second direction Y. In FIG. 6, in order to clearly distinguish different pixel circuit regions, horizontal dashed lines and vertical dashed lines are used to represent the boundaries of adjacent pixel circuit regions along the first direction X and the second direction Y. It can be understood that this boundary is only for ease of explanation and does not limit the pixel circuit 10, and similar situations in other drawings of the present application will not be described again.

[0092] It can be understood that in the direction perpendicular to the plane where the display panel is located, the data signal line ND corresponding to a column of pixel circuits 10 is usually at least partially overlapped with the column of pixel circuits. In this application, taking the second column of pixel circuits 10 from left to right along the second direction Y in FIG. 6 as an example, it can be seen that the two data signal lines ND corresponding to a column of pixel circuits 10 are the first data signal line ND1 and the second data signal line ND2, and the first data signal line ND1 and the second data signal line ND2 are distributed on both sides of the virtual center line O1 of the column of pixel circuits 10 extending along the first direction X, that is, the first data signal line ND1 and the second data signal line ND2 are distributed on the opposite sides of the column of pixel circuits 10 along the second direction Y, and similar cases in other drawings of this application will not be described again.

[0093] For the sake of clarity, FIG. 7 shows a partial layout structure diagram of the data signal line ND, the first auxiliary trace D1 and the second auxiliary trace D2 in the layout structure shown in FIG. 6. Among them, the first auxiliary trace D1 is arranged on the same layer as the data signal line ND, and the second auxiliary trace D2 is arranged on a different layer from the first auxiliary trace D1, that is, the second auxiliary trace D2 is arranged on a different layer from the data signal line ND.

[0094] It can be understood that since the data signal line ND extends along the first direction X and the second auxiliary trace D1 extends along the second direction Y, in order to avoid the second auxiliary trace D2 affecting the data signal line ND that it passes through during the extension along the second direction Y, the data signal line ND and the second auxiliary trace D2 need to be arranged on different layers.

[0095] In order to more clearly show the connection relationship of the data signal line ND, the first connection line segment DV1 in the first auxiliary trace D1 and the second connection line segment DH1 in the second auxiliary trace D2, FIG. 8 further shows a partial layout structure diagram of a larger range than FIG. 7. Specifically, FIG. 8 shows 32 pixel circuits 10, which form a matrix arranged in four rows and eight columns along the first direction X and the second direction Y. Referring to the dotted line path shown in FIG. 8, part of the data signal line ND is electrically connected with the second connection line segment DH1 in the second auxiliary trace D2. Further, the second connection line segment DH1 in the second auxiliary trace D2 is electrically connected with the second connection line segment DV1 in the first auxiliary trace D1, thereby arranging the part of the fan-out trace electrically connected with the part of the data signal line ND in the display area.

[0096] As shown in FIGS. 7 and 8, since the second auxiliary wire D2 is arranged in a layer different from the first auxiliary wire D1 and the second auxiliary wire D2 is arranged in a layer different from the data signal line ND, the data signal line ND and the second connecting line segment DH1 in the second auxiliary wire D2 are electrically connected through the contact hole K1. Moreover, the second connecting line segment DH1 in the second auxiliary wire D2 extends in the first direction X for a distance to be electrically connected to the data signal line D2 through the contact hole K1; the second connecting line segment DH1 in the second auxiliary wire D2 and the first connecting line segment DV1 in the first auxiliary wire D1 are electrically connected through the contact hole K2 in the region where they overlap.

[0097] As shown in FIG. 8, in the first auxiliary wire D1, there is a gap between the first connecting line segment DV1 and the first non-connecting line segment DV2, as shown in the oval frame marked region in FIG. 8, so that the first connecting line segment DV1 and the first non-connecting line segment DV2 are insulated; similarly, in the second auxiliary wire D2, there is a gap between the second connecting line segment DH1 and the second non-connecting line segment DH2, as shown in the rectangular frame marked region in FIG. 8, so that the first connecting line segment DV1 and the first non-connecting line segment DV2 are insulated.

[0098] As shown in FIGS. 6-8, one column of pixel circuits 10 corresponds to one first auxiliary wire D1; it should be noted that in this application, one column of pixel circuits 10 corresponds to one first auxiliary wire D1, which can be a correspondence in quantity between one column of pixel circuits 10 and the first auxiliary wire D1. Specifically, the number of columns of pixel circuits 10 is N10, and the number of first auxiliary wires D1 is also N10, which can also be a correspondence in position between one column of pixel circuits 10 and the first auxiliary wire D1. For example, in the direction perpendicular to the plane where the display panel is located, one column of pixel circuits 10 and one first auxiliary wire D1 at least partially overlap, and for another example, along the second direction Y, one first auxiliary wire D1 is located on one side of one column of pixel circuits 10. The cases of corresponding arrangement of pixel circuits and signal lines in other places of this application are similar, and will not be described in detail.

[0099] FIG. 9 shows a schematic circuit structure diagram of the pixel circuit 10 in the layout structure shown in FIG. 6. As shown in FIG. 6, the pixel circuit 10 includes a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a compensation transistor T4, a gate reset transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7, and a storage capacitor Cst.

[0100] The first electrode of the first light-emitting control transistor T1 is electrically connected to the first power supply signal line PVDD, the second electrode of the first light-emitting control transistor T1 is electrically connected to the second node N2, and the gate of the first light-emitting control transistor T1 is electrically connected to the light-emitting control signal line EMIT.

[0101] A first electrode of the data write transistor T2 is electrically connected with the data signal line ND, a second electrode of the data write transistor T2 is electrically connected with the second node N2, and a gate electrode of the data write transistor T2 is electrically connected with the scan signal line SP*;

[0102] A first electrode of the drive transistor T3 is electrically connected with the second node N2, a second electrode of the drive transistor T3 is electrically connected with the third node N3, and a gate electrode of the drive transistor T3 is electrically connected with the first node N1;

[0103] A first electrode of the compensation transistor T4 is electrically connected with the third node N3, a second electrode of the compensation transistor T4 is electrically connected with the first node N1, and a gate electrode of the compensation transistor T4 is electrically connected with the scan signal line S2;

[0104] A first electrode of the gate reset transistor T5 is electrically connected with the first reference signal line ref1, a second electrode of the gate reset transistor T5 is electrically connected with the first node N1, and a gate electrode of the gate reset transistor T5 is electrically connected with the scan signal line S1;

[0105] A first electrode of the second light emission control transistor T6 is electrically connected with the third node N3, a second electrode of the second light emission control transistor T6 is electrically connected with the fourth node N4, and a gate electrode of the second light emission control transistor T6 is electrically connected with the light emission control signal line EMIT;

[0106] A first electrode of the anode reset transistor T7 is electrically connected with the second reference signal line ref2, a second electrode of the anode reset transistor T7 is electrically connected with the fourth node N4, and a gate electrode of the anode reset transistor T7 is electrically connected with the scan signal line SP;

[0107] A first plate of the storage capacitor Cst is electrically connected with the first node N1, and a second plate of the storage capacitor Cst is electrically connected with the first power supply signal line PVDD;

[0108] Thus, the pixel circuit 10 of the 7T1C structure is realized.

[0109] It can be understood that the first node N1, the second node N2, the third node N3 and the fourth node N4 can be virtually existing connection nodes, or actually existing connection nodes.

[0110] FIG. 10 shows a partial cross-sectional view of a display panel according to an embodiment of the present application. As shown in FIG. 10, the display panel includes a substrate sub, an active layer poly on one side of the substrate sub, a plurality of metal layers and an oxide layer IGZO on a side of the active layer poly away from the substrate sub. The plurality of metal layers includes metal layer M1, metal layer MC, metal layer MG, metal layer M2, metal layer M3, metal layer M4 and metal layer RE arranged in a direction away from the substrate sub. The oxide layer IGZO is between the metal layer MC and the metal layer MG. The different metal layers, the metal layers and the active layer, and the metal layers and the oxide layer are all separated by insulating layers. The metal layer RE includes an anode of a light emitting element 20. In addition, the light emitting element 20 also includes a light emitting layer and a cathode, which are not shown in FIG. 10.

[0111] In combination of FIGS. 9 and 10, each thin film transistor in the pixel circuit 10 can be a low temperature polycrystalline (LTPS) thin film transistor Qx. Specifically, the LTPS thin film transistor Qx includes an active layer b1, a gate electrode g, a source electrode s1 and a drain electrode d1. Alternatively, each thin film transistor in the pixel circuit 10 can be an oxide transistor, specifically, an indium gallium zinc oxide (IGZO) thin film transistor Qy. Specifically, the IGZO thin film transistor Qy includes an oxide layer b2, a bottom gate bg, a top gate tg, a source electrode s2 and a drain electrode d2. In the pixel circuit 10 shown in FIG. 9, the compensation transistor T4 and the gate reset transistor T5 can be IGZO thin film transistors with a dual-gate structure including the bottom gate bg and the top gate tg. Other thin film transistors can be LTPS thin film transistors.

[0112] The layout structure shown in FIG. 6 includes layout structures of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG, the metal layer M2, the metal layer M3 and the metal layer M4. For the sake of clarity, FIG. 11a shows a layout structure schematic diagram of the active layer poly in the layout structure shown in FIG. 6, FIG. 11b shows a layout structure schematic diagram of the metal layer M1 in the layout structure shown in FIG. 6, FIG. 11c shows a layout structure schematic diagram of the metal layer MC in the layout structure shown in FIG. 6, FIG. 11d shows a layout structure schematic diagram of the oxide layer IGZO in the layout structure shown in FIG. 6, FIG. 11e shows a layout structure schematic diagram of the metal layer MG in the layout structure shown in FIG. 6, FIG. 11f shows a layout structure schematic diagram of the metal layer M2 in the layout structure shown in FIG. 6, FIG. 11g shows a layout structure schematic diagram of the metal layer M3 in the layout structure shown in FIG. 6, and FIG. 11h shows a layout structure schematic diagram of the metal layer M4 in the layout structure shown in FIG. 6; FIG. 12a shows a layout structure schematic diagram of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG and the metal layer M2 in the layout structure shown in FIG. 6, and FIG. 12b shows a layout structure schematic diagram of the metal layer M3 and the metal layer M4 in the layout structure shown in FIG. 6.

[0113] As shown in FIG. 11h and FIG. 12b, along the second direction Y, two data signal lines ND corresponding to the pixel circuit 10 are distributed on the opposite sides of the column of pixel circuits 10. The first auxiliary wire D1 is arranged in the same layer as the data signal line ND and is located in the metal layer M4. In addition, the display area includes a first power signal line PVDD, and the first power signal line PVDD includes a first sub-power signal line PVDD1, which extends along the first direction X and is located in the metal layer M4, arranged in the same layer as the data signal line ND and the first auxiliary wire D1.

[0114] As shown in FIG. 11g and FIG. 12b, the second auxiliary wire D2 is arranged in a different layer from the data signal line ND and the first auxiliary wire D1 and is located in the metal layer M3.

[0115] As shown in FIG. 8, FIG. 11g-FIG. 11h and FIG. 12b, the data signal line ND in the metal layer M4 is electrically connected with the second connection line segment DH1 in the second auxiliary trace D2 extending in the first direction X through the connection L1 in the metal layer M4, the connection L2 in the metal layer M3 and the connection L3 in the metal layer M2; and the first connection line segment DV1 in the first auxiliary trace D1 in the metal layer M4 is electrically connected with the second connection line segment DH1 in the second auxiliary trace D2 in the metal layer M3 through the connection L4 in the metal layer M4 and the connection L5 in the metal layer M3. Similarly, the first non-connection line segment DV2 in the first auxiliary trace D1 in the metal layer M4 is electrically connected with the second non-connection line segment DH2 in the second auxiliary trace D2 in the metal layer M3 through the connection L4 in the metal layer M4 and the connection L5 in the metal layer M3.

[0116] As shown in FIG. 9, FIG. 11a and FIG. 12a, the data write transistor T2 includes a channel region p2 in the active layer poly, and a first pole p21 and a second pole p22 connected with the channel region p2; the driving transistor T3 includes a channel region p3 in the active layer poly, and a first pole p31 and a second pole p32 connected with the channel region p3; the second pole p22 of the data write transistor T2 is electrically connected with the first pole p31 of the driving transistor T3 in the same layer.

[0117] As shown in FIG. 9, FIG. 11a, FIG. 11f-FIG. 11h, the first pole p21 of the data write transistor T2 is electrically connected with the data signal line ND through the connection L3 in the metal layer M2, the connection L2 in the metal layer M3 and the connection L1 in the metal layer M4. The connection L2 in the metal layer M3 and the connection L1 in the metal layer M4 are also used to connect the second connection line segment DH1 in the second auxiliary trace D2 with the data signal line ND, that is, the connection position of the second connection line segment DH1 in the second auxiliary trace D2 with the data signal line ND and the connection position of the first pole p21 of the data write transistor T2 with the data signal line ND coincide, so that the number of contact holes between the metal layer M3 and the metal layer M4 can be reduced, so as to leave more setting space for the data signal line ND, the first auxiliary trace D1 and the second auxiliary trace D2.

[0118] As shown in FIGS. 9, 11a-11b and 12a, the scan signal line SP* can be located in the metal layer M1 and extend along the second direction Y, and in the direction perpendicular to the plane where the display panel is located, the scan signal line SP* at least partially overlaps the channel region p2 of the data writing transistor T2. Alternatively, in the direction perpendicular to the plane where the display panel is located, the portion of the active layer poly that overlaps the scan signal line SP* is the channel region p2 of the data writing transistor T2, and the portion of the scan signal line SP* that overlaps the active layer poly is the gate g2 of the data writing transistor T2, so that the gate of the data writing transistor T2 is electrically connected with the scan signal line SP*.

[0119] It should be noted that the application divides the portion of each transistor located in the active layer poly into regions for ease of description, but does not limit the specific regions. The different names and labels are only used to better explain the embodiments of the application.

[0120] As shown in FIGS. 9, 11a and 12a, the first light emitting control transistor T1 includes a channel region p1 located in the active layer poly, and a first pole p11 and a second pole p12 connected with the channel region p1; the second pole p12 of the first light emitting control transistor T1 is electrically connected with the first pole p31 of the driving transistor T3 in the same layer. As shown in FIGS. 9, 11a, 11f-11h, the first pole p11 of the first light emitting control transistor T1 is electrically connected with the first sub power signal line PVDD1 through the connection part L6 located in the metal layer M2, the connection part L7 located in the metal layer M3 and the connection part L8 located in the metal layer M4.

[0121] As shown in FIGS. 9, 11a-11b and 12a, the light emitting control signal line EMIT can be located in the metal layer M1 and extend along the second direction Y, and in the direction perpendicular to the plane where the display panel is located, the light emitting control signal line EMIT at least partially overlaps the channel region p1 of the first light emitting control transistor T1. Alternatively, in the direction perpendicular to the plane where the display panel is located, the portion of the light emitting control signal line EMIT that overlaps the channel region p1 of the first light emitting control transistor T1 is the gate g1 of the first light emitting control transistor T1, so that the gate g1 of the first light emitting control transistor T1 is electrically connected with the light emitting control signal line EMIT.

[0122] As shown in FIG. 9, FIG. 11a-FIG. 11b and FIG. 12a, the first plate Cst1 of the storage capacitor Cst can be located in the metal layer M1, and the first plate Cst1 of the storage capacitor Cst also serves as the gate g3 of the driving transistor T3. In the direction perpendicular to the plane where the display panel is located, the first plate Cst1 of the storage capacitor Cst and the channel region p3 of the driving transistor T3 overlap each other. As shown in FIG. 9, FIG. 11c and FIG. 11f-FIG. 11h, the second plate Cst2 of the storage capacitor Cst can be located in the metal layer MC, and the second plate Cst2 of the storage capacitor Cst is electrically connected with the first sub power signal line PVDD1 through the connection part L6 located in the metal layer M2, the connection part L7 located in the metal layer M3 and the connection part L8 located in the metal layer M4.

[0123] As shown in FIG. 7, FIG. 11h and FIG. 12b, the two data signal lines ND corresponding to the column of pixel circuits 10 are distributed on the two sides of the column of pixel circuits 10 along the second direction Y, and the first sub power signal line PVDD1 corresponding to the column of pixel circuits 10 is electrically connected, and the first sub power signal line PVDD1 is arranged in the same layer as the data signal line ND, and is located in the metal layer M4. It can also be seen that the first auxiliary wire D1 corresponding to the column of pixel circuits 10 is arranged, and the first auxiliary wire D1 is also located in the metal layer M4. The first auxiliary wire D1 and the first sub power signal line PVDD1 are located between the two data signal lines ND corresponding to the column of pixel circuits 10.

[0124] It can be understood that, since the data signal line ND, the first auxiliary wire D1 and the first sub power signal line PVDD1 need to be arranged in the same metal layer (metal layer M4), the width of the first sub power signal line PVDD1 along the second direction Y can be appropriately narrowed to leave more space for the data signal line ND and the first auxiliary wire D1. Considering that the resistance of the first sub power signal line PVDD1 will increase after narrowing the width of the first sub power signal line PVDD1 along the second direction Y, the width of the first sub power signal line PVDD1 along the second direction Y can be appropriately widened in the area where there is space to reduce the resistance of the first sub power signal line PVDD1.

[0125] As shown in FIGS. 7, 11h and 12b, the first sub power supply signal line PVDD1 includes a first sub segment Z1, a second sub segment Z2 and a third sub segment Z3, the first sub segment Z1 is connected with the third sub segment Z3 through the second sub segment Z2, the third sub segment Z3 is connected with the first sub segment Z1 through the second sub segment Z2, the width of the first sub segment Z1 along the second direction Y is greater than 1.5 times of the width of the second sub segment Z2 along the second direction Y, and the width of the third sub segment Z3 is greater than 1.5 times of the width of the second sub segment Z2 along the second direction Y. In this way, the first sub power supply signal line PVDD1 is locally widened and locally narrowed along the first direction X, so as to leave more space for the data signal line ND and the first auxiliary trace D1, while reducing the resistance of the first sub power supply signal line PVDD1.

[0126] As shown in FIGS. 11c and 12a, the second plate Cst2 of the storage capacitor Cst of a row of pixel circuits 10 is electrically connected in the same layer, and as known from the foregoing, the second plate Cst2 of the storage capacitor Cst is also electrically connected with the first sub power supply signal line PVDD1. Thus, the second plates Cst2 of the storage capacitors Cst of a row of pixel circuits 10 electrically connected in the same layer constitute the second sub power supply signal line PVDD2, the second sub power supply signal line PVDD2 extends along the second direction Y, the second sub power supply signal line PVDD2 is arranged in a different layer from the first sub power supply signal line PVDD1, and the second sub power supply signal line PVDD2 is electrically connected with the first sub power supply signal line PVDD1. In this way, the first sub power supply signal line PVDD1 and the second sub power supply signal line PVDD2 constitute a grid structure, which can reduce the overall resistance of the first power supply signal line PVDD, reduce the power consumption of the first power supply signal line PVDD, and improve the signal transmission stability of the first power supply signal line PVDD, which is conducive to improving the display uniformity and other display effects of the display panel.

[0127] It should be noted that, as shown in FIG. 11g, the connection part L7 located in the metal layer M3 can be relatively large, and the connection part L7 is also referred to as a first power supply signal line sub part. Since the first power supply signal line sub part is electrically connected with the first sub power supply signal line PVDD1, the overall resistance of the first power supply signal line PVDD can also be reduced, the power consumption of the first power supply signal line PVDD can be reduced, and the signal transmission stability of the first power supply signal line PVDD can be improved, which is conducive to improving the display uniformity and other display effects of the display panel.

[0128] As shown in FIGS. 9, 11a and 12a, the second light-emitting control transistor T6 includes a channel region p6 in the active layer poly, and a first electrode p61 and a second electrode p62 connected to the channel region p6; the first electrode p61 of the second light-emitting control transistor T6 is electrically connected to the second electrode p32 of the driving transistor T3 in the same layer. As shown in FIGS. 9, 11a, 11f-11h, the second electrode p62 of the second light-emitting control transistor T6 is electrically connected to the light-emitting element 20 through the connection portion L9 in the metal layer M2, the connection portion L10 in the metal layer M3, and the connection portion L11 in the metal layer M4.

[0129] As shown in FIGS. 9, 11a and 11b, in the direction perpendicular to the plane where the display panel is located, the light-emitting control signal line EMIT at least partially overlaps with the channel region p6 of the second light-emitting control transistor T6; optionally, in the direction perpendicular to the plane where the display panel is located, the part of the light-emitting control signal line EMIT overlapping with the channel region p6 of the second light-emitting control transistor T6 is the gate electrode g6 of the second light-emitting control transistor T6, so that the gate electrode g6 of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line EMIT.

[0130] As shown in FIGS. 9, 11d and 12a, the compensation transistor T4 and the gate reset transistor T5 can be oxide thin film transistors, i.e., IGZO thin film transistors; wherein the compensation transistor T4 includes a channel region p4 in the oxide layer IGZO, and a first electrode p41 and a second electrode p42 connected to the channel region p4; the gate reset transistor T5 includes a channel region p5 in the oxide layer IGZO, and a first electrode p51 and a second electrode p52 connected to the channel region p5.

[0131] As shown in FIGS. 9, 11a-11d and 11f, the first electrode p41 of the compensation transistor T4 is electrically connected to the second electrode p32 of the driving transistor T3 through the connection portion L12 in the metal layer M2, the second electrode p42 of the compensation transistor T4 is directly electrically connected to the second electrode p52 of the gate initialization transistor T5 in the oxide layer IGZO, and is electrically connected to the gate electrode g3 of the driving transistor T3 through the via in the second electrode plate Cst2 of the storage capacitor Cst in the metal layer MC and the connection portion L13 in the metal layer M2.

[0132] It should be noted that, as shown in FIGS. 9, 11b, 11d, and 11f-11g, the connection portion L13 in the metal layer M2 is electrically connected to the second electrode p42 of the compensation transistor T4, the second electrode p52 of the gate initialization transistor T5, and the gate g3 of the driving transistor T3, i.e., the connection portion L13 in the metal layer M2 corresponds to the first node N1; and as known from the foregoing, the connection portion L7 in the metal layer M3 is connected to the first power supply signal line PVDD; in the direction perpendicular to the plane in which the display panel is located, the connection portion L7 in the metal layer M3 covers the connection portion L13 in the metal layer M2, i.e., covers the first node N1, so as to maintain the stability of the potential of the first node N1, i.e., maintain the stability of the potential of the gate g3 of the driving transistor T3, which is conducive to improving the display effect of the display panel.

[0133] As shown in FIGS. 9, 11c-11e, and 12a, the display area includes a scan signal line S1 and a scan signal line S2; the scan signal line S1 includes a first sub-scan signal S11 and a second sub-scan signal S12 that transmit the same scan signal, the first sub-scan signal S11 is located in the metal layer MC and extends along the second direction Y, and the second sub-scan signal S12 is located in the metal layer MG and extends along the second direction Y; in the direction perpendicular to the plane in which the display panel is located, the first sub-scan signal S11, the second sub-scan signal S12, and the channel region p5 of the gate reset transistor T5 overlap each other.

[0134] Optionally, in the direction perpendicular to the plane in which the display panel is located, the part of the oxide layer IGZO that overlaps the first sub-scan signal S11 and the second sub-scan signal S12 is the channel region p5 of the gate reset transistor T5, the part of the first sub-scan signal S11 that directly faces the channel region p5 of the gate reset transistor T5 is the bottom gate bg5 of the gate reset transistor T5, so that the bottom gate bg5 of the gate reset transistor T5 is electrically connected to the first sub-scan signal S11; the part of the second sub-scan signal S12 that directly faces the channel region p5 of the gate reset transistor T5 is the top gate tg5 of the gate reset transistor T5, so that the top gate tg5 of the gate reset transistor T5 is electrically connected to the second sub-scan signal S12, so that the top gate tg5 and the bottom gate bg5 of the gate reset transistor T5 are both electrically connected to the first scan signal line S1 and receive the same scan signal.

[0135] Similarly, as shown in FIGS. 9, 11c-11e and 12a, the scan signal line S2 includes a third sub-scan signal line S21 and a fourth sub-scan signal line S22 that transmit the same scan signal, the third sub-scan signal line S21 is located in the metal layer MC and extends along the first direction X, and the fourth sub-scan signal line S22 is located in the metal layer MG and extends along the first direction X; in the direction perpendicular to the plane in which the display panel is located, the third sub-scan signal line S21, the fourth sub-scan signal line S22 and the channel region p4 of the compensation transistor T4 are overlapped.

[0136] Optionally, in the direction perpendicular to the plane in which the display panel is located, the part of the oxide layer IGZO that overlaps the third sub-scan signal line S21 and the fourth sub-scan signal line S22 is the channel region p4 of the compensation transistor T4, the part of the third sub-scan signal line S21 that directly faces the channel region p4 of the compensation transistor T4 is the bottom gate bg4 of the compensation transistor T4, so that the bottom gate bg4 of the compensation transistor T4 is electrically connected with the third sub-scan signal line S21; the part of the fourth sub-scan signal line S22 that directly faces the channel region p4 of the compensation transistor T4 is the top gate tg4 of the compensation transistor T4, so that the top gate tg4 of the compensation transistor T4 is electrically connected with the fourth sub-scan signal line S22, so that the top gate tg4 and the bottom gate bg4 of the compensation transistor T4 are both electrically connected with the second scan signal line S2 and receive the same scan signal.

[0137] As shown in FIGS. 9, 11c, 11f and 12a, the display area includes a first reference signal line ref1, the first reference signal line ref1 includes a first sub-reference signal line ref11 and a second sub-reference signal line ref12, the first sub-reference signal line ref11 extends along the second direction Y and is arranged along the first direction X, the second sub-reference signal line ref12 extends along the first direction X and is arranged along the second direction Y, the first sub-reference signal line ref11 and the second sub-reference signal line ref12 are arranged in different layers and are electrically connected.

[0138] As shown in FIGS. 11c and 11f, the first sub-reference signal line ref11 is located in the metal layer MC, the second sub-reference signal line ref12 is located in the metal layer M2, and the first sub-reference signal line ref11 is electrically connected with the second sub-reference signal line ref12 through the connection part L14 located in the metal layer MC and the connection part L15 located in the metal layer M2. As shown in FIGS. 9, 11d and 11f, the second sub-reference signal line ref12 is electrically connected with the first pole p51 of the gate reset transistor T5 through the connection part L16 located in the metal layer M2; and as shown in FIG. 11d, in a row of pixel circuits 10, the first poles p51 of the gate reset transistors T5 of the pixel circuits 10 that are adjacent to each other along the second direction Y are electrically connected in the same layer.

[0139] Thus, by arranging the first reference signal line ref1 to include the first sub-reference signal line ref11 and the second sub-reference signal line ref12 extending in different directions and being electrically connected, the first reference signal line ref1 in the grid structure is formed. FIG. 13 further shows the grid structure formed by the first sub-reference signal line ref11 and the second sub-reference signal line ref12. Thus, the overall resistance of the first reference signal line ref1 can be reduced, the power consumption of the first reference signal line ref1 is lowered, and the signal transmission stability of the first reference signal line ref1 is improved, which is conducive to improving the display uniformity and other display effects of the display panel.

[0140] As shown in FIGS. 9, 11a, 11f-11h and 12a, the anode reset transistor T7 includes a channel region p7 in the active layer poly, and a first pole p71 and a second pole p72 connected to the channel region p7; the second pole p72 of the anode reset transistor T7 is electrically connected to the light emitting element 20 through the connection portion L9 in the metal layer M2, the connection portion L10 in the metal layer M3, and the connection portion L11 in the metal layer M4.

[0141] As shown in FIGS. 9, 11a-11b and 12a, the display area includes a scan signal line SP, the scan signal line SP is located in the metal layer M1 and extends along the second direction Y, and in a direction perpendicular to the plane of the display panel, the scan signal line SP at least partially overlaps the channel region p7 of the anode reset transistor T7. Optionally, in the direction perpendicular to the plane of the display panel, the portion of the scan signal line SP overlapping the channel region p7 of the anode reset transistor T7 is the gate g7 of the anode reset transistor T7, so that the scan signal line SP is electrically connected to the gate of the anode reset transistor T7.

[0142] As shown in FIGS. 9, 11c, 11f and 12a, the display area includes a second reference signal line ref2, the second reference signal line ref2 includes a third sub-reference signal line ref21 and a fourth sub-reference signal line ref22, the third sub-reference signal line ref21 extends along the second direction Y and is arranged along the first direction X, the fourth sub-reference signal line ref22 extends along the first direction X and is arranged along the second direction Y, the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22 are arranged in different layers, and the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22 are electrically connected.

[0143] As shown in FIG. 9, FIG. 11c and FIG. 11f, the third sub-reference signal line ref21 is located in the metal layer MC, the fourth sub-reference signal line ref22 is located in the metal layer M2, and the third sub-reference signal line ref21 is electrically connected with the fourth sub-reference signal line ref22 through the connection part L17 located in the metal layer MC and the connection part L18 located in the metal layer M2. As shown in FIG. 9, FIG. 11a and FIG. 11f, the fourth sub-reference signal line ref22 is electrically connected with the first electrode p71 of the anode reset transistor T7 through the connection part L19 located in the metal layer M2, and in a row of pixel circuits 10, the first electrodes p71 of the anode reset transistors T7 of the pixel circuits 10 adjacent to each other in the second direction Y are electrically connected in the same layer.

[0144] In this way, by arranging the second reference signal line ref2 to include the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22 extending in different directions and being electrically connected, the second reference signal line ref2 also forms a grid structure, and FIG. 13 further shows the grid structure formed by the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22, so as to reduce the overall resistance of the second reference signal line ref2, thereby reducing the power consumption of the second reference signal line ref2 and improving the signal transmission stability of the second reference signal line ref2, and facilitating the improvement of the display uniformity and other display effects of the display panel.

[0145] As shown in FIG. 11f, FIG. 12a and FIG. 13, in the four adjacent columns of pixel circuits 10, two columns of pixel circuits 10 are arranged to correspond to the second sub-reference signal line ref12, and the other two columns of pixel circuits 10 are arranged to correspond to the fourth sub-reference signal line ref22, and the second sub-reference signal line ref12 and the fourth sub-reference signal line ref22 are arranged alternately in the second direction Y, that is, the columns of pixel circuits arranged to correspond to the second sub-reference signal line ref12 are arranged alternately, and the columns of pixel circuits arranged to correspond to the fourth sub-reference signal line ref22 are arranged alternately, that is, the columns of pixel circuits arranged to correspond to the second sub-reference signal line ref12 and the columns of pixel circuits arranged to correspond to the fourth sub-reference signal line ref22 are arranged alternately in the second direction Y, so as to reduce the number of the second sub-reference signal line ref12 and the fourth sub-reference signal line ref22, and leave more arrangement space for the data signal line ND and the first auxiliary wire D1.

[0146] Similarly, as shown in FIG. 11c, FIG. 12a and FIG. 13, in the four adjacent rows of pixel circuits 10, two rows of pixel circuits 10 are correspondingly provided with the first sub-reference signal line ref11, and the other two rows of pixel circuits 10 are correspondingly provided with the third sub-reference signal line ref21, and the first sub-reference signal line ref11 and the third sub-reference signal line ref21 are alternately arranged along the first direction X, that is, the rows of pixel circuits correspondingly provided with the first sub-reference signal line ref11 are arranged alternately, and the rows of pixel circuits correspondingly provided with the third sub-reference signal line ref21 are arranged alternately, that is, the rows of pixel circuits correspondingly provided with the first sub-reference signal line ref11 and the rows of pixel circuits correspondingly provided with the third sub-reference signal line ref21 are alternately arranged along the first direction X, so that the number of the first sub-reference signal line ref11 and the third sub-reference signal line ref21 can be reduced, and more space can be left for the arrangement of the second auxiliary wire D2.

[0147] As shown in FIG. 12a and FIG. 12b, in a row of pixel circuits 10, every two adjacent pixel circuits 10 form a pixel circuit repeating unit Q, and the two pixel circuits 10 in the pixel circuit repeating unit Q are mirror-symmetrical along the first direction X, and each pixel circuit repeating unit Q is arranged repeatedly along the second direction Y; in two adjacent rows of pixel circuits 10, the pixel circuit repeating units Q in one row of pixel circuits 10 are first repeating units Q1, and the pixel circuit repeating units Q in the other row of pixel circuits 10 are second repeating units Q2, and the first repeating units Q1 and the second repeating units are arranged staggeredly along the second direction Y.

[0148] It should be noted that, in this application, the two pixel circuits 10 in the pixel circuit repeating unit Q are mirror-symmetrical along the first direction X, which means that the two pixel circuits 10 in the pixel circuit repeating unit Q are at least partially mirror-symmetrical along the first direction X, which can be partially mirror-symmetrical or completely mirror-symmetrical. Other similar cases in this application will not be described here.

[0149] As can be seen, when two data signal lines ND corresponding to a column of pixel circuits 10 are distributed on the opposite sides of the column of pixel circuits 10 along the second direction Y, and the data signal line ND is arranged in the same layer as the first auxiliary wire D1, and the second auxiliary wire D2 is arranged in a different layer from the data signal line ND and the first auxiliary wire D1, by reducing the number of contact holes connected to the data signal line ND, locally narrowing the first sub-power signal line PVDD1 along the first direction X, and arranging the first reference signal line ref1 and the second reference signal line ref2 alternately along the row of pixel circuits and alternately along the column of pixel circuits, more space can be left for the arrangement of the double data signal line ND, the first auxiliary wire D1 and the second auxiliary wire D2; one first auxiliary wire D1 can be arranged corresponding to one column of pixel circuits 10, and the first auxiliary wire D1 and the first sub-power signal line PVDD1 can be located between the two data signal lines ND corresponding to the column of pixel circuits 10.

[0150] Figure 14 shows a partial layout structure schematic diagram of another display panel provided by the embodiments of the present application. As shown in Figure 14, along the second direction Y, two data signal lines ND corresponding to the pixel circuit 10 are distributed on the opposite sides of the column of pixel circuits 10. Figure 14 shows eight pixel circuits 10, which form a matrix of two rows and four columns along the first direction X and the second direction Y.

[0151] For the sake of clarity, Figure 15 shows a partial layout structure schematic diagram of the data signal line ND, the first auxiliary trace D1 and the second auxiliary trace D2 in the layout structure shown in Figure 14, wherein the first auxiliary trace D1 is disposed in a different layer from the data signal line ND, and the second auxiliary trace D2 is disposed in a different layer from the data signal line ND. Moreover, the first auxiliary trace D1 is also disposed in a different layer from the second auxiliary trace D2, so that the data signal line ND, the first auxiliary trace D1 and the second auxiliary trace D2 are disposed in different layers from each other.

[0152] Figure 16 shows a partial layout structure schematic diagram of a larger range than Figure 15, specifically, Figure 16 shows 32 pixel circuits 10, which form a matrix of four rows and eight columns along the first direction X and the second direction Y. Referring to the dotted line path shown in Figure 16, part of the data signal line ND is electrically connected to the second connection line segment DH1 in the second auxiliary trace D2, and then the second connection line segment DH1 in the second auxiliary trace D2 is electrically connected to the second connection line segment DV1 in the first auxiliary trace D1, so as to layout part of the fan-out trace electrically connected to the part of the data signal line ND in the display area.

[0153] As shown in FIGS. 15 and 16, since the data signal line ND, the first auxiliary trace D1 and the second auxiliary trace D2 are arranged in different layers, the second connection line segment DH1 in the second auxiliary trace D2 and the second connection line segment DV1 in the first auxiliary trace D1 are electrically connected through the contact hole K2 in the region where they overlap. There are two ways for the connection between the data signal line ND and the second connection line segment DH1 in the second auxiliary trace D2. In the first way, the second connection line segment DH1 in the second auxiliary trace D2 extends in the first direction X for a distance and then extends in the second direction Y for a distance before being electrically connected to the data signal line ND through the contact hole K1. In the second way, the second connection line segment DH1 in the second auxiliary trace D2 is first electrically connected to the first connection line segment DV1 in the second auxiliary trace D1 through the contact hole, and then the first connection line segment DV1 in the second auxiliary trace D1 extends in the first direction Y for a distance and then extends in the second direction Y for a distance before being electrically connected to the data signal line ND through the contact hole K1. In this way, the second connection line segment DH1 in the second auxiliary trace D2 is electrically connected to the data signal line ND through the first connection line segment DV1 in the second auxiliary trace D1, and the second connection line segment DH1 in the second auxiliary trace D2 is electrically connected to the fan-out trace through the first connection line segment DV1 in the second auxiliary trace D1.

[0154] As shown in FIG. 16, the first connection line segment DV1 and the first non-connection line segment DV2 in the first auxiliary trace D1 have a gap therebetween to insulate the first connection line segment DV1 and the first non-connection line segment DV2. Similarly, the second connection line segment DH1 and the second non-connection line segment DH2 in the second auxiliary trace D2 have a gap therebetween to insulate the first connection line segment DV1 and the first non-connection line segment DV2.

[0155] As shown in FIGS. 14-16, two data signal lines ND corresponding to one column of pixel circuits 10 are distributed on the opposite sides of the column of pixel circuits 10 along the second direction Y, and one first auxiliary trace D1 is arranged between the two data signal lines ND between the adjacent two columns of pixel circuits 10. Thus, the two data signal lines ND between the adjacent two columns of pixel circuits 10 belong to two columns of pixel circuits, and the first auxiliary trace D1 is arranged between the two data signal lines ND without overlapping with other traces, so that the distance between the data signal lines ND can be increased, the coupling capacitance between the data signal lines ND can be reduced, and the stability of the signal transmission of the data signal lines ND can be improved.

[0156] Fig. 17 shows a schematic diagram of the circuit structure of the pixel circuit 10 in the layout structure shown in Fig. 14. Compared with the pixel circuit shown in Fig. 6, the pixel circuit 10 shown in Fig. 17 further comprises a bias transistor T8. The first electrode of the bias transistor T8 is electrically connected with the bias signal line DVH, the second electrode of the bias transistor T8 is electrically connected with at least one of the first electrode and the second electrode of the driving transistor T3, and the gate electrode of the bias transistor T8 is electrically connected with the scanning signal line SP. In the pixel circuit 10 shown in Fig. 17, the second electrode of the bias transistor T8 is electrically connected with the first electrode of the driving transistor T3 as an example.

[0157] When the bias transistor T8 is turned on, the bias transistor T8 can transmit the adjustment signal transmitted on the bias signal line DVH to the first electrode and / or the second electrode of the driving transistor T3, so as to bias the first electrode and / or the second electrode of the driving transistor T3, improve the first frame brightness when displaying a picture, avoid the first frame brightness being too low, and ensure that the picture display effect is good in consistency. In addition, before the gate electrode of the driving transistor T3 is reset, by controlling the bias transistor T8 to be turned on, the bias voltage provided by the bias signal line DVH can be written to the first electrode and / or the second electrode of the driving transistor T3, so as to refresh the potential of the first electrode and / or the second electrode of the driving transistor T3, and set the device characteristics of the driving transistor T3 to a determined initial state, so as to eliminate the influence of the data signal written in the last frame on the device characteristics of the driving transistor T3. After the data voltage is written to the driving transistor T3, the voltage of the first electrode and / or the second electrode of the driving transistor T3 will leak, especially under low-frequency driving, the leakage is more obvious, which causes the potential of the first electrode and / or the second electrode of the driving transistor T3 to shift greatly. At this time, by controlling the bias transistor T8 to be turned on, the bias voltage is written to the first electrode and / or the second electrode of the driving transistor T3 by the bias transistor T8, so as to maintain the bias state of the driving transistor T3 consistent with the bias state when the data voltage is written, so as to improve the stability of the working state of the driving transistor T3, improve the low-frequency flicker, and thus improve the picture display effect of the display panel.

[0158] Referring to FIG. 10, the layout structure shown in FIG. 14 includes layout structures of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG, the metal layer M2, the metal layer M3, and the metal layer M4. For the sake of clarity, FIG. 18a shows a layout structure diagram of the active layer poly in the layout structure shown in FIG. 14, FIG. 18b shows a layout structure diagram of the metal layer M1 in the layout structure shown in FIG. 14, FIG. 18c shows a layout structure diagram of the metal layer MC in the layout structure shown in FIG. 14, FIG. 18d shows a layout structure diagram of the oxide layer IGZO in the layout structure shown in FIG. 14, FIG. 18e shows a layout structure diagram of the metal layer MG in the layout structure shown in FIG. 14, FIG. 18f shows a layout structure diagram of the metal layer M2 in the layout structure shown in FIG. 14, FIG. 18g shows a layout structure diagram of the metal layer M3 in the layout structure shown in FIG. 14, and FIG. 18h shows a layout structure diagram of the metal layer M4 in the layout structure shown in FIG. 14. FIG. 19a shows a layout structure diagram of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG, and the metal layer M2 in the layout structure shown in FIG. 14, and FIG. 19b shows a layout structure diagram of the metal layer M2, the metal layer M3, and the metal layer M4 in the layout structure shown in FIG. 14.

[0159] As shown in FIGS. 18g-18h and 19b, along the second direction Y, two data signal lines ND corresponding to the pixel circuit 10 are distributed on opposite sides of the column of pixel circuits 10, and the first auxiliary wire D1 is disposed in a layer different from the data signal line ND. Specifically, the first auxiliary wire D1 is located in the metal layer M3, and the data signal line ND is located in the metal layer M4. In addition, the display area further includes a first power signal line PVDD, and the first power signal line PVDD includes a first sub-power signal line PVDD1 extending along the first direction X, and the first sub-power signal line PVDD1 is also located in the metal layer M4 and disposed in the same layer as the data signal line ND.

[0160] As shown in FIGS. 18f-18h and 19b, the second auxiliary wire D2 is disposed in a layer different from the data signal line ND, and the second auxiliary wire D2 is disposed in a layer different from the first auxiliary wire D1, and the second auxiliary wire D2 is located in the metal layer M2.

[0161] As shown in FIG. 16, FIG. 18f-FIG. 18h and FIG. 19b, the first connection line segment DV1 in the first auxiliary trace D1 in the metal layer M3 is electrically connected with the second connection line segment DH1 in the second auxiliary trace D2 in the metal layer M2 through the connection part C1 in the metal layer M3 and the connection part C2 in the metal layer M2; similarly, the first non-connection line segment DV2 in the first auxiliary trace D1 in the metal layer M3 is electrically connected with the second non-connection line segment DH2 in the second auxiliary trace D2 in the metal layer M3 through the connection part C1 in the metal layer M3 and the connection part C2 in the metal layer M2.

[0162] As shown in FIG. 16, FIG. 18f-FIG. 18h and FIG. 19b, and as known from the foregoing, the second connection line segment DH1 in the second auxiliary trace D2 in the metal layer M2 can be electrically connected with the data signal line ND in the metal layer M4 through extending a distance in the first direction X and a distance in the second direction Y by itself; or, the second connection line segment DH1 in the second auxiliary trace D2 in the metal layer M2 is electrically connected with the first connection line segment DV1 in the first auxiliary trace D1 in the metal layer M3 first. Further, the first connection line segment DV1 in the first auxiliary trace D1 in the metal layer M3 is electrically connected with the data signal line ND in the metal layer M4 through extending a distance in the first direction X and a distance in the second direction Y by itself.

[0163] As shown in FIG. 17, FIG. 18a and FIG. 19a, the data write transistor T2 includes a channel region p2 in the active layer poly, and a first pole p21 and a second pole p22 connected with the channel region p2; the driving transistor T3 includes a channel region p3 in the active layer poly, and a first pole p31 and a second pole p32 connected with the channel region p3; the second pole p22 of the data write transistor T2 is electrically connected with the first pole p31 of the driving transistor T3 in the same layer.

[0164] As shown in FIGS. 17, 18a, 18f-18h, the first electrode p21 of the data writing transistor T2 is electrically connected with the data signal line ND through the connection C4 in the metal layer M2, the connection C5 in the metal layer M3, and the connection C3 in the metal layer M4. The connection C4 in the metal layer M2, the connection C5 in the metal layer M3, and the connection C3 in the metal layer M4 are also used to connect the second connection segment DH1 in the second auxiliary wire D2 with the data signal line ND, i.e., the connection position of the second connection segment DH1 in the second auxiliary wire D2 with the data signal line ND and the connection position of the first electrode p21 of the data writing transistor T2 with the data signal line ND at least partially overlap, so that the number of contact holes between the metal layer M2 and the metal layer M4 can be reduced, thereby leaving more space for the data signal line ND, the first auxiliary wire D1, and the second auxiliary wire D2.

[0165] As shown in FIGS. 17, 18a-18b, and 19a, the scan signal line SP* can be located in the metal layer M1 and extend along the second direction Y. In the direction perpendicular to the plane where the display panel is located, the scan signal line SP* at least partially overlaps with the channel region p2 of the data writing transistor T2. Optionally, in the direction perpendicular to the plane where the display panel is located, the portion of the active layer poly that overlaps with the scan signal line SP* is the channel region p2 of the data writing transistor T2, and the portion of the scan signal line SP* that overlaps with the active layer poly is the gate g2 of the data writing transistor T2, so that the gate of the data writing transistor T2 is electrically connected with the scan signal line SP*.

[0166] As shown in FIGS. 17, 18a, and 19a, the first light-emitting control transistor T1 includes a channel region p1 in the active layer poly, and a first electrode p11 and a second electrode p12 connected with the channel region p1. The second electrode p12 of the first light-emitting control transistor T1 is electrically connected with the first electrode p31 of the driving transistor T3 in the same layer. As shown in FIGS. 17, 18a, and 18f-18h, the first electrode p11 of the first light-emitting control transistor T1 is electrically connected with the first sub power signal line PVDD1 through the connection C6 in the metal layer M2, the connection C7 in the metal layer M3, and the connection C8 in the metal layer M4.

[0167] As shown in FIGS. 17, 18a-18b and 19a, the light emitting control signal line EMIT can be located in the metal layer M1 and extend along the second direction Y, and in the direction perpendicular to the plane where the display panel is located, the light emitting control signal line EMIT at least partially overlaps the channel region p1 of the first light emitting control transistor T1; optionally, in the direction perpendicular to the plane where the display panel is located, the portion of the light emitting control signal line EMIT overlapping the channel region p1 of the first light emitting control transistor T1 is the gate g1 of the first light emitting control transistor T1, so that the gate g1 of the first light emitting control transistor T1 is electrically connected with the light emitting control signal line EMIT.

[0168] As shown in FIGS. 17, 18a-18b and 19a, the first plate Cst1 of the storage capacitor Cst can be located in the metal layer M1, and the first plate Cst1 of the storage capacitor Cst also serves as the gate g3 of the driving transistor T3, and in the direction perpendicular to the plane where the display panel is located, the first plate Cst1 of the storage capacitor Cst overlaps the channel region p3 of the driving transistor T3. As shown in FIGS. 17, 18c and 18f-18h, the second plate Cst2 of the storage capacitor Cst can be located in the metal layer MC, and the second plate Cst2 of the storage capacitor Cst is electrically connected with the first sub power signal line PVDD1 through the connection part C6 located in the metal layer M2, the connection part C7 located in the metal layer M3 and the connection part C8 located in the metal layer M4.

[0169] As shown in FIGS. 18g-18h and 19b, the two data signal lines ND corresponding to the pixel circuit 10 electrically connected are distributed on the two sides of the pixel circuit 10 along the second direction Y, and the first auxiliary wire D1 is arranged between the two data signal lines ND between the two adjacent pixel circuits 10, and the first sub power signal line PVDD1 is located between the two data signal lines ND corresponding to the pixel circuit 10 electrically connected.

[0170] It can be understood that the width of the first sub power signal line PVDD1 along the second direction Y can be appropriately narrowed to leave more space for the data signal line ND and the first auxiliary wire D1; and considering that the resistance of the first sub power signal line PVDD1 will increase after narrowing the width of the first sub power signal line PVDD1 along the second direction Y, the width of the first sub power signal line PVDD1 along the second direction Y is appropriately widened in the region with space to reduce the resistance of the first sub power signal line PVDD1.

[0171] As shown in FIG. 15, FIG. 18h and FIG. 19b, the first sub power supply signal line PVDD1 includes a first sub section Z1, a second sub section Z2 and a third sub section Z3, the first sub section Z1 is connected with the third sub section Z3 through the second sub section Z2, the third sub section Z3 is connected with the first sub section Z1 through the second sub section Z2, the width of the first sub section Z1 along the second direction Y is greater than 1.5 times of the width of the second sub section Z2 along the second direction Y, and the width of the third sub section Z3 is greater than 1.5 times of the width of the second sub section Z2 along the second direction Y. In this way, the first sub power supply signal line PVDD1 is locally widened and locally narrowed along the first direction X, so as to leave more space for the data signal line ND and the first auxiliary trace D1, while reducing the resistance of the first sub power supply signal line PVDD1.

[0172] As shown in FIG. 18c and FIG. 19a, the second plate Cst2 of the storage capacitor Cst of a row of pixel circuits 10 is electrically connected in the same layer, and as known from the foregoing, the second plate Cst2 of the storage capacitor Cst is also electrically connected with the first sub power supply signal line PVDD1. Thus, the second plate Cst2 of the storage capacitor Cst of a row of pixel circuits 10 electrically connected in the same layer constitutes the second sub power supply signal line PVDD2, the second sub power supply signal line PVDD2 extends along the second direction Y, the second sub power supply signal line PVDD2 is arranged in a different layer from the first sub power supply signal line PVDD1, and the second sub power supply signal line PVDD2 is electrically connected with the first sub power supply signal line PVDD1. In this way, the first sub power supply signal line PVDD1 and the second sub power supply signal line PVDD2 constitute a grid structure, which can reduce the overall resistance of the first power supply signal line PVDD, reduce the power consumption of the first power supply signal line PVDD, and improve the signal transmission stability of the first power supply signal line PVDD, thereby improving the display uniformity and other display effects of the display panel.

[0173] As shown in FIG. 17, FIG. 18a and FIG. 19a, the second light emitting control transistor T6 includes a channel region p6 in the active layer poly, and a first pole p61 and a second pole p62 connected with the channel region p6; the first pole p61 of the second light emitting control transistor T6 is electrically connected in the same layer with the second pole p32 of the driving transistor T3. As shown in FIG. 17, FIG. 18a, FIG. 18f-FIG. 18h, the second pole p62 of the second light emitting control transistor T6 is electrically connected with the light emitting element 20 through the connecting part C9 in the metal layer M2.

[0174] In the direction perpendicular to the plane where the display panel is located, the light-emitting control signal line EMIT at least partially overlaps with the channel region p6 of the second light-emitting control transistor T6, as shown in FIGS. 17, 18a and 18b; optionally, in the direction perpendicular to the plane where the display panel is located, the portion of the light-emitting control signal line EMIT overlapping with the channel region p6 of the second light-emitting control transistor T6 is the gate g6 of the second light-emitting control transistor T6, so that the gate g6 of the second light-emitting control transistor T6 is electrically connected with the light-emitting control signal line EMIT.

[0175] In combination with FIGS. 17, 18d and 19a, the compensation transistor T4 and the gate reset transistor T5 can be oxide thin film transistors, i.e., IGZO thin film transistors; wherein the compensation transistor T4 includes a channel region p4 located in an oxide layer IGZO, and a first electrode p41 and a second electrode p42 connected with the channel region p4; the gate reset transistor T5 includes a channel region p5 located in an oxide layer IGZO, and a first electrode p51 and a second electrode p52 connected with the channel region p5.

[0176] In combination with FIGS. 17, 18a-18d and 18f, the first electrode p41 of the compensation transistor T4 is electrically connected with the second electrode p32 of the driving transistor T3 through a connection portion C10 located in the metal layer M2, the second electrode p42 of the compensation transistor T4 is directly electrically connected with the second electrode p52 of the gate initialization transistor T5 in the oxide layer IGZO, and is electrically connected with the gate g3 of the driving transistor T3 through a via in the second electrode plate Cst2 of the storage capacitor Cst in the metal layer MC and a connection portion C11 located in the metal layer M2.

[0177] It should be noted that in combination with FIGS. 17, 18b, 18d and 18f-18h, the connection portion C11 located in the metal layer M2 is electrically connected with the second electrode p42 of the compensation transistor T4, the second electrode p52 of the gate initialization transistor T5 and the gate g3 of the driving transistor T3, i.e., the connection portion C11 located in the metal layer M2 corresponds to the first node N1; and as known from the foregoing, the connection portion C7 located in the metal layer M3 is connected with the first power supply signal line PVDD; in the direction perpendicular to the plane where the display panel is located, the connection portion C7 of the metal layer M3 and the first sub-section Z1 and the third sub-section Z3 of the first sub-power supply signal line PVDD1 cover the connection portion C11 located in the metal layer M2, i.e., cover the first node N1, so as to maintain the stability of the potential of the first node N1, i.e., maintain the stability of the potential of the gate g3 of the driving transistor T3, which is conducive to improving the display effect of the display panel.

[0178] As shown in FIGS. 17, 18c-18e and 19a, the display region includes scan signal lines S1 and S2; the scan signal line S1 includes first and second sub-scan signal lines S11 and S12 that transmit the same scan signal, the first sub-scan signal line S11 is located in the metal layer MC and extends along the second direction Y, and the second sub-scan signal line S12 is located in the metal layer MG and extends along the second direction Y; in the direction perpendicular to the plane in which the display panel is located, the first sub-scan signal line S11, the second sub-scan signal line S12, and the channel region p5 of the gate reset transistor T5 overlap each other. Optionally, in the direction perpendicular to the plane in which the display panel is located, the portion of the oxide layer IGZO that overlaps both the first sub-scan signal line S11 and the second sub-scan signal line S12 is the channel region p5 of the gate reset transistor T5, the portion of the first sub-scan signal line S11 that directly faces the channel region p5 of the gate reset transistor T5 is the bottom gate bg5 of the gate reset transistor T5, so that the bottom gate bg5 of the gate reset transistor T5 is electrically connected to the first sub-scan signal line S11; the portion of the second sub-scan signal line S12 that directly faces the channel region p5 of the gate reset transistor T5 is the top gate tg5 of the gate reset transistor T5, so that the top gate tg5 of the gate reset transistor T5 is electrically connected to the second sub-scan signal line S12, thereby making the top gate tg5 and the bottom gate bg5 of the gate reset transistor T5 both electrically connected to the first scan signal line S1 and receive the same scan signal.

[0179] Similarly, as shown in FIGS. 17, 18c-18e and 19a, the scan signal line S2 includes third and fourth sub-scan signal lines S21 and S22 that transmit the same scan signal, the third sub-scan signal line S21 is located in the metal layer MC and extends along the first direction X, and the fourth sub-scan signal line S22 is located in the metal layer MG and extends along the first direction X; in the direction perpendicular to the plane in which the display panel is located, the third sub-scan signal line S21, the fourth sub-scan signal line S22, and the channel region p4 of the compensation transistor T4 overlap each other. Optionally, in the direction perpendicular to the plane in which the display panel is located, the portion of the oxide layer IGZO that overlaps both the third sub-scan signal line S21 and the fourth sub-scan signal line S22 is the channel region p4 of the compensation transistor T4, the portion of the third sub-scan signal line S21 that directly faces the channel region p4 of the compensation transistor T4 is the bottom gate bg4 of the compensation transistor T4, so that the bottom gate bg4 of the compensation transistor T4 is electrically connected to the third sub-scan signal line S21; the portion of the fourth sub-scan signal line S22 that directly faces the channel region p4 of the compensation transistor T4 is the top gate tg4 of the compensation transistor T4, so that the top gate tg4 of the compensation transistor T4 is electrically connected to the fourth sub-scan signal line S22, thereby making the top gate tg4 and the bottom gate bg4 of the compensation transistor T4 both electrically connected to the second scan signal line S2 and receive the same scan signal.

[0180] As shown in FIGS. 17, 18c and 19a, the display area includes a first reference signal line ref1, which can be located in the metal layer MC, and extends along the second direction Y, and one row of pixel circuits 10 is electrically connected to one first reference signal line ref1. As shown in FIGS. 17, 18c-18d and 18f, the first electrode p51 of the gate reset transistor T5 is electrically connected to the first reference signal line ref1 through the connection part C12 located in the metal layer M2 and the connection part C13 located in the metal layer MC, and as shown in FIG. 18d, the first electrodes p51 of the gate reset transistors T5 of the pixel circuits 10 adjacent to each other along the second direction Y in one row are electrically connected in the same layer.

[0181] As shown in FIGS. 17, 18a and 19a, the anode reset transistor T7 includes a channel region p7 located in the active layer poly, and a first electrode p71 and a second electrode p72 connected to the channel region p7; the second electrode p72 of the anode reset transistor T7 is electrically connected to the light emitting element 20 through the connection part C9 located in the metal layer M2.

[0182] As shown in FIGS. 17, 18a-18b and 19a, the display area includes a scan signal line SP, which is located in the metal layer M1 and extends along the second direction Y, and at least partially overlaps the channel region p7 of the anode reset transistor T7 in the direction perpendicular to the plane where the display panel is located. Optionally, the part of the scan signal line SP overlapping the channel region p7 of the anode reset transistor T7 in the direction perpendicular to the plane where the display panel is located is the gate g7 of the anode reset transistor T7, so that the scan signal line SP is electrically connected to the gate of the anode reset transistor T7.

[0183] As shown in FIGS. 17, 18c, 18g and 12a-12b, the display area includes a second reference signal line ref2, which includes a third sub-reference signal line ref21 and a fourth sub-reference signal line ref22, the third sub-reference signal line ref21 extends along the second direction Y and is arranged along the first direction X, the fourth sub-reference signal line ref22 extends along the first direction X and is arranged along the second direction Y, the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22 are arranged in different layers and are electrically connected.

[0184] Specifically, as shown in FIGS. 18c, 18f-18g, the third sub-reference signal line ref21 is located in the metal layer MC, the fourth sub-reference signal line ref22 is located in the metal layer M3, and the third sub-reference signal line ref21 is electrically connected with the fourth sub-reference signal line ref22 through the connecting part C14 located in the metal layer MC, the connecting part C15 located in the metal layer M2, and the connecting part C16 located in the metal layer M3; and as shown in FIGS. 18a, 18f-18g, the fourth sub-reference signal line ref22 is electrically connected with the first pole p71 of the anode reset transistor T7 through the connecting part C16 located in the metal layer M3 and the connecting part C15 located in the metal layer M2.

[0185] In this way, by arranging the second reference signal line ref2 to include the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22 extending in different directions and being electrically connected, the second reference signal line ref2 also forms a grid structure, and FIG. 20 further shows the grid structure formed by the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22. In this way, the overall resistance of the second reference signal line ref2 is reduced, the power consumption of the second reference signal line ref2 is reduced, and the signal transmission stability of the second reference signal line ref2 is improved, which is beneficial to improving the display uniformity and other display effects of the display panel.

[0186] As shown in FIGS. 17, 18a and 19a, the bias transistor T8 includes a channel region p8 located in the active layer poly, and a first pole p81 and a second pole p82 connected with the channel region p8. As shown in FIGS. 17, 18a-18b and 19a, in the direction perpendicular to the plane where the display panel is located, the scan signal line SP at least partially overlaps with the channel region p8 of the bias transistor T8. Optionally, in the direction perpendicular to the plane where the display panel is located, the part of the scan signal line SP overlapping with the channel region p8 of the bias transistor T8 is the gate g8 of the bias transistor T8, so that the scan signal line SP is electrically connected with the gate of the bias transistor T8.

[0187] As shown in FIGS. 17, 18a and 18f, the second pole p82 of the bias transistor T8 is electrically connected with the first pole p31 of the driving transistor T3 through the connecting part C17 located in the metal layer M2.

[0188] As shown in FIGS. 17, 18c, 18g and 19a-19b, the display area includes a bias signal line DVH, which includes a first sub-bias signal line DVH1 and a second sub-bias signal line DVH2, the first sub-bias signal line DVH1 extends along the second direction Y and is arranged along the first direction X, the second sub-bias signal line DVH2 extends along the first direction X and is arranged along the second direction Y, the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are arranged in different layers and are electrically connected.

[0189] Specifically, as shown in FIGS. 18c, 18f-18g, the first sub-bias signal line DVH1 is located in the metal layer M1, the second sub-bias signal line DVH2 is located in the metal layer M3, the first sub-bias signal line DVH1 is electrically connected to the second sub-bias signal line DVH2 through the connection part C18 in the metal layer M1, the connection part C19 in the metal layer M2 and the connection part C20 in the metal layer M3; and as shown in FIGS. 18a, 18f-18g, the second sub-bias signal line DVH2 is electrically connected to the first electrode p81 of the bias transistor T8 through the connection part C20 in the metal layer M3 and the connection part C19 in the metal layer M2, and in a row of pixel circuits 10, the first electrodes p81 of the bias transistors T8 of the pixel circuits 10 adjacent to each other along the second direction Y are electrically connected in the same layer.

[0190] In this way, by arranging the bias signal line DVH to include the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 extending along different directions and being cross-connected, a grid structure of the bias signal line DVH is formed, as shown in FIG. 20, and thus the overall resistance of the bias signal line DVH is reduced, the power consumption of the bias signal line DVH is reduced, the signal transmission stability of the bias signal line DVH is improved, and the display uniformity and other display effects of the display panel are improved.

[0191] As shown in FIG. 18f and FIG. 20, in the four adjacent pixel circuits 10, two of the pixel circuits 10 are provided with the fourth sub-reference signal line ref22, and the other two of the pixel circuits 10 are provided with the second sub-bias signal line DVH2, and the fourth sub-reference signal line ref22 and the second sub-bias signal line DVH2 are arranged alternately along the second direction Y, that is, the pixel circuit rows provided with the fourth sub-reference signal line ref22 are arranged alternately, and the pixel circuit rows provided with the second sub-bias signal line DVH2 are arranged alternately, that is, the pixel circuit rows provided with the fourth sub-reference signal line ref22 and the pixel circuit rows provided with the second sub-bias signal line DVH2 are arranged alternately along the second direction Y, so that the number of the fourth sub-reference signal line ref22 and the second sub-bias signal line DVH2 can be reduced, and more space can be left for the data signal line ND and the first auxiliary trace D1.

[0192] Similarly, as shown in FIG. 18c and FIG. 20, in the four adjacent pixel circuits 10, two of the pixel circuits 10 are provided with the third sub-reference signal line ref21, and the other two of the pixel circuits 10 are provided with the first sub-bias signal line DVH1, and the third sub-reference signal line ref21 and the first sub-bias signal line DVH1 are arranged alternately along the first direction X, that is, the pixel circuit rows provided with the third sub-reference signal line ref21 are arranged alternately, and the pixel circuit rows provided with the first sub-bias signal line DVH1 are arranged alternately, that is, the pixel circuit rows provided with the third sub-reference signal line ref21 and the pixel circuit rows provided with the first sub-bias signal line DVH1 are arranged alternately along the second direction Y, so that the number of the third sub-reference signal line ref21 and the first sub-bias signal line DVH1 can be reduced, and more space can be left for the second auxiliary trace D2.

[0193] As shown in FIG. 19a and FIG. 19b, in a row of pixel circuits 10, every two adjacent pixel circuits 10 form a pixel circuit repeating unit Q, and the two pixel circuits 10 in the pixel circuit repeating unit Q are mirror-symmetrical along the first direction X, and the pixel circuit repeating units Q are arranged repeatedly along the second direction Y; in two adjacent rows of pixel circuits 10, the pixel circuit repeating units Q in one row of pixel circuits 10 are first repeating units Q1, and the pixel circuit repeating units Q in the other row of pixel circuits 10 are second repeating units Q2, and the first repeating units Q1 and the second repeating units are arranged staggeredly along the second direction Y.

[0194] As can be seen, when the two data signal lines ND corresponding to one column of pixel circuits 10 are distributed on the opposite sides of the column of pixel circuits along the second direction Y, and the data signal lines ND, the first auxiliary trace D1 and the second auxiliary trace D2 are arranged in different layers from each other, more space is left for the double data signal lines ND, the first auxiliary trace D1 and the second auxiliary trace D2 by reducing the number of contact holes connected to the data signal lines ND, locally narrowing the first sub power signal line PVDD1 along the first direction X, and arranging the second reference signal line ref2 and the bias signal line DVH to be spaced from the row arrangement of pixel circuits and the column arrangement of pixel circuits.

[0195] On this basis, one first auxiliary trace D1 can be arranged corresponding to two columns of pixel circuits 10, the first auxiliary trace D1 can be located between the two data signal lines ND between the adjacent two columns of pixel circuits 10, and the first sub power signal line PVDD1 can be located between the two data signal lines ND corresponding to one column of pixel circuits 10. Thus, the two data signal lines ND between the adjacent two columns of pixel circuits 10 belong to two columns of pixel circuits, the first auxiliary trace D1 is arranged between the two data signal lines ND between the adjacent two columns of pixel circuits 10, and the first auxiliary trace D1 does not overlap with other traces, so that the distance between the data signal lines ND can be increased, the coupling capacitance between the data signal lines ND can be reduced, and the stability of the signal transmitted by the data signal lines ND can be improved.

[0196] It can be understood that when the two data signal lines ND corresponding to one column of pixel circuits 10 are distributed on the opposite sides of the column of pixel circuits along the second direction Y, and the data signal lines ND, the first auxiliary trace D1 and the second auxiliary trace D2 are arranged in different layers from each other, one first auxiliary trace D1 can also be arranged corresponding to one column of pixel circuits 10, and the first auxiliary trace D1 and the first sub power signal line PVDD1 can also be located between the two data signal lines ND corresponding to one column of pixel circuits 10.

[0197] FIG. 21 shows a partial layout structure schematic diagram of another display panel provided by an embodiment of the present application. As shown in FIG. 21, along the second direction Y, the two data signal lines ND corresponding to one column of pixel circuits 10 are distributed on the opposite sides of the column of pixel circuits 10. FIG. 21 shows eight pixel circuits 10, which form a matrix arranged in two rows and four columns along the first direction X and the second direction Y.

[0198] For the sake of clarity, FIG. 22 shows a partial layout structure diagram of the data signal line ND, the first auxiliary trace D1 and the second auxiliary trace D2 in the layout structure shown in FIG. 21, wherein the first auxiliary trace D1 is arranged in a different layer from the data signal line ND, the second auxiliary trace D2 is arranged in a different layer from the data signal line ND, and the first auxiliary trace D1 is also arranged in a different layer from the second auxiliary trace D2, so that the data signal line ND, the first auxiliary trace D1 and the second auxiliary trace D2 are arranged in different layers from each other.

[0199] Unlike the layout structure shown in FIG. 14, in the layout structure shown in FIGS. 21 and 22, one or two first auxiliary traces D1 can be arranged corresponding to one column of pixel circuits 10; in the direction perpendicular to the plane in which the display panel is located, the first auxiliary trace D1 and the data signal line ND at least partially overlap, so that in the plane parallel to the plane in which the display panel is located, the data signal line ND and the first auxiliary trace D1 occupy a smaller space, which is conducive to the layout of the data signal line ND and the first auxiliary trace D1, and a larger number of first auxiliary traces D1 can be arranged; as known from the foregoing, the first non-connected line segment DV2 in the first auxiliary trace D1 and the second non-connected line segment DH2 in the second auxiliary trace D1 form a grid structure and are electrically connected to the fixed potential signal, and increasing the number of first auxiliary traces D1 can reduce the resistance of the grid structure formed by the first non-connected line segment DV2 in the first auxiliary trace D1 and the second non-connected line segment DH2 in the second auxiliary trace D1, and further reduce the resistance of the signal line of the fixed potential signal to which the first non-connected line segment DV2 in the first auxiliary trace D1 and the second non-connected line segment DH2 in the second auxiliary trace D1 are connected.

[0200] FIG. 23 shows a partial layout structure diagram of a larger range than FIG. 22, specifically, FIG. 23 shows 32 pixel circuits 10 arranged in a matrix of four rows and eight columns along the first direction X and the second direction Y. Referring to the dotted line path shown in FIG. 16, part of the data signal line ND is electrically connected to the second connected line segment DH1 in the second auxiliary trace D2, and then the second connected line segment DH1 in the second auxiliary trace D2 is electrically connected to the second connected line segment DV1 in the first auxiliary trace D1, so that the part of the fan-out trace electrically connected to the part of the data signal line ND is arranged in the display area.

[0201] As shown in FIGS. 22 and 23, since the data signal line ND, the first auxiliary trace D1 and the second auxiliary trace D2 are arranged in different layers, the data signal line ND and the second connection line segment DH1 in the second auxiliary trace D2 are electrically connected through the contact hole K1, and the second connection line segment DH1 in the second auxiliary trace D2 extends in the first direction X for a distance to be electrically connected with the data signal line D2 through the contact hole K1; the second connection line segment DH1 in the second auxiliary trace D2 and the first connection line segment DV1 in the first auxiliary trace D1 are electrically connected through the contact hole K2 in the region where they overlap, and the first connection line segment DV1 in the first auxiliary trace D1 extends in the second direction Y for a distance to be electrically connected with the second connection line segment DH1 in the second auxiliary trace D2 through the contact hole K2; the second non-connection line segment DH2 in the second auxiliary trace D2 and the first non-connection line segment DV2 in the first auxiliary trace D1 are electrically connected through the contact hole K2 in the region where they overlap, and the first non-connection line segment DV2 in the first auxiliary trace D1 extends in the second direction Y for a distance to be electrically connected with the second non-connection line segment DH2 in the second auxiliary trace D2 through the contact hole K2.

[0202] As shown in FIG. 23, the first auxiliary trace D1 has a gap between the first connection line segment DV1 and the first non-connection line segment DV2 to insulate the first connection line segment DV1 and the first non-connection line segment DV2; similarly, the second auxiliary trace D2 has a gap between the second connection line segment DH1 and the second non-connection line segment DH2 to insulate the first connection line segment DV1 and the first non-connection line segment DV2.

[0203] The circuit structure of the pixel circuit 10 in the layout structure shown in FIG. 21 still refers to FIG. 17. As shown in FIG. 10, the layout structure shown in FIG. 21 includes the layout structures of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG, the metal layer M2, the metal layer M3 and the metal layer M4. For the sake of clear illustration, FIG. 24a shows a layout structure diagram of the active layer poly in the layout structure shown in FIG. 21, FIG. 24b shows a layout structure diagram of the metal layer M1 in the layout structure shown in FIG. 21, FIG. 24c shows a layout structure diagram of the metal layer MC in the layout structure shown in FIG. 21, FIG. 24d shows a layout structure diagram of the oxide layer IGZO in the layout structure shown in FIG. 21, FIG. 24e shows a layout structure diagram of the metal layer MG in the layout structure shown in FIG. 21, FIG. 24f shows a layout structure diagram of the metal layer M2 in the layout structure shown in FIG. 21, FIG. 24g shows a layout structure diagram of the metal layer M3 in the layout structure shown in FIG. 21, and FIG. 24h shows a layout structure diagram of the metal layer M4 in the layout structure shown in FIG. 21.

[0204] Fig. 25a shows a layout structure schematic diagram of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG and the metal layer M2 in the layout structure shown in Fig. 21, and Fig. 25b shows a layout structure schematic diagram of the metal layer M2, the metal layer M3 and the metal layer M4 in the layout structure shown in Fig. 21.

[0205] As shown in Figs. 24g-24h and 25b, along the second direction Y, the pixel circuit 10 in a column corresponds to two data signal lines ND distributed on the opposite sides of the column of pixel circuits 10; the first auxiliary wire D1 is arranged in a layer different from the data signal line ND, specifically, the first auxiliary wire D1 is located in the metal layer M4, and the data signal line ND is located in the metal layer M3; and the display area further includes a first power signal line PVDD, the first power signal line PVDD includes a first sub-power signal line PVDD1, the first sub-power signal line PVDD1 extends along the first direction X, and the first sub-power signal line PVDD1 is also located in the metal layer M4 and arranged in the same layer as the first auxiliary wire D1.

[0206] As shown in Figs. 24f-24h and 25b, the second auxiliary wire D2 is arranged in a layer different from the data signal line ND, and the second auxiliary wire D2 is arranged in a layer different from the first auxiliary wire D1, and the second auxiliary wire D2 is located in the metal layer M2.

[0207] As shown in Figs. 23, 24f-24h and 25b, the first connection line segment DV1 in the first auxiliary wire D1 located in the metal layer M4 is electrically connected with the second connection line segment DH1 in the second auxiliary wire D2 located in the metal layer M2 through the connection part J1 located in the metal layer M4, the connection part J2 located in the metal layer M3 and the connection part J3 located in the metal layer M2; similarly, the first non-connection line segment DV2 in the first auxiliary wire D1 located in the metal layer M4 is electrically connected with the second non-connection line segment DH2 in the second auxiliary wire D2 located in the metal layer M2 through the connection part J1 located in the metal layer M4, the connection part J2 located in the metal layer M3 and the connection part J3 located in the metal layer M2.

[0208] As shown in Figs. 23, 24f-24h and 25b, and as known from the foregoing, the second connection line segment DH1 in the second auxiliary wire D2 located in the metal layer M2 can extend for a distance along the first direction X and then be electrically connected with the data signal line ND through the connection part J4 located in the metal layer M2 and the connection part J5 located in the metal layer M3.

[0209] As shown in FIG. 17, FIG. 24a and FIG. 25a, the data writing transistor T2 includes a channel region p2 in the active layer poly, and a first electrode p21 and a second electrode p22 connected to the channel region p2; the driving transistor T3 includes a channel region p3 in the active layer poly, and a first electrode p31 and a second electrode p32 connected to the channel region p3; the second electrode p22 of the data writing transistor T2 is electrically connected to the first electrode p31 of the driving transistor T3 in the same layer.

[0210] As shown in FIG. 17, FIG. 24a, FIG. 24f-FIG. 24h, the first electrode p21 of the data writing transistor T2 is electrically connected to the data signal line ND through the connection portion J4 in the metal layer M2 and the connection portion J5 in the metal layer M3. The connection portion J4 in the metal layer M2 and the connection portion J5 in the metal layer M3 are also used to connect the second connection line segment DH1 in the second auxiliary wiring D2 and the data signal line ND, that is, the connection position of the second connection line segment DH1 in the second auxiliary wiring D2 and the data signal line ND coincides with the connection position of the first electrode p21 of the data writing transistor T2 and the data signal line ND, so that the number of contact holes between the metal layer M2 and the metal layer M3 can be reduced, so as to leave more space for the data signal line ND, the first auxiliary wiring D1 and the second auxiliary wiring D2.

[0211] As shown in FIG. 17, FIG. 24a-FIG. 24b and FIG. 25a, the scan signal line SP* can be located in the metal layer M1 and extend along the second direction Y. In the direction perpendicular to the plane where the display panel is located, the scan signal line SP* at least partially overlaps with the channel region p2 of the data writing transistor T2. Optionally, in the direction perpendicular to the plane where the display panel is located, the part of the active layer poly overlapping with the scan signal line SP* is the channel region p2 of the data writing transistor T2, and the part of the active layer poly overlapping with the scan signal line SP* is the gate g2 of the data writing transistor T2, so that the gate of the data writing transistor T2 is electrically connected to the scan signal line SP*.

[0212] As shown in FIG. 17, FIG. 24a and FIG. 25a, the first light emitting control transistor T1 includes a channel region p1 in the active layer poly, and a first electrode p11 and a second electrode p12 connected to the channel region p1; the second electrode p12 of the first light emitting control transistor T1 is electrically connected to the first electrode p31 of the driving transistor T3 in the same layer. As shown in FIG. 17, FIG. 18a and FIG. 18f-FIG. 18h, the first electrode p11 of the first light emitting control transistor T1 is electrically connected to the first sub power signal line PVDD1 through the connection portion J6 in the metal layer M2, the connection portion J7 in the metal layer M3 and the connection portion J8 in the metal layer M4.

[0213] As shown in FIG. 17, FIG. 24a-FIG. 24b and FIG. 25a, the light emitting control signal line EMIT can be located in the metal layer M1 and extend along the second direction Y, and in the direction perpendicular to the plane where the display panel is located, the light emitting control signal line EMIT at least partially overlaps with the channel region p1 of the first light emitting control transistor T1; optionally, in the direction perpendicular to the plane where the display panel is located, the part of the light emitting control signal line EMIT overlapping with the channel region p1 of the first light emitting control transistor T1 is the gate g1 of the first light emitting control transistor T1, so that the gate g1 of the first light emitting control transistor T1 is electrically connected with the light emitting control signal line EMIT.

[0214] As shown in FIG. 17, FIG. 24a-FIG. 24b and FIG. 25a, the first plate Cst1 of the storage capacitor Cst can be located in the metal layer M1, and the first plate Cst1 of the storage capacitor Cst also serves as the gate g3 of the driving transistor T3, and in the direction perpendicular to the plane where the display panel is located, the first plate Cst1 of the storage capacitor Cst overlaps with the channel region p3 of the driving transistor T3. As shown in FIG. 17, FIG. 24c and FIG. 24f-FIG. 24h, the second plate Cst2 of the storage capacitor Cst can be located in the metal layer MC, and the second plate Cst2 of the storage capacitor Cst is electrically connected with the first sub power signal line PVDD1 through the connection part J6 located in the metal layer M2, the connection part J7 located in the metal layer M3 and the connection part J8 located in the metal layer M4.

[0215] As shown in FIG. 22, FIG. 24g-FIG. 24h and FIG. 25b, the two data signal lines ND corresponding to a column of pixel circuits 10 are distributed on the two sides of the column of pixel circuits 10 along the second direction Y, and the column of pixel circuits 10 is provided with one or two first auxiliary wires D1, and in the direction perpendicular to the plane where the display panel is located, the first auxiliary wire D1 and the data signal line ND at least partially overlap, so that the space occupied by the first auxiliary wire D1 and the data signal line ND can be reduced, and more space can be left for other signal lines, for example, the first sub power signal line PVDD1 is located between the two data signal lines ND corresponding to a column of pixel circuits 10, so that the overall width of the first sub power signal line PVDD1 along the second direction Y can be increased, and the resistance of the first sub power signal line PVDD1 can be reduced.

[0216] However, in order to arrange the data signal lines ND on both sides of a column of pixel circuits 10 along the second direction Y, in combination with FIGS. 22, 24h and 25b, the first sub power supply signal line PVDD1 includes a first sub section Z1, a second sub section Z2 and a third sub section Z3, wherein the first sub section Z1 is connected with the third sub section Z3 through the second sub section Z2, the third sub section Z3 is connected with the first sub section Z1 through the second sub section Z2, the width of the first sub section Z1 along the second direction Y is greater than 1.5 times the width of the second sub section Z2 along the second direction Y, and the width of the third sub section Z3 is greater than 1.5 times the width of the second sub section Z2 along the second direction Y. In this way, the first sub power supply signal line PVDD1 is locally widened and locally narrowed along the first direction X, so as to leave more arrangement space for the data signal lines ND and the first auxiliary traces D1 while reducing the resistance of the first sub power supply signal line PVDD1.

[0217] In combination with FIGS. 24c and 25a, the second plates Cst2 of the storage capacitors Cst of a row of pixel circuits 10 are electrically connected in the same layer, and, as known from the foregoing, the second plates Cst2 of the storage capacitors Cst are also electrically connected with the first sub power supply signal line PVDD1. Thus, the second plates Cst2 of the storage capacitors Cst of a row of pixel circuits 10 electrically connected in the same layer constitute a second sub power supply signal line PVDD2, the second sub power supply signal line PVDD2 extends along the second direction Y, the second sub power supply signal line PVDD2 is arranged in a different layer from the first sub power supply signal line PVDD1, and the second sub power supply signal line PVDD2 is electrically connected with the first sub power supply signal line PVDD1. In this way, the first sub power supply signal line PVDD1 and the second sub power supply signal line PVDD2 constitute a grid structure, which can reduce the overall resistance of the first power supply signal line PVDD, reduce the power consumption of the first power supply signal line PVDD, and improve the signal transmission stability of the first power supply signal line PVDD, thereby improving the display uniformity and other display effects of the display panel.

[0218] In combination with FIGS. 17, 24a and 25a, the second light emitting control transistor T6 includes a channel region p6 in the active layer poly, and a first pole p61 and a second pole p62 connected with the channel region p6; the first pole p61 of the second light emitting control transistor T6 is electrically connected in the same layer with the second pole p32 of the driving transistor T3. In combination with FIGS. 17, 24a, 24f-24h, the second pole p62 of the second light emitting control transistor T6 is electrically connected with the light emitting element 20 through the connection part J8 in the metal layer M2 and the connection part J9 in the metal layer M3.

[0219] In the direction perpendicular to the plane where the display panel is located, the light-emitting control signal line EMIT at least partially overlaps with the channel region p6 of the second light-emitting control transistor T6, as shown in FIGS. 17, 24a and 24b; optionally, in the direction perpendicular to the plane where the display panel is located, the portion of the light-emitting control signal line EMIT that overlaps with the channel region p6 of the second light-emitting control transistor T6 is the gate g6 of the second light-emitting control transistor T6, so that the gate g6 of the second light-emitting control transistor T6 is electrically connected with the light-emitting control signal line EMIT.

[0220] In combination with FIGS. 17, 24d and 25a, the compensation transistor T4 and the gate reset transistor T5 can be oxide thin film transistors, i.e., IGZO thin film transistors; the compensation transistor T4 includes a channel region p4 located in an oxide layer IGZO, and a first electrode p41 and a second electrode p42 connected with the channel region p4; the gate reset transistor T5 includes a channel region p5 located in an oxide layer IGZO, and a first electrode p51 and a second electrode p52 connected with the channel region p5.

[0221] [Corrected according to Rule 91 on 29.10.2024] In combination with FIGS. 17, 24a-24d, the first electrode p41 of the compensation transistor T4 is electrically connected with the second electrode p32 of the driving transistor T3 through a connection portion J10 located in a metal layer M2, the second electrode p42 of the compensation transistor T4 is directly electrically connected with the second electrode p52 of the gate initialization transistor T5 in an oxide layer IGZO, and is electrically connected with the gate g3 of the driving transistor T3 through a via in a second electrode plate Cst2 of a storage capacitor Cst in a metal layer MC and a connection portion J11 located in the metal layer M2.

[0222] It should be noted that in combination with FIGS. 17, 24b, 24d and 24f-24h, the connection portion J11 of the metal layer M2 is electrically connected with the second electrode p42 of the compensation transistor T4, the second electrode p52 of the gate initialization transistor T5 and the gate g3 of the driving transistor T3, i.e., the connection portion J11 located in the metal layer M2 corresponds to the first node N1; in the direction perpendicular to the plane where the display panel is located, the first sub-section Z1 and the third sub-section Z3 of the first sub-power supply signal line PVDD1 at least partially cover the connection portion C11 located in the metal layer M2, i.e., at least partially cover the first node N1, so as to maintain the stability of the potential of the first node N1, i.e., the stability of the potential of the gate g3 of the driving transistor T3, which is conducive to improving the display effect of the display panel.

[0223] As shown in FIG. 17, FIG. 24c-FIG. 24e and FIG. 25a, the display area includes scan signal lines S1 and S2; the scan signal line S1 includes first and second sub scan signal lines S11 and S12 that transmit the same scan signal, the first sub scan signal line S11 is located in the metal layer MC and extends along the second direction Y, and the second sub scan signal line S12 is located in the metal layer MG and extends along the second direction Y; in the direction perpendicular to the plane on which the display panel is located, the first sub scan signal line S11, the second sub scan signal line S12 and the channel region p5 of the gate reset transistor T5 overlap. Optionally, in the direction perpendicular to the plane on which the display panel is located, the part of the oxide layer IGZO that overlaps both the first and second sub scan signal lines S11 and S12 is the channel region p5 of the gate reset transistor T5, the part of the first sub scan signal line S11 that directly faces the channel region p5 of the gate reset transistor T5 is the bottom gate bg5 of the gate reset transistor T5, so that the bottom gate bg5 of the gate reset transistor T5 is electrically connected to the first sub scan signal line S11; the part of the second sub scan signal line S12 that directly faces the channel region p5 of the gate reset transistor T5 is the top gate tg5 of the gate reset transistor T5, so that the top gate tg5 of the gate reset transistor T5 is electrically connected to the second sub scan signal line S12, so that the top gate tg5 and the bottom gate bg5 of the gate reset transistor T5 are both electrically connected to the first scan signal line S1 and receive the same scan signal.

[0224] Similarly, as shown in FIG. 17, FIG. 24c-FIG. 24e and FIG. 25a, the scan signal line S2 includes third and fourth sub scan signal lines S21 and S22 that transmit the same scan signal, the third sub scan signal line S21 is located in the metal layer MC and extends along the first direction X, and the fourth sub scan signal line S22 is located in the metal layer MG and extends along the first direction X; in the direction perpendicular to the plane on which the display panel is located, the third sub scan signal line S21, the fourth sub scan signal line S22 and the channel region p4 of the compensation transistor T4 overlap. Optionally, in the direction perpendicular to the plane on which the display panel is located, the part of the oxide layer IGZO that overlaps both the third and fourth sub scan signal lines S21 and S22 is the channel region p4 of the compensation transistor T4, the part of the third sub scan signal line S21 that directly faces the channel region p4 of the compensation transistor T4 is the bottom gate bg4 of the compensation transistor T4, so that the bottom gate bg4 of the compensation transistor T4 is electrically connected to the third sub scan signal line S21; the part of the fourth sub scan signal line S22 that directly faces the channel region p4 of the compensation transistor T4 is the top gate tg4 of the compensation transistor T4, so that the top gate tg4 of the compensation transistor T4 is electrically connected to the fourth sub scan signal line S22, so that the top gate tg4 and the bottom gate bg4 of the compensation transistor T4 are both electrically connected to the second scan signal line S2 and receive the same scan signal.

[0225] As shown in FIG. 17, FIG. 24c and FIG. 25a, the display area includes a first reference signal line ref1, the first reference signal line ref1 can be located in the metal layer MC, the first reference signal line ref1 extends along the second direction Y, and one row of pixel circuits 10 corresponds to one first reference signal line ref1. As shown in FIG. 17, FIG. 24c-FIG. 24d and FIG. 24f, the first electrode p51 of the gate reset transistor T5 is electrically connected with the first reference signal line ref1 through the connection part J12 located in the metal layer M2 and the connection part J13 located in the metal layer MC, and as shown in FIG. 18d, in one row of pixel circuits 10, the first electrodes p51 of the gate reset transistors T5 of the pixel circuits 10 adjacent to each other along the second direction Y are electrically connected in the same layer.

[0226] As shown in FIG. 17, FIG. 24a and FIG. 25a, the anode reset transistor T7 includes a channel region p7 located in the active layer poly, and a first electrode p71 and a second electrode p72 connected with the channel region p7; the second electrode p72 of the anode reset transistor T7 is electrically connected with the light emitting element 20 through the connection part J8 located in the metal layer M2 and the connection part J9 located in the metal layer M3.

[0227] As shown in FIG. 17, FIG. 24a-FIG. 24b and FIG. 25a, the display area includes a scan signal line SP, the scan signal line SP is located in the metal layer M1 and extends along the second direction Y, and in the direction perpendicular to the plane where the display panel is located, the scan signal line SP at least partially overlaps with the channel region p7 of the anode reset transistor T7. Optionally, in the direction perpendicular to the plane where the display panel is located, the part of the scan signal line SP overlapping with the channel region p7 of the anode reset transistor T7 is the gate g7 of the anode reset transistor T7, so that the scan signal line SP is electrically connected with the gate of the anode reset transistor T7.

[0228] As shown in FIG. 17, FIG. 24c, FIG. 24g and FIG. 25a-FIG. 25b, the display area includes a second reference signal line ref2, the second reference signal line ref2 includes a third sub-reference signal line ref21 and a fourth sub-reference signal line ref22, the third sub-reference signal line ref21 extends along the second direction Y and is arranged along the first direction X, the fourth sub-reference signal line ref22 extends along the first direction X and is arranged along the second direction Y, the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22 are arranged in different layers, and the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22 are electrically connected.

[0229] Specifically, as shown in FIGS. 24c, 24f-24g, the third sub-reference signal line ref21 is located in the metal layer MC, the fourth sub-reference signal line ref22 is located in the metal layer M3, and the third sub-reference signal line ref21 is electrically connected with the fourth sub-reference signal line ref22 through the connecting part J14 located in the metal layer MC, the connecting part J15 located in the metal layer M2, and the connecting part J16 located in the metal layer M3; and as shown in FIGS. 24a, 24f-24g, the fourth sub-reference signal line ref22 is electrically connected with the first electrode p71 of the anode reset transistor T7 through the connecting part J16 located in the metal layer M3 and the connecting part J15 located in the metal layer M2, and as shown in FIG. 24a, the first electrodes p71 of the anode reset transistors T7 of the pixel circuits 10 adjacent to each other in the second direction Y are electrically connected in the same layer.

[0230] In this way, by arranging the second reference signal line ref2 to include the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22 extending in different directions and being electrically connected, the second reference signal line ref2 also forms a grid structure, and FIG. 26 further shows the grid structure formed by the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22. In this way, the overall resistance of the second reference signal line ref2 is reduced, the power consumption of the second reference signal line ref2 is reduced, and the signal transmission stability of the second reference signal line ref2 is improved, which is beneficial to improving the display uniformity and other display effects of the display panel.

[0231] As shown in FIGS. 17, 24a and 25a, the bias transistor T8 includes a channel region p8 located in the active layer poly, and a first electrode p81 and a second electrode p82 connected with the channel region p8. As shown in FIGS. 17, 24a-24b and 25a, in the direction perpendicular to the plane where the display panel is located, the scan signal line SP at least partially overlaps with the channel region p8 of the bias transistor T8. Optionally, in the direction perpendicular to the plane where the display panel is located, the part of the scan signal line SP overlapping with the channel region p8 of the bias transistor T8 is the gate electrode g8 of the bias transistor T8, so that the scan signal line SP is electrically connected with the gate electrode of the bias transistor T8.

[0232] As shown in FIGS. 17, 24a and 24f, the second electrode p82 of the bias transistor T8 is electrically connected with the first electrode p31 of the driving transistor T3 through the connecting part J17 located in the metal layer M2.

[0233] As shown in FIG. 17, FIG. 24c, FIG. 24g and FIG. 25a-FIG. 25b, the display area includes a bias signal line DVH, the bias signal line DVH includes a first sub-bias signal line DVH1 and a second sub-bias signal line DVH2, the first sub-bias signal line DVH1 extends along the second direction Y and is arranged along the first direction X, the second sub-bias signal line DVH2 extends along the first direction X and is arranged along the second direction Y, the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are arranged in different layers, and the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are electrically connected.

[0234] Specifically, as shown in FIG. 24c, FIG. 24f-FIG. 24g, the first sub-bias signal line DVH1 is located in the metal layer M1, the second sub-bias signal line DVH2 is located in the metal layer M3, the first sub-bias signal line DVH1 is electrically connected with the second sub-bias signal line DVH2 through the connection part J18 located in the metal layer M1, the connection part J19 located in the metal layer M2 and the connection part J20 located in the metal layer M3; and as shown in FIG. 24a, FIG. 24f-FIG. 24g, the second sub-bias signal line DVH2 is electrically connected with the first electrode p81 of the bias transistor T8 through the connection part J20 located in the metal layer M3 and the connection part J19 located in the metal layer M2, and in a row of pixel circuits 10, the first electrodes p81 of the bias transistors T8 of the pixel circuits 10 adjacent to each other along the second direction Y are electrically connected in the same layer.

[0235] In this way, by arranging the bias signal line DVH to include the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 extending along different directions and cross-connected, a grid structure of the bias signal line DVH is also formed, and FIG. 26 further shows the grid structure formed by the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2. In this way, the overall resistance of the bias signal line DVH is reduced, the power consumption of the bias signal line DVH is reduced, the signal transmission stability of the bias signal line DVH is improved, and the display uniformity and other display effects of the display panel are improved.

[0236] As shown in FIG. 24f and FIG. 26, in the four adjacent pixel circuits 10, two of the pixel circuits 10 are provided with the fourth sub-reference signal line ref22, and the other two of the pixel circuits 10 are provided with the second sub-bias signal line DVH2, and the fourth sub-reference signal line ref22 and the second sub-bias signal line DVH2 are arranged alternately along the second direction Y, that is, the pixel circuit rows provided with the fourth sub-reference signal line ref22 are arranged alternately, and the pixel circuit rows provided with the second sub-bias signal line DVH2 are arranged alternately, that is, the pixel circuit rows provided with the fourth sub-reference signal line ref22 and the pixel circuit rows provided with the second sub-bias signal line DVH2 are arranged alternately along the second direction Y, so that the number of the fourth sub-reference signal line ref22 and the second sub-bias signal line DVH2 can be reduced, and more space can be left for the data signal line ND and the first auxiliary trace D1.

[0237] Similarly, as shown in FIG. 18c and FIG. 26, in the four adjacent pixel circuits 10, two of the pixel circuits 10 are provided with the third sub-reference signal line ref21, and the other two of the pixel circuits 10 are provided with the first sub-bias signal line DVH1, and the third sub-reference signal line ref21 and the first sub-bias signal line DVH1 are arranged alternately along the first direction X, that is, the pixel circuit rows provided with the third sub-reference signal line ref21 are arranged alternately, and the pixel circuit rows provided with the first sub-bias signal line DVH1 are arranged alternately, that is, the pixel circuit rows provided with the third sub-reference signal line ref21 and the pixel circuit rows provided with the first sub-bias signal line DVH1 are arranged alternately along the second direction Y, so that the number of the third sub-reference signal line ref21 and the first sub-bias signal line DVH1 can be reduced, and more space can be left for the second auxiliary trace D2.

[0238] As shown in FIG. 25a and FIG. 25b, in a row of pixel circuits 10, every two adjacent pixel circuits 10 form a pixel circuit repeating unit Q, and the two pixel circuits 10 in the pixel circuit repeating unit Q are mirror-symmetrical along the first direction X, and the pixel circuit repeating units Q are arranged repeatedly along the second direction Y; in two adjacent rows of pixel circuits 10, the pixel circuit repeating units Q in one row of pixel circuits 10 are first repeating units Q1, and the pixel circuit repeating units Q in the other row of pixel circuits 10 are second repeating units Q2, and the first repeating units Q1 and the second repeating units are arranged staggeredly along the second direction Y.

[0239] It can be seen that when two data signal lines ND corresponding to a column of pixel circuits 10 are distributed on the opposite sides of the column of pixel circuits along the second direction Y, and the data signal lines ND, the first auxiliary wires D1 and the second auxiliary wires D2 are arranged in different layers from each other, by reducing the number of contact holes connected to the data signal lines ND, locally narrowing the first sub-power signal lines PVDD1 along the first direction X, arranging the second reference signal lines ref2 and the bias signal lines DVH in the form of pixel circuit row arrangement and pixel circuit column arrangement, more space is left for the double data signal lines ND, the first auxiliary wires D1 and the second auxiliary wires D2. In the direction perpendicular to the plane of the display panel, the data signal lines ND and the first auxiliary wires are at least partially overlapped, so as to reduce the space occupied by the double data signal lines ND and the first auxiliary wires D1.

[0240] In the direction perpendicular to the plane of the display panel, the data signal lines ND and the first auxiliary wires are at least partially overlapped, so that a column of pixel circuits 10 can correspond to one or two first auxiliary wires D1. In particular, when a column of pixel circuits 10 can correspond to two first auxiliary wires D1, the number of first auxiliary wires D1 can be increased, and the resistance of the grid structure formed by the first non-connected line segments DV2 in the first auxiliary wires D1 and the second non-connected line segments DH2 in the second auxiliary wires D1 can be reduced, and the resistance of the signal line of the fixed potential signal connected to the first non-connected line segments DV2 in the first auxiliary wires D1 and the second non-connected line segments DH2 in the second auxiliary wires D1 can be further reduced.

[0241] It can be understood that when two data signal lines ND corresponding to a column of pixel circuits 10 are distributed on the opposite sides of the column of pixel circuits along the second direction Y, and the data signal lines ND, the first auxiliary wires D1 and the second auxiliary wires D2 are arranged in different layers from each other, as shown in FIG. 27, three first auxiliary wires D1 can be arranged corresponding to two columns of pixel circuits 10, and the first auxiliary wires D1 are located between any two adjacent data signal lines ND.

[0242] FIG. 28 shows a partial layout structure schematic diagram of another display panel provided by an embodiment of the present application. As shown in FIG. 28, along the second direction Y, two data signal lines ND corresponding to a column of pixel circuits 10 are distributed on the opposite sides of the column of pixel circuits 10. FIG. 28 shows eight pixel circuits 10, which are arranged in the form of a two-row and four-column matrix along the first direction X and the second direction Y.

[0243] For the sake of clarity, FIG. 29 shows a partial layout structure diagram of the data signal lines ND, the first auxiliary traces D1 and the second auxiliary traces D2 in the layout structure shown in FIG. 28, wherein the first auxiliary traces D1 are arranged in a layer different from the data signal lines ND, the second auxiliary traces D2 are arranged in a layer different from the data signal lines ND, and the first auxiliary traces D1 and the second auxiliary traces D2 are arranged in the same layer.

[0244] FIG. 30 shows a partial layout structure diagram of a larger range than FIG. 29, specifically, FIG. 30 shows 32 pixel circuits 10 arranged in a matrix of four rows and eight columns along the first direction X and the second direction Y. In combination of FIG. 29 and FIG. 30, since the first auxiliary traces D1 and the second auxiliary traces D2 are arranged in the same layer, the second connection line segments DH1 in the second auxiliary traces D2 and the first connection line segments DV1 in the first auxiliary traces D1 can be electrically connected in the same layer in the region where they overlap each other, without the need of punching holes; similarly, the second non-connection line segments DH2 in the second auxiliary traces D2 and the first non-connection line segments DV2 in the first auxiliary traces D1 can also be electrically connected in the same layer in the region where they overlap each other.

[0245] Referring to the dotted line path shown in FIG. 30, some of the data signal lines ND are electrically connected with the second connection line segments DH1 in the second auxiliary traces D2, and then the second connection line segments DH1 in the second auxiliary traces D2 are electrically connected with the second connection line segments DV1 in the first auxiliary traces D1, so as to arrange the part of the fan-out traces electrically connected with the data signal lines ND in the display area.

[0246] In combination of FIG. 29 and FIG. 30, since the data signal lines ND are arranged in a layer different from the second auxiliary traces D2, the data signal lines ND are electrically connected with the second connection line segments DH1 in the second auxiliary traces D2 through the contact holes K1, and the second connection line segments DH1 in the second auxiliary traces D2 extend in the first direction X for a distance to be electrically connected with the data signal lines D2 through the contact holes K1; and since the first auxiliary traces D1 and the second auxiliary traces D2 are arranged in the same layer, the second connection line segments DH1 in the second auxiliary traces D2 are electrically connected with the first connection line segments DV1 in the first auxiliary traces D1 in the same layer in the region where they overlap each other.

[0247] Referring to FIG. 30, the first auxiliary wire D1 has a gap between the first connection segment DV1 and the first non-connection segment DV2, so that the first connection segment DV1 and the first non-connection segment DV2 are insulated; similarly, the second auxiliary wire D2 has a gap between the second connection segment DH1 and the second non-connection segment DH2, so that the first connection segment DV1 and the first non-connection segment DV2 are insulated; and the first connection segment DV1 in the first auxiliary wire D1 and the second non-connection segment DH2 in the second auxiliary wire D2 have a gap, so that the first connection segment DV1 in the first auxiliary wire D1 and the second non-connection segment DH2 in the second auxiliary wire D2 are insulated; similarly, the second connection segment DH1 in the second auxiliary wire D2 and the first non-connection segment DV2 in the first auxiliary wire D1 have a gap, so that the second connection segment DH1 in the second auxiliary wire D2 and the first non-connection segment DV2 in the first auxiliary wire D1 are insulated.

[0248] In combination with FIGS. 28-30, two data signal lines ND corresponding to one column of pixel circuits 10 are distributed on the two sides of the column of pixel circuits 10 along the second direction Y, and one first auxiliary wire D1 is arranged between the two data signal lines ND corresponding to two adjacent columns of pixel circuits 10, so that the two data signal lines ND between the two adjacent columns of pixel circuits 10 belong to two columns of pixel circuits, and the first auxiliary wire D1 is arranged between the two data signal lines ND and does not overlap with other wires, thereby increasing the distance between the data signal lines ND, reducing the coupling capacitance between the data signal lines ND, and improving the stability of the signal transmitted by the data signal lines ND.

[0249] The circuit structure of the pixel circuit 10 in the layout structure shown in FIG. 28 still refers to FIG. 17. Referring to FIG. 10, the layout structure shown in FIG. 28 includes the layout structures of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG, the metal layer M2, the metal layer M3, and the metal layer M4. For the sake of clarity, FIG. 31a shows a layout structure diagram of the active layer poly in the layout structure shown in FIG. 28, FIG. 31b shows a layout structure diagram of the metal layer M1 in the layout structure shown in FIG. 28, FIG. 31c shows a layout structure diagram of the metal layer MC in the layout structure shown in FIG. 28, FIG. 31d shows a layout structure diagram of the oxide layer IGZO in the layout structure shown in FIG. 28, FIG. 31e shows a layout structure diagram of the metal layer MG in the layout structure shown in FIG. 28, FIG. 31f shows a layout structure diagram of the metal layer M2 in the layout structure shown in FIG. 28, FIG. 31g shows a layout structure diagram of the metal layer M3 in the layout structure shown in FIG. 28, and FIG. 31h shows a layout structure diagram of the metal layer M4 in the layout structure shown in FIG. 28. FIG. 32a shows a layout structure diagram of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG, and the metal layer M2 in the layout structure shown in FIG. 28, and FIG. 32b shows a layout structure diagram of the metal layer M2, the metal layer M3, and the metal layer M4 in the layout structure shown in FIG. 28.

[0250] As shown in FIG. 31g-31h and FIG. 32b, along the second direction Y, the two data signal lines ND corresponding to the pixel circuit 10 are distributed on the opposite sides of the column of pixel circuits 10. The first auxiliary wiring D1 and the second auxiliary wiring D2 are arranged in different layers from the data signal line ND, and the first auxiliary wiring D1 and the second auxiliary wiring D2 are arranged in the same layer. Specifically, the data signal line ND is located in the metal layer M4, and the first auxiliary wiring D1 and the second auxiliary wiring D2 are located in the metal layer M3. In addition, the display area further includes a first power signal line PVDD, and the first power signal line PVDD includes a first sub-power signal line PVDD1, which extends along the first direction X and is located in the metal layer M4, and is arranged in the same layer as the data signal line ND.

[0251] As shown in FIG. 30, FIG. 31g-31h, and the foregoing, the second connection segment DH1 in the second auxiliary wiring D2 located in the metal layer M3 can extend for a distance along the first direction X and then be electrically connected to the data signal line ND through the connection portion U1 located in the metal layer M3 and the connection portion U2 located in the metal layer M4.

[0252] As shown in FIG. 17, FIG. 31a and FIG. 32a, the data writing transistor T2 includes a channel region p2 in the active layer poly, and a first electrode p21 and a second electrode p22 connected to the channel region p2; the driving transistor T3 includes a channel region p3 in the active layer poly, and a first electrode p31 and a second electrode p32 connected to the channel region p3; the second electrode p22 of the data writing transistor T2 is electrically connected to the first electrode p31 of the driving transistor T3 in the same layer.

[0253] As shown in FIG. 17, FIG. 31a, FIG. 31f-FIG. 31h, the first electrode p21 of the data writing transistor T2 is electrically connected to the data signal line ND through the connection portion U3 in the metal layer M2, the connection portion U1 in the metal layer M3 and the connection portion U2 in the metal layer M4. The connection portion U1 in the metal layer M3 and the connection portion U2 in the metal layer M4 are also used to connect the second connection line segment DH1 in the second auxiliary wiring D2 and the data signal line ND, that is, the connection position of the second connection line segment DH1 in the second auxiliary wiring D2 and the data signal line ND coincides with the connection position of the first electrode p21 of the data writing transistor T2 and the data signal line ND, so that the number of contact holes between the metal layer M3 and the metal layer M4 can be reduced, so as to leave more space for the data signal line ND, the first auxiliary wiring D1 and the second auxiliary wiring D2.

[0254] As shown in FIG. 17, FIG. 31a-FIG. 31b and FIG. 32a, the scan signal line SP* can be located in the metal layer M1 and extend along the second direction Y, and in the direction perpendicular to the plane where the display panel is located, the scan signal line SP* at least partially overlaps with the channel region p2 of the data writing transistor T2; optionally, in the direction perpendicular to the plane where the display panel is located, the part of the active layer poly overlapping with the scan signal line SP* is the channel region p2 of the data writing transistor T2, and the part of the scan signal line SP* overlapping with the active layer poly is the gate g2 of the data writing transistor T2, so that the gate of the data writing transistor T2 is electrically connected to the scan signal line SP*.

[0255] As shown in FIG. 17, FIG. 31a and FIG. 32a, the first light emitting control transistor T1 includes a channel region p1 in the active layer poly, and a first electrode p11 and a second electrode p12 connected to the channel region p1; the second electrode p12 of the first light emitting control transistor T1 is electrically connected to the first electrode p31 of the driving transistor T3 in the same layer. As shown in FIG. 17, FIG. 31a and FIG. 31f-FIG. 31h, the first electrode p11 of the first light emitting control transistor T1 is electrically connected to the first sub power signal line PVDD1 through the connection portion U4 in the metal layer M2, the connection portion U5 in the metal layer M3 and the connection portion U6 in the metal layer M4.

[0256] As shown in FIG. 17, FIG. 31a-31b and FIG. 32a, the light emitting control signal line EMIT can be located in the metal layer M1 and extend along the second direction Y, and in the direction perpendicular to the plane where the display panel is located, the light emitting control signal line EMIT at least partially overlaps with the channel region p1 of the first light emitting control transistor T1; optionally, in the direction perpendicular to the plane where the display panel is located, the portion of the light emitting control signal line EMIT overlapping with the channel region p1 of the first light emitting control transistor T1 is the gate g1 of the first light emitting control transistor T1, so that the gate g1 of the first light emitting control transistor T1 is electrically connected with the light emitting control signal line EMIT.

[0257] As shown in FIG. 17, FIG. 31a-31b and FIG. 32a, the first plate Cst1 of the storage capacitor Cst can be located in the metal layer M1, and the first plate Cst1 of the storage capacitor Cst also serves as the gate g3 of the driving transistor T3, and in the direction perpendicular to the plane where the display panel is located, the first plate Cst1 of the storage capacitor Cst overlaps with the channel region p3 of the driving transistor T3. As shown in FIG. 17, FIG. 31c and FIG. 31f-31h, the second plate Cst2 of the storage capacitor Cst can be located in the metal layer MC, and the second plate Cst2 of the storage capacitor Cst is electrically connected with the first sub power supply signal line PVDD1 through the connection part U4 located in the metal layer M2, the connection part U5 located in the metal layer M3 and the connection part U6 located in the metal layer M4.

[0258] As shown in FIG. 29, FIG. 31g-31h and FIG. 25b, two data signal lines ND corresponding to one column of pixel circuits 10 are distributed on the two sides of the column of pixel circuits 10 along the second direction Y, and one first auxiliary wire D1 is arranged between the two data signal lines ND between the two adjacent columns of pixel circuits 10.

[0259] And the first sub power supply signal line PVDD1 is located between the two data signal lines ND corresponding to one column of pixel circuits 10.

[0260] It can be understood that the width of the first sub power supply signal line PVDD1 along the second direction Y can be appropriately narrowed to leave more space for the data signal line ND and the first auxiliary wire D1; and considering that the resistance of the first sub power supply signal line PVDD1 will increase after narrowing the width of the first sub power supply signal line PVDD1 along the second direction Y, the width of the first sub power supply signal line PVDD1 along the second direction Y can be appropriately widened in the area with space to reduce the resistance of the first sub power supply signal line PVDD1.

[0261] As shown in FIG. 29, FIG. 31h and FIG. 19b, the first sub power supply signal line PVDD1 includes a first sub segment Z1, a second sub segment Z2 and a third sub segment Z3, the first sub segment Z1 is connected with the third sub segment Z3 through the second sub segment Z2, the third sub segment Z3 is connected with the first sub segment Z1 through the second sub segment Z2, the width of the first sub segment Z1 along the second direction Y is greater than 1.5 times of the width of the second sub segment Z2 along the second direction Y, and the width of the third sub segment Z3 is greater than 1.5 times of the width of the second sub segment Z2 along the second direction Y. In this way, the first sub power supply signal line PVDD1 is locally widened and locally narrowed along the first direction X, so as to leave more space for the data signal line ND and the first auxiliary trace D1 while reducing the resistance of the first sub power supply signal line PVDD1.

[0262] As shown in FIG. 31c and FIG. 32a, the second plate Cst2 of the storage capacitor Cst of a row of pixel circuits 10 is electrically connected in the same layer, and as known from the foregoing, the second plate Cst2 of the storage capacitor Cst is also electrically connected with the first sub power supply signal line PVDD1. Thus, the second plate Cst2 of the storage capacitor Cst of a row of pixel circuits 10 electrically connected in the same layer constitutes the second sub power supply signal line PVDD2, the second sub power supply signal line PVDD2 extends along the second direction Y, the second sub power supply signal line PVDD2 is arranged in a different layer from the first sub power supply signal line PVDD1, and the second sub power supply signal line PVDD2 is electrically connected with the first sub power supply signal line PVDD1. In this way, the first sub power supply signal line PVDD1 and the second sub power supply signal line PVDD2 constitute a grid structure, which can reduce the overall resistance of the first power supply signal line PVDD, reduce the power consumption of the first power supply signal line PVDD, and improve the signal transmission stability of the first power supply signal line PVDD, thereby improving the display uniformity and other display effects of the display panel.

[0263] As shown in FIG. 17, FIG. 31a and FIG. 32a, the second light emitting control transistor T6 includes a channel region p6 in the active layer poly, and a first pole p61 and a second pole p62 connected with the channel region p6; the first pole p61 of the second light emitting control transistor T6 is electrically connected in the same layer with the second pole p32 of the driving transistor T3. As shown in FIG. 17, FIG. 31a, FIG. 31f-FIG. 31h, the second pole p62 of the second light emitting control transistor T6 is electrically connected with the light emitting element 20 through the connection portion U7 in the metal layer M2, the connection portion U8 in the metal layer M3 and the connection portion U9 in the metal layer M4.

[0264] In the direction perpendicular to the plane where the display panel is located, the light-emitting control signal line EMIT at least partially overlaps with the channel region p6 of the second light-emitting control transistor T6, as shown in FIGS. 17, 31a and 31b. Optionally, in the direction perpendicular to the plane where the display panel is located, the portion of the light-emitting control signal line EMIT that overlaps with the channel region p6 of the second light-emitting control transistor T6 is the gate g6 of the second light-emitting control transistor T6, so that the gate g6 of the second light-emitting control transistor T6 is electrically connected with the light-emitting control signal line EMIT.

[0265] The compensation transistor T4 and the gate reset transistor T5 can be oxide thin film transistors, i.e., IGZO thin film transistors, as shown in FIGS. 17, 31d and 32a. The compensation transistor T4 includes a channel region p4 in an oxide layer IGZO, and a first electrode p41 and a second electrode p42 connected with the channel region p4. The gate reset transistor T5 includes a channel region p5 in the oxide layer IGZO, and a first electrode p51 and a second electrode p52 connected with the channel region p5.

[0266] The first electrode p41 of the compensation transistor T4 is electrically connected with the second electrode p32 of the driving transistor T3 through a connection portion U10 in the metal layer M2, as shown in FIGS. 17, 31a-31d and 31f. The second electrode p42 of the compensation transistor T4 is directly electrically connected with the second electrode p52 of the gate initialization transistor T5 in the oxide layer IGZO, and is electrically connected with the gate g3 of the driving transistor T3 through a via in the second electrode plate Cst2 of the storage capacitor Cst in the metal layer MC and a connection portion U11 in the metal layer M2.

[0267] It should be noted that the connection portion U11 in the metal layer M2 is electrically connected with the second electrode p42 of the compensation transistor T4, the second electrode p52 of the gate initialization transistor T5 and the gate g3 of the driving transistor T3 at the same time, i.e., the connection portion U11 in the metal layer M2 corresponds to the first node N1, as shown in FIGS. 17, 31b, 31d and 31f-31h. In the direction perpendicular to the plane where the display panel is located, the connection portion U5 in the metal layer M3, the first sub segment Z1 and the third sub segment Z3 of the first sub power supply signal line PVDD1 cover the connection portion U11 in the metal layer M2, i.e., at least partially cover the first node N1, so as to maintain the stability of the potential of the first node N1, i.e., the stability of the potential of the gate g3 of the driving transistor T3, which is beneficial to improve the display effect of the display panel.

[0268] As shown in FIG. 17, FIG. 31c-31e and FIG. 32a, the display area includes scan signal lines S1 and S2; the scan signal line S1 includes first and second sub scan signal lines S11 and S12 which transmit the same scan signal, the first sub scan signal line S11 is located in the metal layer MC and extends along the second direction Y, and the second sub scan signal line S12 is located in the metal layer MG and extends along the second direction Y; in the direction perpendicular to the plane where the display panel is located, the first sub scan signal line S11, the second sub scan signal line S12 and the channel region p5 of the gate reset transistor T5 are overlapped. Optionally, in the direction perpendicular to the plane where the display panel is located, the part of the oxide layer IGZO which is overlapped by the first and second sub scan signal lines S11 and S12 is the channel region p5 of the gate reset transistor T5, the part of the first sub scan signal line S11 which is directly opposite the channel region p5 of the gate reset transistor T5 is the bottom gate bg5 of the gate reset transistor T5, so that the bottom gate bg5 of the gate reset transistor T5 is electrically connected with the first sub scan signal line S11; the part of the second sub scan signal line S12 which is directly opposite the channel region p5 of the gate reset transistor T5 is the top gate tg5 of the gate reset transistor T5, so that the top gate tg5 of the gate reset transistor T5 is electrically connected with the second sub scan signal line S12, thereby making the top gate tg5 and the bottom gate bg5 of the gate reset transistor T5 both electrically connected with the first scan signal line S1 and receive the same scan signal.

[0269] Similarly, as shown in FIG. 17, FIG. 31c-31e and FIG. 32a, the scan signal line S2 includes third and fourth sub scan signal lines S21 and S22 which transmit the same scan signal, the third sub scan signal line S21 is located in the metal layer MC and extends along the first direction X, and the fourth sub scan signal line S22 is located in the metal layer MG and extends along the first direction X; in the direction perpendicular to the plane where the display panel is located, the third sub scan signal line S21, the fourth sub scan signal line S22 and the channel region p4 of the compensation transistor T4 are overlapped. Optionally, in the direction perpendicular to the plane where the display panel is located, the part of the oxide layer IGZO which is overlapped by the third and fourth sub scan signal lines S21 and S22 is the channel region p4 of the compensation transistor T4, the part of the third sub scan signal line S21 which is directly opposite the channel region p4 of the compensation transistor T4 is the bottom gate bg4 of the compensation transistor T4, so that the bottom gate bg4 of the compensation transistor T4 is electrically connected with the third sub scan signal line S21; the part of the fourth sub scan signal line S22 which is directly opposite the channel region p4 of the compensation transistor T4 is the top gate tg4 of the compensation transistor T4, so that the top gate tg4 of the compensation transistor T4 is electrically connected with the fourth sub scan signal line S22, thereby making the top gate tg4 and the bottom gate bg4 of the compensation transistor T4 both electrically connected with the second scan signal line S2 and receive the same scan signal.

[0270] As shown in FIG. 17, FIG. 31c, FIG. 31f and FIG. 19a, the display area includes the first reference signal line ref1, the first reference signal line ref1 includes a first sub-reference signal line ref11 and a second sub-reference signal line ref12, the first sub-reference signal line ref11 extends along the second direction Y and is arranged along the first direction X, the second sub-reference signal line ref12 extends along the first direction X and is arranged along the second direction Y, the first sub-reference signal line ref11 and the second sub-reference signal line ref12 are arranged in different layers, and the first sub-reference signal line ref11 and the second sub-reference signal line ref12 are electrically connected.

[0271] As shown in FIG. 31c and FIG. 31f, the first sub-reference signal line ref11 is located in the metal layer MC, the second sub-reference signal line ref12 is located in the metal layer M2, and the first sub-reference signal line ref11 is electrically connected with the second sub-reference signal line ref12 through the connecting part U12 located in the metal layer MC and the connecting part U13 located in the metal layer M2. As shown in FIG. 17, FIG. 31d and FIG. 31f, the second sub-reference signal line ref12 is electrically connected with the first electrode p51 of the gate reset transistor T5 through the connecting part U13 located in the metal layer M2; and as shown in FIG. 31d, in a row of pixel circuits 10, the first electrodes p51 of the gate reset transistors T5 of the pixel circuits 10 adjacent to each other along the second direction Y are electrically connected in the same layer.

[0272] In this way, by arranging the first reference signal line ref1 to include the first sub-reference signal line ref11 and the second sub-reference signal line ref12 extending along different directions and being electrically connected in cross, the first reference signal line ref1 forms a grid structure, as shown in FIG. 33, and thus the overall resistance of the first reference signal line ref1 can be reduced, the power consumption of the first reference signal line ref1 is further reduced, the signal transmission stability of the first reference signal line ref1 is improved, and the display uniformity and other display effects of the display panel are improved.

[0273] As shown in FIG. 17, FIG. 31a, FIG. 31f-FIG. 31h and FIG. 32a, the anode reset transistor T7 includes a channel region p7 located in the active layer poly, and a first electrode p71 and a second electrode p72 connected with the channel region p7; the second electrode p72 of the anode reset transistor T7 is electrically connected with the light emitting element 20 through the connecting part U7 located in the metal layer M2, the connecting part U8 located in the metal layer M3 and the connecting part U9 located in the metal layer M4.

[0274] As shown in FIG. 17, FIG. 31a-FIG. 31b and FIG. 32a, the display area includes a scan signal line SP, the scan signal line SP is located in the metal layer M1 and extends along the second direction Y, and the scan signal line SP at least partially overlaps with the channel region p7 of the anode reset transistor T7 in the direction perpendicular to the plane where the display panel is located. Optionally, the portion of the scan signal line SP overlapping with the channel region p7 of the anode reset transistor T7 in the direction perpendicular to the plane where the display panel is located is the gate g7 of the anode reset transistor T7, so that the scan signal line SP is electrically connected with the gate of the anode reset transistor T7.

[0275] As shown in FIG. 17, FIG. 31c, FIG. 31f and FIG. 32a, the display area includes a second reference signal line ref2, the second reference signal line ref2 includes a third sub-reference signal line ref21 and a fourth sub-reference signal line ref22, the third sub-reference signal line ref21 extends along the second direction Y and is arranged along the first direction X, the fourth sub-reference signal line ref22 extends along the first direction X and is arranged along the second direction Y, the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22 are arranged in different layers and are electrically connected.

[0276] As shown in FIG. 17, FIG. 31c and FIG. 31f, the third sub-reference signal line ref21 is located in the metal layer MC, the fourth sub-reference signal line ref22 is located in the metal layer M2, and the third sub-reference signal line ref21 is electrically connected with the fourth sub-reference signal line ref22 through the connection part U14 located in the metal layer MC and the connection part U15 located in the metal layer M2. As shown in FIG. 17, FIG. 31a and FIG. 31f, the fourth sub-reference signal line ref22 is electrically connected with the first pole p71 of the anode reset transistor T7 through the connection part U15 located in the metal layer M2, and in a row of pixel circuits 10, the first poles p71 of the anode reset transistors T7 of the pixel circuits 10 adjacent to each other along the second direction Y are electrically connected in the same layer.

[0277] In this way, by arranging the second reference signal line ref2 to include the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22 extending in different directions and cross-connected, thereby forming a grid structure of the second reference signal line ref2, and as shown in FIG. 33, the grid structure formed by the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22, so as to reduce the overall resistance of the second reference signal line ref2, thereby reducing the power consumption of the second reference signal line ref2 and improving the signal transmission stability of the second reference signal line ref2, which is conducive to improving the display uniformity and other display effects of the display panel.

[0278] As shown in FIG. 17, FIG. 31a and FIG. 32a, the bias transistor T8 includes a channel region p8 in the active layer poly, and a first electrode p81 and a second electrode p82 connected to the channel region p8. As shown in FIG. 17, FIG. 31a-31b and FIG. 32a, in a direction perpendicular to the plane on which the display panel lies, the scan signal line SP at least partially overlaps the channel region p8 of the bias transistor T8. Optionally, in the direction perpendicular to the plane on which the display panel lies, the scan signal line SP overlaps the gate g8 of the bias transistor T8, so that the scan signal line SP is electrically connected to the gate g8 of the bias transistor T8.

[0279] As shown in FIG. 17, FIG. 31a and FIG. 31f, the second electrode p82 of the bias transistor T8 is electrically connected to the first electrode p31 of the drive transistor T3 through the connection U16 in the metal layer M2.

[0280] As shown in FIG. 17, FIG. 31e, FIG. 31f and FIG. 32a, the display area includes a bias signal line DVH, the bias signal line DVH includes a first sub-bias signal line DVH1 and a second sub-bias signal line DVH2, the first sub-bias signal line DVH1 extends along the second direction Y and is arranged along the first direction X, the second sub-bias signal line DVH2 extends along the first direction X and is arranged along the second direction Y, the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are arranged in different layers, and the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are electrically connected.

[0281] Specifically, as shown in FIG. 31e and FIG. 31f, the first sub-bias signal line DVH1 is located in the metal layer MG, the second sub-bias signal line DVH2 is located in the metal layer M2, the first sub-bias signal line DVH1 is electrically connected to the second sub-bias signal line DVH2 through the connection U17 in the metal layer MG and the connection U18 in the metal layer M2; and as shown in FIG. 31a, FIG. 31e and FIG. 31f, the second sub-bias signal line DVH2 is electrically connected to the first electrode p81 of the bias transistor T8 through the connection U18 in the metal layer M2, and in a row of pixel circuits 10, the first electrodes p81 of the bias transistors T8 of the pixel circuits 10 adjacent to each other along the second direction Y are electrically connected in the same layer.

[0282] Thus, by setting the bias signal line DVH including the first sub bias signal line DVH1 and the second sub bias signal line DVH2 extending in different directions and cross-connected, a grid structure of the bias signal line DVH is also formed, and FIG. 33 further shows the grid structure formed by the first sub bias signal line DVH1 and the second sub bias signal line DVH2, so as to reduce the overall resistance of the bias signal line DVH, thereby reducing the power consumption of the bias signal line DVH and improving the signal transmission stability of the bias signal line DVH, which is conducive to improving the display uniformity and other display effects of the display panel.

[0283] As shown in FIGS. 31c, 31e-31f and 33, the fourth sub reference signal line ref22 of the second reference signal line ref2 includes a plurality of fourth sub reference signal line segments ref220 extending along the first direction Y, and the fourth sub reference signal line segments ref220 are electrically connected with the third sub reference signal line ref21; the second sub bias signal line DVH2 of the bias signal line DVH includes a plurality of second sub bias signal line segments DVH20 extending along the second direction Y, and the second sub bias signal line segments DVH20 are electrically connected with the first sub bias signal line DVH1.

[0284] As shown in FIGS. 31c, 31e-31f and 33, the fourth sub reference signal line segments ref220 and the second sub bias signal line segments DVH20 are alternately arranged along the first direction X and alternately arranged along the second direction Y; in the adjacent four columns of pixel circuits 10, two columns of pixel circuits 10 are correspondingly provided with the second sub reference signal line ref12, and the other two columns of pixel circuits 10 are correspondingly provided with the fourth sub reference signal line segments ref220 and the second sub bias signal line segments DVH20, that is, the pixel circuit columns correspondingly provided with the second sub reference signal line ref12 are arranged alternately with the pixel circuit columns correspondingly provided with the fourth sub reference signal line segments ref220 and the second sub bias signal line segments DVH20 along the second direction Y; thus, the number of the second sub reference signal line ref12, the fourth sub reference signal line segments ref220 and the second sub bias signal line segments DVH20 can be reduced, and more space can be left for the data signal line ND and the first auxiliary trace D1.

[0285] As shown in FIG. 31c, FIG. 31e and FIG. 33, one row of pixel circuits 10 is provided with one first sub-reference signal line ref11 to form a grid structure with the second sub-reference signal line ref12; one row of pixel circuits 10 is provided with one third sub-reference signal line ref21 to form a grid structure with the fourth sub-reference signal line sub-section ref220; one row of pixel circuits 10 is provided with one first sub-bias signal line DVH1 to form a grid structure with the second sub-bias signal line sub-section DVH20.

[0286] As shown in FIG. 32a and FIG. 32b, in one row of pixel circuits 10, two adjacent pixel circuits 10 form a pixel circuit repeating unit Q, the two pixel circuits 10 in the pixel circuit repeating unit Q are mirror-symmetrical along the first direction X, and the pixel circuit repeating units Q are arranged repeatedly along the second direction Y; in two adjacent rows of pixel circuits 10, the pixel circuit repeating units Q in one row of pixel circuits 10 are first repeating units Q1, the pixel circuit repeating units Q in the other row of pixel circuits 10 are second repeating units Q2, and the first repeating units Q1 and the second repeating units are staggered along the second direction Y.

[0287] As can be seen, when the two data signal lines ND corresponding to one column of pixel circuits 10 are distributed on the opposite sides of the column of pixel circuits along the second direction Y, and the data signal lines ND are arranged in different layers from the first auxiliary traces D1, and the first auxiliary traces D1 and the second auxiliary traces D2 are arranged in the same layer, by reducing the number of contact holes connected to the data signal lines ND, locally narrowing the first sub-power signal line PVDD1 along the first direction X, alternately arranging the second reference signal line sub-section ref20 in the second reference signal line ref and the second sub-bias signal line DVH2 in the bias signal line DVH along the first direction X and along the second direction Y, and arranging the second sub-reference signal line ref12 in two columns of pixel circuits 10 and the fourth sub-reference signal line sub-section ref220 and the second sub-bias signal line sub-section DVH20 in the other two columns of pixel circuits 10 in the adjacent four columns of pixel circuits 10, and arranging the pixel circuit columns corresponding to the second sub-reference signal line ref12 and the pixel circuit columns corresponding to the fourth sub-reference signal line sub-section ref220 and the second sub-bias signal line sub-section DVH20 alternately, more space is left for the double data signal lines ND, the first auxiliary traces D1 and the second auxiliary traces D2.

[0288] It can be understood that when two data signal lines ND corresponding to the electrically connected one column of pixel circuits 10 are distributed on the opposite sides of the column of pixel circuits along the second direction Y, and the data signal lines ND are arranged in different layers from the first auxiliary wires D1, and the first auxiliary wires D1 and the second auxiliary wires D2 are arranged in the same layer, one first auxiliary wire D1 can be arranged corresponding to two columns of pixel circuits 10, and the first auxiliary wire D1 is located between the two data signal lines ND between the adjacent two columns of pixel circuits 10. Thus, the two data signal lines ND between the adjacent two columns of pixel circuits 10 belong to two columns of pixel circuits, and the first auxiliary wire D1 is arranged between the two data signal lines ND between the adjacent two columns of pixel circuits 10, and the first auxiliary wire D1 does not overlap with other wires, so that the distance between the data signal lines ND can be increased, the coupling capacitance between the data signal lines ND can be reduced, and the stability of the signal transmitted by the data signal lines ND can be improved.

[0289] It can also be understood that since the data signal lines ND are arranged in different layers from the first auxiliary wires D1, the data signal lines ND and the first auxiliary wires can also be arranged at least partially overlapped in the direction perpendicular to the plane where the display panel is located, so as to reduce the space occupied by the double data signal lines ND and the first auxiliary wires D1. When the data signal lines ND and the first auxiliary wires are arranged at least partially overlapped in the direction perpendicular to the plane where the display panel is located, one column of pixel circuits 10 can correspond to one or two first auxiliary wires D1. In particular, when one column of pixel circuits 10 corresponds to two first auxiliary wires D1, the number of first auxiliary wires D1 can be increased, the resistance of the grid structure formed by the first non-connected line segments DV2 in the first auxiliary wires D1 and the second non-connected line segments DH2 in the second auxiliary wires D1 can be reduced, and the resistance of the signal line of the fixed potential signal connected by the first non-connected line segments DV2 in the first auxiliary wires D1 and the second non-connected line segments DH2 in the second auxiliary wires D1 can be further reduced.

[0290] It can be understood that when two data signal lines ND corresponding to the electrically connected one column of pixel circuits 10 are distributed on the opposite sides of the column of pixel circuits along the second direction Y, and the data signal lines ND are arranged in different layers from the first auxiliary wires D1, and the first auxiliary wires D1 and the second auxiliary wires D2 are arranged in the same layer, as shown in FIG. 27, three first auxiliary wires D1 can be arranged corresponding to two columns of pixel circuits 10, and the first auxiliary wires D1 are located between any two adjacent data signal lines ND.

[0291] FIG. 34 shows a partial layout structure schematic diagram of yet another display panel provided by the embodiments of the present application. As shown in FIG. 34, along the second direction Y, two data signal lines ND corresponding in electrically connecting one column of pixel circuits 10 are located at the same side of the column of pixel circuits 10. FIG. 34 shows eight pixel circuits 10, which form a matrix of two rows and four columns along the first direction X and the second direction Y.

[0292] For the sake of clarity, FIG. 35 shows a partial layout structure schematic diagram of the data signal lines ND, the first auxiliary traces D1 and the second auxiliary traces D2 in the layout structure shown in FIG. 34. In combination with FIG. 34 and FIG. 35, the display area includes a plurality of column repeat units R arranged along the second direction Y, the column repeat unit R includes two columns of pixel circuits 10 arranged adjacently along the second direction Y, and the two columns of pixel circuits 10 in the column repeat unit R are mirror-symmetrical along the first direction X.

[0293] It should be noted that, in the present application, the two columns of pixel circuits 10 in the column repeat unit R are mirror-symmetrical along the first direction X, which means that the two columns of pixel circuits 10 in the column repeat unit R are at least partially mirror-symmetrical along the first direction X, which can be partially mirror-symmetrical or completely mirror-symmetrical. Other similar cases in the present application will not be described here.

[0294] In combination with FIG. 34 and FIG. 35, the four data signal lines ND corresponding in electrically connecting the two columns of pixel circuits 10 in the column repeat unit R are located between the two columns of pixel circuits 10, and the two data signal lines ND corresponding in electrically connecting one column of pixel circuits 10 are mirror-symmetrical along the first direction X with the two data signal lines ND corresponding in electrically connecting the other column of pixel circuits 10, where the mirror-symmetry also means at least partial mirror-symmetry, which can be partial mirror-symmetry or complete mirror-symmetry.

[0295] As shown in FIGS. 34 and 35, the first auxiliary wire D1 and the data signal line ND are arranged in different layers, and the second auxiliary wire D2 and the data signal line ND are arranged in different layers. Since the first auxiliary wire D1 and the data signal line ND are arranged in different layers, optionally, one column of pixel circuits 10 can correspond to one first auxiliary wire D1, and on this basis, one optional mode is that, as shown in FIGS. 34 and 35, the first auxiliary wire D1 can be located between two data signal lines ND corresponding to the electrical connection of one column of pixel circuits 10, so that the first auxiliary wire D1 does not overlap with other wires, thereby increasing the distance between the data signal lines ND, reducing the coupling capacitance between the data signal lines ND, and improving the stability of the signal transmission of the data signal lines ND; another optional mode is that the first auxiliary wire D1 can also be located on one side of two data signal lines ND corresponding to the electrical connection of one column of pixel circuits 10 along the second direction Y, when the first auxiliary wire D1 is located between the data signal lines ND corresponding to the electrical connection of two columns of pixel circuits 10 in the column repetition unit R, the distance between the data signal lines ND can also be increased, the coupling capacitance between the data signal lines ND can be reduced, and the stability of the signal transmission of the data signal lines ND can be improved; yet another optional mode is that in the direction perpendicular to the plane where the display panel is located, the first auxiliary wire D1 corresponding to one column of pixel circuits 10 can also at least partially overlap with the data signal lines ND corresponding to the electrical connection of the pixel circuits 10 in the same column, so that the space occupied by the data signal lines ND and the first auxiliary wire D1 can be reduced; still another optional mode is that three first auxiliary wires D1 can be arranged corresponding to two columns of pixel circuits 10 in the column repetition unit R, the three first auxiliary wires D1 are located between the two columns of pixel circuits 10 in the column repetition unit R, and the first auxiliary wire D1 is located between two adjacent data signal lines ND, as shown in FIG. 27, so that the distance between the data signal lines ND can also be increased, the coupling capacitance between the data signal lines ND can be reduced, and the stability of the signal transmission of the data signal lines ND can be improved. FIGS. 34 and 35 take the first auxiliary wire D1 located between two data signal lines ND corresponding to the electrical connection of one column of pixel circuits 10 as an example for illustration.

[0296] As shown in FIGS. 34 and 35, the first auxiliary wire D1 and the second auxiliary wire D2 are arranged in the same layer. FIG. 36 shows a partial layout structure diagram in a larger range than FIG. 35. Specifically, FIG. 36 shows 40 pixel circuits 10 arranged in a matrix of five rows and eight columns along the first direction X and the second direction Y. As shown in FIGS. 34 and 36, since the first auxiliary wire D1 and the second auxiliary wire D2 are arranged in the same layer, the second connection line segment DH1 in the second auxiliary wire D2 and the first connection line segment DV1 in the first auxiliary wire D1 can be electrically connected in the same layer in the region where they overlap each other, without the need for punching. Similarly, the second non-connection line segment DH2 in the second auxiliary wire D2 and the first non-connection line segment DV2 in the first auxiliary wire D1 can also be electrically connected in the same layer in the region where they overlap each other.

[0297] As shown by the dotted line path in FIG. 36, part of the data signal lines ND are electrically connected to the first connection line segment DV1 in the first auxiliary wire D1 through a contact hole, and the first connection line segment DV1 in the first auxiliary wire D1 is electrically connected to the second connection line segment DH1 in the second auxiliary wire D2 in the same layer. Part of the data signal lines ND can pass through the first connection line segment DV1 in the first auxiliary wire D1, the second connection line segment DH1 in the second auxiliary wire D2, and the first connection line segment DV1 in the first auxiliary wire D1 in sequence, and then be electrically connected to the fan-out wire, so that part of the fan-out wires electrically connected to the data signal lines ND are arranged in the display area.

[0298] The circuit structure of the pixel circuit 10 in the layout structure shown in FIG. 34 still refers to FIG. 17. Referring to FIG. 10, the layout structure shown in FIG. 34 includes the layout structures of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG, the metal layer M2, the metal layer M3 and the metal layer M4. For the sake of clarity, FIG. 37a shows a layout structure diagram of the active layer poly in the layout structure shown in FIG. 34, FIG. 37b shows a layout structure diagram of the metal layer M1 in the layout structure shown in FIG. 34, FIG. 37c shows a layout structure diagram of the metal layer MC in the layout structure shown in FIG. 34, FIG. 37d shows a layout structure diagram of the oxide layer IGZO in the layout structure shown in FIG. 34, FIG. 37e shows a layout structure diagram of the metal layer MG in the layout structure shown in FIG. 34, FIG. 37f shows a layout structure diagram of the metal layer M2 in the layout structure shown in FIG. 34, FIG. 37g shows a layout structure diagram of the metal layer M3 in the layout structure shown in FIG. 34, and FIG. 37h shows a layout structure diagram of the metal layer M4 in the layout structure shown in FIG. 34. FIG. 38a shows a layout structure diagram of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, the metal layer MG and the metal layer M2 in the layout structure shown in FIG. 34, and FIG. 38b shows a layout structure diagram of the metal layer M3 and the metal layer M4 in the layout structure shown in FIG. 34.

[0299] As shown in FIGS. 37g-37h and 38b, along the second direction Y, the two data signal lines ND corresponding to the pixel circuit 10 in the same column are located on the same side of the pixel circuit 10. The first auxiliary wiring D1 and the second auxiliary wiring D2 are located in different layers from the data signal line ND, and the first auxiliary wiring D1 and the second auxiliary wiring D2 are located in the same layer. Specifically, the data signal line ND is located in the metal layer M3, and the first auxiliary wiring D1 and the second auxiliary wiring D2 are located in the metal layer M4. In addition, the display area further includes a first power signal line PVDD, and the first power signal line PVDD includes a first sub-power signal line PVDD1, the first sub-power signal line PVDD1 extends along the first direction X, and the first sub-power signal line PVDD1 is also located in the metal layer M3 and is located in the same layer as the data signal line ND.

[0300] As shown in FIGS. 35, 37g-37h, the first connection line segment DV1 in the first auxiliary wiring D1 located in the metal layer M4 can be electrically connected to the data signal line ND through the connection part E1 located in the metal layer M4 and the connection part E2 located in the metal layer M3.

[0301] As shown in FIGS. 17, 37a and 38a, the data writing transistor T2 includes a channel region p2 in the active layer poly, and a first electrode p21 and a second electrode p22 connected to the channel region p2; the driving transistor T3 includes a channel region p3 in the active layer poly, and a first electrode p31 and a second electrode p32 connected to the channel region p3; the second electrode p22 of the data writing transistor T2 is electrically connected to the first electrode p31 of the driving transistor T3 in the same layer.

[0302] As shown in FIGS. 17, 37a, 37f-37h, the first electrode p21 of the data writing transistor T2 is electrically connected to the data signal line ND through the connection part R3 in the metal layer M2, the connection part R2 in the metal layer M3 and the connection part R1 in the metal layer M4. The connection part R2 in the metal layer M3 and the connection part R1 in the metal layer M4 are also used to connect the first connection line segment DV1 in the first auxiliary wiring D1 and the data signal line ND, i.e., the connection position of the first connection line segment DV1 in the first auxiliary wiring D1 and the data signal line ND coincides with the connection position of the first electrode p21 of the data writing transistor T2 and the data signal line ND, so that the number of contact holes between the metal layer M3 and the metal layer M4 can be reduced, thereby leaving more space for the data signal line ND, the first auxiliary wiring D1 and the second auxiliary wiring D2.

[0303] As shown in FIGS. 17, 37a-37b and 38a, the scan signal line SP* can be located in the metal layer M1 and extend along the second direction Y, and in the direction perpendicular to the plane where the display panel is located, the scan signal line SP* at least partially overlaps the channel region p2 of the data writing transistor T2; optionally, in the direction perpendicular to the plane where the display panel is located, the part of the active layer poly overlapping the scan signal line SP* is the channel region p2 of the data writing transistor T2, and the part of the scan signal line SP* overlapping the active layer poly is the gate g2 of the data writing transistor T2, so that the gate of the data writing transistor T2 is electrically connected to the scan signal line SP*.

[0304] As shown in FIGS. 17, 37a and 38a, the first light emitting control transistor T1 includes a channel region p1 in the active layer poly, and a first electrode p11 and a second electrode p12 connected to the channel region p1; the second electrode p12 of the first light emitting control transistor T1 is electrically connected to the first electrode p31 of the driving transistor T3 in the same layer.

[0305] As shown in FIG. 17, FIG. 37a-FIG. 37b and FIG. 38a, the light emitting control signal line EMIT can be located in the metal layer M1 and extend along the second direction Y, and in the direction perpendicular to the plane where the display panel is located, the light emitting control signal line EMIT at least partially overlaps with the channel region p1 of the first light emitting control transistor T1; optionally, in the direction perpendicular to the plane where the display panel is located, the part of the light emitting control signal line EMIT overlapping with the channel region p1 of the first light emitting control transistor T1 is the gate g1 of the first light emitting control transistor T1, so that the gate g1 of the first light emitting control transistor T1 is electrically connected with the light emitting control signal line EMIT.

[0306] As shown in FIG. 17, FIG. 37a-FIG. 37b and FIG. 38a, the first plate Cst1 of the storage capacitor Cst can be located in the metal layer M1, and the first plate Cst1 of the storage capacitor Cst also serves as the gate g3 of the driving transistor T3, and in the direction perpendicular to the plane where the display panel is located, the first plate Cst1 of the storage capacitor Cst overlaps with the channel region p3 of the driving transistor T3.

[0307] As shown in FIG. 17 and FIG. 37c, the second plate Cst2 of the storage capacitor Cst can be located in the metal layer MC; as shown in FIG. 37c and FIG. 38a, the second plates Cst2 of the storage capacitors Cst of a row of pixel circuits 10 are electrically connected in the same layer, so that the second plates Cst2 of the storage capacitors Cst of a row of pixel circuits 10 electrically connected in the same layer constitute a second sub power supply signal line PVDD2, the second sub power supply signal line PVDD2 extends along the second direction Y, and the second sub power supply signal line PVDD2 is arranged in a different layer from the first sub power supply signal line PVDD1.

[0308] As shown in FIG. 17, FIG. 37a, FIG. 37c and FIG. 37f, the first electrode p11 of the first light emitting control transistor T1 is electrically connected with the second sub power supply signal line PVDD2 through the connection part E4 located in the metal layer M2, and the second sub power supply signal line PVDD is in turn electrically connected with the first sub power supply signal line PVDD1 through the connection part E5 located in the metal layer M2.

[0309] As shown in FIG. 17, FIG. 37a and FIG. 38a, the second light emitting control transistor T6 includes a channel region p6 located in the active layer poly, and a first electrode p61 and a second electrode p62 connected with the channel region p6; the first electrode p61 of the second light emitting control transistor T6 is electrically connected in the same layer with the second electrode p32 of the driving transistor T3. As shown in FIG. 17, FIG. 37a, FIG. 37f-FIG. 37h, the second electrode p62 of the second light emitting control transistor T6 is in turn electrically connected with the light emitting element through the connection part E6 located in the metal layer M2 and the connection part E7 located in the metal layer M3.

[0310] It can be understood that the width of the first sub power signal line PVDD1 along the second direction Y can be appropriately narrowed to leave more setting space for the data signal line ND and the first auxiliary trace D1, but since the second electrode p62 of the second light emitting control transistor T6 needs to be electrically connected to the light emitting element through at least one via, the via is indispensable, therefore, the first sub power signal line PVDD1 cannot be narrowed unlimitedly between the at least one via through which the second light emitting control transistor T6 is electrically connected to the light emitting element and the data signal line ND; meanwhile, considering that the width of the first sub power signal line PVDD1 along the second direction Y is narrowed, the resistance of the first sub power signal line PVDD1 will increase, so the width of the first sub power signal line PVDD1 along the second direction Y is appropriately widened in the region with space to reduce the resistance of the first sub power signal line PVDD1.

[0311] As shown in FIGS. 35, 37g and 37b, the first sub power signal line PVDD1 includes a first sub section Z1 and a second sub section Z2, the width of the first sub section Z2 along the second direction Y is greater than 1.5 times the width of the second sub section Z2 along the second direction Y, and the second sub section Z2 corresponds to the at least one via through which the second light emitting control transistor T6 is electrically connected to the light emitting element; along the first direction X, the first sub section Z1 and the second sub section are alternately connected, and two adjacent first sub sections Z1 are connected through two second sub sections Z2 symmetrically arranged along the first direction Y.

[0312] Furthermore, as shown in FIGS. 35, 37g and 37b, the two column pixel circuits in one column repeat unit R are respectively a first pixel circuit column R1 and a second pixel circuit column R2, along the second direction Y, the first pixel circuit column R1 in one column repeat unit R and the second pixel circuit column R2 in the adjacent another column repeat unit R share the first sub power signal line PVDD1, in this way, the width of the first sub section Z1 in the first sub power signal line PVDD1 along the second direction Y can be larger, so that the first sub section Z1 in the first sub power signal line PVDD1 has a larger area, further reducing the resistance of the first sub power signal line PVDD1, thereby reducing the power consumption of the first power signal line PVDD and improving the signal transmission stability of the first power signal line PVDD, which is conducive to improving the display uniformity and other display effects of the display panel.

[0313] As shown in FIGS. 37c and 37g, and known from the foregoing, the second sub power signal line PVDD2 is arranged in a layer different from the first sub power signal line PVDD1, and the second sub power signal line PVDD2 is electrically connected to the first sub power signal line PVDD1. In this way, the first sub power signal line PVDD1 and the second sub power signal line PVDD2 form a grid structure, which can reduce the overall resistance of the first power signal line PVDD, reduce the power consumption of the first power signal line PVDD, and improve the signal transmission stability of the first power signal line PVDD, thereby improving the display uniformity and other display effects of the display panel.

[0314] As shown in FIGS. 35, 37h and 38b, the first power signal line PVDD further includes a plurality of first power signal line sub-parts PVDD3. The first power signal line sub-part PVDD3 is arranged in a layer different from the first sub power signal line PVDD1, and is arranged in the same layer as the first auxiliary trace D1 and the second auxiliary trace D2. Different first power signal line sub-parts PVDD3 are separated by the first auxiliary trace D2 and the second auxiliary trace D2. Specifically, the first power signal line sub-part PVDD3 is located in the metal layer M4, and the first power signal line sub-part PVDD3 is electrically connected to the first sub power signal line PVDD1 through a contact hole. In this way, the overall resistance of the first power signal line PVDD can be further reduced, the power consumption of the first power signal line PVDD can be reduced, and the signal transmission stability of the first power signal line PVDD can be improved, thereby improving the display uniformity and other display effects of the display panel.

[0315] As shown in FIGS. 17, 37d and 38a, the compensation transistor T4 and the gate reset transistor T5 can be oxide thin film transistors, i.e., IGZO thin film transistors. The compensation transistor T4 includes a channel region p4 located in an oxide layer IGZO, and a first electrode p41 and a second electrode p42 connected to the channel region p4. The gate reset transistor T5 includes a channel region p5 located in the oxide layer IGZO, and a first electrode p51 and a second electrode p52 connected to the channel region p5.

[0316] As shown in FIGS. 17, 37a-37d and 37f, the first electrode p41 of the compensation transistor T4 is electrically connected to the second electrode p32 of the driving transistor T3 through a connection part E8 located in the metal layer M2. The second electrode p42 of the compensation transistor T4 is directly electrically connected to the second electrode p52 of the gate initialization transistor T5 in the oxide layer IGZO, and is electrically connected to the gate g3 of the driving transistor T3 through a via in the second electrode plate Cst2 of the storage capacitor Cst in the metal layer MC and a connection part E9 located in the metal layer M2.

[0317] As shown in FIGS. 37d and 37g, in a direction perpendicular to the plane where the display panel is located, the first sub-section Z1 in the first sub-power supply signal line PVDD1 can cover the gate reset transistor T5 and / or the compensation transistor T4 due to the large area, so as to reduce the influence of ambient light on the compensation transistor T4 and the gate reset transistor T5, and further improve the display effect.

[0318] As shown in FIGS. 17, 37c-37e and 38a, the display area includes the scan signal line S1 and the scan signal line S2; the scan signal line S1 includes the first sub-scan signal S11 and the second sub-scan signal S12 which transmit the same scan signal, the first sub-scan signal S11 is located in the metal layer MC and extends along the second direction Y, and the second sub-scan signal S12 is located in the metal layer MG and extends along the second direction Y; in a direction perpendicular to the plane where the display panel is located, the first sub-scan signal S11, the second sub-scan signal S12 and the channel region p5 of the gate reset transistor T5 are overlapped. Optionally, in the direction perpendicular to the plane where the display panel is located, the part of the oxide layer IGZO which is overlapped with the first sub-scan signal S11 and the second sub-scan signal S12 is the channel region p5 of the gate reset transistor T5, the part of the first sub-scan signal S11 which is opposite to the channel region p5 of the gate reset transistor T5 is the bottom gate bg5 of the gate reset transistor T5, so that the bottom gate bg5 of the gate reset transistor T5 is electrically connected with the first sub-scan signal S11; the part of the second sub-scan signal S12 which is opposite to the channel region p5 of the gate reset transistor T5 is the top gate tg5 of the gate reset transistor T5, so that the top gate tg5 of the gate reset transistor T5 is electrically connected with the second sub-scan signal S12, so that the top gate tg5 and the bottom gate bg5 of the gate reset transistor T5 are both electrically connected with the first scan signal line S1 and receive the same scan signal.

[0319] Similarly, as shown in FIG. 17, FIG. 37c-FIG. 37e and FIG. 38a, the scan signal line S2 includes a third sub-scan signal line S21 and a fourth sub-scan signal line S22 that transmit the same scan signal, the third sub-scan signal line S21 is located in the metal layer MC and extends along the first direction X, and the fourth sub-scan signal line S22 is located in the metal layer MG and extends along the first direction X; in the direction perpendicular to the plane where the display panel is located, the third sub-scan signal line S21, the fourth sub-scan signal line S22 and the channel region p4 of the compensation transistor T4 are overlapped. Optionally, in the direction perpendicular to the plane where the display panel is located, the part of the oxide layer IGZO that overlaps with the third sub-scan signal line S21 and the fourth sub-scan signal line S22 is the channel region p4 of the compensation transistor T4, the part of the third sub-scan signal line S21 that directly faces the channel region p4 of the compensation transistor T4 is the bottom gate bg4 of the compensation transistor T4, so that the bottom gate bg4 of the compensation transistor T4 is electrically connected with the third sub-scan signal line S21; the part of the fourth sub-scan signal line S22 that directly faces the channel region p4 of the compensation transistor T4 is the top gate tg4 of the compensation transistor T4, so that the top gate tg4 of the compensation transistor T4 is electrically connected with the fourth sub-scan signal line S22, thereby making the top gate tg4 and the bottom gate bg4 of the compensation transistor T4 both electrically connected with the second scan signal line S2 to receive the same scan signal.

[0320] As shown in FIG. 17, FIG. 37c, FIG. 37f and FIG. 38a, the display area includes a first reference signal line ref1, the first reference signal line ref1 includes a first sub-reference signal line ref11 and a second sub-reference signal line ref12, the first sub-reference signal line ref11 extends along the second direction Y and is arranged along the first direction X, the second sub-reference signal line ref12 extends along the first direction X and is arranged along the second direction Y, the first sub-reference signal line ref11 and the second sub-reference signal line ref12 are arranged in different layers and are electrically connected.

[0321] As shown in FIG. 37c and FIG. 37f, the first sub-reference signal line ref11 is located in the metal layer MC, the second sub-reference signal line ref12 is located in the metal layer M2, and the first sub-reference signal line ref11 is electrically connected with the second sub-reference signal line ref12 through the connection part E10 located in the metal layer MC and the connection part E11 located in the metal layer M2. As shown in FIG. 17, FIG. 31d and FIG. 31f, the second sub-reference signal line ref12 is electrically connected with the first pole p51 of the gate reset transistor T5 through the connection part E11 located in the metal layer M2; and as shown in FIG. 31d, in a row of pixel circuits 10, the first poles p51 of the gate reset transistors T5 of the pixel circuits 10 that are adjacent to each other along the second direction Y are electrically connected in the same layer.

[0322] Thus, by arranging the first reference signal line ref1 to include the first sub-reference signal line ref11 and the second sub-reference signal line ref12 extending in different directions and being electrically connected, the first reference signal line ref1 in a grid structure is formed, and the grid structure formed by the first sub-reference signal line ref11 and the second sub-reference signal line ref12 is further shown in FIG. 39. In this way, the overall resistance of the first reference signal line ref1 can be reduced, the power consumption of the first reference signal line ref1 is further reduced, the signal transmission stability of the first reference signal line ref1 is improved, and the display uniformity and other display effects of the display panel are improved.

[0323] As shown in FIGS. 17, 37a, 37f-37g, and 38a, the anode reset transistor T7 includes a channel region p7 in the active layer poly, and a first pole p71 and a second pole p72 connected to the channel region p7; the second pole p72 of the anode reset transistor T7 is electrically connected to the light emitting element 20 through the connection portion E6 in the metal layer M2 and the connection portion E7 in the metal layer M3.

[0324] As shown in FIGS. 17, 37a-37b, and 38a, the display area includes a scan signal line SP, the scan signal line SP is located in the metal layer M1 and extends along the second direction Y, and in a direction perpendicular to the plane of the display panel, the scan signal line SP at least partially overlaps the channel region p7 of the anode reset transistor T7. Optionally, in the direction perpendicular to the plane of the display panel, the portion of the scan signal line SP overlapping the channel region p7 of the anode reset transistor T7 is the gate g7 of the anode reset transistor T7, so that the scan signal line SP is electrically connected to the gate of the anode reset transistor T7.

[0325] As shown in FIGS. 17, 37c, 37f, and 38a, the display area includes a second reference signal line ref2, the second reference signal line ref2 includes a third sub-reference signal line ref21 and a fourth sub-reference signal line ref22, the third sub-reference signal line ref21 extends along the second direction Y and is arranged along the first direction X, the fourth sub-reference signal line ref22 extends along the first direction X and is arranged along the second direction Y, the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22 are arranged in different layers, and the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22 are electrically connected.

[0326] Referring to FIGS. 17, 31c and 31f, the third sub-reference signal line ref21 is located in the metal layer MC, the fourth sub-reference signal line ref22 is located in the metal layer M2, and the third sub-reference signal line ref21 is electrically connected to the fourth sub-reference signal line ref22 through the connecting part E12 located in the metal layer MC and the connecting part E13 located in the metal layer M2. Referring to FIGS. 17, 31a and 31f, the fourth sub-reference signal line ref22 is electrically connected to the first electrode p71 of the anode reset transistor T7 through the connecting part E13 located in the metal layer M2, and in a row of pixel circuits 10, the first electrodes p71 of the anode reset transistors T7 of two-by-two adjacent pixel circuits 10 in the second direction Y are electrically connected in the same layer.

[0327] In this way, by arranging the second reference signal line ref2 to include the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22 extending in different directions and being cross-connected, the second reference signal line ref2 also forms a grid structure, and FIG. 39 further shows the grid structure formed by the third sub-reference signal line ref21 and the fourth sub-reference signal line ref22. In this way, the overall resistance of the second reference signal line ref2 is reduced, the power consumption of the second reference signal line ref2 is reduced, the signal transmission stability of the second reference signal line ref2 is improved, and the display uniformity and other display effects of the display panel are improved.

[0328] Referring to FIGS. 17, 37a and 38a, the bias transistor T8 includes a channel region p8 located in the active layer poly, and a first electrode p81 and a second electrode p82 connected to the channel region p8. Referring to FIGS. 17, 37a-37b and 38a, in a direction perpendicular to the plane of the display panel, the scan signal line SP at least partially overlaps the channel region p8 of the bias transistor T8. Optionally, in the direction perpendicular to the plane of the display panel, the portion of the scan signal line SP overlapping the channel region p8 of the bias transistor T8 is the gate g8 of the bias transistor T8, so that the scan signal line SP is electrically connected to the gate of the bias transistor T8.

[0329] Referring to FIGS. 17, 37a and 37f, the second electrode p82 of the bias transistor T8 is electrically connected to the first electrode p31 of the driving transistor T3 through the connecting part E14 located in the metal layer M2.

[0330] As shown in FIGS. 17, 37e, 37f and 38a, the display area includes a bias signal line DVH, the bias signal line DVH includes a first sub-bias signal line DVH1 and a second sub-bias signal line DVH2, the first sub-bias signal line DVH1 extends along the second direction Y and is arranged along the first direction X, the second sub-bias signal line DVH2 extends along the first direction X and is arranged along the second direction Y, the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are arranged in different layers and are electrically connected.

[0331] Specifically, as shown in FIGS. 37e and 37f, the first sub-bias signal line DVH1 is located in the metal layer M1, the second sub-bias signal line DVH2 is located in the metal layer M2, and the first sub-bias signal line DVH1 is electrically connected to the second sub-bias signal line DVH2 through the connection part E15 located in the metal layer M1 and the connection part E16 located in the metal layer M2; and as shown in FIGS. 37a, 37e and 37f, the second sub-bias signal line DVH2 is electrically connected to the first electrode p81 of the bias transistor T8 through the connection part E16 located in the metal layer M2, and in a row of pixel circuits 10, the first electrodes p81 of the bias transistors T8 of the pixel circuits 10 adjacent to each other along the second direction Y are electrically connected in the same layer.

[0332] In this way, by arranging the bias signal line DVH to include the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 extending along different directions and being electrically connected in a cross manner, a grid structure of the bias signal line DVH is also formed, and FIG. 39 further shows the grid structure formed by the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2. In this way, the overall resistance of the bias signal line DVH is reduced, the power consumption of the bias signal line DVH is further reduced, the signal transmission stability of the bias signal line DVH is improved, and the display uniformity and other display effects of the display panel are improved.

[0333] As shown in FIGS. 37c, 37e-37f and 39, the fourth sub-reference signal line ref22 of the second reference signal line ref2 includes a plurality of fourth sub-reference signal line segments ref220, the fourth sub-reference signal line segments ref220 extend along the first direction Y, and the fourth sub-reference signal line segments ref220 are electrically connected to the third sub-reference signal line ref21; the second sub-bias signal line DVH2 of the bias signal line DVH includes a plurality of second sub-bias signal line segments DVH20, the second sub-bias signal line segments DVH20 extend along the second direction Y, and the second sub-bias signal line segments DVH20 are electrically connected to the first sub-bias signal line DVH1.

[0334] As shown in FIGS. 37c, 37e-37f and 39, the fourth sub-reference signal line segment ref220 and the second sub-bias signal line segment DVH20 are arranged alternately along the first direction X and the second direction Y; in every four pixel circuit columns, two pixel circuit columns are provided with the second sub-reference signal line ref12, and the other two pixel circuit columns are provided with the fourth sub-reference signal line segment ref220 and the second sub-bias signal line segment DVH20, i.e., the pixel circuit columns provided with the second sub-reference signal line ref12 are arranged alternately with the pixel circuit columns provided with the fourth sub-reference signal line segment ref220 and the second sub-bias signal line segment DVH20 along the second direction Y; in this way, the number of the second sub-reference signal line ref12, the fourth sub-reference signal line segment ref220 and the second sub-bias signal line segment DVH20 can be reduced, and more space can be left for the data signal line ND and the first auxiliary trace D1.

[0335] As shown in FIGS. 37c, 37e and 39, one row of pixel circuits 10 is provided with one first sub-reference signal line ref11 to form a grid structure with the second sub-reference signal line ref12; one row of pixel circuits 10 is provided with one third sub-reference signal line ref21 to form a grid structure with the fourth sub-reference signal line segment ref220; and one row of pixel circuits 10 is provided with one first sub-bias signal line DVH1 to form a grid structure with the second sub-bias signal line segment DVH20.

[0336] As shown in FIGS. 38a and 38b, in one column repeat unit R, every two pixel circuits 10 arranged alternately along the second direction Y form a pixel circuit repeat unit Q, and the two pixel circuits 10 in the pixel circuit repeat unit Q are at least partially mirror-symmetrical along the first direction X.

[0337] Therefore, when the two data signal lines ND corresponding to the column of pixel circuits 10 are located on the same side of the column of pixel circuits 10 along the second direction Y, the data signal line ND is arranged in a layer different from the first auxiliary trace D1, the first auxiliary trace D1 and the second auxiliary trace D2 are arranged in the same layer, the number of contact holes connected to the data signal line ND is reduced, the first sub power signal line PVDD1 is partially narrowed along the first direction X, the second reference signal line sub-section ref20 in the second reference signal line ref and the second sub bias signal line DVH2 in the bias signal line DVH are arranged alternately along the first direction X and alternately along the second direction Y, and in the adjacent four columns of pixel circuits 10, two columns of pixel circuits 10 are correspondingly provided with the second sub reference signal line ref12, and the other two columns of pixel circuits 10 are correspondingly provided with the fourth sub reference signal line sub-section ref220 and the second sub bias signal line sub-section DVH20, and the column of pixel circuits corresponding to the second sub reference signal line ref12 is arranged with a column spacing, and the column of pixel circuits corresponding to the fourth sub reference signal line sub-section ref220 and the second sub bias signal line sub-section DVH20 is arranged with a column spacing, thereby leaving more space for the double data signal lines ND, the first auxiliary trace D1 and the second auxiliary trace D2.

[0338] Further, by arranging the first sub power signal line PVDD1 to include a first sub-section Z1 and a second sub-section Z2, the width of the first sub-section Z2 along the second direction Y is greater than the width of the second sub-section Z2 along the second direction Y, along the first direction X, the first sub-section Z1 and the second sub-section are alternately connected, and the adjacent two first sub-sections Z1 are connected by two second sub-sections Z2 arranged symmetrically along the first direction Y.

[0339] Further, along the second direction Y, the first pixel circuit column R1 in one column repetition unit R and the second pixel circuit column R2 in the adjacent another column repetition unit R share the first sub power signal line PVDD1, so that the first sub-section Z1 in the first sub power signal line PVDD1 has a larger area; and a plurality of first power signal line sub-sections PVDD3 are arranged in the metal layer where the first auxiliary trace D1 and the second auxiliary trace D2 are located, and the first power signal line sub-section PVDD3 is electrically connected with the first sub power signal line PVDD1, further reducing the resistance of the first sub power signal line PVDD1, thereby reducing the power consumption of the first power signal line PVDD and improving the signal transmission stability of the first power signal line PVDD, which is beneficial to improve the display uniformity and other display effects of the display panel.

[0340] In addition, the first sub-section Z1 in the first sub power signal line PVDD1 can cover the gate reset transistor T5 and / or the compensation transistor T4, so as to reduce the influence of ambient light on the compensation transistor T4 and the gate reset transistor T5, and further improve the display effect.

[0341] Figure 40 shows a partial layout structure diagram of another display panel provided in the embodiment of this application. For clarity, Figure 41a shows a layout structure diagram of metal layer M3 in the layout structure shown in Figure 40, Figure 41b shows a layout structure diagram of metal layer M4 in the layout structure shown in Figure 40, and Figure 41c shows a layout structure diagram of metal layers M3 and M4 in the layout structure shown in Figure 40. The layout structures of other film layers are referenced to the layout of the corresponding film layers in the layout structure shown in Figure 34, and will not be described again.

[0342] The layout structure shown in Figure 40 is the same as that shown in Figure 34. Along the second direction Y, the two data signal lines ND that are electrically connected to a column of pixel circuits 10 are located on the same side of the column of pixel circuits 10. The first auxiliary trace D1 is set on a different layer from the data signal line ND, and the second auxiliary trace D2 is set on a different layer from the data signal line ND. In addition, the first auxiliary trace D1 and the second auxiliary trace D2 are set on the same layer. Specifically, the data signal line ND is located on the metal layer M3, and the first auxiliary trace D1 and the second auxiliary trace D2 are located on the metal layer M4.

[0343] The layout structure shown in Figure 40 differs from that shown in Figure 34 in that each column of pixel circuits 10 has two first auxiliary traces D1. In the direction perpendicular to the plane of the display panel, the first auxiliary traces D1 and the data signal line ND at least partially overlap. This reduces the space occupied by the data signal line ND and the first auxiliary traces D1.

[0344] It is understandable that, along the second direction Y, when the two data signal lines ND corresponding to the pixel circuit 10 are located on the same side of the pixel circuit 10, the first auxiliary trace D1 can also be set on the same layer as the data signal line ND, and the second auxiliary trace D2 can be set on a different layer from the data signal line ND and the second auxiliary trace D1. The second connecting segment DH1 in the data signal line ND and the second auxiliary trace D2 is electrically connected through a contact hole, and the second connecting segment DH1 in the second auxiliary trace D2 is electrically connected to the first connecting segment DV1 in the first auxiliary trace D1 through a contact hole. At this time, the layout structure can be adjusted with reference to the aforementioned embodiments, and will not be described in detail here.

[0345] This application also provides a display device, as shown in FIG42, which includes the display panel 200 provided in any of the above embodiments. Since the display panel 200 has been described in detail in the foregoing embodiments, it will not be described again here.

[0346] The display device 100 may be, for example, a touch screen, a mobile phone, a tablet computer, or a laptop computer.

[0347] Various portions of the specification are presented in terms of sequences of actions, procedures, steps, logic blocks, processing, and other symbolic representations of operational data mapping or the like that can be described herein in a specific manner for purposes of clarity. The various portions of the specification can be presented in terms of sequences of actions, procedures, steps, logic blocks, processing, and other symbolic representations of operational data mapping or the like that can be described herein in a specific manner for purposes of clarity.

[0348] The above description of disclosed embodiments is presented in terms of a particular sequence of actions, procedures, steps, logic blocks, processing, and other symbolic representations of operational data mapping or the like that can be described herein in a specific manner for purposes of clarity. The various portions of the specification can be presented in terms of sequences of actions, procedures, steps, logic blocks, processing, and other symbolic representations of operational data mapping or the like that can be described herein in a specific manner for purposes of clarity. The various portions of the specification can be presented in terms of sequences of actions, procedures, steps, logic blocks, processing, and other symbolic representations of operational data mapping or the like that can be described herein in a specific manner for purposes of clarity.

Claims

1. A display panel, comprising a display area and a non-display area at least partially surrounding the display area; the display area comprises an array of pixel circuits, two data signal lines corresponding to a column of the pixel circuits are electrically connected, the data signal lines extend along a first direction and are arranged along a second direction, the first direction and the second direction intersect; the display area comprises a first display area and a second display area located at least one side of the first display area along the second direction, the non-display area comprises a fan-out area located at one side of the display area along the first direction, the fan-out area comprises a plurality of fan-out wires, the data signal lines are electrically connected with the fan-out wires; the display area comprises a plurality of first auxiliary wires extending along the first direction and a plurality of second auxiliary wires extending along the second direction, at least part of the first auxiliary wires comprises a first connection line segment, at least part of the second auxiliary wires comprises a second connection line segment, the data signal lines in the second display area are electrically connected with the fan-out wires through the first connection line segment and the second connection line segment.

2. The display panel of claim 1, wherein, Along the second direction, two data signal lines corresponding to a column of the pixel circuits are distributed on opposite sides of the column of the pixel circuits.

3. The display panel of claim 2, wherein, The first auxiliary wires are arranged in the same layer as the data signal lines, and the second auxiliary wires are arranged in different layers from the first auxiliary wires; The data signal lines are electrically connected with the second connection line segment through a contact hole, and the second connection line segment is electrically connected with the first connection line segment through a contact hole.

4. The display panel of claim 3, wherein, The display area comprises a first power signal line, the first power signal line comprises a first sub-power signal line and a second sub-power signal line arranged in different layers, the first sub-power signal line extends along the first direction, the second sub-power signal line extends along the second direction, and the first sub-power signal line and the second sub-power signal line are electrically connected; a column of the pixel circuits corresponds to a first sub-power signal line, and the first sub-power signal line is arranged in the same layer as the data signal lines; a column of the pixel circuits corresponds to a first auxiliary wire; The first auxiliary wire and the first sub-power signal line are located between two data signal lines corresponding to a column of the pixel circuits.

5. The display panel of claim 4, wherein, The first power signal line further comprises a plurality of first power signal line sub-parts, the first power signal line sub-parts are arranged in the same layer as the second auxiliary wires, and the first power signal line sub-parts are electrically connected with the first sub-power signal line.

6. The display panel of claim 4, wherein, The display area comprises a plurality of light emitting elements, the pixel circuit comprises a driving transistor, a gate reset transistor and an anode reset transistor; The display area comprises a first reference signal line and a second reference signal line, the gate reset transistor is electrically connected between the gate of the driving transistor and the first reference signal line, and the anode reset transistor is electrically connected between the light emitting element and the second reference signal line. The first reference signal line includes a first sub-reference signal line and a second sub-reference signal line, the first sub-reference signal line extends along the second direction and is arranged along the first direction, the second sub-reference signal line extends along the first direction and is arranged along the second direction, the first sub-reference signal line and the second sub-reference signal line are arranged in different layers, and the first sub-reference signal line and the second sub-reference signal line are electrically connected; The second reference signal line includes a third sub-reference signal line and a fourth sub-reference signal line, the third sub-reference signal line extends along the second direction and is arranged along the first direction, the fourth sub-reference signal line extends along the first direction and is arranged along the second direction, the third sub-reference signal line and the fourth sub-reference signal line are arranged in different layers, and the third sub-reference signal line and the fourth sub-reference signal line are electrically connected; Among the four adjacent columns of pixel circuits, two columns of pixel circuits are correspondingly provided with the second sub-reference signal line, and the other two columns of pixel circuits are correspondingly provided with the fourth sub-reference signal line, and the second sub-reference signal line and the fourth sub-reference signal line are alternately arranged along the second direction.

7. The display panel of claim 2, wherein, The first auxiliary wire and the second auxiliary wire are arranged in different layers.

8. The display panel of claim 7, wherein, The first auxiliary wire and the second auxiliary wire are arranged in different layers. The data signal line and the second connection line segment or the data signal line and the first connection line segment are electrically connected through a contact hole, and the second connection line segment and the first connection line segment are electrically connected through a contact hole.

9. The display panel of claim 7, wherein, The first auxiliary wire and the second auxiliary wire are arranged in different layers. The data signal line and the second connection line segment are electrically connected through a contact hole, and the second connection line segment and the first connection line segment are electrically connected in the same layer.

10. The display panel of claim 7, wherein, The display area includes a first power signal line, the first power signal line includes a first sub-power signal line and a second sub-power signal line arranged in different layers, the first sub-power signal line extends along the first direction, the second sub-power signal line extends along the second direction, and the first sub-power signal line and the second sub-power signal line are electrically connected; One column of pixel circuits is correspondingly electrically connected to one first sub-power signal line, and the first sub-power signal line is arranged in the same layer as the data signal line; The first sub-power signal line is located between two data signal lines correspondingly electrically connected by one column of pixel circuits. Two columns of pixel circuits are correspondingly provided with one first auxiliary wire, and the first auxiliary wire is located between two data signal lines between two adjacent columns of pixel circuits.

11. The display panel of claim 7, wherein, One column of pixel circuits is correspondingly provided with one or two first auxiliary wires. In a direction perpendicular to the plane on which the display panel is located, the first auxiliary wire and the data signal line at least partially overlap.

12. The display panel of claim 7, wherein, Two columns of pixel circuits are correspondingly provided with three first auxiliary wires, and the first auxiliary wires are located between any two adjacent data signal lines.

13. The display panel of claim 8, wherein, The display area includes a plurality of light emitting elements; the pixel circuit includes a driving transistor, a biasing transistor, and an anode reset transistor; The display area comprises a bias signal line and a first reference voltage line, the bias transistor is electrically connected between at least one of the first electrode and the second electrode of the driving transistor and the bias signal line, and the anode reset transistor is electrically connected between the light-emitting element and the second reference signal line; The bias signal line comprises a first sub-bias signal line and a second sub-bias signal line, the first sub-bias signal line extends along the second direction and is arranged along the first direction, the second sub-bias signal line extends along the first direction and is arranged along the second direction, the first sub-bias signal line and the second sub-bias signal line are arranged in different layers, and the first sub-bias signal line and the second sub-bias signal line are electrically connected; The second reference signal line comprises a third sub-reference signal line and a fourth sub-reference signal line, the third sub-reference signal line extends along the second direction and is arranged along the first direction, the fourth sub-reference signal line extends along the first direction and is arranged along the second direction, the third sub-reference signal line and the fourth sub-reference signal line are arranged in different layers, and the third sub-reference signal line and the fourth sub-reference signal line are electrically connected; In the four adjacent columns of the pixel circuits, two columns of the pixel circuits are correspondingly provided with the second sub-bias signal line, and the other two columns of the pixel circuits are correspondingly provided with the fourth sub-reference signal line, and the second sub-bias signal line and the fourth sub-reference signal line are alternately arranged along the second direction.

14. The display panel of claim 2, wherein, The display area comprises a first power signal line, the first power signal line comprises a first sub-power signal line and a second sub-power signal line arranged in different layers, the first sub-power signal line extends along the first direction, the second sub-power signal line extends along the second direction, and the first sub-power signal line and the second sub-power signal line are electrically connected; One column of the pixel circuits is correspondingly electrically connected to one first sub-power signal line, and the first sub-power signal line is arranged in the same layer as the data signal line; The first sub-power signal line is located between two data signal lines correspondingly electrically connected to one column of the pixel circuits; The first sub-power signal line comprises a first sub-section, a second sub-section and a third sub-section, the first sub-section is electrically connected to the third sub-section through the second sub-section, the third sub-section is electrically connected to the first sub-section through the second sub-section, the width of the first sub-section along the second direction is greater than 1.5 times the width of the second sub-section along the second direction, and the width of the third sub-section along the second direction is greater than 1.5 times the width of the second sub-section along the second direction.

15. The display panel of claim 1, wherein, Along the second direction, two data signal lines correspondingly electrically connected to one column of the pixel circuits are located on the same side of the column of the pixel circuits.

16. The display panel of claim 15, wherein, The display area comprises a plurality of column repeat units arranged along the second direction, each column repeat unit comprises two columns of pixel circuits arranged adjacent along the second direction, and the two columns of pixel circuits in the column repeat unit are mirror-symmetrical along the first direction. Two columns of the pixel circuits in the column repeat unit correspond to four data signal lines electrically connected in total, and one column of the pixel circuits corresponds to two data signal lines electrically connected and the other column of the pixel circuits corresponds to two data signal lines electrically connected, which are mirror-symmetrical along the first direction.

17. The display panel of claim 16, wherein, The first auxiliary wires and the data signal lines are arranged in different layers, and the second auxiliary wires and the data signal lines are arranged in different layers.

18. The display panel of claim 17, wherein, One column of the pixel circuits corresponds to one first auxiliary wire; The first auxiliary wire is located between two data signal lines electrically connected corresponding to one column of the pixel circuits; Alternatively, the first auxiliary wire is located on one side of two data signal lines electrically connected corresponding to one column of the pixel circuits along the second direction; Alternatively, in a direction perpendicular to a plane where the display panel is located, the first auxiliary wire corresponding to one column of the pixel circuits and the data signal lines electrically connected corresponding to the same column of the pixel circuits at least partially overlap.

19. The display panel of claim 17, wherein, Three first auxiliary wires corresponding to two columns of the pixel circuits in the column repeat unit are arranged, the three first auxiliary wires are located between the two columns of the pixel circuits in the column repeat unit, and the first auxiliary wires are located between two adjacent data signal lines.

20. The display panel of claim 17, wherein, One column of the pixel circuits corresponds to two first auxiliary wires; In a direction perpendicular to a plane where the display panel is located, the first auxiliary wires and the data signal lines at least partially overlap.

21. The display panel of claim 17, wherein, The first auxiliary wires and the second auxiliary wires are arranged in different layers; The data signal lines and the second connection line segment or the data signal lines and the first connection line segment are electrically connected through contact holes, and the second connection line segment and the first connection line segment are electrically connected through contact holes.

22. The display panel of claim 17, wherein, The first auxiliary wires and the second auxiliary wires are arranged in the same layer; The data signal lines and the first connection line segment are electrically connected through contact holes, and the second connection line segment and the first connection line segment are electrically connected in the same layer.

23. The display panel of claim 22, wherein, The pixel circuit includes a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor; The display area includes a plurality of light-emitting elements, and the light-emitting elements correspond one-to-one to the pixel circuits; The display area includes a first power signal line, and the first power signal line includes a first sub-power signal line extending along the first direction, and the first sub-power signal line is arranged in the same layer as the data signal line; The first light-emitting control transistor is electrically connected between a first electrode of the driving transistor and the first sub-power signal line, the second light-emitting control transistor is electrically connected between a second electrode of the driving transistor and the light-emitting element, and the second light-emitting control transistor is electrically connected to the light-emitting element through at least one via hole; The first sub-power signal line is located between the at least one via hole and the data signal line.

24. The display panel of claim 23, wherein, Two of the pixel circuits in one of the column repeat units are a first pixel circuit column and a second pixel circuit column, respectively, and the first pixel circuit column in one of the column repeat units and the second pixel circuit column in another adjacent column repeat unit share the first sub power supply signal line in the second direction.

25. The display panel of claim 23, wherein, The first sub power supply signal line includes a first sub segment and a second sub segment, a width of the first sub segment in the second direction is greater than 1.5 times a width of the second sub segment in the second direction, and the second sub segment corresponds to the at least one via hole; In the first direction, the first sub segment and the second sub segment are alternately connected, and two adjacent first sub segments are connected by two second sub segments symmetrically arranged in the first direction.

26. The display panel of claim 25, wherein, The pixel circuit includes a gate reset transistor, the display area includes a first reference signal line, and the gate reset transistor is electrically connected between the gate of the driving transistor and the first reference signal line; The pixel circuit includes a threshold compensation transistor, and the threshold compensation transistor is electrically connected between the gate and the second electrode of the driving transistor; The first sub segment covers the gate reset transistor and / or the threshold compensation transistor.

27. The display panel of claim 25, wherein, The first power supply signal line further includes a plurality of first power supply signal line subparts, the first power supply signal line subparts are arranged in different layers from the first sub power supply signal line, and the first power supply signal line subparts are arranged in the same layer as the first auxiliary trace and the second auxiliary trace, different first power supply signal line subparts are separated by the first auxiliary trace and the second auxiliary trace; The first power supply signal line subpart and the first sub power supply signal line are electrically connected through a contact hole.

28. The display panel of claims 23-27, wherein, The first power supply signal line further includes a second sub power supply signal line extending in the first direction, the second sub power supply signal line and the first sub power supply signal line are arranged in different layers, and the second sub power supply signal line and the first sub power supply signal line are electrically connected.

29. The display panel of claim 9 or 22, wherein, The pixel circuit includes a driving transistor, a biasing transistor, a gate reset transistor, and an anode reset transistor; and the display area includes a light emitting element; The display area includes a biasing signal line, a first reference signal line, and a second reference signal line, the biasing transistor is electrically connected between at least one of the first electrode and the second electrode of the driving transistor and the biasing signal line, the gate reset transistor is electrically connected between the gate of the driving transistor and the first reference voltage line, and the anode reset transistor is electrically connected between the light emitting element and the second reference signal line; The biasing signal line includes a first sub biasing signal line and a second sub biasing signal line, the first sub biasing signal line extends in the second direction and is arranged in the first direction, the second sub biasing signal line extends in the first direction and is arranged in the second direction, the first sub biasing signal line and the second sub biasing signal line are arranged in different layers, and the first sub biasing signal line and the second sub biasing signal line are electrically connected. The first reference signal line comprises a first sub-reference signal line and a second sub-reference signal line, the first sub-reference signal line extends along the second direction and is arranged along the first direction, the second sub-reference signal line extends along the first direction and is arranged along the second direction, the first sub-reference signal line and the second sub-reference signal line are arranged in different layers, and the first sub-reference signal line and the second sub-reference signal line are electrically connected; The second reference signal line comprises a third sub-reference signal line and a fourth sub-reference signal line, the third sub-reference signal line extends along the second direction and is arranged along the first direction, the fourth sub-reference signal line extends along the first direction and is arranged along the second direction, the third sub-reference signal line and the fourth sub-reference signal line are arranged in different layers, and the third sub-reference signal line and the fourth sub-reference signal line are electrically connected; The fourth sub-reference signal line comprises a plurality of fourth sub-reference line segments, and the second sub-offset signal line comprises a plurality of second sub-offset signal line segments, the fourth sub-reference line segments and the second sub-offset signal line segments are alternately arranged along the first direction and alternately arranged along the second direction; Among the four adjacent columns of the pixel circuits, two columns of the pixel circuits are correspondingly provided with the second sub-reference signal line, and the other two columns of the pixel circuits are correspondingly provided with the fourth sub-reference signal line segments and the second sub-offset signal line segments, the columns of the pixel circuits correspondingly provided with the second sub-reference signal line are arranged alternately, and the columns of the pixel circuits correspondingly provided with the fourth sub-reference signal line segments and the second sub-offset signal line segments are arranged alternately.

30. The display panel of claim 1, wherein, The first auxiliary wiring further comprises a first non-connected line segment, and the first non-connected line segment is insulatively arranged in the same layer as the first connected line segment; The second auxiliary wiring further comprises a second non-connected line segment, and the second non-connected line segment is insulatively arranged in the same layer as the second connected line segment; The first non-connected line segment and the second non-connected line segment are grid-connected.

31. The display panel of claim 1, wherein, The pixel circuit comprises an LTPS transistor and an oxide transistor.

32. The display panel of claim 1, wherein, Among the columns of the pixel circuits, the pixel circuits in odd-numbered rows share one data signal line, and the pixel circuits in even-numbered rows share one data signal line; The display panel comprises a plurality of light emitting elements, the pixel circuits and the light emitting elements one-to-one correspondingly electrically connected, and the light emitting elements electrically connected by the pixel circuits sharing the same data signal line have the same display color.

33. A display device comprising the display panel of any one of claims 1-32.

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