Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises data signal lines (DATA), data auxiliary lines (FIAA), a display region (AA) and a non-display region (NAA). The display region (AA) comprises a first display region (AA1) and a second display region (AA2), and the non-display region (NAA) comprises a fan-out region (NAA1), wherein the fan-out region (NAA1) comprises a plurality of fan-out traces (FANOUT), data signal lines (DATA) located in the first display region (AA1) are directly electrically connected to the fan-out traces (FANOUT), and data signal lines (DATA) located in the second display region (AA2) are electrically connected to the fan-out traces (FANOUT) by means of the data auxiliary lines (FIAA). The display panel further comprises a substrate (10) and a first coupling adjustment structure (11) located between a film layer in which the substrate (10) is located and a film layer in which the data auxiliary lines (FIAA) are located, wherein in the direction of thickness of the display panel, the first coupling adjustment structure (11) overlaps with the data auxiliary lines (FIAA) and is connected to a fixed potential signal line.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202411253265.2, filed on September 6, 2024, to the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, for example, to a display panel and a display device. BACKGROUND

[0003] With the continuous development of display technology, display panels have been widely used in people's production and life. However, there are still some technical problems in the display panel in the related art that need to be solved. For example, the signals on some signal lines will exist coupling interference, thereby affecting the display effect of the display panel.

[0004] SUMMARY

[0005] Embodiments of the present application provide a display panel and a display device, by arranging a first coupling adjustment structure electrically connected with the fixed potential signal line between the film layer where the data auxiliary line is located and the film layer where the substrate is located, a stable capacitance structure is formed between the first coupling adjustment structure and the data auxiliary line to avoid the interference of other signals on the signals in the data auxiliary line, and the display stability is ensured.

[0006] In a first aspect, a display panel is provided, comprising a plurality of signal lines;

[0007] The signal lines include data signal lines, and the plurality of data signal lines extend along a first direction and are arranged along a second direction; the first direction and the second direction intersect;

[0008] The display panel further comprises a display area and a non-display area surrounding at least part of the display area, the display area comprises a first display area and a second display area, the second display area is located at least one side of the first display area along the second direction; the first display area and the second display area both comprise a plurality of data signal lines; the non-display area comprises a fan-out area located at one side of the display area along the first direction, and the fan-out area comprises a plurality of fan-out wires;

[0009] The signal lines further comprise a data auxiliary line, at least part of a data auxiliary line is located in the display area, and the data signal lines located in the second display area are electrically connected with the fan-out wires through the data auxiliary line;

[0010] The display panel further comprises a substrate and a first coupling adjustment structure between a film layer where the substrate is located and a film layer where the data auxiliary line is located; the first coupling adjustment structure overlaps the data auxiliary line in a thickness direction of the display panel, and the first coupling adjustment structure is configured to receive a fixed potential signal.

[0011] In a second aspect, the display device provided by the embodiments of the present application comprises the display panel of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0012] The drawings needed in the following embodiment description will be introduced as follows, and the drawings in the following description are some drawings related to the present application. Other drawings can also be obtained according to these drawings without creative labor for those skilled in the art.

[0013] FIG. 1 is a structural schematic diagram of a display panel provided by the embodiments of the present application;

[0014] FIG. 2 is a structural schematic diagram of another display panel provided by the embodiments of the present application;

[0015] FIG. 3 is a cross-sectional structural schematic diagram of a display panel provided by the embodiments of the present application;

[0016] FIG. 4 is a structural schematic diagram of a multiplexing unit provided by the embodiments of the present application;

[0017] FIG. 5 is a cross-sectional structural schematic diagram of another display panel provided by the embodiments of the present application;

[0018] FIG. 6 is a circuit connection schematic diagram of a pixel circuit provided by the embodiments of the present application;

[0019] FIG. 7 is a timing diagram of an embodiment of signals provided to the pixel circuit shown in FIG. 6 in a driving period provided by the embodiments of the present application;

[0020] FIG. 8 is a circuit connection schematic diagram of another pixel circuit provided by the embodiments of the present application;

[0021] FIG. 9 is a timing diagram of an embodiment of signals provided to the pixel circuit shown in FIG. 8 in a driving period provided by the embodiments of the present application;

[0022] FIG. 10 is a film layer structural schematic diagram of a display panel provided by the embodiments of the present application;

[0023] FIG. 11 is a structural schematic diagram of a zeroth metal layer in the display panel shown in FIG. 10;

[0024] FIG. 12 is a structural schematic diagram of a first semiconductor layer in the display panel shown in FIG. 10;

[0025] Fig. 13 is a structural diagram of a first metal layer in the display panel of Fig. 10;

[0026] Fig. 14 is a structural diagram of a second metal layer in the display panel of Fig. 10;

[0027] Fig. 15 is a structural diagram of a third metal layer in the display panel of Fig. 10;

[0028] Fig. 16 is a structural diagram of a partial layer stack in the display panel of Fig. 10;

[0029] Fig. 17 is a structural diagram of a fifth metal layer in the display panel of Fig. 10;

[0030] Fig. 18 is a structural diagram of an anode layer in the display panel of Fig. 10;

[0031] Fig. 19 is a structural diagram of a partial layer stack in the display panel of Fig. 10;

[0032] Fig. 20 is a structural diagram of a full layer stack in the display panel of Fig. 10;

[0033] Fig. 21 is a structural diagram of a layer stack of another display panel according to an embodiment of the present application;

[0034] Fig. 22 is a structural diagram of a first zero metal layer in the display panel of Fig. 21;

[0035] Fig. 23 is a structural diagram of a first semiconductor layer in the display panel of Fig. 21;

[0036] Fig. 24 is a structural diagram of a first metal layer in the display panel of Fig. 21;

[0037] Fig. 25 is a structural diagram of a second metal layer in the display panel of Fig. 21;

[0038] Fig. 26 is a structural diagram of a second semiconductor layer in the display panel of Fig. 21;

[0039] Fig. 27 is a structural diagram of a fourth metal layer in the display panel of Fig. 21;

[0040] Fig. 28 is a structural diagram of a third metal layer in the display panel of Fig. 21;

[0041] Fig. 29 is a structural diagram of a partial layer stack in the display panel of Fig. 21;

[0042] Fig. 30 is a structural diagram of a fifth metal layer in the display panel of Fig. 21;

[0043] Fig. 31 is a structural diagram of an anode layer in the display panel of Fig. 21;

[0044] Figure 32 is a schematic diagram of a partial stack of layers of the display panel of Figure 21;

[0045] Figure 33 is a schematic diagram of a full stack of layers of the display panel of Figure 21;

[0046] Figure 34 is a schematic diagram of an alternative zeroth metal layer of the display panel of Figure 21;

[0047] Figure 35 is a schematic diagram of an alternative first semiconductor layer of the display panel of Figure 21;

[0048] Figure 36 is a schematic diagram of an alternative first metal layer of the display panel of Figure 21;

[0049] Figure 37 is a schematic diagram of an alternative second metal layer of the display panel of Figure 21;

[0050] Figure 38 is a schematic diagram of an alternative second semiconductor layer of the display panel of Figure 21;

[0051] Figure 39 is a schematic diagram of an alternative fourth metal layer of the display panel of Figure 21;

[0052] Figure 40 is a schematic diagram of an alternative third metal layer of the display panel of Figure 21;

[0053] Figure 41 is a schematic diagram of a partial stack of layers of the display panel of Figure 21;

[0054] Figure 42 is a schematic diagram of an alternative fifth metal layer of the display panel of Figure 21;

[0055] Figure 43 is a schematic diagram of an alternative anode layer of the display panel of Figure 21;

[0056] Figure 44 is a schematic diagram of a partial stack of layers of the display panel of Figure 21;

[0057] Figure 45 is a schematic diagram of a full stack of layers of the display panel of Figure 21;

[0058] Figure 46 is a schematic diagram of a further zeroth metal layer of the display panel of Figure 21;

[0059] Figure 47 is a schematic diagram of a further first semiconductor layer of the display panel of Figure 21;

[0060] Figure 48 is a schematic diagram of a further first metal layer of the display panel of Figure 21;

[0061] Figure 49 is a schematic diagram of a further second metal layer of the display panel of Figure 21;

[0062] FIG. 50 is a structure diagram of a second semiconductor layer in the display panel of FIG. 21;

[0063] FIG. 51 is a structure diagram of a fourth metal layer in the display panel of FIG. 21;

[0064] FIG. 52 is a structure diagram of a third metal layer in the display panel of FIG. 21;

[0065] FIG. 53 is a structure diagram of a partial film layer in the display panel of FIG. 21;

[0066] FIG. 54 is a structure diagram of a fifth metal layer in the display panel of FIG. 21;

[0067] FIG. 55 is a structure diagram of an anode layer in the display panel of FIG. 21;

[0068] FIG. 56 is a structure diagram of a partial film layer in the display panel of FIG. 21;

[0069] FIG. 57 is a structure diagram of a partial film layer in the display panel of FIG. 21;

[0070] FIG. 58 is a structure diagram of a partial film layer in the display panel of FIG. 21;

[0071] FIG. 59 is a structure diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0072] The embodiments of the present application will be described hereinafter with reference to the drawings. The embodiments described are some of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of the present application.

[0073] The terms "first", "second", and the like in the description and in the claims of the present application and the above-described drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged, where appropriate, so that the embodiments of the present application described herein can be carried out in other sequences than those illustrated or described herein. Moreover, the terms "comprise", "have" and any variations thereof are intended to cover a non-exclusive inclusion, for example, a system, product or apparatus that comprises a list of components does not necessarily include only those components in the list, but can include additional components not expressly listed or inherent to such system, product or apparatus.

[0074] FIG. 1 is a structural schematic diagram of a display panel according to an embodiment of the present application, FIG. 2 is a structural schematic diagram of another display panel according to an embodiment of the present application, and FIG. 3 is a structural schematic diagram of a cross section of a display panel according to an embodiment of the present application. In combination with FIGS. 1, 2 and 3, the display panel according to an embodiment of the present application includes a plurality of signal lines. The signal lines include data signal lines DATA, and the plurality of data signal lines DATA extend along a first direction (e.g., the X direction shown in the figure) and are arranged along a second direction (e.g., the Y direction shown in the figure). The first direction and the second direction intersect. The display panel further includes a display area AA and a non-display area NAA at least partially surrounding the display area AA. The display area AA includes a first display area AA1 and a second display area AA2, and the second display area AA2 is located at least one side of the first display area AA1 along the second direction. The first display area AA1 and the second display area AA2 each include a plurality of data signal lines DATA. The non-display area NAA includes a fan-out area NAA1 located at one side of the display area along the first direction, and the fan-out area NAA1 includes a plurality of fan-out lines FANOUT. The signal lines further include a data auxiliary line FIAA, and at least part of one data auxiliary line FIAA is located in the display area AA. The data signal lines DATA located in the second display area AA2 are electrically connected to the fan-out lines FANOUT through the data auxiliary line FIAA. The display panel further includes a substrate 10 and a first coupling adjustment structure 11 located between a film layer where the substrate is located and a film layer where the data auxiliary line FANOUT is located. In the thickness direction of the display panel (e.g., the Z direction shown in the figure), the first coupling adjustment structure 11 overlaps the data auxiliary line FIAA, and the first coupling adjustment structure 11 is electrically connected to a fixed potential signal line.

[0075] For example, referring to FIGS. 1 and 2, the display panel includes signal lines, which include data signal lines DATA and other signal lines required for ensuring normal operation of the display panel, such as power signal lines, scanning signal lines, and touch signal lines. In some embodiments, referring to FIG. 1, the display panel can further include pixel circuits 20 and light emitting elements 30. The signal lines are electrically connected to the pixel circuits 20 and are configured to provide at least one of a voltage signal and a current signal to the pixel circuits 20. The pixel circuits 20 are electrically connected to the light emitting elements 30 and are configured to drive the light emitting elements 30 to emit light under the action of at least one of the voltage signal and the current signal. The pixel circuits 20 can have various configurations, and can be “2T1C”, “7T1C”, or “8T1C”, where “T” represents a transistor and “C” represents a storage capacitor. The configuration of the pixel circuits in the embodiments of the present application, such as “3T1C” and “6T1C” pixel circuits, are also within the scope of protection of the embodiments of the present application. The light emitting elements 30 can be at least one of a light emitting diode, an organic light emitting diode, and a micro light emitting diode.

[0076] With reference to FIGS. 1 and 2, the display panel provided by the embodiments of the present application includes a display area AA and a non-display area NAA, and the data signal line DATA, the pixel circuit 20 and the light emitting element 30 described above can be arranged in the display area AA. The display area AA can include a first display area AA1 and a second display area AA2. As an example, the second display area AA2 is located on both sides of the first display area AA1 along the second direction Y in FIG. 2. In this arrangement, along the orientation shown in FIG. 2, the second display area AA2 is located between the first display area AA1 and the non-display areas NAA on the left and right sides, and along the second direction Y, the first display area AA1 is closer to the center of the display panel, and the second display area AA2 is closer to the edge of the display panel. The non-display area NAA includes a fan-out area NAA1, which is located on one side of the display area AA along the first direction X. As an example, the lower side in the figure, the fan-out area NAA1 can be arranged with a plurality of fan-out wires FANOUT, which are electrically connected to the data signal line DATA, thereby connecting the data signal line DATA to the display controller and ensuring stable transmission of the data signal. With reference to FIG. 2, a plurality of data signal lines DATA are arranged in the first display area AA1 and the second display area AA2. The data signal lines DATA located in the first display area AA1 can be directly electrically connected to the fan-out wires FANOUT, and the data signal lines DATA located in the second display area AA2 are electrically connected to the fan-out wires FANOUT through the data auxiliary lines FIAA in the display area AA. The data auxiliary line FIAA can be understood as a connection bridge between the data signal line DATA and the fan-out wire FANOUT in the second display area AA2, and at least part of a data auxiliary line FIAA is located in the display area AA. In this way, the fan-out wires FANOUT can be concentratedly arranged in the fan-out area NAA1 below the first display area AA1, thereby reducing the occupied space of the fan-out wires FANOUT, reducing the arrangement area of the fan-out area NAA1, effectively reducing the proportion of the non-display area NAA, increasing the proportion of the display area AA of the display panel, increasing the display effect of the display panel, and achieving a narrow frame.

[0077] In some embodiments, since the signal transmitted in the data auxiliary line FIAA is a data signal, when the potential in the data auxiliary line FIAA is floating, the signal in the data auxiliary line FIAA will change due to the interference of other jump signals, and the change of the signal in the data auxiliary line FIAA will cause the signal in the data signal line DATA in the second display area AA2 connected thereto to change, thereby affecting the display brightness of the light emitting element 30 electrically connected to the data signal line DATA in the second display area AA2, and causing display abnormalities. Based on this, the display panel in the embodiments of the present application further comprises a first coupling adjustment structure 11, which is located below the film layer of the data auxiliary line FIAA and overlaps the data auxiliary line FIAA in the thickness direction of the display panel, so that a capacitor structure is formed between the first coupling adjustment structure 11 and the data auxiliary line FIAA. Since the first coupling adjustment structure 11 is electrically connected to the fixed potential signal line, and the fixed potential signal line transmits a fixed potential signal, the two capacitor plates of the capacitor structure formed between the first coupling adjustment structure 11 and the data auxiliary line FIAA, that is, the potentials in the first coupling adjustment structure 11 and the data auxiliary line FIAA, can be kept stable, ensuring that the data signal on the data auxiliary line FIAA will not change due to the interference of other jump signals even if the potential is floating, or ensuring that the data signal on the data auxiliary line FIAA is less affected by other jump signals when the potential is floating, ensuring good signal stability in the data auxiliary line FIAA, and further ensuring the stability of the signal in the data signal line DATA in the second display area AA2 connected thereto, and ensuring the normal display effect of the display panel.

[0078] In some embodiments, the fixed potential signal line can be one or more of the first power signal line, the anode reset signal line, the initialization reset signal line, and the bias adjustment signal line. Correspondingly, the fixed potential signal can be one or more of the first power signal, the anode reset signal, the initialization reset signal, and the bias adjustment signal.

[0079] The display panel provided by the embodiments of the present application can avoid the direct electrical connection between the data signal line in the second display area and the fan-out wire, can avoid the increase of the area of the fan-out area due to the setting of the fan-out wire, improves the area ratio of the display area, and improves the screen ratio of the display panel. The projection of the first coupling adjustment structure and the data auxiliary line on the plane of the substrate overlaps, that is, the first coupling adjustment structure and the data auxiliary line form a capacitor structure, and the first coupling adjustment structure is electrically connected with the fixed potential signal line. In this way, the signals in the first coupling adjustment structure and the data auxiliary line can remain stable, the interference of other changing signals on the signals in the data auxiliary line can be reduced, and the display effect of the second display area and the entire display area can be ensured to be stable. On the other hand, a stable capacitor structure can be formed between the data auxiliary line and the first coupling adjustment structure. In this way, the lateral capacitance formed between the data auxiliary line and other signal lines is small, the interference of other changing signals on the signals in the data auxiliary line can be reduced, the data signal potential of the signals in the data auxiliary line can be ensured to be stable, and the display effect of the second display area and the entire display area can be ensured to be stable.

[0080] In some embodiments, FIG. 4 is a structural schematic diagram of a demultiplexer provided by the embodiments of the present application. As shown in FIG. 4, the display panel further includes a plurality of demultiplexers DEMUX arranged in the non-display area and at least two switch control lines SW; the demultiplexer DEMUX includes at least two demultiplexing switches K, the demultiplexing switch K includes an input end, an output end and a control end; in the same demultiplexer DEMUX, the input ends of the at least two demultiplexing switches K are connected, the output ends of the at least two demultiplexing switches K are respectively electrically connected with different data signal lines DATA, and the control ends of the at least two demultiplexing switches K are respectively electrically connected with different switch control lines SW, and the data signal line DATA located in the second display area AA2 is electrically connected with the output end of the demultiplexing switch K through the data auxiliary line FIAA.

[0081] As shown in FIG. 4, the display panel further includes a plurality of demultiplexers DEMUX arranged in the non-display area NAA. The demultiplexer DEMUX can be understood as a combined logic circuit, which includes at least two demultiplexing switches K. In the same demultiplexer DEMUX, the input ends of the at least two demultiplexing switches K are connected and electrically connected with the same signal output terminal, and the output ends of the at least two demultiplexing switches K are respectively electrically connected with different data signal lines DATA. That is, the same demultiplexer DEMUX can time-divisionally distribute the input signals transmitted by the same signal output terminal to any one of the plurality of data signal lines DATA, so as to reduce the number of signal output terminals under the premise of realizing normal output of the data signal, and reduce the layout difficulty of the signal output terminals in the display panel.

[0082] For example, FIG. 4 illustrates an example in which the demultiplexing unit DEMUX includes two demultiplexing switches K1 and K2. Correspondingly, the display panel includes two switch control lines SW1 and SW2, the control end of the demultiplexing switch K1 is electrically connected to the switch control line SW1, the control end of the demultiplexing switch K2 is electrically connected to the switch control line SW2, and the switch control lines SW1 and SW2 transmit the enable signals of the demultiplexing switches in time division. When the enable signal is transmitted in the switch control line SW1, the demultiplexing switch K1 is turned on, and the demultiplexing switch K1 is configured to transmit the data signal input from the input end to the data signal line connected thereto through the data auxiliary line FIAA. At this time, the non-enable signal is transmitted in the switch control line SW2, the demultiplexing switch K2 is turned off, and the data auxiliary line FIAA connected to the demultiplexing switch K2 is in a floating state of the potential, and the signal on the data auxiliary line FIAA connected to the demultiplexing switch K2 is easily disturbed by other jumping signals. Similarly, when the enable signal is transmitted in the switch control line SW2, the demultiplexing switch K2 is turned on, and the demultiplexing switch K2 is configured to transmit the data signal input from the input end to the data signal line connected thereto through the data auxiliary line FIAA. At this time, the non-enable signal is transmitted in the switch control line SW1, the demultiplexing switch K1 is turned off, and the data auxiliary line FIAA connected to the demultiplexing switch K1 is in a floating state of the potential, and the signal on the data auxiliary line FIAA connected to the demultiplexing switch K1 is easily disturbed by other jumping signals. Therefore, the embodiment of the present application adds the first coupling adjustment structure 11, forms a capacitor structure between the first coupling adjustment structure 11 and the data auxiliary line FIAA, and transmits a fixed potential signal in the capacitor structure, so as to ensure that the potentials in the first coupling adjustment structure 11 and the data auxiliary line FIAA can be kept stable, ensure that the data signal on the data auxiliary line FIAA will not change due to the disturbance of other jumping signals even in the floating state of the potential, and ensure that the signal stability of the data auxiliary line FIAA is good.

[0083] The demultiplexing unit DEMUX shown in FIG. 4 can include a demultiplexing unit DEMUX connected to the data auxiliary line FIAA and a demultiplexing unit DEMUX connected to the data signal line DATA, and the distribution mode of the demultiplexing unit DEMUX connected to the data auxiliary line FIAA and the demultiplexing unit DEMUX connected to the data signal line DATA can be set according to actual needs.

[0084] In some embodiments, FIG. 5 is a schematic diagram of a cross-sectional structure of another display panel according to embodiments of the present application. Referring to FIGS. 2 and 5, the data auxiliary line FIAA includes a first wire segment FIAA1 and a second wire segment FIAA2 connected together, the first wire segment FIAA1 extends in the second direction and is electrically connected to the data signal line DATA of the second display area AA1, and the second wire segment FIAA2 extends in the first direction and is electrically connected to the fan-out wire FANOUT. The first coupling adjustment structure 11 includes at least one of a first coupling segment 111 and a second coupling segment 112. The first coupling segment 111 is located between the substrate 10 and the first wire segment FIAA1 and extends in the second direction. In the thickness direction of the display panel, the first coupling segment 111 overlaps the first wire segment FIAA1, and the first coupling segment 111 is electrically connected to the fixed potential signal line. The second coupling segment 112 is located between the substrate 10 and the second wire segment FIAA2 and extends in the first direction. In the thickness direction of the display panel, the second coupling segment 112 overlaps the second wire segment FIAA2, and the second coupling segment 112 is electrically connected to the fixed potential signal line.

[0085] For example, the data auxiliary line FIAA includes a first wire segment FIAA1 and a second wire segment FIAA2 connected together, the first wire segment FIAA1 extends in the second direction and is electrically connected to the data signal line DATA of the second display area AA1, and the second wire segment FIAA2 extends in the first direction and is electrically connected to the fan-out wire FANOUT. The first wire segment FIAA1 and the second wire segment FIAA2 can be arranged in the same layer or in different layers. FIG. 5 illustrates an example in which the first wire segment FIAA1 and the second wire segment FIAA2 are arranged in different layers and are electrically connected by a via. The first coupling adjustment structure 11 can include a first coupling segment 111 that is coupled to the first wire segment FIAA1 to form a capacitor structure. The first coupling segment 111 is electrically connected to the fixed potential signal line. In this way, a stable capacitor structure is formed between the first coupling segment 111 and the first wire segment FIAA1, and the potentials in the first coupling segment 111 and the first wire segment FIAA1 can be kept stable. This ensures that the data signal on the first wire segment FIAA1 does not change due to interference from other jump signals even if the potential of the first wire segment FIAA1 is floating, and ensures good signal stability in the first wire segment FIAA1.

[0086] In some embodiments, the first coupling adjustment structure 11 can also include a second coupling sub-portion 112 coupled with the second trace sub-portion FIAA2 to form a capacitive structure, the second coupling sub-portion 112 being electrically connected with a fixed potential signal line, so that a stable capacitive structure is formed between the second coupling sub-portion 112 and the second trace sub-portion FIAA2, and the potentials in the second coupling sub-portion 112 and the second trace sub-portion FIAA2 can be kept stable, ensuring that the data signal on the second trace sub-portion FIAA2 will not change due to interference from other jump signals even if the potential of the second trace sub-portion FIAA2 is floating, and ensuring good signal stability in the second trace sub-portion FIAA2.

[0087] In actual processes, the first coupling adjustment structure 11 can include at least one of the first coupling sub-portion 111 and the second coupling sub-portion 112 according to actual needs and wiring space. By setting the first coupling adjustment structure 11 to include at least one of the first coupling sub-portion 111 and the second coupling sub-portion 112, at least part of the data auxiliary line FIAA is formed with the first coupling adjustment structure 11 to form a stable capacitive structure, ensuring that the signal potential in the data auxiliary line FIAA is stable and is not disturbed by other jump signals.

[0088] In some embodiments, when the first coupling adjustment structure 11 includes the first coupling sub-portion 111 and the second coupling sub-portion 112, the first coupling sub-portion 111 and the second coupling sub-portion 112 can be arranged in the same layer or in different layers. When the first coupling sub-portion 111 and the second coupling sub-portion 112 are arranged in the same layer, the first coupling sub-portion 111 and the second coupling sub-portion 112 can be connected to form an integrated structure, to ensure that the capacitive structure between the first coupling adjustment structure 11 and the data auxiliary line FIAA is stable in performance.

[0089] FIG. 6 is a circuit connection schematic diagram of a pixel circuit according to an embodiment of the present application, FIG. 7 is a timing diagram of an embodiment of signals provided to the pixel circuit shown in FIG. 6 in a driving period according to an embodiment of the present application, FIG. 8 is a circuit connection schematic diagram of another pixel circuit according to an embodiment of the present application, and FIG. 9 is a timing diagram of an embodiment of signals provided to the pixel circuit shown in FIG. 8 in a driving period according to an embodiment of the present application. As shown in FIGS. 1 and 6-9, the display panel further includes a pixel circuit 20, the pixel circuit 20 including at least one first type transistor including a first active layer POLY, the first coupling sub-portion 111 including a first sub-coupling sub-portion 1111, the first sub-coupling sub-portion 1111 being located in a film layer between a film layer in which the substrate 10 is located and a film layer in which the first active layer POLY is located.

[0090] For example, referring to FIG. 6, the pixel circuit can include a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7, and a storage capacitor Cst. For example, referring to the pixel circuit shown in FIG. 6, the working process of the pixel circuit can include the following: the scan signal line (shown as S1 in the figure) connected to the control end of the initialization reset transistor T5 can control the on and off of the initialization reset transistor T5, and when the initialization reset transistor T5 is turned on, the reset signal in the reset signal line (shown as VREF1 in the figure) connected to the input end of the initialization reset transistor T5 is written to the gate of the driving transistor T3, and the first node N1 is reset. The storage capacitor Cst can ensure that the potential of the first node N1 is stable. The scan signal line (shown as S2 in the figure) connected to the control end of the threshold compensation transistor T4 can control the on and off of the threshold compensation transistor T4, and when the threshold compensation transistor T4 is turned on, the threshold voltage compensation of the driving transistor T3 is performed. The scan signal line (shown as S2 in the figure) connected to the control end of the data writing transistor T2 can control the on and off of the data writing transistor T2, and when the data writing transistor T2 is turned on, the data signal on the data signal line DATA is written to the first electrode of the driving transistor T3. At the same time, the scan signal line (shown as S2 in the figure) connected to the control end of the anode reset transistor T7 can control the on and off of the anode reset transistor T7, and when the anode reset transistor T7 is turned on, the anode of the light-emitting element 30 connected to the pixel circuit is reset, that is, the reset signal on the reset signal line (shown as VREF2 in the figure) is written to the anode of the light-emitting element 30. The light-emitting control signal line EMIT connected to the control end of the first light-emitting control transistor T1 and the control end of the second light-emitting control transistor T6 can control the on and off of the control end of the first light-emitting control transistor T1 and the second light-emitting control transistor T6, and when the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned on, the power signal transmitted by the power signal line PVDD is written to the light-emitting element 3, thereby realizing the display and light emission of the light-emitting element 30. For example, referring to FIG. 7, one frame of picture time Y of the display panel at least includes an initialization writing stage Y1, a data writing stage Y2, and a light-emitting stage Y3. In the initialization stage Y1, the initialization reset transistor T5 is turned on under the control of the scan signal S1, and the initialization signal VREF1 is written to the first node N1 electrically connected to the gate of the driving transistor T3, so as to initialize the gate of the driving transistor T3. In the data writing stage Y2, the data writing transistor T2 and the threshold compensation transistor T4 are turned on under the control of the scan signal S2, so that the data signal Vdata is sequentially written to the gate of the driving transistor T3 through the data writing transistor T2, the driving transistor T3, and the threshold compensation transistor T4.Meanwhile, in the data writing stage Y2, the anode reset transistor T7 is turned on under the control of the scanning signal S2, and the reset signal Vref2 is written into the anode of the light emitting element 30 to initialize the anode of the light emitting element 30. In the light emitting stage Y3, the first light emitting transistor T1 and the second light emitting control transistor T6 are turned on under the control of the light emitting control signal Emit, so that the driving transistor T3 generates a driving current capable of being transmitted to the anode of the light emitting element 30, and the light emitting element 30 is driven to emit light.

[0091] In some embodiments, referring to FIG. 8, the pixel circuit can include a first light emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light emitting control transistor T6, an anode reset transistor T7, a bias transistor T8, and a storage capacitor Cst. The working process of the pixel circuit is similar to the above process. In the pixel circuit of FIG. 8, the scanning signal line (shown as SP in the figure) connected to the control end of the bias transistor T8 can control the turn-on and turn-off of the bias transistor T8, and when the bias transistor T8 is turned on, the bias signal transmitted by the reset signal line (shown as DVH in the figure) is written into the bias transistor T8, and the second node N2 is biased and adjusted.

[0092] For example, referring to FIG. 9, in one driving period Y of the pixel circuit, the driving period Y includes a data writing stage Y1, a light emitting stage Y2, and a light emitting maintaining stage Y3. The data writing stage Y1 includes a non-enabling stage of the light emitting control signal Emit, the light emitting stage Y2 includes an enabling stage of the light emitting control signal Emit, and the light emitting maintaining stage Y3 includes a plurality of non-enabling stages and at least one enabling stage (one enabling stage is shown in FIG. 9 as an example). The level of the bias voltage signal line DVH in the data writing stage Y1 and the light emitting stage Y2 can be the same as or different from the level of the bias voltage signal line DVH in the light emitting maintaining stage Y3 (shown in FIG. 9 as an example). In the data writing stage Y1, a first bias adjusting stage Y11 is included. In the first bias adjusting stage Y11, the signal transmitted by the scan signal line SP includes at least one low voltage period, and the signal transmitted by the scan signal line S2N includes at least one high voltage period. In other words, in the first bias adjusting stage Y11, at least the bias transistor T8 and the threshold compensation transistor T4 are turned on, the bias signal of the bias voltage signal line DVH is transmitted to the driving transistor T3 through the bias transistor T8, and is further transmitted to the gate of the driving transistor T3 through the threshold compensation transistor T4. In other words, in the first bias adjusting stage Y11, the bias signal can be used to adjust the first node N1, the second node N2, and the third node N3. The data writing stage Y1 further includes an initialization and second bias adjusting stage Y12. In the initialization and second bias adjusting stage Y12, the signal transmitted by the scan signal line S2N includes at least one high voltage period, and the signal transmitted by the scan signal line S1N includes at least one high voltage period. In other words, in the initialization and second bias adjusting stage Y12, the initialization transistor T5 is turned on, and the threshold compensation transistor T4 is also turned on later. The initialization signal line VREF1 can be used to adjust the gate of the driving transistor T3 through the initialization transistor T5, and can be used to adjust the third node N3 through the initialization transistor T5 and the threshold compensation transistor T4. The data writing stage Y1 further includes a data signal writing stage Y13. In the data signal writing stage Y13, the signal transmitted by the scan signal line S2N includes a high voltage period, and the signal transmitted by the scan signal line SP* includes at least one low voltage period. In other words, in the data signal writing stage Y13, the data writing transistor T2 and the threshold compensation transistor T4 are turned on, and the data signal Vdata can be transmitted to the gate of the driving transistor T3 through the data writing transistor T2 and the threshold compensation transistor T4.The data writing stage Y1 further comprises a third bias adjusting stage Y14, in which the signal transmitted by the scan signal line SP comprises at least one low level period, and the second node N2 can be further biased by the bias transistor T8 during the period.

[0093] The types of the transistors in the pixel circuit can be diverse, and the pixel circuit can comprise first type transistors comprising a first active layer POLY. For example, the first type transistors can be low temperature poly-silicon (LTPS) transistors, which have high switching speed, high carrier mobility and low power consumption, etc. For example, as shown in FIGS. 6 and 8, the transistors in FIG. 6 are all first type transistors, i.e., the first light emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the threshold compensation transistor T4, the initialization reset transistor T5, the second light emitting control transistor T6 and the anode reset transistor T7 are all LTPS transistors. In FIG. 8, some of the transistors are first type transistors, i.e., the first light emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the second light emitting control transistor T6, the anode reset transistor T7 and the bias transistor T8 are all first type transistors. The threshold compensation transistor T4 and the initialization reset transistor T5 in FIG. 8 can be second type transistors, which can be Indium Gallium Zinc Oxide (IGZO) transistors, which have low leakage current, etc.

[0094] In some embodiments, the first coupling sub-portion 111 comprises a first sub-coupling portion 1111, and the film layer in which the first sub-coupling portion 1111 is located is between the film layer in which the substrate 10 is located and the film layer in which the first active layer POLY is located, i.e., the first sub-coupling portion 1111 is located in a film layer closer to the substrate 10 in the display panel. In the thickness direction of the display panel, the distance between the film layer in which the first sub-coupling portion 1111 is located and the first wiring portion FIAA1 is large, so that the first sub-coupling portion 1111 has little influence on the first wiring portion FIAA1 in the case that a coupling capacitor can be formed between the first sub-coupling portion 1111 and the first wiring portion FIAA1, and the first sub-coupling portion 1111 will not affect the size of the data signal in the first wiring portion FIAA1 when the data signal is normally transmitted in the first wiring portion FIAA1.

[0095] In some embodiments, the display panel further comprises a light shielding structure 12, a film layer where the light shielding structure 12 is located is between a film layer where the substrate 10 is located and a film layer where the first active layer POLY is located; the light shielding structure 12 comprises a plurality of light shielding subparts 121, along a thickness direction of the display panel, the light shielding subparts 121 overlap with channel regions in the first active layer POLY; the first sub-coupling part 1111 is arranged in the same layer as the light shielding structure 12.

[0096] Exemplarily, the display panel is overlapped by multiple film layers, FIG. 10 is a schematic diagram of a film layer structure of a display panel according to an embodiment of the present application, referring to FIG. 10, the film layer structure of the pixel circuit can be, from the bottom to the light-out side of the display panel, substrate 10, first buffer layer 201, zeroth metal layer 202 (M0), second buffer layer 203, first semiconductor layer 204, first insulating layer 205, first metal layer 206 (M1), interlayer insulating layer 207, second metal layer 208 (MC), second insulating layer 209, third metal layer 210 (M2), first planarization layer 211, fifth metal layer 212 (M3), second planarization layer 213, and anode layer 214 (RE). FIG. 11 is a schematic diagram of the structure of the zeroth metal layer in the display panel of FIG. 10, FIG. 12 is a schematic diagram of the structure of the first semiconductor layer in the display panel of FIG. 10, FIG. 13 is a schematic diagram of the structure of the first metal layer in the display panel of FIG. 10, FIG. 14 is a schematic diagram of the structure of the second metal layer in the display panel of FIG. 10, FIG. 15 is a schematic diagram of the structure of the third metal layer in the display panel of FIG. 10, FIG. 16 is a schematic diagram of the stack structure of part of the film layers in the display panel of FIG. 10, such as the stack structure from the zeroth metal layer to the third metal layer, FIG. 17 is a schematic diagram of the structure of the fifth metal layer in the display panel of FIG. 10, FIG. 18 is a schematic diagram of the structure of the anode layer in the display panel of FIG. 10, FIG. 19 is a schematic diagram of the stack structure of part of the film layers in the display panel of FIG. 10, such as the stack structure from the fifth metal layer to the anode layer, and FIG. 20 is a schematic diagram of the stack structure of all the film layers in the display panel of FIG. 10, such as the stack structure from the zeroth metal layer to the anode layer. In combination with FIGS. 10-20, the film layer structure described in FIGS. 10-20 can correspond to the case that the pixel circuit includes a first type transistor. Among them, the first active layer POLY can be located in the first semiconductor layer 204; the film layer where the light shielding structure 12 is located is between the film layer where the substrate 10 is located and the film layer where the first active layer POLY is located, which can be located in the zeroth metal layer 202; the film layer where the first sub-coupling structure 1111 is located is between the film layer where the substrate 10 is located and the film layer where the first active layer POLY is located, which can be located in the zeroth metal layer 202; the gate of the first type transistor can be located in the first metal layer 206, the two capacitor plates of the storage capacitor can be located in the first metal layer 206 and the second metal layer 208 respectively, the first wiring part FIAA1 can be located in the third metal layer 209, and the second wiring part FIAA2 can be located in the fifth metal layer 210.

[0097] In some embodiments, FIG. 21 is a schematic diagram of a film layer structure of another display panel according to embodiments of the present application. Referring to FIG. 11, the film layer structure of the pixel circuit can be, from bottom to the light exit side of the display panel, substrate 10, first buffer layer 201, zeroth metal layer 202, second buffer layer 203, first semiconductor layer 204, first insulating layer 205, first metal layer 206, interlayer insulating layer 207, second metal layer 208, second insulating layer 209, second semiconductor layer 215 (IGZO), third insulating layer 216, fourth metal layer 217 (MG), fifth insulating layer 218, third metal layer 210 (M3), first planarization layer 211, fifth metal layer 212 (M3), second planarization layer 213, and anode layer 214. FIG. 22 is a schematic diagram of a structure of a zeroth metal layer in the display panel of FIG. 21, FIG. 23 is a schematic diagram of a structure of a first semiconductor layer in the display panel of FIG. 21, FIG. 24 is a schematic diagram of a structure of a first metal layer in the display panel of FIG. 21, FIG. 25 is a schematic diagram of a structure of a second metal layer in the display panel of FIG. 21, FIG. 26 is a schematic diagram of a structure of a second semiconductor layer in the display panel of FIG. 21, FIG. 27 is a schematic diagram of a structure of a fourth metal layer in the display panel of FIG. 21, FIG. 28 is a schematic diagram of a structure of a third metal layer in the display panel of FIG. 21, FIG. 29 is a schematic diagram of a stack structure of a portion of the film layers in the display panel of FIG. 21, such as a schematic diagram of a stack structure from the zeroth metal layer to the third metal layer, FIG. 30 is a schematic diagram of a structure of a fifth metal layer in the display panel of FIG. 21, FIG. 31 is a schematic diagram of a structure of an anode layer in the display panel of FIG. 21, FIG. 32 is a schematic diagram of a stack structure of a portion of the film layers in the display panel of FIG. 21, such as a schematic diagram of a stack structure from the fifth metal layer to the anode layer, and FIG. 33 is a schematic diagram of a stack structure of all the film layers in the display panel of FIG. 21, such as a schematic diagram of a stack structure from the zeroth metal layer to the anode layer.FIG. 34 is a structure diagram of another type of the zeroth metal layer in the display panel of FIG. 21, FIG. 35 is a structure diagram of another type of the first semiconductor layer in the display panel of FIG. 21, FIG. 36 is a structure diagram of another type of the first metal layer in the display panel of FIG. 21, FIG. 37 is a structure diagram of another type of the second metal layer in the display panel of FIG. 21, FIG. 38 is a structure diagram of another type of the second semiconductor layer in the display panel of FIG. 21, FIG. 39 is a structure diagram of another type of the fourth metal layer in the display panel of FIG. 21, FIG. 40 is a structure diagram of another type of the third metal layer in the display panel of FIG. 21, FIG. 41 is a structure diagram of another type of the partial layer stack in the display panel of FIG. 21, such as a structure diagram of the layer stack from the zeroth metal layer to the third metal layer, FIG. 42 is a structure diagram of another type of the fifth metal layer in the display panel of FIG. 21, FIG. 43 is a structure diagram of another type of the anode layer in the display panel of FIG. 21, FIG. 44 is a structure diagram of another type of the partial layer stack in the display panel of FIG. 21, such as a structure diagram of the layer stack from the fifth metal layer to the anode layer, and FIG. 45 is a structure diagram of another type of the entire layer stack in the display panel of FIG. 21, such as a structure diagram of the layer stack from the zeroth metal layer to the anode layer. FIG. 46 is a structure diagram of another type of the zeroth metal layer in the display panel of FIG. 21, FIG. 47 is a structure diagram of another type of the first semiconductor layer in the display panel of FIG. 21, FIG. 48 is a structure diagram of another type of the first metal layer in the display panel of FIG. 21, FIG. 49 is a structure diagram of another type of the second metal layer in the display panel of FIG. 21, FIG. 50 is a structure diagram of another type of the second semiconductor layer in the display panel of FIG. 21, FIG. 51 is a structure diagram of another type of the fourth metal layer in the display panel of FIG. 21, FIG. 52 is a structure diagram of another type of the third metal layer in the display panel of FIG. 21, FIG. 53 is a structure diagram of another type of the partial layer stack in the display panel of FIG. 21, such as a structure diagram of the layer stack from the zeroth metal layer to the third metal layer, FIG. 54 is a structure diagram of another type of the fifth metal layer in the display panel of FIG. 21, FIG. 55 is a structure diagram of another type of the anode layer in the display panel of FIG. 21, FIG. 56 is a structure diagram of another type of the partial layer stack in the display panel of FIG. 21, such as a structure diagram of the layer stack from the fifth metal layer to the anode layer, and FIG. 57 is a structure diagram of another type of the entire layer stack in the display panel of FIG. 21, such as a structure diagram of the layer stack from the zeroth metal layer to the anode layer. In combination with FIGS. 21-57, the layer structures of FIGS. 21-57 can correspond to a case where the pixel circuit includes a first type of transistor and a second type of transistor.The first active layer POLY can be located in the first semiconductor layer 204; the light-shielding structure 12 is located between the substrate 10 and the first active layer POLY, and can be located in the zeroth metal layer 202; the first sub-coupling structure 1111 is located between the substrate 10 and the first active layer POLY, and can be located in the zeroth metal layer 202; the gate of the first type transistor can be located in the first metal layer 206, the two capacitor plates of the storage capacitor can be located in the first metal layer 206 and the second metal layer 208 respectively, the active layer of the second type transistor can be located in the second semiconductor layer 213, the top gate of the second type transistor can be located in the fourth metal layer 215, the first wiring part FIAA1 can be located in the third metal layer 209, and the second wiring part FIAA2 can be located in the fifth metal layer 210. For the film layer structure of the pixel circuit, adaptive adjustments such as adding or removing part of the film layer can be made according to actual needs, and any one of the above film layers can contain at least one sub-layer.

[0098] For example, because the channel region of the first active layer POLY will generate a light leakage current under the irradiation of external environmental light, thereby affecting the conduction performance of the first type transistor, the light-shielding structure 12 can be arranged between the substrate 10 and the first active layer POLY, and the light-shielding structure 12 includes a plurality of light-shielding parts 121, which overlap the channel region in the first active layer along the thickness direction of the display panel. In this way, the channel region of the first active layer POLY can be shielded by the light-shielding part 121 to prevent the channel region of the first active layer POLY from being disturbed by external environmental light. It should be noted that the light-shielding structure 12 can only shield the channel region of part of the transistors in the aforementioned pixel circuit, or can shield the channel region of all the transistors in the aforementioned pixel circuit.

[0099] The first sub-coupling part 1111 is arranged in the same layer as the light-shielding structure 12, for example, both are located in the zeroth metal layer 202. In this way, on the one hand, a coupling capacitor can be formed between the first sub-coupling part 1111 and the first wiring part FIAA1 to prevent the first wiring part FIAA1 from being disturbed by other jump signals when it is in a potential floating state. On the other hand, the arrangement of the first sub-coupling part 1111 does not increase the film layer structure of the display panel, which is conducive to the thinness of the display panel. On the other hand, the first sub-coupling part 1111 is arranged in the same layer as the light-shielding structure 12 and can be prepared in the same mask process. The arrangement of the first sub-coupling part 1111 does not increase the process difficulty of the display panel, and ensures that the process of the display panel is simple.

[0100] The film layer in which the first sub-coupling section 1111 is located is between the film layer in which the substrate 10 is located and the film layer in which the first active layer POLY is located, that is, the first sub-coupling section 1111 is located in the zeroth metal layer M0. In the display panel, the zeroth metal layer M0 is the lowest metal layer, and various signal lines such as scan signal lines, data signal lines, or power signal lines are not usually formed in this metal layer. Therefore, the wiring space in the zeroth metal layer M0 is relatively sufficient, and the layout design is relatively simple, and the first sub-coupling section 1111 and other signal lines will not be short-circuited due to insufficient wiring space. Moreover, the first sub-coupling section 1111 and the first wiring section FIAA1 are arranged to overlap in the present application, which can avoid the influence of the coupling capacitance on the first wiring section FIAA1 and other jump signal lines on the transmission of the signal on the first wiring section FIAA1, which also means that the first sub-coupling section 1111 and the first wiring section FIAA1 will also have a capacitance. Although the first sub-coupling section 1111 and the first wiring section FIAA1 need to form a capacitance to play a shielding role, the capacitance should not be too large to avoid the adverse effects of the large capacitance on the signal on the first wiring section FIAA1. Therefore, the first sub-coupling section 1111 can be arranged in the lowest zeroth metal layer M0, so that the distance between the first sub-coupling section 1111 and the first wiring section FIAA1 is large, so that the capacitance formed between the first sub-coupling section 1111 and the first wiring section FIAA1 is small, avoiding the adverse effects of the large capacitance on the signal on the first wiring section FIAA1.

[0101] In some embodiments, continuing to refer to FIGS. 6-57, the display panel further includes a pixel circuit including a driving transistor T3 and at least one switching transistor; the light shielding structure 12 includes a first light shielding section 121a and a second light shielding section 121b, along the thickness direction of the display panel, the first light shielding section 121a overlaps the channel region of the first active layer of the driving transistor T3, and the second light shielding section 121b overlaps the channel region of the first active layer of at least part of the switching transistor; the first sub-coupling structure 1111 is connected to at least two second light shielding sections 121b arranged along the second direction.

[0102] Exemplarily, as shown in combination with FIG. 6 and FIG. 8, the pixel circuit includes a driving transistor and a switching transistor, the driving transistor can be understood as a transistor for converting a driving voltage signal into a driving current signal, in the pixel circuit shown in FIG. 6 and FIG. 8, the driving transistor is T3. The transistor in the pixel circuit other than the driving transistor can be understood as a switching transistor. Taking FIG. 6 as an example, the first light-emitting control transistor T1, the data writing transistor T2, the threshold compensation transistor T4, the initialization reset transistor T5, the second light-emitting control transistor T6 and the anode reset transistor T7 are all switching transistors. Taking FIG. 8 as an example, the first light-emitting control transistor T1, the data writing transistor T2, the threshold compensation transistor T4, the initialization reset transistor T5, the second light-emitting control transistor T6, the anode reset transistor T7 and the bias adjustment transistor T8 are all switching transistors.

[0103] In some embodiments, referring to FIG. 11, FIG. 12, FIG. 16, FIG. 22, FIG. 23, FIG. 29, FIG. 34, FIG. 35, FIG. 41, FIG. 46, FIG. 47 and FIG. 53, the light shielding structure 12 includes a first light shielding part 121a and a second light shielding part 121b. In the thickness direction of the display panel, the first light shielding part 121a overlaps the channel region of the first active layer of the driving transistor T3, and the second light shielding part 121b overlaps the channel region of the first active layer of at least part of the switching transistor. The second light shielding part 121b has various corresponding cases with the channel region of the first active layer of the switching transistor. For example, the pixel circuit shown in FIG. 11, FIG. 12 and FIG. 16 is described by taking the case that the second light shielding structure 121b overlaps the channel region of the first active layer of the initialization reset transistor T5; the pixel circuit shown in FIG. 22, FIG. 23 and FIG. 29 is described by taking the case that the second light shielding structure 121b overlaps the channel region of the first active layer of the anode reset transistor T7 and the bias adjustment transistor T8; the pixel circuit shown in FIG. 34, FIG. 35 and FIG. 41 is described by taking the case that the second light shielding structure 121b overlaps the channel region of the first active layer of the anode reset transistor T7 and the bias adjustment transistor T8; and the pixel circuit shown in FIG. 46, FIG. 47 and FIG. 53 is described by taking the case that the second light shielding structure 121b overlaps the channel region of the first active layer of the anode reset transistor T7 and the bias adjustment transistor T8. In actual design, the corresponding case of the second light shielding part 121b with the channel region of the first active layer of the switching transistor can be set according to requirements. In some embodiments, referring to FIG. 11, FIG. 22, FIG. 34 and FIG. 46, the first sub-coupling structure 1111 is connected to at least two second light shielding parts 121b arranged in the second direction, and FIG. 11, FIG. 22, FIG. 34 and FIG. 46 all take the example of the first sub-coupling structure 1111 connected to a row of multiple second light shielding parts 121b arranged in the second direction. Since the first sub-coupling structure 1111 is electrically connected to the fixed potential signal line, at least two second light shielding parts 121b arranged in the second direction are connected to the first sub-coupling structure 1111, so that at least two second light shielding parts 121b arranged in the second direction are also electrically connected to the fixed potential signal line, and the potential of the second light shielding part 121b and the entire light shielding structure is stable, which will not interfere with the potential in the first active layer shielded by the second light shielding part 121b, thereby ensuring the normal operation of the entire pixel circuit.

[0104] The above embodiments are described by taking the case that the first coupling part includes the first sub-coupling part. In some embodiments, the first coupling part can also include other sub-coupling parts with other settings, which are described below.

[0105] Exemplarily, referring to FIGS. 11-57, the display panel further includes a pixel circuit, the pixel circuit includes at least one first type transistor, the first type transistor includes a first active layer POLY; the first coupling part 111 includes a second sub-coupling part 1112, the second sub-coupling part 1112 is located between the film layer where the first active layer POLY is located and the film layer where the first wiring part FIAA1 is located.

[0106] In some embodiments, the first type transistor can be a low-temperature polysilicon transistor, the first active layer includes silicon, for example, can be low-temperature polysilicon. In some embodiments, the first coupling part 111 includes a second sub-coupling part 1112 located between the film layer where the first active layer POLY is located and the film layer where the first wiring part FIAA1 is located, the second sub-coupling part 1112 is electrically connected with a fixed potential, and overlaps the first wiring part FIAA1 in the thickness direction of the display panel. A stable coupling capacitor is formed between the second sub-coupling part 1112 and the first wiring part FIAA1, which ensures that the first wiring part FIAA1 is not disturbed by the jump signal when it is floating in potential, or is less disturbed, ensures the stability of the signal in the first wiring part FIAA1, and further ensures the stability of the signal in the data signal line connected thereto, and ensures the stability of the display effect of the entire display panel.

[0107] In addition, referring to FIGS. 16, 29, 41 and 53, the orthographic projection of the second sub-coupling part 1112 on the substrate is located between the orthographic projection of the first wiring part FIAA1 on the substrate and the orthographic projection of the at least one scanning signal line on the substrate. In this way, the second sub-coupling part 1112 can also avoid coupling between the first wiring part FIAA1 and the scanning signal line.

[0108] In some embodiments, referring to FIGS. 11-33, the pixel circuit further includes a storage capacitor Cst, the storage capacitor Cst includes a first plate Cst1 and a second plate Cst2 arranged oppositely, the second plate Cst2 is located on the side of the first plate Cst1 away from the first active layer POLY; the display panel further includes a first semiconductor layer 204, a first metal layer 206, a second metal layer 208 and a third metal layer 210 arranged in layers, the first active layer POLY is located in the first semiconductor layer 204, the first plate Cst1 is located in the first metal layer 206, the second plate Cst2 is located in the second metal layer 208; the first wiring part FIAA1 is located in the third metal layer 210; the second sub-coupling part 1112 is located in the second metal layer 208.

[0109] The active layer of the first type transistor can be located in the first semiconductor layer 204, the gate of the first type transistor and the first plate Cst1 of the storage capacitor Cst can be located in the first metal layer 206, that is, the M1 metal layer; the second plate Cst2 of the storage capacitor Cst can be located in the second metal layer 208, that is, the MC metal layer; the first trace part FIAA1 can be located in the third metal layer 210, that is, the M2 metal layer. As shown in FIGS. 14, 16, 25 and 29, the second sub-coupling part 1112 is arranged in the second metal layer 208, and the arrangement of the second sub-coupling part 1112 does not increase the film layer of the display panel, which is beneficial to the thin design of the display panel. Moreover, the second sub-coupling part 1112 is located in the second metal layer 208, which can correspond to the pixel circuit including only the first type transistor, as shown in FIGS. 14 and 16; or the pixel circuit including both the first type transistor and the second type transistor, as shown in FIGS. 25 and 29; the arrangement of the second sub-coupling part 1112 in the second metal layer 208 is suitable for various types of pixel circuits, and has a wide range of applications. The second sub-coupling part 1112 is arranged in the second metal layer 208, which is relatively close to the third metal layer 210 where the first trace part FIAA1 is located in the thickness direction of the display panel, so that the coupling effect between the second sub-coupling part 1112 and the first trace part FIAA1 is obvious, the coupling capacitor formed has strong stability, which is beneficial to the first trace part FIAA1 to be free from or less interfered by the jumping signal when floating in potential, and ensures the stability of the signal in the first trace part FIAA1.

[0110] In some embodiments, as shown in FIGS. 34-57, the pixel circuit further includes at least one second type transistor, the second type transistor including a second active layer IGZO and a top gate located on a side of the second active layer IGZO away from the first active layer POLY; the pixel circuit further includes a storage capacitor Cst including a first plate Cst1 and a second plate Cst2 arranged oppositely, the second plate Cst2 located on a side of the first plate Cst1 away from the first active layer POLY; the display panel further includes a first semiconductor layer 204, a first metal layer 206, a second metal layer 208, a second semiconductor layer 215, a fourth metal layer 217 and a third metal layer 210 arranged in layers; the first active layer POLY is located in the first semiconductor layer 204, the first plate Cst1 is located in the first metal layer 206, the second plate Cst2 is located in the second metal layer 208, the second active layer IGZO is located in the second semiconductor layer 215, the top gate is located in the fourth metal layer 217, and the first trace part FIAA1 is located in the third metal layer 210; the second sub-coupling part 1112 is located in at least one of the second metal layer 208 and the fourth metal layer 217.

[0111] The active layer of the first type transistor can be located in the first semiconductor layer 204, the gate of the first type transistor and the first plate Cst1 of the storage capacitor Cst can be located in the first metal layer 206, that is, the M1 metal layer; the second plate Cst2 of the storage capacitor Cst can be located in the second metal layer 208, that is, the MC metal layer; the active layer of the second type transistor can be located in the second semiconductor layer 215, and the top gate of the second type transistor can be located in the fourth metal layer 217, that is, the MG metal layer; and the first trace part FIAA1 can be located in the third metal layer 210, that is, the M2 metal layer. In some embodiments, as shown in FIGS. 39, 41, 49 and 53, the second sub-coupling part 1112 is arranged in at least one of the second metal layer 208 and the fourth metal layer 217. The arrangement of the second sub-coupling part 1112 does not increase the film layers of the display panel, which is conducive to the thinness of the display panel. It should be noted that, as an example, the second sub-coupling part 1112 is arranged in the fourth metal layer 217 in FIGS. 39 and 41, and the second sub-coupling part 1112 is arranged in the second metal layer 208 in FIGS. 49 and 53. The second sub-coupling part 1112 is arranged in at least one of the second metal layer 208 and the fourth metal layer 217, which is relatively close to the third metal layer 210 where the first trace part FIAA1 is located in the thickness direction of the display panel. Therefore, the coupling effect between the second sub-coupling part 1112 and the first trace part FIAA1 is obvious, the coupling capacitor formed thereby has strong stability, which is conducive to preventing the first trace part FIAA1 from being disturbed by the jumping signal when the first trace part FIAA1 is in a floating state, or the degree of disturbance is small, thereby ensuring the stability of the signal in the first trace part FIAA1.

[0112] In some embodiments, continuing to refer to FIGS. 6, 8 and 11-57, the pixel circuit includes a voltage adjustment transistor; the signal line further includes a voltage adjustment signal line, the voltage adjustment signal line being electrically connected to the first electrode of the voltage adjustment transistor; the voltage adjustment signal line includes a first voltage adjustment part, the first voltage adjustment part extending along the second direction, and at least part of the first voltage adjustment part being located between the film layer where the first active layer POLY is located and the film layer where the first trace part FIAA1 is located; and the second sub-coupling part 1112 is multiplexed as at least part of the first voltage adjustment part.

[0113] For example, referring to FIGS. 6 and 8, the pixel circuit includes a voltage adjustment transistor, the signal line further includes a voltage adjustment signal line, the voltage adjustment signal line is electrically connected with the first electrode (i.e., the input end) of the voltage adjustment transistor, so that the voltage adjustment signal is input into the pixel circuit through the voltage adjustment transistor to the position requiring voltage adjustment, such as the gate of the driving transistor, at least one of the first electrode and the second electrode of the driving transistor, the anode of the light emitting element, and the like. For example, the voltage adjustment transistor can include the initialization reset transistor T5 and the anode reset transistor T7 as shown in FIG. 6, and include the initialization reset transistor T5, the anode reset transistor T7, and the bias adjustment transistor T8 as shown in FIG. 8; that is, the voltage adjustment transistor includes one or more of the initialization reset transistor T5, the anode reset transistor T7, and the bias adjustment transistor T8. The voltage adjustment signal line is a signal line for transmitting a fixed potential signal, and outputs the fixed potential signal, such as the initialization reset signal, the bias adjustment signal, and the anode reset signal, to the first electrode (i.e., the input end) of the voltage adjustment transistor. Correspondingly, the voltage adjustment signal line can include the initialization reset signal line, the anode reset signal line, and the bias adjustment signal line. Moreover, the voltage adjustment signal line can include a first voltage adjustment sub-portion extending along the second direction and located between the film layer where the first active layer POLY is located and the film layer where the first trace sub-portion FIAA1 is located, so that the second sub-coupling sub-portion 1112 can be multiplexed as at least part of the first voltage adjustment sub-portion, and the structure of the display panel is ensured to be simple.

[0114] In some embodiments, continuing to refer to FIGS. 6, 8, and 11-57, the voltage adjustment transistor includes the initialization reset transistor T5 and the anode reset transistor T7; the voltage adjustment signal line includes the initialization reset signal line VREF1 and the anode reset signal line VREF2; the pixel circuit further includes the driving transistor T3, and the display panel further includes the light emitting element 30; the initialization reset transistor T5 is electrically connected between the initialization reset signal line VREF1 and the gate of the driving transistor T3; the anode reset transistor T7 is electrically connected between the anode reset signal line VREF2 and the light emitting element 30; the initialization reset signal line VREF1 includes a plurality of first initialization reset lines VREF11 arranged along the first direction and extending along the second direction, and the first voltage adjustment sub-portion includes the first initialization reset lines VREF11; the second sub-coupling sub-portion 1112 is multiplexed as the first initialization reset lines VREF11; and / or, the anode reset signal line VREF2 includes a plurality of first anode reset lines VREF21 arranged along the first direction and extending along the second direction, and the first voltage adjustment sub-portion includes the first anode reset lines VREF21; the second sub-coupling sub-portion 1112 is multiplexed as the first anode reset lines VREF21.

[0115] The voltage regulating transistor comprises an initialization reset transistor T5 and an anode reset transistor T7. The initialization reset transistor T5 is configured to transmit an initialization reset signal provided by an initialization reset signal line VREF1 to the gate of the driving transistor T3 when the initialization reset transistor T5 is turned on, so as to reset the first node N1. The anode reset transistor T7 is configured to transmit an anode reset signal provided by an anode reset signal line VREF2 to the anode of the light emitting element when the anode reset transistor T7 is turned on, so as to reset the anode of the light emitting element and avoid the influence of the display signal of the previous frame on the display effect of the current frame.

[0116] The initialization reset signal line VREF1 comprises a first initialization reset line VREF11. A plurality of first initialization reset lines VREF11 are arranged along a first direction and extend along a second direction. The first initialization reset line VREF11 is electrically connected with a plurality of initialization reset transistors T5 arranged in the same row, and is configured to provide an initialization reset signal for the plurality of initialization reset transistors T5 arranged in the same row. Since the initialization reset signal is a fixed potential signal and the second sub-coupling part 1112 also extends along the second direction, as shown in FIGS. 14 and 16, the second sub-coupling part 1112 can be multiplexed as the first initialization reset line VREF11. In this way, the second sub-coupling part 1112 and the first initialization reset line VREF11 are the same structure, which can form a stable capacitive structure with the first wiring part FIAA1, so as to prevent the first wiring part FIAA1 from being disturbed by other jump signals when the potential of the first wiring part FIAA1 is floating, and can also provide the initialization reset signal for the initialization reset transistor T5, so as to realize a simple and efficient wiring scheme in the display panel. The anode reset signal line VREF2 comprises a first anode reset line VREF21. A plurality of first anode reset lines VREF21 are arranged along a first direction and extend along a second direction. The first anode reset line VREF21 is electrically connected with a plurality of anode reset transistors T7 arranged in the same row, and is configured to provide an anode reset signal for the plurality of anode reset transistors T7 arranged in the same row. Since the anode reset signal is a fixed potential signal and the second sub-coupling part 1112 also extends along the second direction, as shown in FIGS. 25 and 29, FIGS. 39 and 41, and FIGS. 51 and 53, the second sub-coupling part 1112 can be multiplexed as the first anode reset line VREF21. In this way, the second sub-coupling part 1112 and the first anode reset line VREF21 are the same structure, which can form a stable capacitive structure with the first wiring part FIAA1, so as to prevent the first wiring part FIAA1 from being disturbed by other jump signals when the potential of the first wiring part FIAA1 is floating, and can also provide the anode reset signal for the anode reset transistor T7, so as to realize a simple and efficient wiring scheme in the display panel.

[0117] In some embodiments, continuing to refer to FIGS. 14 and 16, the second sub-coupling sections 1112 are multiplexed as the first initialization reset lines VREF11 and the first anode reset lines VREF21; along the first direction, the first initialization reset lines VREF11 and the first anode reset lines VREF21 are arranged alternately.

[0118] For example, the initialization reset signal lines VREF1 include the first initialization reset lines VREF11, the anode reset signal lines VREF2 include the first anode reset lines VREF21, and among two second sub-coupling sections 1112 arranged adjacently along the first direction, one of the second sub-coupling sections 1112 is multiplexed as the first initialization reset lines VREF11, and the other of the second sub-coupling sections 1112 is multiplexed as the first anode reset lines VREF21. In this way, the first initialization reset lines VREF11 and the first anode reset lines VREF21 are uniformly distributed in the entire display area, and the initialization reset signal and the anode reset signal can be transmitted well in the entire display area.

[0119] In some embodiments, continuing to refer to FIGS. 6, 8, and 11-57, the voltage adjustment signal lines include second voltage adjustment sections, the second voltage adjustment sections extend along the first direction, and the second voltage adjustment sections are arranged in different layers from the first voltage adjustment sections and are electrically connected.

[0120] The voltage adjustment signal lines include first voltage adjustment sections extending along the second direction. In some embodiments, the voltage adjustment signal lines can further include second voltage adjustment sections extending along the first direction, and the second voltage adjustment sections are arranged in different layers from the first voltage adjustment sections and are electrically connected, so that the first voltage adjustment sections and the second voltage adjustment sections form a grid-shaped voltage adjustment signal line, so that the voltage adjustment signal line is uniformly distributed in the entire display area, and the voltage adjustment transistors at different positions can be connected to the voltage adjustment signal line, so as to ensure good voltage adjustment effect. In some embodiments, the second voltage adjustment sections are arranged in different layers from the first voltage adjustment sections and are electrically connected, and the second voltage adjustment sections are arranged in parallel with the first voltage adjustment sections, which is beneficial to reduce the resistance of the voltage adjustment signal line, reduce the signal attenuation of the voltage adjustment signal caused by impedance in the transmission process, and ensure the accuracy of the voltage adjustment signal.

[0121] In some embodiments, referring to FIG. 15 and FIG. 17, the initialization reset signal line VREF1 includes second initialization reset lines VREF12, the second initialization reset lines VREF12 extend along a first direction and are arranged along a second direction, the second voltage adjustment sub-portion can include the second initialization reset lines VREF12, the second initialization reset lines VREF12 extending along the first direction and the first initialization reset lines VREF11 extending along the second direction form a grid structure of the initialization reset signal line VREF1, ensuring that the initialization reset signal line VREF1 is evenly distributed throughout the display area, and the resistance in the initialization reset signal line VREF1 can be reduced, ensuring that the initialization reset signal is accurate.

[0122] In some embodiments, referring to FIG. 17, FIG. 30, FIG. 42 and FIG. 54, the anode reset signal line VREF2 includes second anode reset lines VREF22, the second anode reset lines VREF22 extend along a first direction and are arranged along a second direction, the second voltage adjustment sub-portion can include the second anode reset lines VREF22, the second anode reset lines VREF22 extending along the first direction and the first anode reset lines VREF21 extending along the second direction form a grid structure of the anode reset signal line VREF2, ensuring that the anode reset signal line VREF2 is evenly distributed throughout the display area, and the resistance in the anode reset signal line VREF2 can be reduced, ensuring that the anode reset signal is accurate.

[0123] In some embodiments, referring to FIG. 30, FIG. 42 and FIG. 54, the bias adjustment signal line DVH includes second bias adjustment lines DVH2, the second bias adjustment lines DVH2 extend along a first direction and are arranged along a second direction, the second voltage adjustment sub-portion can include the second bias adjustment lines DVH2, the second bias adjustment lines DVH2 extending along the first direction and the first bias adjustment lines DVH1 extending along the second direction form a grid structure of the bias adjustment signal line DVH, ensuring that the bias adjustment signal line DVH is evenly distributed throughout the display area, and the resistance in the bias adjustment signal line DVH can be reduced, ensuring that the bias adjustment signal is accurate.

[0124] In some embodiments, when the second voltage adjustment part comprises at least two of the second initialization reset line VREF12, the second anode reset signal line VREF22 and the second bias adjustment line DVH2, the two different signal lines can be arranged alternately in the second direction. Referring to FIG. 17, when the second voltage adjustment part comprises the second initialization reset line VREF12 and the second anode reset signal line VREF22, the second initialization reset line VREF12 and the second anode reset signal line VREF22 are arranged alternately in the second direction, ensuring that the second initialization reset line VREF12 and the second anode reset signal line VREF22 are evenly distributed in the entire display area. Referring to FIG. 30, FIG. 42 and FIG. 54, when the second voltage adjustment part comprises the second anode reset signal line VREF22 and the second bias adjustment line DVH2, the second anode reset signal line VREF22 and the second bias adjustment line DVH2 are arranged alternately in the second direction, ensuring that the second anode reset signal line VREF22 and the second bias adjustment line DVH2 are evenly distributed in the entire display area. When the second voltage adjustment part comprises the second initialization reset line VREF12, the second anode reset signal line VREF22 and the second bias adjustment line DVH2, the second initialization reset line VREF12, the second anode reset signal line VREF22 and the second bias adjustment line DVH2 can have multiple feasible arrangements in the second direction, such as the second initialization reset line VREF12-the second anode reset signal line VREF22-the second bias adjustment line DVH-the second initialization reset line VREF12-the second anode reset signal line VREF22-the second bias adjustment line DVH, or the second initialization reset line VREF12-the second bias adjustment line DVH-the second anode reset signal line VREF22-the second initialization reset line VREF12-the second bias adjustment line DVH-the second anode reset signal line VREF22, or the second anode reset signal line VREF22-the second bias adjustment line DVH-the second initialization reset line VREF12-the second anode reset signal line VREF22-the second bias adjustment line DVH-the second initialization reset line VREF12. The arrangement of the second initialization reset line VREF12, the second anode reset signal line VREF22 and the second bias adjustment line DVH2 in the embodiments of the present application can be set according to actual needs, as long as the second initialization reset line VREF12, the second anode reset signal line VREF22 and the second bias adjustment line DVH2 can be evenly distributed in the display area.

[0125] In some embodiments, continuing to refer to FIGS. 30, 42 and 54, the signal lines further include a plurality of first power signal lines PVDD extending in the first direction and arranged in the second direction, and between any two adjacent first power signal lines PVDD, a second voltage adjustment section, a second trace section FIAA2 and two data signal lines DATA are arranged; the second voltage adjustment section and the second trace section FIAA2 are arranged between the two data signal lines DATA, or the two data signal lines DATA are arranged between the second voltage adjustment section and the second trace section FIAA2.

[0126] As shown in FIGS. 30, 42 and 54, the signal lines further include a plurality of first power signal lines PVDD serving as positive power signal lines and arranged to provide positive power signals for the pixel circuits. In order to ensure that the positive power signals have small loss during transmission, the line width of the first power signal lines PVDD is generally large. In some embodiments, the first power signal lines PVDD, the data signal lines DATA, the second trace section FIAA2 and the second voltage adjustment section are all signal lines extending in the first direction and can be arranged in the same layer, for example, in the metal layer closest to the anode side. Moreover, between any two adjacent first power signal lines PVDD, a second voltage adjustment section, a second trace section FIAA2 and two data signal lines DATA are arranged, wherein the second voltage adjustment section can be one of the second initialization reset line VREF12, the second anode reset signal line VREF22 and the second bias adjustment line DVH2. As shown in FIGS. 30, 42 and 54, there are two adjacent first power signal lines PVDD between which two data signal lines DATA, a second trace section FIAA2 and a second anode reset signal line VREF22 are arranged; there are two adjacent first power signal lines PVDD between which two data signal lines DATA, a second trace section FIAA2 and a second bias adjustment line DVH2 are arranged.

[0127] In some embodiments, the data signal lines DATA, the second trace portion FIAA2, and the second voltage adjustment portion are arranged to match the positions of different transistors in the pixel circuit. The second voltage adjustment portion and the second trace portion FIAA2 can be arranged between two adjacent data signal lines DATA, or the two data signal lines DATA can be arranged between the second voltage adjustment portion and the second trace portion FIAA2. The relative positions between the data signal lines DATA and the second trace portion FIAA2 can be various, and can match different pixel circuit arrangements. In some embodiments, the second voltage adjustment portion and the second trace portion FIAA2 are arranged between two adjacent data signal lines DATA. The second voltage adjustment portion (one of the second initialization reset line VREF12, the second anode reset signal line VREF22, and the second bias adjustment line DVH2) can serve as a shielding signal line between the two adjacent data signal lines DATA, and the second trace portion FIAA2 can serve as a shielding signal line between the second voltage adjustment portion and the data signal lines DATA, thereby reducing interference between different data signals.

[0128] In some embodiments, continuing to refer to FIGS. 8 and 22-57, the voltage adjustment transistor includes an initialization reset transistor, an anode reset transistor, and a bias adjustment transistor; the voltage adjustment signal line includes an initialization reset signal line, an anode reset signal line, and a bias adjustment signal line; the pixel circuit further includes a driving transistor, and the display panel further includes a light emitting element; the initialization reset transistor is electrically connected between the initialization reset signal line and the gate of the driving transistor; the anode reset transistor is electrically connected between the anode reset signal line and the light emitting element; the bias adjustment transistor is electrically connected between the bias adjustment signal line and at least one of the first electrode and the second electrode of the driving transistor; the initialization reset signal line includes a first initialization reset line, a plurality of first initialization reset lines are arranged along a first direction and extend along a second direction, and the first voltage adjustment portion includes the first initialization reset line; the anode reset signal line includes a first anode reset line, a plurality of first anode reset lines are arranged along the first direction and extend along the second direction, and the first voltage adjustment portion includes the first anode reset line; the bias adjustment signal line includes a first bias adjustment line, a plurality of first bias adjustment lines are arranged along the first direction and extend along the second direction, and the first voltage adjustment portion includes the first bias adjustment line; and the second sub-coupling portion is multiplexed as at least one of the first initialization reset line, the first anode reset line, and the first bias adjustment line.

[0129] The voltage regulating transistor includes an initialization reset transistor T5, an anode reset transistor T7, and a bias regulating transistor T8. The initialization reset transistor T5 is configured to transmit an initialization reset signal provided by an initialization reset signal line VREF1 to a gate of the driving transistor T3 when the initialization reset transistor T5 is turned on, so as to reset the first node N1. The anode reset transistor T7 is configured to transmit an anode reset signal provided by an anode reset signal line VREF2 to the anode of the light emitting element when the anode reset transistor T7 is turned on, so as to reset the anode of the light emitting element and avoid the display signal of the previous frame from affecting the display effect of the current frame. The bias regulating transistor T8 is configured to transmit a bias regulating signal provided by a bias regulating signal line DVH to at least one of the second node N2 and the third node N3 when the bias regulating transistor T8 is turned on, so as to bias and regulate at least one of the second node N2 and the third node N3.

[0130] In some embodiments, the initialization reset signal line VREF1 includes a first initialization reset line VREF11, the first initialization reset line VREF11 is arranged along a first direction and extends along a second direction, the first initialization reset line VREF11 is electrically connected with a plurality of initialization reset transistors T5 arranged in the same row, and is configured to provide an initialization reset signal for the plurality of initialization reset transistors T5 arranged in the same row. Since the initialization reset signal is a fixed potential signal and the second sub-coupling section 1112 also extends along the second direction, as shown in FIGS. 14 and 16, the second sub-coupling section 1112 can be multiplexed as the first initialization reset line VREF11. In this way, the second sub-coupling section 1112 and the first initialization reset line VREF11 are the same structure, which can form a stable capacitive structure with the first wiring section FIAA1, so as to ensure that the first wiring section FIAA1 is not affected by other jump signals when the potential is floating, and also provide the initialization reset signal for the initialization reset transistor T5, so as to realize a simple and efficient wiring scheme in the display panel.

[0131] The anode reset signal line VREF2 includes a first anode reset line VREF21, a plurality of first anode reset lines VREF21 are arranged along a first direction and extend along a second direction, the first anode reset line VREF21 is electrically connected with a plurality of anode reset transistors T7 arranged in the same row, and is configured to provide an anode reset signal for the plurality of anode reset transistors T7 arranged in the same row. Since the anode reset signal is a fixed potential signal, the second sub-coupling section 1112 also extends along the second direction, and therefore, as shown in FIGS. 25 and 29, FIGS. 39 and 41, and FIGS. 51 and 53, the second sub-coupling section 1112 can be multiplexed as the first anode reset line VREF21. In this way, the second sub-coupling section 1112 and the first anode reset line VREF21 are the same structure, which can form a stable capacitive structure with the first wiring section FIAA1, ensure that the first wiring section FIAA1 is not disturbed by other jump signals when the potential is floating, and also provide an anode reset signal for the anode reset transistor T7, realizing a simple and efficient wiring scheme in the display panel.

[0132] The bias adjustment signal line DVH includes a first bias adjustment line DVH1, a plurality of first bias adjustment lines DVH1 are arranged along a first direction and extend along a second direction, the first bias adjustment line DVH1 is electrically connected with a plurality of bias adjustment transistors T8 arranged in the same row, and is configured to provide a bias adjustment signal for the plurality of bias adjustment transistors T8 arranged in the same row. Since the bias adjustment signal is a fixed potential signal, the second sub-coupling section 1112 also extends along the second direction, and therefore, the second sub-coupling section 1112 can be multiplexed as the first bias adjustment line DVH1. In this way, the second sub-coupling section 1112 and the first bias adjustment line DVH1 are the same structure, which can form a stable capacitive structure with the first wiring section FIAA1, ensure that the first wiring section FIAA1 is not disturbed by other jump signals when the potential is floating, and also provide an anode reset signal for the anode reset transistor T7, realizing a simple and efficient wiring scheme in the display panel.

[0133] Therefore, the second sub-coupling section 1112 can be multiplexed as at least one of the first initialization reset line VREF11, the first anode reset line VREF21, and the first bias adjustment line DVH1. While ensuring that the second sub-coupling section 1112 forms a stable capacitive structure with the first wiring section FIAA1, and ensuring that the first wiring section FIAA1 is not disturbed by other jump signals when the potential is floating, the second sub-coupling section 1112 can also provide a voltage adjustment signal for at least one of the initialization reset transistor T5, the anode reset transistor T7, and the bias adjustment transistor T8, realizing a simple and efficient wiring scheme in the display panel.

[0134] The above embodiments describe the setting mode of the first coupling structure. By setting the longitudinal (thickness direction of the display panel) coupling capacitance between the first coupling sub-portion and the first wiring sub-portion, the first wiring sub-portion can have a relatively stable potential when the potential is floating.

[0135] In some embodiments, continuing to refer to FIGS. 22-57, the display panel further includes a plurality of pixel circuits, the pixel circuit further includes at least one second type transistor; the pixel circuit includes a driving transistor T3 and an initial reset transistor T5, the signal line includes an initial reset signal line VREF1, and the initial reset transistor T5 is electrically connected between the initial reset signal line VREF1 and the gate of the driving transistor T3; the second type transistor includes the initial reset transistor T5; the plurality of initial reset transistors includes a first initial reset transistor T51, a second initial reset transistor T52 and a third initial reset transistor T53 arranged adjacent along the second direction; the distance between the active layer of the first initial reset transistor T51 and the active layer of the second initial reset transistor T52 is a first distance, and the distance between the active layer of the second initial reset transistor T52 and the active layer of the third initial reset transistor T53 is a second distance; the first distance is less than the second distance; the signal line further includes a plurality of first scan signal lines SIN, the first scan signal lines SIN extend along the second direction and are arranged along the first direction, and along the thickness direction of the display panel, the first scan signal lines SIN overlap the active layer of the first initial reset transistor T51, the active layer of the second initial reset transistor T52 and the active layer of the third initial reset transistor T53; the display panel further includes a second coupling adjustment structure 13, the second coupling adjustment structure 13 is connected to the active layer of the second initial reset transistor T52 and the active layer of the third initial reset transistor T53; the second coupling adjustment structure 13 is electrically connected to the fixed potential signal line, and the orthographic projection of the second coupling adjustment structure 13 on the plane where the substrate is located is located between the orthographic projection of the first wiring sub-portion FIAA1 on the plane where the substrate is located and the orthographic projection of the first scan signal line SIN on the plane where the substrate is located.

[0136] For example, the pixel circuit includes the second type transistor, which can be an oxide semiconductor transistor having a small leakage current. In some embodiments, the second type transistor can include the initial reset transistor T5, which is electrically connected between the initial reset signal line VREF1 and the gate of the driving transistor T3. Since the initial reset transistor T5 is the second type transistor, its small leakage current characteristic can ensure that the potential of the gate of the driving transistor T3, i.e., the first node N1, is stable.

[0137] In some embodiments, referring to FIG. 26, FIG. 38 and FIG. 50, the plurality of initialization reset transistors include a first initialization reset transistor T51, a second initialization reset transistor T52 and a third initialization reset transistor T53 arranged adjacently along the second direction; the distance between the active layer of the first initialization reset transistor T51 and the active layer of the second initialization reset transistor T52 is a first distance, and the distance between the active layer of the second initialization reset transistor T52 and the active layer of the third initialization reset transistor T53 is a second distance; the first distance is smaller than the second distance, that is, the distance between the active layer of the first initialization reset transistor T51 and the active layer of the second initialization reset transistor T52 is smaller than the distance between the active layer of the second initialization reset transistor T52 and the active layer of the third initialization reset transistor T53, and the second initialization reset transistor T52 and the third initialization reset transistor T53 are two initialization reset transistors T5 with a relatively long distance between the active layers along the second direction. In some embodiments, referring to FIG. 26, FIG. 27, FIG. 29, FIG. 38, FIG. 39, FIG. 41, FIG. 50, FIG. 51 and FIG. 53, the signal line further includes a plurality of first scan signal lines SIN, the first scan signal lines SIN extend along the second direction and are arranged along the first direction, and along the thickness direction of the display panel, the first scan signal lines SIN overlap the active layer of the first initialization reset transistor T51, the active layer of the second initialization reset transistor T52 and the active layer of the third initialization reset transistor T53, and the first scan signal lines SIN transmit a scan signal for controlling the first initialization reset transistor T51, the second initialization reset transistor T52 and the third initialization reset transistor T53 to be turned on or turned off, and the scan signal is a jump signal, so that the first scan signal lines SIN can pull down or pull up the potential of the signal in the first wiring part FIAA1 in the case of potential floating in the first wiring part FIAA1, resulting in display abnormalities. Therefore, the above embodiments illustrate that by arranging the first coupling part 111 overlapping the first wiring part FIAA1 and electrically connected with the fixed potential signal line, the coupling capacitance in the longitudinal direction (the thickness direction of the display panel) is formed by the first coupling part 111 overlapping the first wiring part FIAA1 to ensure the stability of the signal in the first wiring part FIAA1.In some embodiments, the display panel provided by the embodiments of the present application can further include a second coupling adjustment structure 13 connected to the active layer of the second initialization reset transistor T52 and the active layer of the third initialization reset transistor T53; the second coupling adjustment structure 13 is electrically connected to the fixed potential signal line, and the orthographic projection of the second coupling adjustment structure 13 on the plane where the substrate 10 is located is located between the orthographic projection of the first wiring section FIAA1 on the plane where the substrate 10 is located and the orthographic projection of the first scan signal line S1N on the plane where the substrate is located, so that the second coupling adjustment structure 13 can form a lateral coupling capacitor with the first wiring section FIAA1 and the first scan signal line S1N, respectively. The lateral coupling capacitor formed between the second coupling adjustment structure 13 and the first wiring section FIAA1 can ensure that the first wiring section FIAA1 maintains a relatively stable potential when floating in potential. The lateral coupling capacitor formed between the second coupling adjustment structure 13 and the first scan signal line S1N can disperse a part of the signal in the first scan signal line SIN, reduce the coupling capacitor between the first scan signal line SIN and the first wiring section FIAA1, reduce the interference of the jump signal in the first scan signal line SIN on the signal in the first wiring section FIAA1, and ensure that the signal in the first wiring section FIAA1 is relatively stable when floating in potential.

[0138] In some embodiments, the second coupling adjustment structure 13 can be arranged in the same layer as the active layer of the initialization reset transistor T5, that is, the second coupling adjustment structure 13 can be arranged in the second semiconductor layer 215, so that the arrangement of the second coupling adjustment structure 13 does not increase the film layer structure of the display panel, and ensures that the structure of the display panel is relatively simple.

[0139] In some embodiments, the initialization reset signal line VREF1 includes a first initialization reset line VREF11, and a plurality of first initialization reset lines are arranged in a first direction and extend in a second direction; the second coupling adjustment structure 13 is electrically connected to the first initialization reset line VREF11; and in the thickness direction of the display panel, the second coupling adjustment structure 13 overlaps the first initialization reset line VREF11.

[0140] With continued reference to FIGS. 26, 27, 29, 38, 39, 41, 50, 51 and 53, the initialization reset signal line VREF1 includes a first initialization reset line VREF11, and the second coupling adjustment structure 13 overlaps and is electrically connected with the first initialization reset line VREF11, so that a fixed potential signal can be transmitted in the second coupling adjustment structure 13, and a more stable side coupling capacitance is formed in the first wiring section FIAA1 and the first scan signal line S1N. Moreover, the second coupling adjustment structure 13 overlaps and is electrically connected with the first initialization reset line VREF11, that is, the second coupling adjustment structure 13 is arranged in parallel with the first initialization reset line VREF11, and the resistance on the first initialization reset line VREF11 can be reduced, the loss of the initialization reset signal in the transmission process is reduced, and the accuracy of the initialization signal is good.

[0141] The above embodiments describe the arrangement mode of the second coupling structure, and by arranging the transverse (substrate plane) coupling capacitance between the second coupling section and the first wiring section, the first wiring section can have a more stable potential when the potential is floating.

[0142] In some embodiments, with continued reference to FIGS. 6, 8, 11-57, the signal line further includes a plurality of second scan signal lines extending along a second direction and arranged along a first direction; along the thickness direction of the display panel, the first wiring section FIAA1 does not overlap with the second scan signal line; the display panel further includes a third coupling adjustment structure 14; along the thickness direction of the display panel, the third coupling adjustment structure 14 overlaps with the second scan signal line, and the third coupling adjustment structure 14 is electrically connected with the fixed potential signal line.

[0143] For example, the second scan signal line is a signal line overlapping with the active layer of the anode reset transistor T7. For example, the pixel circuit shown in FIGS. 6, 11-20 includes a first type of transistor, and the second scan signal line is S1. For example, the pixel circuit shown in FIGS. 8, 22-57 includes a first type of transistor and a second type of transistor, and the second scan signal line is SP. Since the first trace part FIAA1 does not overlap with the second scan signal line in the thickness direction of the display panel, there is a lateral coupling interference between the first trace part FIAA1 and the second scan signal line. When the signal on the second scan signal line jumps, it will affect the potential in the first trace part FIAA1 when the potential of the first trace part FIAA1 is floating. Therefore, in the embodiment of the present application, the third coupling adjustment structure 14 is electrically connected to the fixed potential signal line, and the third coupling adjustment structure 14 overlaps with the second scan signal line in the thickness direction of the display panel. Thus, the longitudinal coupling capacitor is formed between the third coupling adjustment structure 14 and the second scan signal line, which can disperse a part of the signal in the second scan signal line, reduce the coupling capacitance between the second scan signal line and the first trace part FIAA1, reduce the interference of the jumping signal in the second scan signal line on the signal in the first trace part FIAA1, and ensure that the signal in the first trace part FIAA1 is relatively stable when the potential is floating.

[0144] In some embodiments, the display panel further includes a pixel circuit, the pixel circuit includes at least one first type of transistor, the first type of transistor includes a first active layer; and the third coupling adjustment structure includes a third coupling part, a film layer where the third coupling part is located is between a film layer where the substrate is located and a film layer where the first active layer is located.

[0145] The pixel circuit includes at least one first type of transistor, the first type of transistor is a low-temperature polysilicon transistor, and the first active layer includes silicon, for example, low-temperature polysilicon. The third coupling adjustment structure includes a third coupling part, a film layer where the third coupling part is located is between a film layer where the substrate is located and a film layer where the first active layer is located, for example, the third coupling part and the light shielding structure are disposed in the same layer, and are both located in the zeroth metal layer M0. Thus, the setting of the third coupling part does not increase the film layer structure of the display panel, which is beneficial to realize the thin display panel structure.

[0146] In some embodiments, continuing to refer to FIGS. 22-57, the display panel further includes a pixel circuit, the pixel circuit includes at least one first type of transistor, the first type of transistor includes a first active layer; and the third coupling adjustment structure 14 includes a fourth coupling part 141, a film layer where the fourth coupling part 141 is located is between a film layer where the second scan signal line is located and a film layer where the first trace part FIAA1 is located.

[0147] The pixel circuit includes at least one first type transistor, the first type transistor is a low-temperature polysilicon transistor, and the first active layer includes silicon, for example, low-temperature polysilicon. The third coupling adjustment structure 14 includes a fourth coupling sub-part 141, and the film layer where the fourth coupling sub-part 141 is located is between the film layer where the second scan signal line is located and the film layer where the first wire sub-part FIAA1 is located. In this way, the distance between the fourth coupling sub-part 141 and the film layer where the second scan signal line is located is small, and the fourth coupling sub-part 141 and the second scan signal line can form a coupling capacitance structure with relatively stable coupling effect, sufficiently dispersing the signals in the second scan signal line and reducing the interference of the signals jumping in the second scan signal line on the signals in the first wire sub-part FIAA1.

[0148] For example, as shown in FIGS. 27, 29, 39, 41, 49, and 53, the fourth coupling sub-part 141 can be located in at least one of the second metal layer 208 (i.e., the MC metal layer) and the fourth metal layer 217 (i.e., the MG metal layer). Among them, FIGS. 27, 29, 39, 41, 49, and 53 all take the fourth coupling sub-part 141 located in the fourth metal layer 217 as an example for description. By setting the fourth coupling sub-part 141 in at least one of the second metal layer 208 and the fourth metal layer 217, the fourth coupling sub-part 141 can form a coupling capacitance structure with relatively stable coupling effect between the fourth coupling sub-part 141 and the second scan signal line, and the setting of the fourth coupling sub-part 141 does not increase the film layers of the display panel, which is conducive to the thin design of the display panel.

[0149] In some embodiments, the second sub-coupling sub-part 1112 can be multiplexed as at least one of the first initialization reset line VREF11, the first anode reset line VREF21, and the first bias adjustment line DVH1, the fourth coupling sub-part 141 can be multiplexed as at least one of the first initialization reset line VREF11, the first anode reset line VREF21, and the first bias adjustment line DVH1, and the signal lines multiplexed by the second sub-coupling sub-part 1112 and the fourth coupling sub-part 141 are different. For example, as shown in FIGS. 25, 27, and 29, the second sub-coupling sub-part 1112 is multiplexed as the first anode reset line VREF21, and the fourth coupling sub-part 141 can be multiplexed as the first bias adjustment line DVH1; as shown in FIGS. 39 and 41, the second sub-coupling sub-part 1112 is multiplexed as the first anode reset line VREF21, and the fourth coupling sub-part 141 can be multiplexed as the first bias adjustment line DVH1; as shown in FIGS. 49, 51, and 53, the second sub-coupling sub-part 1112 is multiplexed as the first bias adjustment line DVH1, and the fourth coupling sub-part 141 can be multiplexed as the first anode reset line VREF21.

[0150] The above embodiment describes the setting mode of the third coupling adjustment structure. By setting the third coupling adjustment structure to form a coupling capacitor with the second scan signal line, the signal in the second scan signal line can be dispersed, and the interference of the jump signal in the second scan signal line on the signal in the first trace part can be reduced.

[0151] In some embodiments, continuing to refer to FIGS. 6, 11-20, the display panel further includes a pixel circuit, the pixel circuit including a driving transistor T3 and a threshold compensation transistor T4, a gate of the driving transistor T3 and a first electrode of the threshold compensation transistor T4 are electrically connected with the first connection structure 15; the display panel further includes a first shielding structure 16, the first shielding structure 16 is electrically connected with a fixed potential signal line; in a thickness direction of the display panel, the first shielding structure 16 covers at least part of the first connection structure 15.

[0152] Referring to FIGS. 6, 15, 16 and 17, the pixel circuit includes a driving transistor T3 and a threshold compensation transistor T4, a gate of the driving transistor T3 and a first electrode of the threshold compensation transistor T4 are electrically connected with the first connection structure 15, or the first connection structure connects the gate of the driving transistor T3 and the first electrode of the threshold compensation transistor T4. That is, the potential at the first connection structure 15 is equivalent to the potential of the first node N1. In order to ensure the normal work of the driving transistor T3, it is necessary to ensure that the potential at the position of the first connection structure 15 remains stable. Therefore, the first shielding structure 16 is provided in the embodiment of the present application, the first shielding structure 16 is electrically connected with a fixed potential signal line; in a thickness direction of the display panel, the first shielding structure 16 covers at least part of the first connection structure 15. That is, a coupling capacitor is formed between the first shielding structure 16 and the first connection structure 15, and since the first shielding structure 16 is electrically connected with the fixed potential signal line, the potential of the first shielding structure 16 is stable, and the coupling capacitor structure formed between the first shielding structure 16 and the first connection structure 15 is stable, so that the potential of the first connection structure 15 can be ensured to be stable, and the driving transistor T3 can work normally.

[0153] In some embodiments, continuing to refer to FIGS. 6, 11-20, the pixel circuit further includes a voltage adjusting transistor; the signal line further includes a voltage adjusting signal line, the voltage adjusting signal line is electrically connected with a first electrode of the voltage adjusting transistor; the voltage adjusting signal line includes a second voltage adjusting part, the second voltage adjusting part extends in the first direction; the first shielding structure is electrically connected with at least part of the second voltage adjusting part.

[0154] The pixel circuit comprises a voltage regulating transistor, and the signal line further comprises a voltage regulating signal line electrically connected to the first electrode (i.e. input end) of the voltage regulating transistor. In this way, the voltage regulating signal is input into the pixel circuit at a position requiring voltage regulation, such as the gate of the driving transistor and the anode of the light emitting element, through the voltage regulating transistor. In some embodiments, the voltage regulating signal line can comprise a second voltage regulating sub-portion extending in the first direction, and the first shielding structure 16 is electrically connected to at least part of the second voltage regulating sub-portion. In this way, a fixed voltage regulating signal is transmitted in the first shielding structure 16, and there is no need to additionally provide a fixed potential signal for the first shielding structure 16. The first shielding structure 16 is electrically connected to the fixed potential signal line in a simple implementation manner. As shown in FIG. 17, the first shielding structure 16 can be an initialization reset signal line VREF1, or an anode reset signal line VREF2.

[0155] For example, the voltage regulating transistor comprises an initialization reset transistor T5 and an anode reset transistor T7, the voltage regulating signal line comprises an initialization reset signal line VREF1 and an anode reset signal line VREF2, the display panel further comprises a light emitting element 30, the initialization reset transistor T5 is electrically connected between the initialization reset signal line VREF1 and the gate of the driving transistor T3, the anode reset transistor T7 is electrically connected between the anode reset signal line VREF2 and the anode of the light emitting element 30, the initialization reset signal line VREF1 comprises a second initialization reset line VREF12, a plurality of second initialization reset lines VREF12 extend in the first direction and are arranged in the second direction, and the first shielding structure 16 is electrically connected to the second initialization reset line VREF12; and / or, the anode reset signal line VREF2 comprises a second anode reset line VREF22, a plurality of second anode reset lines VREF22 extend in the first direction and are arranged in the second direction, and the first shielding structure 16 is electrically connected to the second anode reset line VREF22.

[0156] The voltage regulating transistor comprises an initialization reset transistor T5, the voltage regulating signal line comprises an initialization reset signal line VREF1, and the initialization reset transistor T5 is electrically connected between the initialization reset signal line VREF1 and the gate of the driving transistor T3, so as to initialize the gate of the driving transistor T3. In some embodiments, the voltage regulating transistor further comprises an anode reset transistor T7, the voltage regulating signal line further comprises an anode reset signal line VREF2, and the anode reset transistor T7 is electrically connected between the anode reset signal line VREF2 and the anode of the light emitting element 30, so as to reset the anode of the light emitting element 30.

[0157] In some embodiments, the initialization reset signal line VREF1 includes a first initialization reset line VREF11 extending in the second direction and a second initialization reset line VREF12 extending in the first direction, the first initialization reset line VREF11 and the second initialization reset line VREF12 are electrically connected to form a grid-shaped initialization reset signal line VREF1, which on the one hand ensures the uniform distribution of the initialization reset signal line VREF1 in the entire display area, and on the other hand reduces the resistance of the initialization reset signal line VREF1. Similarly, the anode reset signal line VREF2 includes a first anode reset line VREF21 extending in the second direction and a second anode reset line VREF22 extending in the first direction, the first anode reset line VREF21 and the second anode reset line VREF22 are electrically connected to form a grid-shaped anode reset signal line VREF2, which on the one hand ensures the uniform distribution of the anode reset signal line VREF2 in the entire display area, and on the other hand reduces the resistance of the anode reset signal line VREF2.

[0158] In some embodiments, as shown in FIGS. 15, 16 and 17, the second initialization reset line VREF12 includes a first reset part VREF12a and a second reset part VREF12b arranged in different layers, the first reset part VREF12a is connected to two second reset parts VREF12b arranged adjacent in the first direction, so as to obtain the second initialization reset line VREF12 extending in the first direction. As shown in FIG. 17, the electrical connection between the first shielding structure 16 and the second initialization reset line VREF12 can be the electrical connection between the first shielding structure 16 and the first reset part VREF12a, so as to ensure the electrical connection between the first shielding structure 16 and the fixed potential signal line, and to achieve the shielding protection of the first connection structure 16. Similarly, as shown in FIGS. 15, 16 and 17, the second anode reset line VREF22 includes a third reset part VREF22a and a fourth reset part VREF22b arranged in different layers, the third reset part VREF22a is connected to two fourth reset parts VREF22b arranged adjacent in the first direction, so as to obtain the second anode reset line VREF22 extending in the first direction. As shown in FIG. 17, the electrical connection between the first shielding structure 16 and the second anode reset line VREF22 can be the electrical connection between the first shielding structure 16 and the third reset part VREF22a, so as to ensure the electrical connection between the first shielding structure 16 and the fixed potential signal line, and to achieve the shielding protection of the first connection structure 16.

[0159] In some embodiments, as shown in FIG. 17, the first shielding structure 16 is arranged in at least one of the following manners: the first shielding structure 16 is arranged in the same layer as the second initialization reset line VREF12, and the first shielding structure 16 is arranged in the same layer as the second anode reset line VREF22, so that the arrangement of the first shielding structure 16 does not increase the number of film layers in the display panel, and the structure of the display panel is simple.

[0160] In some embodiments, as shown in FIG. 17, the initialization reset signal line VREF1 includes the second initialization reset line VREF12, and the anode reset signal line VREF2 includes the second anode reset line VREF22; along the second direction, the second initialization reset line VREF12 and the second anode reset line VREF22 are arranged alternately. In some embodiments, the first shielding structure electrically connected to the second initialization reset line VREF12 and the first shielding structure electrically connected to the second anode reset line VREF22 are arranged alternately along the second direction.

[0161] In some embodiments, as shown in FIGS. 6, 11-20, the display panel further includes a pixel circuit, the pixel circuit includes a driving transistor T3 and a threshold compensation transistor T4, the gate of the driving transistor T3 and the first electrode of the threshold compensation transistor T4 are electrically connected to the first connection structure 15; the data auxiliary line FIAA includes a second wiring part FIAA2, the second wiring part FIAA2 extends along the first direction and is electrically connected to the fan-out wiring; the display panel further includes a second shielding structure 17, the second shielding structure 17 is electrically connected to the fixed potential signal line; at least part of the second shielding structure 17 satisfies at least one of the following conditions: at least part of the second shielding structure 17 is located between the orthogonal projection of the data signal line DATA on the substrate and the orthogonal projection of the first connection structure 15 on the substrate; and at least part of the second shielding structure 17 is located between the orthogonal projection of the second wiring part FIAA2 on the substrate and the orthogonal projection of the first connection structure 15 on the substrate.

[0162] The pixel circuit includes a driving transistor T3 and a threshold compensation transistor T4, a gate of the driving transistor T3 and a first electrode of the threshold compensation transistor T4 are electrically connected with the first connection structure 15, or the first connection structure connects the gate of the driving transistor T3 and the first electrode of the threshold compensation transistor T4. In order to ensure the normal work of the driving transistor T3, it is necessary to ensure that the potential at the position of the first connection structure 15 remains stable, and it is necessary to shield the interference caused by the jumping signal in the data signal line DATA to the position of the first connection structure 15. Therefore, the second shielding structure 17 is arranged in the embodiment of the present application, the second shielding structure 17 is electrically connected with the fixed potential signal line, and at least part of the second shielding structure 17 is located between the normal projection of the data signal line DATA on the substrate and the normal projection of the first connection structure 15 on the substrate, that is, the second shielding structure 17 can shield the interference of the jumping signal in the data signal line DATA to the position of the first connection structure 15, and ensure the stability of the potential at the position of the first connection structure 15. At least part of the second shielding structure 17 is located between the normal projection of the second wire section FIAA2 on the substrate and the normal projection of the first connection structure 15 on the substrate, that is, the second shielding structure 17 can shield the interference of the jumping signal in the second wire section FIAA2 to the position of the first connection structure 15, and ensure the stability of the potential at the position of the first connection structure 15.

[0163] In some embodiments, continuing to refer to FIG. 14, FIG. 15, FIG. 16 and FIG. 20, the second shielding structure 17 can include a first sub-shielding structure 171 and a second sub-shielding structure 172, the first sub-shielding structure 171 is located between the normal projection of the data signal line DATA on the substrate and the normal projection of the first connection structure 15 on the substrate in the normal projection of the substrate, and is arranged to shield the interference of the jumping signal in the data signal line DATA to the position of the first connection structure 15; the second sub-shielding structure 172 is located between the normal projection of the second wire section FIAA2 on the substrate and the normal projection of the first connection structure 15 on the substrate in the normal projection of the substrate, and is arranged to shield the interference of the jumping signal in the second wire section FIAA2 to the position of the first connection structure 15.

[0164] Referring to FIG. 14, the first sub-shielding structure 171 and the second sub-shielding structure 172 can be arranged in the same layer, for example, both are located in the second metal layer 208, that is, both are located in the MC metal layer. In this way, the arrangement of the second shielding structure 17 will not increase the film layer in the display panel, which is conducive to the design of the thin display panel.

[0165] In some embodiments, continuing to refer to FIGS. 22-33, the display panel further includes a pixel circuit, the pixel circuit includes a driving transistor T3 and a data writing transistor T2, a second electrode of the data writing transistor T2 and a first electrode of the driving transistor T3 are electrically connected with the second connection structure 18; the signal line further includes a plurality of light emitting control signal lines EMIT, the plurality of light emitting control signal lines EMIT are arranged along a first direction and extend along a second direction; the display panel further includes a third shielding structure 19, the third shielding structure 19 is electrically connected with the fixed potential signal line; a film layer where the third shielding structure 19 is located is between a film layer where the second connection structure 18 is located and a film layer where the light emitting control signal line EMIT is located, and a projection of the third shielding structure 19 on a plane where the substrate is located overlaps with a projection of the second connection structure 18 on the plane where the substrate is located and a projection of the light emitting control signal line EMIT on the plane where the substrate is located.

[0166] The pixel circuit includes the driving transistor T3, the data writing transistor T2 and the bias adjusting transistor T8, a second electrode of the data writing transistor T2, a first electrode of the driving transistor T3 and a first electrode of the bias adjusting transistor T8 are electrically connected with the second connection structure 18, that is, the second connection structure 18 connects the second electrode of the data writing transistor T2, the first electrode of the driving transistor T3 and the first electrode of the bias adjusting transistor T8. That is, the potential of the second connection structure 18 is equivalent to the potential of the second node N2. The signal line further includes a plurality of light emitting control signal lines EMIT, along the thickness direction of the display panel, the light emitting control signal line EMIT overlaps with the second connection structure 18, so the signal jumping in the light emitting control signal line EMIT will interfere with the potential at the position of the second connection structure 18, affecting the normal work of the driving transistor. Therefore, in the embodiment of the present application, the third shielding structure 19 is additionally provided, the third shielding structure 19 is electrically connected with the fixed potential signal line, a film layer where the third shielding structure 19 is located is between a film layer where the second connection structure 18 is located and a film layer where the light emitting control signal line EMIT is located, and a projection of the third shielding structure 19 on a plane where the substrate is located overlaps with a projection of the second connection structure 18 on the plane where the substrate is located and a projection of the light emitting control signal line EMIT on the plane where the substrate is located, so that the third shielding structure 19 can shield the signal jumping in the light emitting control signal line EMIT, avoid the interference of the signal jumping in the light emitting control signal line EMIT on the potential at the position of the second connection structure 18, ensure the stability of the potential at the position of the second connection structure 18, and further ensure the normal work of the driving transistor and the entire pixel circuit.

[0167] In some embodiments, referring to FIG. 24, FIG. 27 and FIG. 28, the light emitting control signal line EMIT can be located in the first metal layer 206, that is, in the M1 metal layer; the third shielding structure 19 can be located in the fourth metal layer 217, that is, in the MG metal layer; and the second connection structure 18 can be located in the third metal layer 210, that is, in the M2 metal layer. The arrangement of the third shielding structure 19 does not increase the film layers in the display panel, which is conducive to the thin design of the display panel.

[0168] FIG. 58 is a schematic view of the stack of some film layers in another display panel according to an embodiment of the present application. As shown in FIG. 2 and FIG. 58, the display panel further includes a virtual auxiliary line L0, which is arranged in the same layer as the data auxiliary line FIAA and has a break D with the data auxiliary line FIAA; and the display panel further includes a light emitting element 30, which covers the break D in the thickness direction of the display panel.

[0169] In some embodiments, the display area AA can further include a virtual auxiliary line L0, which includes a first virtual auxiliary line L01 and a second virtual auxiliary line L02. As shown in FIG. 2 and FIG. 58, the first virtual auxiliary line L01 and the second virtual auxiliary line L02 are both arranged in isolation from the data auxiliary line FIAA. The arrangement of the virtual auxiliary line L0 can compensate for the length of the data auxiliary line FIAA, for example, the first virtual auxiliary line L01 can be arranged to compensate for the first wire section FIAA1, and the second virtual auxiliary line L02 can be arranged to compensate for the first wire section FIAA2. That is, by arranging the virtual auxiliary line L0, the arrangement area of the data auxiliary line FIAA is balanced in the whole, ensuring that the density of the wire arrangement in different areas is balanced, thereby avoiding the difference in light reflectivity in different areas of the display panel due to the unbalanced wire arrangement, and avoiding the situation that the display effect of the display panel is unbalanced.

[0170] In some embodiments, the virtual auxiliary line L0 can be electrically connected to the fixed potential end. On the one hand, it can avoid the interference of the display effect of the display panel caused by the coupling of the virtual auxiliary line L0 with a floating potential to other signals, and on the other hand, the virtual auxiliary line L0 is connected in parallel with the fixed potential end, which can reduce the resistance on the fixed signal end or the fixed potential signal line, so as to ensure that the loss of the fixed potential signal in the transmission process is small.

[0171] In some embodiments, continuing to refer to FIG. 58, due to the insulation between the virtual auxiliary line L0 and the data auxiliary line FIAA, there is a break between the virtual auxiliary line L0 and the data auxiliary line FIAA. For example, there is a break D between the first virtual auxiliary line L01 and the first trace FIAA1, and there is a break D between the second virtual auxiliary line L02 and the second trace L2. In some embodiments, in the thickness direction of the display panel, the light emitting element 30 covers the break D. For example, the anode RE of the light emitting element 30 covers the break D, which can be understood as the projection of at least one anode RE in the substrate in the display panel can cover the projection of the break D in the substrate, that is, it can be ensured that the set break D is blocked, ensuring that the density of the traces set in different areas is balanced, thereby avoiding different light reflectivity in different areas of the display panel due to unbalanced trace settings, and avoiding uneven display effect of the display panel.

[0172] In some embodiments, in the thickness direction of the display panel, the first coupling adjustment structure overlaps the break. That is, in the thickness direction of the display panel, the first coupling adjustment structure covers the break, or in other words, there is no break in the first coupling adjustment structure, and the first coupling adjustment structure is a continuous structure. For example, the first coupling adjustment structure is set in at least one of the following ways: the first coupling adjustment structure is a continuous structure in the first direction, and the first coupling adjustment structure is a continuous structure in the second direction. By setting the first coupling adjustment structure as a continuous structure, it can be ensured that the coupling effect between the first coupling structure and the data auxiliary line is good, and it can be ensured that the potential in the data auxiliary line is stable when the data auxiliary line is floating.

[0173] Continuing to refer to FIGS. 18, 31, 43, and 55, the display panel further includes a light emitting element 30; the light emitting element includes a first color light emitting element 301, a second color light emitting element 302, and a third color light emitting element 303, the first color light emitting element 301, the second color light emitting element 302, and the third color light emitting element 303 are one of a red light emitting element, a blue light emitting element, and a green light emitting element and are all different; a plurality of first color light emitting elements 301 and second color light emitting elements 302 form a first virtual quadrilateral S1, the first color light emitting element 301 is at a first vertex of the first virtual quadrilateral S1, the second color light emitting element 302 is at a second vertex of the first virtual quadrilateral S1, and the third color light emitting element 303 is inside the first virtual quadrilateral S1; a plurality of third color light emitting elements 303 form a second virtual quadrilateral S2, and the plurality of third color light emitting elements 303 are respectively at the vertices of the second virtual quadrilateral S2, and the first color light emitting element 301 or the second color light emitting element 302 is inside the second virtual quadrilateral S2.

[0174] For example, referring to FIG. 18, FIG. 31, FIG. 43 and FIG. 55, the plurality of first color light emitting elements 301 and the plurality of second color light emitting elements 302 form a first virtual quadrilateral S1, two first color light emitting elements 301 are located at opposite corners of the first virtual quadrilateral S1, and two second color light emitting elements 302 are located at the other two opposite corners of the first virtual quadrilateral S1. A third color light emitting element 303 is located inside the first virtual quadrilateral S1.

[0175] In some embodiments, the plurality of third color light emitting elements 303 can also form a second virtual quadrilateral S2, and in the second virtual quadrilateral S2, the first color light emitting elements 301 can be located inside the second virtual quadrilateral S2, or the second color light emitting elements 302 can be located inside the second virtual quadrilateral S2. For example, the first color, the second color and the third color correspond to one of red, blue and green respectively. Through the above arrangement of the light emitting elements, the rendering effect of the light emitting elements can be better, and the color display effect of the display panel can be ensured.

[0176] Embodiments of the present application also provide a display device, which includes any one of the display panels provided in the above embodiments. FIG. 59 is a structural schematic diagram of a display device provided in an embodiment of the present application. As shown in FIG. 59, the display device 1 includes a display panel 100. Therefore, the display device also has the beneficial effects of the display panel in the above embodiments, and the same parts can be understood with reference to the above explanation and description of the display panel.

[0177] In some embodiments, the display device 1 further includes a power module for supplying power to the display device 1.

[0178] The display device 1 provided in the embodiments of the present application can be a mobile phone as shown in FIG. 59, or other electronic products with display functions, for example, can include the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, industrial control equipment, medical display screen and touch interactive terminal, etc.

Claims

1. A display panel comprising a plurality of signal lines; the signal lines comprise data signal lines, a plurality of the data signal lines extending along a first direction and arranged along a second direction; the first direction and the second direction intersecting; the display panel further comprises a display area and a non-display area at least partially surrounding the display area, the display area comprising a first display area and a second display area, the second display area being located at least one side of the first display area along the second direction; the first display area and the second display area each comprising a plurality of the data signal lines; the non-display area comprising a fan-out area located at one side of the display area along the first direction, the fan-out area comprising a plurality of fan-out lines; the signal lines further comprise data auxiliary lines, at least part of a data auxiliary line being located in the display area, the data signal lines in the second display area being electrically connected to the fan-out lines through the data auxiliary lines; the display panel further comprises a substrate and a first coupling adjustment structure between a film layer where the substrate is located and a film layer where the data auxiliary lines are located; along a thickness direction of the display panel, the first coupling adjustment structure overlaps the data auxiliary lines, and the first coupling adjustment structure is configured to receive a fixed potential signal.

2. The display panel of claim 1, wherein, the data auxiliary lines comprise a first line segment and a second line segment connected in series, the first line segment extending along the second direction and being electrically connected to the data signal lines in the second display area, the second line segment extending along the first direction and being electrically connected to the fan-out lines; the first coupling adjustment structure comprises at least one of a first coupling segment and a second coupling segment; the first coupling segment is located between the film layer where the substrate is located and the film layer where the first line segment is located and extends along the second direction; along the thickness direction of the display panel, the first coupling segment overlaps the first line segment, and the first coupling segment is configured to receive a fixed potential signal; the second coupling segment is located between the film layer where the substrate is located and the film layer where the second line segment is located and extends along the first direction; along the thickness direction of the display panel, the second coupling structure overlaps the second line segment, and the second coupling segment is configured to receive a fixed potential signal.

3. The display panel of claim 2, further comprising a pixel circuit, the pixel circuit comprising at least one first type transistor, the first type transistor comprising a first active layer; the first coupling segment comprises a first sub-coupling segment, a film layer where the first sub-coupling segment is located being between a film layer where the substrate is located and a film layer where the first active layer is located.

4. The display panel of claim 3, further comprising a light shielding structure, a film layer where the light shielding structure is located being between the film layer where the substrate is located and the film layer where the first active layer is located; the light shielding structure comprises a plurality of light shielding segments, along the thickness direction of the display panel, the light shielding segments overlapping channel regions in the first active layer; the first sub-coupling segment is disposed in the same layer as the light shielding structure.

5. The display panel of claim 4, further comprising a pixel circuit, the pixel circuit comprising a driving transistor and at least one switching transistor; the light shielding structure comprises a first light shielding sub-portion and a second light shielding sub-portion, along a thickness direction of the display panel, the first light shielding sub-portion overlaps with a channel region of the first active layer in the driving transistor, the second light shielding sub-portion overlaps with a channel region of the first active layer of at least part of the switching transistor; the first sub-coupling structure is connected to at least two second light shielding sub-portions arranged along the second direction.

6. The display panel of claim 2, further comprising a pixel circuit, the pixel circuit comprising at least one first type transistor, the first type transistor comprising a first active layer; the first coupling sub-portion comprises a second sub-coupling sub-portion, a film layer where the second sub-coupling sub-portion is located is between a film layer where the first active layer is located and a film layer where the first wiring sub-portion is located.

7. The display panel of claim 6, wherein, the pixel circuit further comprises a storage capacitor, the storage capacitor comprises a first plate and a second plate arranged oppositely, the second plate is located on a side of the first plate away from the first active layer; the display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer and a third metal layer arranged in a stack, the first active layer is located in the first semiconductor layer, the first plate is located in the first metal layer, the second plate is located in the second metal layer; the first wiring sub-portion is located in the third metal layer; the second sub-coupling sub-portion is located in the second metal layer.

8. The display panel of claim 6, wherein, the pixel circuit further comprises at least one second type transistor, the second type transistor comprises a second active layer and a top gate, the top gate is located on a side of the second active layer away from the first active layer; the pixel circuit further comprises a storage capacitor, the storage capacitor comprises a first plate and a second plate arranged oppositely, the second plate is located on a side of the first plate away from the first active layer; the display panel further comprises a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a fourth metal layer and a third metal layer arranged in a stack; the first active layer is located in the first semiconductor layer, the first plate is located in the first metal layer, the second plate is located in the second metal layer, the second active layer is located in the second semiconductor layer, the top gate is located in the fourth metal layer, the first wiring sub-portion is located in the third metal layer; the second sub-coupling sub-portion is located in at least one of the second metal layer and the fourth metal layer. the pixel circuit comprises a voltage regulating transistor; 9. The display panel of claim 6, wherein, the signal line further comprises a voltage regulating signal line, the voltage regulating signal line is electrically connected to a first electrode of the voltage regulating transistor; the voltage regulating signal line comprises a first voltage regulating sub-portion, the first voltage regulating sub-portion extends along the second direction, and at least part of the first voltage regulating sub-portion is located between a film layer where the first active layer is located and a film layer where the first wiring sub-portion is located; the second sub-coupling sub-portion is multiplexed as at least part of the first voltage regulating sub-portion. ​ 10. The display panel of claim 9, wherein, The voltage regulating transistor comprises an initialization reset transistor and an anode reset transistor; The voltage regulating signal line comprises an initialization reset signal line and an anode reset signal line; The pixel circuit further comprises a driving transistor, and the display panel further comprises a light emitting element; The initialization reset transistor is electrically connected between the initialization reset signal line and the gate of the driving transistor; the anode reset transistor is electrically connected between the anode reset signal line and the light emitting element; The initialization reset signal line comprises a first initialization reset line, a plurality of the first initialization reset lines are arranged along the first direction and extend along the second direction, and the first voltage regulating subpart comprises the first initialization reset line; the second sub-coupling part is multiplexed as the first initialization reset line; Or, The anode reset signal line comprises a first anode reset line, a plurality of the first anode reset lines are arranged along the first direction and extend along the second direction, and the first voltage regulating subpart comprises the first anode reset line; the second sub-coupling part is multiplexed as the first anode reset line; Or, The initialization reset signal line comprises a first initialization reset line, a plurality of the first initialization reset lines are arranged along the first direction and extend along the second direction, and the first voltage regulating subpart comprises the first initialization reset line; the second sub-coupling part is multiplexed as the first initialization reset line; the anode reset signal line comprises a first anode reset line, a plurality of the first anode reset lines are arranged along the first direction and extend along the second direction, and the first voltage regulating subpart comprises the first anode reset line; the second sub-coupling part is multiplexed as the first anode reset line.

11. The display panel of claim 10, wherein, The second sub-coupling part is multiplexed as the first initialization reset line and the first anode reset line; Along the first direction, the first initialization reset line and the first anode reset line are arranged alternately.

12. The display panel of claim 9, wherein, The voltage regulating transistor comprises an initialization reset transistor, an anode reset transistor and a bias regulating transistor; The voltage regulating signal line comprises an initialization reset signal line, an anode reset signal line and a bias regulating signal line; The pixel circuit further comprises a driving transistor, and the display panel further comprises a light emitting element; The initialization reset transistor is electrically connected between the initialization reset signal line and the gate of the driving transistor; the anode reset transistor is electrically connected between the anode reset signal line and the light emitting element; the bias regulating transistor is electrically connected between the bias regulating signal line and at least one of the first electrode and the second electrode of the driving transistor; The initialization reset signal line comprises a first initialization reset line, a plurality of the first initialization reset lines are arranged along the first direction and extend along the second direction, and the first voltage regulating subpart comprises the first initialization reset line; The anode reset signal line comprises a first anode reset line, a plurality of the first anode reset lines are arranged along the first direction and extend along the second direction, and the first voltage regulating subpart comprises the first anode reset line; The bias adjustment signal lines include first bias adjustment lines, a plurality of the first bias adjustment lines are arranged along the first direction and extend along the second direction, and the first voltage adjustment subpart includes the first bias adjustment lines; The second sub-coupling part is multiplexed into at least one of the first initialization reset line, the first anode reset line, and the first bias adjustment line.

13. The display panel of claim 2, further comprising a plurality of pixel circuits, the pixel circuits further comprising at least one second type transistor; The pixel circuit includes a driving transistor and an initial reset transistor, the signal line includes an initialization reset signal line, and the initialization reset transistor is electrically connected between the initialization reset signal line and the gate of the driving transistor; the second type transistor includes the initialization reset transistor; A plurality of the initialization reset transistors include a first initialization reset transistor, a second initialization reset transistor, and a third initialization reset transistor arranged adjacent along a second direction; A distance between the active layer of the first initialization reset transistor and the active layer of the second initialization reset transistor is a first distance, and a distance between the active layer of the second initialization reset transistor and the active layer of the third initialization reset transistor is a second distance; the first distance is less than the second distance; The signal line further includes a plurality of first scan signal lines, the first scan signal lines extend along the second direction and are arranged along the first direction, and along the thickness direction of the display panel, the first scan signal lines overlap the active layer of the first initialization reset transistor, the active layer of the second initialization reset transistor, and the active layer of the third initialization reset transistor; The display panel further includes a second coupling adjustment structure, the second coupling adjustment structure connects the active layer of the second initialization reset transistor and the active layer of the third initialization reset transistor; the second coupling adjustment structure is arranged to receive a fixed potential signal, and a projection of the second coupling adjustment structure on the plane where the substrate is located is located between a projection of the first wiring part on the plane where the substrate is located and a projection of the first scan signal line on the plane where the substrate is located. The second coupling structure is arranged in the same layer as the active layer of the initialization reset transistor.

14. The display panel of claim 13, wherein, The initialization reset signal line includes first initialization reset lines, a plurality of the first initialization reset lines are arranged along the first direction and extend along the second direction; 15. The display panel of claim 13, wherein, The second coupling adjustment structure is electrically connected with the first initialization reset line; along the thickness direction of the display panel, the second coupling adjustment structure overlaps the first initialization reset line. The signal line further includes a plurality of second scan signal lines, a plurality of the second scan signal lines extend along the second direction and are arranged along the first direction; 16. The display panel of claim 2, wherein, Along the thickness direction of the display panel, the first wiring part does not overlap the second scan signal line; The display panel further includes a third coupling adjustment structure; ​ The third coupling adjustment structure overlaps the second scan signal line in the thickness direction of the display panel, and the third coupling adjustment structure is configured to receive a fixed potential signal.

17. The display panel of claim 16, further comprising a pixel circuit, the pixel circuit comprising at least one first type transistor, the first type transistor comprising a first active layer; The third coupling adjustment structure comprises a third coupling subpart, and a film layer where the third coupling subpart is located is between a film layer where the substrate is located and a film layer where the first active layer is located.

18. The display panel of claim 16, further comprising a pixel circuit, the pixel circuit comprising at least one first type transistor, the first type transistor comprising a first active layer; The third coupling adjustment structure comprises a fourth coupling subpart, and a film layer where the fourth coupling subpart is located is between a film layer where the second scan signal line is located and a film layer where the first wiring subpart is located.

19. The display panel of claim 1, further comprising a pixel circuit, the pixel circuit comprising a driving transistor and a threshold compensation transistor, a gate of the driving transistor and a first pole of the threshold compensation transistor being electrically connected with a first connection structure; The display panel further comprises a first shielding structure, the first shielding structure being configured to receive a fixed potential signal; in the thickness direction of the display panel, the first shielding structure covers at least part of the first connection structure.

20. The display panel of claim 19, wherein, The pixel circuit further comprises a voltage adjustment transistor; The signal line further comprises a voltage adjustment signal line, the voltage adjustment signal line being electrically connected with a first pole of the voltage adjustment transistor; The voltage adjustment signal line comprises a second voltage adjustment subpart, the second voltage adjustment subpart extending in the first direction; The first shielding structure is electrically connected with at least part of the second voltage adjustment subpart.

21. The display panel of claim 20, wherein, The voltage adjustment transistor comprises an initialization reset transistor and an anode reset transistor; The voltage adjustment signal line comprises an initialization reset signal line and an anode reset signal line; The display panel further comprises a light emitting element; The initialization reset transistor is electrically connected between the initialization reset signal line and a gate of the driving transistor; the anode reset transistor is electrically connected between the anode reset signal line and the light emitting element; The initialization reset signal line comprises a second initialization reset line, a plurality of the second initialization reset lines extending in the first direction and arranged in the second direction, and the first shielding structure is electrically connected with the second initialization reset line; Or, The anode reset signal line comprises a second anode reset line, a plurality of the second anode reset lines extending in the first direction and arranged in the second direction, and the first shielding structure is electrically connected with the second anode reset line; Or, The initialization reset signal lines comprise second initialization reset lines, a plurality of the second initialization reset lines extend along the first direction and are arranged along the second direction, and the first shielding structure is electrically connected with the second initialization reset lines.

22. The display panel of claim 1, further comprising a pixel circuit, the pixel circuit comprising a driving transistor and a threshold compensation transistor, a gate of the driving transistor and a first pole of the threshold compensation transistor being electrically connected to a first connection structure; The data auxiliary lines comprise second trace subparts, the second trace subparts extend along the first direction and are electrically connected with the fan-out traces; The display panel further comprises a second shielding structure, the second shielding structure is configured to receive a fixed potential signal; At least part of the second shielding structure has a projection on the plane of the substrate that satisfies at least one of the following conditions: At least part of the second shielding structure has a projection on the plane of the substrate that is located between a projection of the data signal lines on the plane of the substrate and a projection of the first connection structure on the plane of the substrate; and At least part of the second shielding structure has a projection on the plane of the substrate that is located between a projection of the second trace subparts on the plane of the substrate and a projection of the first connection structure on the plane of the substrate.

23. The display panel of claim 1, further comprising a pixel circuit, the pixel circuit comprising a driving transistor and a data write transistor, a second pole of the data write transistor and a first pole of the driving transistor being electrically connected to a second connection structure; The signal lines further comprise a plurality of light-emitting control signal lines, a plurality of the light-emitting control signal lines are arranged along the first direction and extend along the second direction; The display panel further comprises a third shielding structure, the third shielding structure is configured to receive a fixed potential signal; The third shielding structure is located between a film layer in which the second connection structure is located and a film layer in which the light-emitting control signal lines are located, and a projection of the third shielding structure on the plane of the substrate overlaps with a projection of the second connection structure on the plane of the substrate and a projection of the light-emitting control signal lines on the plane of the substrate.

24. The display panel of claim 9, wherein, The voltage regulation signal lines comprise second voltage regulation subparts, the second voltage regulation subparts extend along the first direction, and the second voltage regulation subparts are located in a different layer from the first voltage regulation subparts and are electrically connected with the first voltage regulation subparts.

25. The display panel of claim 24, wherein, The signal lines further comprise a plurality of first power supply signal lines, a plurality of the first power supply signal lines extend along the first direction and are arranged along the second direction; Between two adjacent first power supply signal lines, one second voltage regulation subpart, one second trace subpart, and two data signal lines are arranged. The second voltage regulating part and the second trace part are arranged between two adjacent data signal lines, or the two data signal lines are arranged between the second voltage regulating part and the second trace part.

26. The display panel of claim 1, further comprising a virtual auxiliary line, the virtual auxiliary line is arranged in the same layer as the data auxiliary line, and there is a break between the virtual auxiliary line and the data auxiliary line; The display panel further comprises a light emitting element, along the thickness direction of the display panel, the light emitting element covers the break.

27. The display panel of claim 26, wherein, Along the thickness direction of the display panel, the first coupling adjustment structure overlaps the break.

28. The display panel of claim 1, further comprising a plurality of demultiplexing units arranged in the non-display area and at least two switch control lines; The demultiplexing unit comprises at least two demultiplexing switches, the demultiplexing switch comprises an input end, an output end and a control end; in the same demultiplexing unit, the input ends of the at least two demultiplexing switches are connected, the output ends of the at least two demultiplexing switches are respectively electrically connected with different data signal lines, the control ends of the at least two demultiplexing switches are respectively electrically connected with different switch control lines, and the data signal lines located in the second display area are electrically connected with the output ends of the demultiplexing switches through the data auxiliary line.

29. The display panel of claim 1, further comprising a light emitting element; The light emitting element comprises a first color light emitting element, a second color light emitting element and a third color light emitting element, the first color light emitting element, the second color light emitting element and the third color light emitting element are one of red light emitting element, blue light emitting element and green light emitting element and are different from each other; A plurality of the first color light emitting elements and a plurality of the second color light emitting elements constitute a first virtual quadrilateral, the first color light emitting element is located at a first vertex of the first virtual quadrilateral, the second color light emitting element is located at a second vertex of the first virtual quadrilateral, and the third color light emitting element is located inside the first virtual quadrilateral; A plurality of the third color light emitting elements constitute a second virtual quadrilateral, the plurality of the third color light emitting elements are respectively located at the vertices of the second virtual quadrilateral, and the first color light emitting element or the second color light emitting element is located inside the second virtual quadrilateral.

30. A display device comprising the display panel of any one of claims 1-29.

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