Adapter board structure and preparation method therefor

Abstract

An adapter board structure and a preparation method therefor. The adapter board structure comprises: a first adapter board (1), the first adapter board (1) comprising a first substrate (11) and a plurality of first through-silicon vias (12) passing through the first substrate (11); an interconnection layer (2) located on a side surface of the first adapter board (1), the interconnection layer (2) comprising an RDL layer (21) and a passivation layer (22) covering the RDL layer (21), and the RDL layer (21) being connected to the first through-silicon vias (12); a second adapter board (3) located on the side surface of the first adapter board (1) facing away from the interconnection layer (2), the second adapter board (3) comprising a second substrate (31) and a plurality of second through-silicon vias (32) passing through the second substrate (31); and a plurality of DTC chips (4) embedded in the side surface of the second adapter board (3) facing the first adapter board (1), the plurality of DTC chips (4) being connected to some of the first through-silicon vias (12), and the remaining first through-silicon vias (12) being connected to the second through-silicon vias (32). Accordingly, the adapter board structure enables connection to more external chips, thereby reducing the footprint of the semiconductor structure and improving the integration of the semiconductor structure, while reducing current-transmission power consumption, increasing the capacitance of silicon capacitors, and enhancing the performance and operational stability of the semiconductor structure.

Description

An adapter plate structure and a preparation method thereof

[0001] Cross-reference to Related Applications

[0002] The present application claims priority to the Chinese patent application No. 202411233320.1, filed on September 3, 2024, and entitled "An adapter plate structure and a preparation method thereof", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of adapter plate structure, and particularly relates to an adapter plate structure and a preparation method thereof. BACKGROUND

[0004] Integrated circuits are widely used in the electronics industry to provide electronic devices such as smart phones, computers, etc. An integrated circuit (IC) includes many semiconductor devices, such as transistors, capacitors, etc., which are interconnected by wiring on a semiconductor substrate. There is an increasing need for smaller and faster ICs to support a larger number of complex functions for electronic devices. Conventional organic substrates, ceramic substrates, etc. cannot meet the requirements of small line width, high wiring density, and high I / O density, and an adapter plate (especially a silicon-based adapter plate) has become the best choice for the current packaging substrate. The adapter plate can be arranged between the components and the circuit board, and the upper and lower surfaces are distributed with metal redistribution layers (RDLs). After packaging, the components are generally interconnected with the adapter plate by flip-chip bonding, and the adapter plate is interconnected with the underlying circuit board (PCB) through through-silicon vias (TSVs) or ball grid arrays (BGAs). As an intermediary bridge between components and circuit boards, the adapter plate can realize interconnection between multiple chips through RDLs, and can also realize interconnection between chip components and circuit boards,

[0005] In existing packaging technology, as the number of external chips to be connected gradually increases, a scheme of directly connecting external chips and semiconductor passive devices (such as embedded deep trench capacitors DTC) using an adapter plate can result in a larger area of the semiconductor structure, higher current transmission power consumption, lower capacitance of the silicon capacitor, and poorer performance and working stability of the semiconductor structure. In addition, the number of chips connected by a single-layer adapter plate is limited, which also increases the area of the semiconductor structure and results in lower integration of the semiconductor structure.

[0006] Therefore, there is a need for a scheme that can integrate semiconductor passive devices inside the adapter plate, connect as many external chips as possible, reduce the area of the semiconductor structure, improve the integration of the semiconductor structure, reduce current transmission power consumption, increase the capacitance of the silicon capacitor, and improve the performance and working stability of the semiconductor structure. SUMMARY

[0007] Therefore, the application provides a transition plate structure and a preparation method thereof to solve the problems of large area, low integration, high current transmission power consumption, low silicon capacitor capacity, poor performance and working stability of the semiconductor structure packaged by using the existing transition plate structure.

[0008] The application provides a transition plate structure, comprising:

[0009] A first transition plate, comprising a first substrate and a plurality of first through silicon vias penetrating through the first substrate;

[0010] An interconnection layer located on one side surface of the first transition plate, comprising an RDL layer and a passivation layer covering the RDL layer, and the RDL layer is connected with the first through silicon vias;

[0011] A second transition plate located on one side surface of the first transition plate away from the interconnection layer, comprising a second substrate and a plurality of second through silicon vias penetrating through the second substrate;

[0012] A plurality of DTC chips embedded on one side surface of the second transition plate facing the first transition plate and connected with part of the first through silicon vias; the remaining first through silicon vias are connected with the second through silicon vias.

[0013] Optionally, the first transition plate and the second transition plate are connected together by hybrid bonding.

[0014] Optionally, the DTC chips are connected with part of the first through silicon vias by hybrid bonding; and the second through silicon vias are connected with the remaining first through silicon vias by hybrid bonding.

[0015] Optionally, the DTC chips are connected with part of the first through silicon vias one by one; and the remaining first through silicon vias are connected with the second through silicon vias one by one.

[0016] Optionally, one side surface of the second transition plate facing the first transition plate has a plurality of grooves, and the DTC chips are embedded in the grooves one by one.

[0017] Optionally, the material of the passivation layer is polyimide.

[0018] The filling material of the first through silicon vias is a conductive material.

[0019] The filling material of the second through silicon vias is a conductive material.

[0020] Optionally, further comprising: a UBM metal layer located on a side surface of the interconnection layer facing away from the first adapter plate, the UBM metal layer being connected with the RDL layer; the RDL layer being adapted to connect an external chip through the UBM metal layer; the external chip being adapted to be connected with the UBM metal layer through flip-chip bonding.

[0021] A plurality of solder balls are located on a side surface of the second adapter plate facing away from the first adapter plate, the solder balls being connected with the second through silicon vias one-to-one; the solder balls being adapted to connect an external substrate.

[0022] The application also provides a preparation method of an adapter plate structure, characterized by comprising the following steps:

[0023] A first adapter plate is provided, the first adapter plate comprising a first substrate and a plurality of first through silicon vias penetrating through the first substrate;

[0024] An interconnection layer is formed on a side surface of the first adapter plate, the interconnection layer comprising an RDL layer and a passivation layer covering the RDL layer, the RDL layer being connected with the first through silicon vias;

[0025] A second adapter plate is provided, the second adapter plate comprising a second substrate and a plurality of second through silicon vias penetrating through the second substrate;

[0026] A plurality of DTC chips are embedded on a side surface of the second adapter plate;

[0027] The first adapter plate and the second adapter plate are connected, so that the DTC chips are located on a side of the second adapter plate facing the first adapter plate and are connected with part of the first through silicon vias; the remaining first through silicon vias are connected with the second through silicon vias.

[0028] Optionally, in the step of connecting the first adapter plate and the second adapter plate,

[0029] The first adapter plate and the second adapter plate are connected together through hybrid bonding;

[0030] Among them, the DTC chips and part of the first through silicon vias are connected one-to-one through hybrid bonding; the second through silicon vias and the remaining first through silicon vias are connected one-to-one through hybrid bonding.

[0031] Optionally, in the step of embedding a plurality of DTC chips on a side surface of the second adapter plate,

[0032] A plurality of grooves are formed on a side surface of the second adapter plate facing the first adapter plate; the DTC chips are embedded one-to-one in the grooves.

[0033] Optionally, after the step of forming the interconnection layer on the side surface of the first adapter plate, the method further comprises:

[0034] forming a UBM metal layer on the side surface of the interconnection layer away from the first adapter plate, the UBM metal layer being connected with the RDL layer;

[0035] after the step of connecting the first adapter plate with the second adapter plate, the method further comprises:

[0036] forming a plurality of solder balls on the side surface of the second adapter plate away from the first adapter plate, the solder balls being connected with the second through silicon vias one by one.

[0037] The technical scheme of the present application has the following advantages:

[0038] (1) The adapter plate structure provided by the present application integrates semiconductor passive devices DTCs inside the adapter plate and sets a double-layer adapter plate, which can connect more external chips on the one hand, thereby reducing the area of the semiconductor structure and improving the integration of the semiconductor structure, and can reduce the current transmission power consumption, increase the capacitance of the silicon capacitor, and improve the performance and working stability of the semiconductor structure on the other hand.

[0039] (2) The adapter plate structure provided by the present application connects the first adapter plate and the second adapter plate together through hybrid bonding technology, combines the through silicon via filling materials and DTC chips in different adapter plates and the through silicon via filling materials of different adapter plates together, and realizes firm connection of the first adapter plate and the second adapter plate.

[0040] The preparation method of the adapter plate structure provided by the present application can prepare the adapter plate structure provided by the present application. The adapter plate structure provided by the present application integrates semiconductor passive devices DTCs inside the adapter plate and sets a double-layer adapter plate, which can connect more external chips on the one hand, thereby reducing the area of the semiconductor structure and improving the integration of the semiconductor structure, and can reduce the current transmission power consumption, increase the capacitance of the silicon capacitor, and improve the performance and working stability of the semiconductor structure on the other hand. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical scheme in the specific embodiments or prior art of the present application, the drawings needed in the description of the specific embodiments or prior art will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0042] FIG. 1 is a structural schematic view of an adapter plate structure according to an embodiment of the present application;

[0043] Fig. 2 is a flowchart of a method for manufacturing a structure of a transition plate according to an embodiment of the present application;

[0044] Fig. 3 is a flowchart of a method for manufacturing a structure of a transition plate according to an embodiment of the present application;

[0045] Figs. 4-8 are structural diagrams of various processes of a method for manufacturing a structure of a transition plate according to an embodiment of the present application.

[0046] Legend: 1 - first transition plate; 2 - interconnection layer; 3 - second transition plate; 4 - plurality of DTC chips; 11 - first substrate; 12 - first through-silicon via; 21 - RDL layer; 22 - passivation layer; 31 - second substrate; 32 - second through-silicon via; 5 - UBM metal layer; 6 - solder ball. DETAILED DESCRIPTION

[0047] To solve the problems of a large area, low integration, high current transmission power consumption, low silicon capacitance, poor performance and working stability of a semiconductor structure packaged by using an existing structure of a transition plate, the present application provides a structure of a transition plate, which comprises: a first transition plate, the first transition plate comprising a first substrate and a plurality of first through-silicon vias penetrating through the first substrate; an interconnection layer located on one side surface of the first transition plate, the interconnection layer comprising an RDL layer and a passivation layer covering the RDL layer, the RDL layer being connected with the first through-silicon vias; a second transition plate located on one side surface of the first transition plate facing away from the second transition plate, the second transition plate comprising a second substrate and a plurality of second through-silicon vias penetrating through the second substrate; a plurality of DTC chips embedded on one side surface of the second transition plate facing the first transition plate and connected with part of the first through-silicon vias; and the remaining first through-silicon vias being connected with the second through-silicon vias.

[0048] The present application also provides a method for manufacturing a structure of a transition plate, which comprises the following steps: providing a first transition plate, the first transition plate comprising a first substrate and a plurality of first through-silicon vias penetrating through the first substrate; forming an interconnection layer on one side surface of the first transition plate, the interconnection layer comprising an RDL layer and a passivation layer covering the RDL layer, the RDL layer being connected with the first through-silicon vias; providing a second transition plate, the second transition plate comprising a second substrate and a plurality of second through-silicon vias penetrating through the second substrate; embedding a plurality of DTC chips on one side of the second transition plate; connecting the first transition plate with the second transition plate, so that the DTC chips are located on one side of the second transition plate facing the first transition plate and connected with part of the first through-silicon vias; and the remaining first through-silicon vias being connected with the second through-silicon vias.

[0049] The technical solutions of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of the present application. In the description of the present application, it should be noted that the terms "first", "second", "third" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0050] Embodiment 1

[0051] Referring to FIG. 1, the present embodiment provides a structure of a transition board, comprising:

[0052] a first transition board 1, the first transition board 1 comprising a first substrate 11 and a plurality of first through silicon vias 12 penetrating the first substrate 11;

[0053] an interconnection layer 2 located on one side surface of the first transition board 1, the interconnection layer 2 comprising an RDL layer 21 and a passivation layer 22 covering the RDL layer 21, the RDL layer 21 being connected with the first through silicon vias 12;

[0054] a second transition board 3 located on one side surface of the first transition board 1 away from the interconnection layer 2, the second transition board 3 comprising a second substrate 31 and a plurality of second through silicon vias 32 penetrating the second substrate 31;

[0055] a plurality of DTC chips 4 embedded on one side surface of the second transition board 3 facing the first transition board 1 and connected with part of the first through silicon vias 12; the remaining first through silicon vias 12 being connected with the second through silicon vias 32.

[0056] The structure of the transition board provided by the present embodiment integrates semiconductor passive devices DTC inside the transition board and sets a double-layer transition board, which can connect more external chips on one hand, thereby reducing the area of the semiconductor structure and improving the integration of the semiconductor structure, and on the other hand, can reduce the power consumption of current transmission, increase the capacitance of silicon capacitors, and improve the performance and working stability of the semiconductor structure.

[0057] Optionally, in the present embodiment, the first transition board 1 and the second transition board 3 are connected together by hybrid bonding;

[0058] wherein the DTC chips 4 are connected with part of the first through silicon vias 12 by hybrid bonding; and the second through silicon vias 32 are connected with the remaining first through silicon vias 12 by hybrid bonding.

[0059] In actual implementation, the inner wall of the first adapter plate 1 and the inner wall of the first through silicon via 12, the surface of the second adapter plate 3 and the inner wall of the second through silicon via 32 are provided with a SiO2 insulation layer. Therefore, mixed bonding is performed by using the metal layer (such as Cu) exposed on the surface of the DTC chip 4, the metal (such as Cu) filled in the first through silicon via 12, the SiO2 on the inner wall of the first through silicon via 12 and the SiO2 on the surface of the two adapter plates, so as to realize the connection between the DTC chip 4 and part of the first through silicon via 12; and mixed bonding is performed by using the metal (such as Cu) filled in the first through silicon via 12, the metal (such as Cu) filled in the second through silicon via 32, the SiO2 on the inner wall of the remaining first through silicon via 12, the SiO2 on the inner wall of the second through silicon via 32 and the SiO2 on the surface of the two adapter plates, so as to realize the connection between the second through silicon via 32 and the remaining first through silicon via 12.

[0060] In the embodiment, the first adapter plate and the second adapter plate are connected together by using the mixed bonding technology, the through silicon via filling materials in different adapter plates and the DTC chip are combined together, and the through silicon via filling materials in different adapter plates are combined together, so as to realize the firm connection between the first adapter plate and the second adapter plate.

[0061] Optionally, in the embodiment, the DTC chip 4 is connected in one-to-one correspondence with part of the first through silicon via 12; and the remaining first through silicon via 12 is connected in one-to-one correspondence with the second through silicon via 32.

[0062] Optionally, in the embodiment, the surface of the side of the second adapter plate 3 facing the first adapter plate 1 is provided with a plurality of grooves, and the DTC chip 4 is embedded in the grooves in one-to-one correspondence.

[0063] Optionally, in the embodiment, the material of the passivation layer 22 is polyimide.

[0064] The filling material of the first through silicon via 12 is a conductive material, for example, copper, tungsten or the like.

[0065] The filling material of the second through silicon via 32 is a conductive material, for example, copper, tungsten or the like.

[0066] Optionally, in the embodiment, further comprising: a UBM metal layer 5 located on the side surface of the interconnection layer 2 away from the first adapter plate 1, the UBM metal layer 5 being connected with the RDL layer 21; the RDL layer 21 being adapted to connect an external chip through the UBM metal layer 5; and the external chip being adapted to be connected with the UBM metal layer 5 through flip-chip bonding.

[0067] A plurality of solder balls 6 are located on the side surface of the second adapter plate 3 away from the first adapter plate 1, the solder balls 6 being connected in one-to-one correspondence with the second through silicon via 32; and the solder balls 6 being adapted to connect an external substrate.

[0068] Embodiment 2

[0069] Referring to FIG. 2, the application further provides a preparation method of the adapter plate structure, which is used for preparing the adapter plate structure of Embodiment 1. The method comprises the following steps:

[0070] S201, providing a first adapter plate, wherein the first adapter plate comprises a first substrate and a plurality of first through silicon vias penetrating through the first substrate;

[0071] S202, forming an interconnection layer on one side surface of the first adapter plate, wherein the interconnection layer comprises an RDL layer and a passivation layer covering the RDL layer, and the RDL layer is connected with the first through silicon vias;

[0072] S203, providing a second adapter plate, wherein the second adapter plate comprises a second substrate and a plurality of second through silicon vias penetrating through the second substrate;

[0073] S204, embedding a plurality of DTC chips on one side of the second adapter plate;

[0074] S205, connecting the first adapter plate with the second adapter plate, so that the DTC chips are located on the side of the second adapter plate facing the first adapter plate and connected with part of the first through silicon vias, and the remaining first through silicon vias are connected with the second through silicon vias.

[0075] The adapter plate structure provided by the embodiment can connect more external chips by integrating semiconductor passive devices DTCs inside the adapter plate and arranging double-layer adapter plates, thereby reducing the area of the semiconductor structure, improving the integration of the semiconductor structure, reducing the current transmission power consumption, increasing the capacitance of the silicon capacitor, and improving the performance and working stability of the semiconductor structure.

[0076] Optionally, in some embodiments, in the step of connecting the first adapter plate with the second adapter plate,

[0077] the first adapter plate and the second adapter plate are connected together by hybrid bonding;

[0078] wherein the DTC chips and part of the first through silicon vias are connected one by one through hybrid bonding, and the second through silicon vias and the remaining first through silicon vias are connected one by one through hybrid bonding.

[0079] In the process of preparing the first adapter plate and the second adapter plate, a SiO2 layer is deposited on the inner wall of the first adapter plate and the inner wall of the first through silicon via, the surface of the second adapter plate and the inner wall of the second through silicon via as an insulating layer before the first through silicon via and the second through silicon via are filled. Therefore, in the embodiment, mixed bonding is performed by using the metal layer (such as Cu) exposed on the surface of the DTC chip, the metal (such as Cu) filled in the first through silicon via, the SiO2 on the inner wall of the first through silicon via and the SiO2 on the surface of the adapter plate, so as to realize the connection between the DTC chip and part of the first through silicon via; and mixed bonding is performed by using the metal (such as Cu) filled in the first through silicon via, the metal (such as Cu) filled in the second through silicon via, the SiO2 on the remaining inner wall of the first through silicon via, the SiO2 on the inner wall of the second through silicon via and the SiO2 on the surface of the adapter plate, so as to realize the connection between the second through silicon via and the remaining first through silicon via.

[0080] Optionally, in some embodiments, the step of embedding a plurality of DTC chips on one side of the second adapter plate comprises:

[0081] forming a plurality of grooves on the surface of the side of the second adapter plate facing the first adapter plate; and embedding the DTC chips into the grooves one by one.

[0082] In particular implementation, the second adapter plate with the second through silicon via can be formed first, and then the grooves are formed on the second adapter plate; or the grooves can be formed on the second substrate first, and then the DTC chips are embedded, and then the second through silicon via is formed.

[0083] In one example, a plurality of second through silicon vias are formed on the second substrate first, then a plurality of grooves are formed between adjacent two second through silicon vias on one side of the second substrate, and finally the DTC chips are embedded into the grooves one by one.

[0084] In another example, a plurality of grooves are formed on the second substrate first, then the DTC chips are embedded into the grooves one by one, and finally a plurality of second through silicon vias are formed between adjacent two grooves on the second substrate.

[0085] Optionally, in some embodiments, after the step of forming the interconnection layer on the surface of one side of the first adapter plate, the method further comprises:

[0086] forming a UBM metal layer on the surface of the side of the interconnection layer away from the first adapter plate, wherein the UBM metal layer is connected with the RDL layer;

[0087] after the step of connecting the first adapter plate with the second adapter plate, the method further comprises:

[0088] A plurality of solder balls are formed on a side surface of the second adapter plate facing away from the first adapter plate, and the solder balls are connected to the second through silicon vias one by one.

[0089] In one specific embodiment, the present embodiment also provides a specific preparation method of the adapter plate structure, referring to FIG. 3, including steps S301-S307:

[0090] S301, a plurality of first through silicon vias are formed on a surface of a first substrate to form a first adapter plate.

[0091] S302, an interconnection layer is formed on a side surface of the first adapter plate, the interconnection layer including an RDL layer and a passivation layer covering the RDL layer, and the RDL layer is connected to the first through silicon vias.

[0092] S303, a UBM metal layer is formed on a side surface of the interconnection layer facing away from the first adapter plate, and the UBM metal layer is connected to the RDL layer, as shown in FIG. 4.

[0093] S304, a plurality of recesses are formed on a second substrate, and a plurality of DTC chips are embedded in the recesses one by one, as shown in FIG. 5.

[0094] S305, a plurality of second through silicon vias are formed between adjacent two recesses of the second substrate to form a second adapter plate, as shown in FIG. 6.

[0095] S306, the first adapter plate and the second adapter plate are connected together by hybrid bonding; wherein the DTC chips and part of the first through silicon vias are connected one by one by hybrid bonding, and the second through silicon vias and the remaining first through silicon vias are connected one by one by hybrid bonding, as shown in FIG. 7.

[0096] S307, a plurality of solder balls are formed on a side surface of the second adapter plate facing away from the first adapter plate, and the solder balls are connected to the second through silicon vias one by one, as shown in FIG. 8.

[0097] Obviously, the above-mentioned embodiments are only examples for clear illustration, and are not a limitation on the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments need not and cannot be exhausted. The changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. An adapter plate structure, characterized by, Comprising: a first adapter plate comprising a first substrate and a plurality of first through silicon vias penetrating through the first substrate; an interconnection layer on a side surface of the first adapter plate, the interconnection layer comprising an RDL layer and a passivation layer covering the RDL layer, the RDL layer being connected with the first through silicon vias; a second adapter plate on a side surface of the first adapter plate facing away from the interconnection layer, the second adapter plate comprising a second substrate and a plurality of second through silicon vias penetrating through the second substrate; a plurality of DTC chips embedded on a side surface of the second adapter plate facing the first adapter plate and connected with part of the first through silicon vias; the remaining first through silicon vias being connected with the second through silicon vias.

2. The adapter plate structure according to claim 1, wherein: the first adapter plate and the second adapter plate are connected together by hybrid bonding; wherein the DTC chips are connected with part of the first through silicon vias by hybrid bonding; the second through silicon vias are connected with the remaining first through silicon vias by hybrid bonding.

3. The adapter plate structure according to claim 2, wherein: the DTC chips are connected with part of the first through silicon vias one-to-one; the remaining first through silicon vias are connected with the second through silicon vias one-to-one.

4. The adapter plate structure according to claim 1, wherein: a side surface of the second adapter plate facing the first adapter plate has a plurality of grooves, the DTC chips are embedded in the grooves one-to-one.

5. The adapter plate structure according to claim 1, wherein: the material of the passivation layer is polyimide; the filling material of the first through silicon vias is conductive material; the filling material of the second through silicon vias is conductive material.

6. The adapter plate structure of claim 1, wherein, Further comprising: a UBM metal layer on a side surface of the interconnection layer facing away from the first adapter plate, the UBM metal layer being connected with the RDL layer; the RDL layer is adapted to connect external chips through the UBM metal layer; the external chips are adapted to be connected with the UBM metal layer by flip-chip bonding; a plurality of solder balls on a side surface of the second adapter plate facing away from the first adapter plate, the solder balls being connected with the second through silicon vias one-to-one; the solder balls are adapted to connect external substrates.

7. A method of manufacturing a board structure, characterized by, Comprising the following steps: providing a first adapter plate comprising a first substrate and a plurality of first through silicon vias penetrating through the first substrate; forming an interconnection layer on a side surface of the first adapter plate, the interconnection layer comprising an RDL layer and a passivation layer covering the RDL layer, the RDL layer being connected with the first through silicon vias; providing a second adapter plate comprising a second substrate and a plurality of second through silicon vias penetrating through the second substrate; embedding a plurality of DTC chips on a side surface of the second adapter plate; connecting the first adapter plate and the second adapter plate so that the DTC chips are located on a side surface of the second adapter plate facing the first adapter plate and connected with part of the first through silicon vias; the remaining first through silicon vias are connected with the second through silicon vias.

8. The preparation method of the adapter plate structure according to claim 7, wherein: The step of connecting the first adapter plate and the second adapter plate, The first adapter plate and the second adapter plate are connected together by hybrid bonding; Among them, the DTC chip and part of the first through silicon via are connected one by one through hybrid bonding; the second through silicon via and the remaining first through silicon via are connected one by one through hybrid bonding.

9. The preparation method of the adapter plate structure according to claim 7, wherein, The step of embedding a plurality of DTC chips on one side of the second adapter plate, A plurality of grooves are formed on the side surface of the second adapter plate facing the first adapter plate; the DTC chips are embedded one by one in the grooves.

10. The preparation method of the adapter plate structure according to claim 7, wherein, After the step of forming an interconnection layer on the side surface of the first adapter plate, further comprising: An UBM metal layer is formed on the side surface of the interconnection layer away from the first adapter plate, and the UBM metal layer is connected with the RDL layer; After the step of connecting the first adapter plate and the second adapter plate, further comprising: A plurality of solder balls are formed on the side surface of the second adapter plate away from the first adapter plate, and the solder balls are connected one by one with the second through silicon via.

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