Display apparatus and driving method

Abstract

A display apparatus and a driving method. A display apparatus (300a, 300b, 800, 1100) comprises: a display panel (310, 810, 1110) comprising a plurality of pixel circuits (400); and a drive circuit (320, 820, 1120) electrically connected to the display panel (310, 810, 1110) and m first clock terminals, wherein the drive circuit (320, 820, 1120) is configured to output a first scan signal to the display panel (310, 810, 1110), and on the basis of m first clock signals of the m first clock terminals, output a reset signal to the display panel (310, 810, 1110), the reset signal is used for controlling an initialization signal to initialize drive transistors, the first scan signal is used for controlling a data signal to be written into the drive transistors in the plurality of pixel circuits (400), the duration of an active level of the first scan signal is greater than or equal to a preset value, the preset value is determined on the basis of the duration of an active level of the reset signal, and the duration of the active level of the reset signal is (1+m)K*H, K being the number of rows of pixel circuits driven by the reset signal, and H being the ratio of a display frame rate to the total number of rows of pixel circuits (400) of the display panel (310, 810, 1110).

Description

Display device and driving method

[0001] This application claims priority to Chinese Patent Application No. 202411237417.X, filed September 4, 2024, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a display device and a driving method. BACKGROUND

[0003] Some display products usually use local refresh technology for picture display to reduce the data line loss caused by picture refresh. However, the connection between two areas in the display picture refreshed at different refresh rates will appear display uneven phenomenon, thereby affecting the display effect. SUMMARY

[0004] The present disclosure provides a display device and a driving method.

[0005] According to a first aspect, the present disclosure provides a display device, comprising: a display panel comprising a plurality of pixel circuits; a driving circuit electrically connected with the display panel and m first clock terminals, the driving circuit being configured to output a first scan signal to the display panel, and output a reset signal to the display panel based on m first clock signals of the m first clock terminals, the reset signal being used to control initialization of a driving transistor by an initialization signal, and the first scan signal being used to control writing of a data signal into the driving transistor in the plurality of pixel circuits; wherein a duration of an effective level of the first scan signal is greater than or equal to a preset value, the preset value being determined based on a duration of an effective level of the reset signal, the duration of the effective level of the reset signal being (1+m)K*H, m and K being positive integers, K being a number of pixel circuit rows driven by the reset signal, and H being a ratio of a display frame rate to a total number of pixel circuit rows of the display panel.

[0006] According to a second aspect, the present disclosure provides a driving method, comprising: outputting a first scan signal to a display panel, and outputting a reset signal to the display panel based on m first clock signals of m first clock terminals, the reset signal being used to control initialization of a driving transistor by an initialization signal, and the first scan signal being used to control writing of a data signal into the driving transistor in a plurality of pixel circuits of the display panel; wherein a duration of an effective level of the first scan signal is greater than or equal to a preset value, the preset value being determined based on a duration of an effective level of the reset signal, the duration of the effective level of the reset signal being (1+m)K*H, m and K being positive integers, K being a number of pixel circuit rows driven by the first scan signal and the reset signal, and H being a ratio of a display frame rate to a total number of pixel circuit rows of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0007] FIG. 1 shows a schematic diagram of a principle of a partial refresh according to an embodiment of the present disclosure;

[0008] FIG. 2 shows a schematic diagram of a display screen of a partial refresh according to an embodiment of the present disclosure;

[0009] FIG. 3A shows a schematic diagram of a structure of a display device according to an embodiment of the present disclosure;

[0010] FIG. 3B shows a schematic diagram of a structure of a display device according to another embodiment of the present disclosure;

[0011] FIG. 4A shows a schematic diagram of a structure of a pixel circuit according to an embodiment of the present disclosure;

[0012] FIG. 4B shows a schematic diagram of a structure of an output unit of a driving circuit according to an embodiment of the present disclosure;

[0013] FIG. 4C shows a schematic diagram of a timing of a scan signal and a working power supply voltage according to an embodiment of the present disclosure;

[0014] FIG. 5 shows a schematic diagram of a timing of a scan signal and a working power supply voltage according to another embodiment of the present disclosure;

[0015] FIG. 6 shows a schematic diagram of a timing of a scan signal according to an embodiment of the present disclosure;

[0016] FIG. 7A shows a schematic diagram of a timing of a driving signal according to an embodiment of the present disclosure;

[0017] FIG. 7B shows a schematic diagram of a timing of a driving signal according to another embodiment of the present disclosure;

[0018] FIG. 8 shows a schematic diagram of a structure of a display device according to another embodiment of the present disclosure;

[0019] FIG. 9 shows a schematic diagram of a timing of a scan signal and a working power supply voltage according to another embodiment of the present disclosure;

[0020] FIG. 10 shows a schematic diagram of compensation of a working power supply voltage according to an embodiment of the present disclosure;

[0021] FIG. 11 shows a schematic diagram of a structure of a display device according to another embodiment of the present disclosure;

[0022] FIG. 12 shows a schematic diagram of a structure of a control circuit according to an embodiment of the present disclosure;

[0023] FIG. 13 shows a schematic diagram of a timing of a scan signal and a working power supply voltage according to another embodiment of the present disclosure; and

[0024] FIG. 14 shows a schematic diagram of a flow of a driving method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the accompanying drawings to make a clear and complete description of the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure. In the following description, some specific embodiments are only for the purpose of description, and should not be understood as any limitation on the present disclosure, but only as examples of the embodiments of the present disclosure. When it is possible to cause confusion to the understanding of the present disclosure, the conventional structures or configurations will be omitted. It should be noted that the shapes and sizes of the components in the drawings do not reflect the actual sizes and proportions, but only illustrate the contents of the embodiments of the present disclosure.

[0026] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood as the common meanings of the terms by the person skilled in the art. The terms "first", "second" and the like used in the embodiments of the present disclosure do not represent any order, number or importance, but are only used to distinguish different components.

[0027] In addition, in the description of the embodiments of the present disclosure, the term "connected to" or "connected" can mean that two components are directly connected, or that two components are connected via one or more other components, and the connection mode is electrical connection or electrical coupling. In addition, the two components can also be connected or coupled by wired or wireless means.

[0028] It should be noted that in the description of the embodiments of the present disclosure, the node nodeM is not an actual component in the circuit, but represents a certain point on a certain circuit in the circuit diagram. The symbol CLK can represent a clock terminal, a clock signal, or a clock signal level. The following embodiments are the same, and will not be described again.

[0029] FIG. 1 shows a schematic diagram of the principle of an example partial refresh.

[0030] As shown in FIG. 1, the display screen 100 can be a display screen of any display device. In the display screen 100, the region 101 displays weather information, and the region 102 displays time information. The display screen in the regions 101 and 102 needs to be refreshed in real time. The regions in the display screen 100 other than the regions 101 and 102 can be kept static display, and the display screen is not refreshed.

[0031] For example, the horizontal direction signal pulse HCT pulse can be a pulse of a scanning signal, and the vertical direction signal pulse VCT pulse can be a pulse of a data signal.

[0032] In the row direction of the display screen 100, the horizontal signal pulse HCT pulse can control the transistor in the pixel circuit in the region 101 and the region 102 to be turned on, so that the vertical signal pulse VCT pulse is written into the pixel circuit in the region 101 and the region 102 in the column direction of the display screen 100. This makes the region 101 and the region 102 realize the refresh in the row direction.

[0033] For the region in the display screen 100 except the region 101 and the region 102, the horizontal signal pulse HCT pulse can control the transistor in the pixel circuit in the region to be turned off, and the vertical signal pulse VCT pulse cannot be written, so the region will not be refreshed.

[0034] FIG. 2 shows a schematic diagram of an example of a partially refreshed display screen.

[0035] As shown in FIG. 2, the display screen 200 includes a region 201 and a region 202, the region 201 is a high refresh region, and the region 202 is a low refresh region. For example, the refresh rate of the region 201 can be 120 Hz, and the refresh rate of the region 202 can be 30 Hz.

[0036] There is a luminance gradient stripe region in the part of the region 201 close to the region 202, in which the luminance of the pixel row in the region 201 closer to the region 202 is larger, which leads to the phenomenon of luminance unevenness in the display screen 200, thereby limiting the application of the partially refreshed display device.

[0037] The display device provided by the present disclosure can control the conduction ability of the transistor in the pixel circuit and the writing ability of the data signal in the display panel by controlling the level and the level duration of the scanning signal provided to the display panel by the driving circuit, thereby improving the luminance unevenness phenomenon in the display screen.

[0038] FIG. 3A shows a structural schematic diagram of a display device according to an embodiment of the present disclosure.

[0039] As shown in FIG. 3A, the display device 300a includes a display panel 310 and a driving circuit 320.

[0040] In an embodiment of the present disclosure, the display panel 310 includes a plurality of pixel circuits, and the plurality of pixel circuits can be arranged in an array. For example, the display panel 310 can be an organic light emitting diode (OLED) display panel, and each pixel unit includes one light emitting element. The display panel 110 displays a picture after the light emitting element in the display panel 110 is lit.

[0041] In the embodiment of the present disclosure, the driving circuit 320 is electrically connected with the display panel 310 and m first clock terminals CLK1-1, …, CLK1-m. The driving circuit outputs a first scan signal to the display panel 310, and outputs a reset signal to the display panel based on m first clock signals CLK1-1, …, CLK1-m of the m first clock terminals CLK1-1, …, CLK1-m. The first scan signal and the reset signal can control different transistors in the pixel circuit to switch between the on state and the off state.

[0042] The first scan signal and the reset signal are used to jointly control the initialization of the driving transistor in the pixel circuit by the initialization signal. The effective level of the reset signal can control a transistor in the pixel circuit to be turned on, and the effective level of the first scan signal can control another transistor in the pixel circuit to be turned on, so that the initialization signal can be provided to the control electrode of the driving transistor through the two transistors, thereby initializing the driving transistor.

[0043] The first scan signal is also used to control the writing of the data signal to the driving transistor in the plurality of pixel circuits. For example, when the control electrode of the driving transistor is initialized by the initialization signal, the initialization signal also charges the storage capacitor, so that the level stored in the storage capacitor can control the driving transistor to be turned on. After the initialization is completed, the storage capacitor is discharged so that the driving transistor is turned on, the transistor controlled by the first scan signal is turned on, and the transistor controlled by the reset signal is turned off, and the data signal is written to the control electrode of the driving transistor through the turned-on transistor.

[0044] After the data signal is written to the control electrode of the driving transistor, the driving transistor is in the on state. The driving current can be provided to the light emitting element through the driving transistor, and the light emitting element is driven to emit light.

[0045] The driving circuit 320 can be a gate driving circuit, which provides the first scan signal and the reset signal for the pixel circuit. The data signal can be provided by a source driving circuit. The first scan signal and the reset signal control the transistors in the pixel circuit to be turned on, so that the data signal is written, thereby driving the light emitting element to emit light.

[0046] In the embodiment of the present disclosure, the duration of the effective level of the first scan signal is greater than or equal to a preset value, and the preset value is determined based on the duration of the effective level of the reset signal. The duration of the effective level of the reset signal is (1+m)K*H, K is a positive integer, K is the number of rows of pixel circuits driven by the reset signal, and H is the ratio of the display frame rate to the total number of rows of pixel circuits of the display panel 310. For example, the duration of the reset signal scanning one row of pixel circuits is 1H.

[0047] In the embodiments of the present disclosure, the driving circuit 320 can include a first driving sub-circuit and a second driving sub-circuit, and the first driving sub-circuit and the second driving sub-circuit provide the first scan signals and the reset signals respectively. For example, the first driving sub-circuit and the second driving sub-circuit each include a plurality of cascaded shift registers. The plurality of cascaded shift registers included in the first driving sub-circuit can sequentially shift and output a plurality of first scan signals based on m second clock signals of m second clock terminals, and the plurality of cascaded shift registers included in the second driving sub-circuit can sequentially shift and output a plurality of reset signals based on m first clock signals of m first clock terminals CLK1-1, …, CLK1-m. The plurality of first scan signals and the plurality of reset signals are sequentially provided to a plurality of rows of pixel circuits in the display panel 310. A single first scan signal can be provided to K rows of pixel circuits in the display panel 310, and the time length of the first scan signal for scanning a row of pixel circuits is about 1H.

[0048] In the refreshing process of a frame of display image, the levels of the plurality of first scan signals output by the plurality of shift registers are all valid levels in the same time period. At least two shift registers outputting the first scan signals with valid levels output the working power supply voltage of the working power supply at the same time, which causes the working power supply voltage for providing the valid levels of the first scan signals to be unstable, and causes the valid levels of the plurality of first scan signals to be unstable, thereby affecting the writing of the data signals to the pixel circuits and causing the display panel to have a brightness uneven phenomenon.

[0049] In the embodiments of the present disclosure, the time length of the valid level of the first scan signal output by the driving circuit 320 is shortened to shorten the time length of the valid level of the first scan signal. Since the time length of the valid level of the plurality of first scan signals is shortened, the number of the first scan signals with valid levels at a certain moment is also reduced, and thus the influence on the working power supply voltage is reduced, thereby improving the stability of the working power supply voltage.

[0050] In the embodiments of the present disclosure, before the first scan signal controls the writing of the data signal to the driving transistor, the valid level of the first scan signal and the valid level of the reset signal jointly control the writing of the initialization signal to the driving transistor. After the writing of the initialization signal is completed, the time duration of the valid level of the reset signal ends.

[0051] After the time duration of the valid level of the reset signal ends, the valid level of the first scan signal controls the writing of the data signal to the driving transistor. Therefore, the time length of the valid level of the first scan signal is determined based on the time length of the valid level of the reset signal. For example, the valid level of the reset signal is a low level, and the level of the first scan signal is a high level.

[0052] In the initialization phase, the level of the reset signal remains low. In the data writing phase, the level of the reset signal remains low. In the initialization phase and the data writing phase, the level of the first scan signal remains high. The duration of the active level of the first scan signal is greater than the duration of the active level of the reset signal.

[0053] Under the premise of ensuring that the reset signal can control the initialization signal to completely initialize the driving transistor, the driving circuit 320 can shorten the duration of the active level of the reset signal as much as possible. The preset value is determined based on the duration of the active level of the reset signal. The preset value can be the shortest duration of the active level of the first scan signal. The shortest duration of the active level of the first scan signal can be determined based on the shortest duration of the active level of the reset signal.

[0054] The shortest duration means that if the duration of the active level of the first scan signal is greater than or equal to the shortest duration, the active level of the first scan signal can achieve initialization of the driving transistor and data writing to the driving transistor.

[0055] In the embodiments of the present disclosure, the duration of the active level of the reset signal is (1+m)K*H, m and K are positive integers, and K is the number of rows of pixel circuits driven by the reset signal. For example, a single reset signal can also be provided to K rows of pixel circuits of the display panel 310, and a single first scan signal can be provided to K rows of pixel circuits of the display panel 310.

[0056] For example, m is an even number, m=2. The levels of the first clock signal CLK1-1 and the first clock signal CLK1-2 are opposite to each other, for example, the first clock signal CLK1-1 and the first clock signal CLK1-2 are not simultaneously active. For example, the first clock signal CLK1-1 is provided to the first-stage shift register in the second driving sub-circuit, and the first clock signal CLK1-2 is provided to the second-stage shift register. When the reset signal output by the first-stage shift register is provided to 2 rows of pixel circuits, the clock period of the first clock signal CLK1-1 and the first clock signal CLK1-2 is 2*2=4H. For example, the high level of the first clock signal CLK1-1 is maintained for 2H, and at this time, the low level of the first clock signal CLK1-2 is located for 2H. The low level of the first clock signal CLK1-1 is maintained for 2H, and at this time, the high level of the first clock signal CLK1-2 is located for 2H. Similarly, the clock period of the second clock signal CLK2-1 and the second clock signal CLK2-2 is also 4H.

[0057] In the theoretical application scenario, the reset signal scans K rows of pixel circuits, which needs K*H time, and thus the duration of the effective level of the reset signal can be K*H. In the actual application scenario, because there is a rising delay and a falling delay when the signal level is switched, in order to ensure that the reset signal can complete the complete initialization of the driving transistor, the duration of the effective level of the reset signal can be controlled to increase by one clock cycle, and thus the duration of the effective level of the reset signal is (1+m)K*H. For example, m=2, the duration of the effective level of the reset signal is (K+2K)*H, and under the control of the reset signal with the duration of 3K*H of the effective level, the complete initialization of the driving transistor by the initialization signal can be completed.

[0058] In the embodiment of the present disclosure, the shortest duration of the effective level of the reset signal can be (1+m)K*H, and the shortest duration of the effective level of the first scanning signal is determined based on the shortest duration of the effective level of the reset signal, so that the complete initialization of the driving transistor and the complete writing of the data signal into the driving transistor can be ensured.

[0059] In the embodiment of the present disclosure, by controlling the duration of the effective level of the first scanning signal provided to the display panel by the driving circuit 320, the stability of the working power supply voltage can be improved, and thus the stability of the driving of the pixel circuit can be improved, so as to improve the brightness unevenness in the display picture.

[0060] FIG. 3B shows a structural schematic diagram of a display device according to another embodiment of the present disclosure.

[0061] As shown in FIG. 3B, the display device 300b includes a display panel 310 and a driving circuit 320.

[0062] In the embodiment of the present disclosure, the driving circuit 320 is electrically connected to m first clock terminals CLK1-1, …, CLK1-m, a second clock terminal CLK2, and a third clock terminal CLK3.

[0063] The driving circuit 320 outputs the first scanning signal under the control of the second clock terminal CLK2 and the second clock signal. The driving circuit 320 outputs the second scanning signal under the control of the third clock signal CLK3 from the third clock terminal CLK3. The second scanning signal is used to control the writing of the data signal into the plurality of pixel circuits.

[0064] In the embodiments of the present disclosure, the first scan signal and the second scan signal can control different transistors in the pixel circuit to switch between the on state and the off state. The second scan signal is used to control the data signal to be written into the plurality of pixel circuits in the display panel 310. For example, the active level of the second scan signal controls a transistor to be turned on, and the active level of the first scan signal can control another transistor in the pixel circuit to be turned on, so that the data signal can pass through the two transistors and be provided to the control electrode of the driving transistor, thereby writing the data signal into the driving transistor.

[0065] When the data signal is written into the driving transistor, the data signal also charges the storage capacitor, so that the level of the data signal stored in the storage capacitor can control the driving transistor to be turned on. In the light-emitting stage after the data writing is completed, the storage capacitor is discharged so that the driving transistor is turned on. The driving current can be provided to the light-emitting element through the driving transistor to drive the light-emitting element to emit light.

[0066] In the embodiments of the present disclosure, after the duration of the active level of the reset signal ends, the active level of the second scan signal controls the data signal to be written into the pixel circuit. After the data signal is completely written into the pixel circuit, the duration of the active level of the second scan signal ends to avoid that the data signal belonging to other pixel circuits is not written. After the duration of the active level of the second scan signal ends, the active level of the first scan signal controls the data signal to be written into the driving transistor. Therefore, the duration of the active level of the first scan signal is related to the duration of the active level of the second scan signal.

[0067] Under the premise that the reset signal can control the initialization signal to completely initialize the driving transistor, the driving circuit 320 can shorten the duration of the active level of the reset signal as much as possible. Under the premise that the second scan signal can control the data signal to be written into the pixel circuit, the driving circuit 320 can shorten the duration of the active level of the second scan signal as much as possible. Based on the duration of the active level of the second scan signal and the duration of the active level of the reset signal, a preset value is determined. Based on the shortest duration of the active level of the reset signal and the shortest duration of the active level of the second scan signal, the shortest duration of the active level of the first scan signal can be determined.

[0068] In the embodiments of the present disclosure, the preset value can be the sum of the duration of the active level of the reset signal, the duration of the active level of the second scan signal, and the duration required for the data signal to be completely written into the driving transistor. If the duration of the active level of the first scan signal is the preset value, the active level of the first scan signal can realize the initialization of the driving transistor and the data writing to the driving transistor in an ideal state.

[0069] In actual driving process, there is a certain delay in the rising process and the falling process of the level, and therefore the minimum value in the preset range can be slightly greater than the sum of the duration of the effective level of the reset signal, the duration of the effective level of the second scanning signal and the duration required for the data signal to be completely written into the driving transistor.

[0070] In the embodiment of the present disclosure, a single second scanning signal is provided to 1 row of pixel circuits of the display panel 310, for providing the data signal belonging to the row of pixel circuits to the inside of the row of pixel circuits. The duration of the effective level of the second scanning signal is 1H, so as to avoid the data signal belonging to other pixel circuits from being written without writing.

[0071] Since the first scanning signal is provided to K rows of pixel circuits in the display panel 310, K second scanning signals and 1 first scanning signal are required to realize the scanning of the K rows of pixel circuits, so that the data signal can be written into the K rows of pixel circuits in sequence. Therefore, the duration of the effective level of the second clock signal is K times of the duration of the effective level of the third clock signal.

[0072] The clock period of the second clock signal is also twice of the clock period of the third clock signal. For example, m=2. For example, the clock period of the second clock signal is 4H, and the clock period of the third clock signal is 2H. The high level of the third clock signal CLK3-1 is maintained for 1H, and at this time, the low level of the third clock signal CLK3-2 is maintained for 1H. The low level of the third clock signal CLK3-1 is maintained for 1H, and at this time, the high level of the first clock signal CLK3-2 is maintained for 1H.

[0073] In the embodiment of the present disclosure, the maximum value of the duration of the effective level of the first scanning signal is related to the level rising delay and the level falling delay of each signal, and is related to the opening time and the closing time of the transistor in the pixel circuit. After fully considering the rising delay and the falling delay of each signal in the actual driving process and the opening delay and the closing delay of the transistor that can be caused by aging, the maximum value of the duration of the effective level of the first scanning signal can be determined.

[0074] In the embodiment of the present disclosure, the end time of the effective level of the first scanning signal is related to the time of the initialization of the light emitting element. Before the driving current is provided to the light emitting element, the initialization of the light emitting element is required, which can avoid the influence of the data signal of the previous frame.

[0075] For example, the anode of the light emitting element is initialized after the data signal is written into the driving transistor. The duration of the active level of the first scan signal ends before the anode of the light emitting element is initialized. For example, the anode of the light emitting element can also be initialized before the reset signal initializes the driving transistor. The duration of the active level of the first scan signal ends after the data signal is completely written into the driving transistor.

[0076] In the embodiments of the present disclosure, the minimum value of the duration of the active level of the reset signal can be determined in advance by testing. According to the minimum value of the duration of the active level of the reset signal, the duration of the active level of the first scan signal can also be determined in advance. When the minimum value of the duration of the active level of the reset signal and the duration of the active level of the first scan signal are determined, the driving circuit 320 can directly output the first scan signal, the second scan signal and the reset signal with the corresponding duration of the active level in the driving process without adjusting the duration of the active level of each signal in the driving process.

[0077] In the embodiments of the present disclosure, the driving circuit 320 can also adjust the duration of the active level of each signal according to the actual driving state.

[0078] The driving process of the pixel circuit by the driving circuit is schematically described in combination with FIGS. 4A, 4B and 4C.

[0079] FIG. 4A shows a structural schematic diagram of an example pixel circuit.

[0080] As shown in FIG. 4A, the pixel circuit 400 is an 8T1C circuit, which includes transistors T1-T8, a capacitor Cst and a light emitting element OLED. The transistors T1, T3-T8 are Pmos transistors, the transistor T2 is an Nmos transistor, and the transistor T3 is a driving transistor.

[0081] In an example, the active level of the first scan signal Ngate output by the driving circuit controls the transistor T2 to be turned on, and the active level of the first scan signal Ngate is a high level. The active level of the second scan signal Pgate output by the driving circuit controls the transistor T4 to be turned on, and the active level of the second scan signal Pgate is a low level. The active level of the reset signal P_Reset output by the driving circuit controls the transistor T1 to be turned on, and the active level of the reset signal P_Reset is a low level.

[0082] In the case that the transistor T1 and the transistor T2 are turned on, the initialization signal Vinit1 is provided to the gate of the transistor T3 through the transistor T1 and the transistor T2, the transistor T3 is initialized, and the capacitor Cst is charged by the low level of the initialization signal Vinit1, so that the transistor T3 remains in the on state.

[0083] When the transistors T2, T3 and T4 are turned on, the data signal Data is provided to the gate of the transistor T3 through the transistors T2, T3 and T4, the data write to the transistor T3 is performed, and the capacitor Cst is charged by the low level of the data signal Data, so that the transistor T3 remains in the on state.

[0084] When the reset signal H_Reset controls the transistors T7 and T8 to be turned on, the initialization signal Vinit2 initializes the light emitting element OLED, and the initialization signal Vint3 initializes the source and drain of the transistor T3.

[0085] When the light emitting control signal EM controls the transistors T5 and T6 to be turned on, the driving voltage VDD forms a driving current through the transistors T5, T3 and T6, the driving current is provided to the light emitting element OLED, and the light emitting element OLED emits light.

[0086] FIG. 4B shows a structural schematic diagram of an output unit of a driving circuit according to an embodiment of the present disclosure. FIG. 4B schematically shows the circuit structure of the output end of one shift register in the driving circuit.

[0087] As shown in FIG. 4B, the output unit of the driving circuit includes a transistor M1 and a transistor M2, both of which are Nmos.

[0088] Under the control of the high level of the node N1, the transistor M1 is turned on, and the working power voltage VGHN is provided to the output end OUT through the transistor M1. Under the control of the high level of the node N2, the transistor M2 is turned on, and the working power voltage VGLN is provided to the output end OUT through the transistor M2. The signal output by the output end OUT is the first scan signal Ngate.

[0089] For example, the working power voltage VGHN and the working power voltage VGLN are only used to distinguish the amplitudes of the two power voltages. For example, the working power voltage VGHN is a relatively high voltage, and the working power voltage VGLN is a relatively low voltage.

[0090] When the working power voltage VGHN is provided to the output end OUT, the first scan signal Ngate output by the output end OUT is high. When the working power voltage VGLN is provided to the output end OUT, the first scan signal Ngate output by the output end OUT is low.

[0091] Referring to the foregoing description, at least two first scan signals output by the driving circuit can be high at the same time. At this time, the transistors M1 of the at least two shift registers are all turned on, and the at least two shift registers output the first scan signals Ngate with high levels in turn.

[0092] The output end OUT of the shift register is electrically connected to the gate of the transistor T2 in the pixel circuit via a gate line, and the transistor M1 receives the working power supply voltage VGHN via a power supply line. The working power supply voltage VGHN charges the gate line via the transistor M1, resulting in a large instantaneous current. Due to the resistance load in the power supply line, the voltage value of the working power supply voltage VGHN is pulled down instantaneously, and then the output end OUT outputs stably, and the voltage value of the working power supply voltage VGHN returns to the set voltage value. The process of the decrease and recovery of the voltage value of the working power supply voltage VGHN causes a pull-down noise on the power supply line.

[0093] The plurality of shift registers output the first scan signals in turn, and the charging process of the plurality of shift registers on the gate lines connected thereto in turn causes the pull-down noise on the power supply line, so that the first scan signals received in the display panel also have the pull-down noise.

[0094] In addition, under the continuous pull-down effect, the process of outputting the first scan signals by the driving circuit has a delay, which causes the high voltage value of the first scan signal Ngate output by the driving circuit to be lower than the set voltage value of the working power supply voltage VGHN. At this time, the voltage value of the first scan signal received by the display panel is reduced and has the pull-down noise.

[0095] In an example, the first scan signal Ngate output by each shift register can be provided to two rows of pixel circuits in the display panel. Therefore, the noise period of the first scan signal Ngate is two rows in a cycle. In this case, the odd and even rows of pixel circuits in the display panel are opened in turn by the second scan signal PGate, and the noise states of the first scan signal Ngate received by the odd and even rows of pixel circuits are also different, which causes the writing states of the data signals in the odd and even rows of pixel circuits to also be different, and finally forms the horizontal stripe defect phenomenon of uneven brightness of the odd and even rows on the display screen.

[0096] In an example, in a local refresh scenario, the pixel circuits in the low brush area do not need to write data signals, so the first scan signal Ngate output by the shift register corresponding to the low brush area is low, and the working power supply voltage VGHN does not need to charge the gate line connected to the shift register.

[0097] In the process of gradually switching the scanned pixel row from the high brush area to the low brush area, the number of first scanning signals Ngate with high level needs to be gradually reduced. Since the first scanning signal output by the shift register corresponding to the first row of pixel circuits in the low brush area is at low level, the next stage of shift register corresponding to the last row of pixel circuits in the high brush area will not pull down the working power supply voltage VGHN.

[0098] Therefore, the pull-down noise in the working power supply voltage VGHN will suddenly disappear, and the working power supply voltage VGHN will gradually rise to the set value voltage, which causes the voltage value of the first scanning signal Ngate received by the last few rows of pixel circuits in the high brush area to be slightly higher than that of the other rows of pixel circuits in the high brush area, and the writing ability of the last few rows of pixel circuits in the high brush area to the data signal is different from that of the other rows of pixel circuits in the high brush area. Therefore, the brightness of the last few rows of pixel circuits in the high brush area is higher than that of the other rows of pixel circuits in the high brush area, and the display screen appears uneven in brightness. For the high brush area, the voltage value of the first scanning signal Ngate received by the last row of pixel circuits in the high brush area is the highest, so the brightness of the last row of pixel circuits in the high brush area is the highest, and the display effect of the display screen can be referred to as FIG. 2.

[0099] FIG. 4C shows a timing diagram of an example of a scanning signal and a working power supply voltage.

[0100] The horizontal dashed line shown in FIG. 4C represents the set voltage value of the working power supply voltage VGHN, i.e. the voltage value of the working power supply provided by the power supply. The power supply voltage VGHN in represents the voltage value of the working power supply voltage received by the driving circuit. In the refresh of the high brush area, there is a pull-down noise in the power supply voltage VGHN in, and the voltage value of the power supply voltage VGHN in is also lower than the set value of the working power supply voltage VGHN.

[0101] The first scanning signals Ngate n+1 to Ngate n+12 are provided to the nth+1 to nth+12 rows of pixel circuits in the display panel. The first scanning signals Ngate m+1 to Ngate m+12 are provided to the m+1 to m+12 rows of pixel circuits in the display panel.

[0102] The second scanning signals Pgate n+1 to Pgate n+12 are provided to the nth+1 to nth+12 rows of pixel circuits in the display panel. The second scanning signals Pgate m+1 to Pgate m+12 are provided to the m+1 to m+12 rows of pixel circuits in the display panel.

[0103] The n+1th row of pixel circuits to the n+12th row of pixel circuits are 12 rows of pixel circuits far from the low brush area in the high brush area. The m+1th row of pixel circuits to the m+12th row of pixel circuits are 12 rows of pixel circuits close to the low brush area in the high brush area.

[0104] The first scan signal Ngate n+1 to the first scan signal Ngate n+12 have pull-down noise, and the voltage value of the high level is slightly lower than the set voltage value of the working power supply voltage VGHN. The pull-down noise in the first scan signal Ngate m+1 to the first scan signal Ngate m+12 decreases in turn, and the voltage value of the high level also gradually increases to the set voltage value of the working power supply voltage VGHN.

[0105] When the two second scan signals corresponding to each first scan signal are low, if the first scan signal has pull-down noise. At the two times when the two second scan signals are low, the noise state of the first scan signal is different, which makes the display brightness of the odd and even rows of pixel circuits different.

[0106] FIG. 5 shows a timing diagram of a scan signal and a working power supply voltage according to an embodiment of the present disclosure.

[0107] The first scan signal Ngate n+1 to the first scan signal Ngate n+12 and the first scan signal Ngate m+1 to the first scan signal Ngate m+12 shown in FIG. 5 can be the first scan signals output by the driving circuit in the embodiment of the present disclosure.

[0108] The duration of the effective level of the first scan signal shown in FIG. 5 is less than the duration of the effective level of the first scan signal shown in FIG. 4. Compared with the first scan signal Ngate n+1 to the first scan signal Ngaten+12 and the first scan signal Ngate m+1 to the first scan signal Ngate m+12 shown in FIG. 4, the voltage value of the effective level of the first scan signal Ngate n+1 to the first scan signal Ngate n+12 and the first scan signal Ngate m+1 to the first scan signal Ngate m+12 shown in FIG. 5 is closer to the set voltage value of the continuous working power supply voltage VGHN.

[0109] For example, for the scanning process of a row of pixel circuits, the duration of the effective level of the first scan signal shown in FIG. 4 can be the maximum value in the preset range.

[0110] In the embodiments of the present disclosure, the driving circuit controls the duration of the active level of the first scan signal within a preset range, which can effectively reduce the number of first scan signals outputting high level at the same time, reduce the number of shift registers charging the gate trace with the working power supply voltage VGHN at the same time, thereby stabilizing the voltage value of the working power supply voltage VGHN and the voltage value of the high level of the first scan signal.

[0111] FIG. 6 shows timing diagrams of scan signals according to an embodiment of the present disclosure. FIG. 6 shows timing diagrams of three first scan signals with different durations of active level under the same output load.

[0112] FIG. 6 shows timing diagrams of first scan signals Ngate1, Ngate2, and Ngate3 with durations of active level of 14H, 30H, and 46H, respectively. H represents the duration of the first scan signal scanning a row of pixel circuits. The abscissa of FIG. 6 represents time, and the ordinate represents voltage value.

[0113] As shown in FIG. 6, the duration of the active level of the first scan signal Ngate1 is the shortest, and the voltage value of the high level is the largest. The duration of the active level of the first scan signal Ngate3 is the longest, and the voltage value of the high level is the smallest. The durations of the active levels of the first scan signals Ngate1, Ngate2, and Ngate3 increase in turn, and the voltage values of the high levels of the first scan signals Ngate2 and Ngate3 decrease in turn.

[0114] The longer the duration of the active level of the first scan signal, the slower the recovery speed of the voltage value of the working power supply voltage VGHN, and thus the lower the voltage value of the high level of the first scan signal.

[0115] FIG. 7A shows a timing diagram of an example driving signal.

[0116] FIG. 7A shows the duration of the high level of the emission control signal EM, the duration of the high level of the first scan signal Ngate, the duration of the low level of the second scan signal Pgate, the duration of the low level of the reset signal P_Reset, and the duration of the low level of the reset signal H_Reset. The active level of the emission control signal EM is low level, the active level of the first scan signal Ngate is high level, the active level of the second scan signal Pgate is low level, and the active levels of the reset signals P_Reset and H_Reset are low level.

[0117] As shown in FIG. 7A, the duration of the high level of the light-emitting control signal EM is 60H, the duration of the high level of the first scan signal Ngate is 34H, the duration of the low level of the second scan signal Pgate is 1H, the duration of the low level of the reset signal P_Reset is 22H, and the duration of the low level of the reset signal H_Reset is 6H.

[0118] The time when the light-emitting control signal EM is switched from the low level to the high level is 4H earlier than the time when the first scan signal Ngate is switched from the low level to the high level. The time when the first scan signal Ngate is switched from the low level to the high level is 2H earlier than the time when the reset signal P_Reset is switched from the high level to the low level.

[0119] The time when the reset signal P_Reset is switched from the low level to the high level is 2H earlier than the time when the second scan signal Pgate is switched from the high level to the low level. The time when the second scan signal Pgate is switched from the low level to the high level is 7H earlier than the time when the first scan signal Ngate is switched from the high level to the low level.

[0120] The time when the first scan signal Ngate is switched from the high level to the low level is 12H earlier than the time when the reset signal H_Reset is switched from the high level to the low level. The time when the reset signal H_Reset is switched from the low level to the high level is 4H earlier than the time when the light-emitting control signal EM is switched from the high level to the low level.

[0121] The duration of the active level of the first scan signal Ngate shown in FIG. 7A can be the maximum value in the preset range. Under the driving of the light-emitting control signal EM, the first scan signal Ngate, the second scan signal Pgate, the low level of the reset signal P_Reset, and the reset signal H_Reset shown in FIG. 7A, the pixel circuit can complete the driving of the light-emitting element, but the first scan signal Ngate in the actual driving process has the pull-down noise shown in FIG. 4C, and the voltage value of the high level is less than the set value of the operating power supply voltage VGHN.

[0122] In some embodiments, the active level of the reset signal and the active level of the second scan signal are the first level, the first level is the low level, and the second level is the high level.

[0123] For the scanning of a row of pixel circuits in the display panel, the time when the reset signal output by the driving circuit of the present disclosure is switched from the low level to the high level is K*H earlier than the time when the second scan signal is switched from the low level to the high level, and the duration of the second scan signal for scanning a row of pixel circuits is also 1H.

[0124] In the embodiments of the present disclosure, K can be the number of pixel circuit rows driven by a single first scan signal. For example, the number of pixel circuit rows driven by the first scan signal is 2 rows, and K = 2. The reset signal needs to complete the initialization of the driving transistor at least 2H in advance, so that the second scan signal can control the data signal to be completely written into the pixel circuit.

[0125] In some embodiments, the effective level of the first scan signal is a high level, and the time when the reset signal is switched from a high level to a low level is K*H earlier than the time when the first scan signal is switched from a low level to a high level.

[0126] For example, the number of pixel circuit rows driven by a single first scan signal is K rows, and the reset signal starts to initialize the driving transistor at least K*H in advance, so that the transistor T1 shown in FIG. 4A is opened K*H earlier than the transistor T2. At this time, the initialization signal Vinit1 can be written through the transistor T1 first, and then written through the transistor T2 after K*H.

[0127] Based on this writing process, the initialization signal Vinit1 can be successfully written into the driving transistor, and the level transition of the first scan signal to the effective level can also be delayed to shorten the duration of the effective level of the first scan signal. Since the number of pixel circuit rows driven by the first scan signal is K rows, the reset signal opens the transistor T1 K*H in advance, and writes the initialization signal Vinit1 between the transistor T2 and the transistor T1, so that when the transistor T2 is opened after K*H, the initialization signal Vinit1 can be directly provided to the driving transistor through the transistor T2.

[0128] In the embodiments of the present disclosure, when the initialization signal Vinit1 is provided to the gate of the driving transistor, the transistor T2 is turned on, so that the initialization signal Vinit1 starts to initialize the transistor T3. Based on the first scan signal, it takes at least a time period of mK*H to complete the initialization of K rows of pixel circuits, and in addition, based on the duration of the low level of the reset signal described in the foregoing, it is (1+m)K*H, so the time when the first scan signal is switched from a low level to a high level is mK*H earlier than the time when the reset signal is switched from a low level to a high level.

[0129] In some embodiments, the time when the second scan signal is switched from a low level to a high level is (mK-1)*H earlier than the time when the first scan signal is switched from a high level to a low level.

[0130] In the embodiments of the present disclosure, the K rows of pixel circuits are driven by a single first scan signal, and the single first scan signal needs to complete data writing to the K rows of pixel circuits within a clock period of mK*H. When the second scan signal and the first scan signal are both at an effective level, the second scan signal controls the transistor T4 to be turned on, and the first scan signal also controls the transistor T2 to be turned on. Since the second scan signal writes the data signal to the 1 row of pixel circuits for a time period of 1H, the time when the second scan signal is switched from a low level to a high level is earlier than the time when the first scan signal is switched from a high level to a low level by (mK-1)*H.

[0131] In an ideal case, it takes at least K*H to completely write the data signal to the driving transistor. Therefore, to ensure that the data signal is completely written to the driving transistor of the K rows of pixel circuits, the high level of the first scan signal needs to be maintained for at least KH when the second scan signal is switched from a high level to a low level. The time when the second scan signal is switched from a low level to a high level is earlier than the time when the first scan signal is switched from a high level to a low level by a time period of (mK-1)*H, which also needs to be greater than or equal to 1H.

[0132] In some embodiments, the pixel circuit needs to complete initialization of the driving transistor and data writing to the driving transistor within the duration of the effective level of the first scan signal. Since the first scan signal scans the K rows of pixel circuits, the high level of the first scan signal needs to continue for K*H after the reset signal is switched from a low level to a high level. Therefore, the duration of the effective level of the first scan signal is (mK+K+mK)*H. For example, when m=2, the duration of the effective level of the first scan signal is at least 5K*H, and the duration of the effective level of the second scan signal is 1H.

[0133] In some embodiments, the driving circuit can also output a light emission control signal to the display panel, and the light emission control signal is used to control the driving current to write to the light emitting element of the pixel circuit.

[0134] In the embodiments of the present disclosure, within the duration of the high level of the light emission control signal, the pixel circuit needs to complete initialization of the driving transistor, data writing to the driving transistor, and initialization of the light emitting element, etc. The light emitting element is initialized after the first scan signal completes data writing to the row of pixel circuits and K*H elapses. The time length of the initialization of the light emitting element can refer to the time length of the initialization of the driving transistor by the reset signal. Based on the duration of the effective level of the first scan signal, the second scan signal, and the reset signal, and to determine that the initialization of the driving transistor, the data writing to the driving transistor, and the initialization of the light emitting element, etc. can be completed, the duration of the second level of the light emission control signal is at least (5mK+4K)*H.

[0135] FIG. 7B shows a timing diagram of a driving signal according to an embodiment of the present disclosure. FIG. 7B shows the duration of the high level of the light emitting control signal EM, the duration of the high level of the first scan signal Ngate, the duration of the low level of the second scan signal Pgate, the duration of the low level of the reset signal P_Reset, and the duration of the low level of the reset signal H_Reset when K = 2 and m = 2.

[0136] As shown in FIG. 7B, the duration of the high level of the light emitting control signal EM is 32H, the duration of the high level of the first scan signal Ngate is 10H, the duration of the low level of the second scan signal Pgate is 1H, the duration of the low level of the reset signal P_Reset is 6H, and the duration of the low level of the reset signal H_Reset is 6H.

[0137] The time at which the light emitting control signal EM switches from the low level to the high level is 4H earlier than the time at which the reset signal P_Reset switches from the high level to the low level. The time at which the reset signal P_Reset switches from the high level to the low level is 2H earlier than the time at which the first scan signal Ngate switches from the high level to the low level.

[0138] The time at which the first scan signal Ngate switches from the high level to the low level is 4H earlier than the time at which the reset signal P_Reset switches from the low level to the high level. The time at which the reset signal P_Reset switches from the low level to the high level is 2H earlier than the time at which the second scan signal Pgate switches from the high level to the low level.

[0139] The time at which the second scan signal Pgate switches from the low level to the high level is 3H earlier than the time at which the first scan signal Ngate switches from the high level to the low level.

[0140] The time at which the first scan signal Ngate switches from the high level to the low level is 2H earlier than the time at which the reset signal H_Reset switches from the high level to the low level. The time at which the reset signal H_Reset switches from the low level to the high level is 8H earlier than the time at which the light emitting control signal EM switches from the high level to the low level.

[0141] In the embodiments of the present disclosure, the duration of the high level of the light emitting control signal EM can be set according to actual driving requirements. For example, by setting the time difference between the pull-down time of the first scan signal Ngate and the pull-down time of the reset signal H_Reset and the time difference between the pull-up time of the reset signal H_Reset and the pull-down time of the light emitting control signal EM, the duration of the high level of the light emitting control signal can be increased or shortened.

[0142] For example, the time when the first scan signal Ngate is switched from high level to low level is 2H earlier than the time when the reset signal H_Reset is switched from high level to low level. The time when the reset signal H_Reset is switched from low level to high level is 4H earlier than the time when the light emission control signal EM is switched from high level to low level.

[0143] For another example, the time when the first scan signal Ngate is switched from high level to low level is 3H earlier than the time when the reset signal H_Reset is switched from high level to low level. The time when the reset signal H_Reset is switched from low level to high level is 7H earlier than the time when the light emission control signal EM is switched from high level to low level.

[0144] It should be noted that the signals shown in FIG. 7B can be provided to the pixel circuit shown in FIG. 4A. The levels of the signals shown in FIG. 7B are only illustrative. When the structure of the pixel circuit and the type of the transistor in the pixel circuit are changed, the levels of the signals can be changed accordingly.

[0145] FIG. 8 shows a structural schematic diagram of a display device according to another embodiment of the present disclosure.

[0146] As shown in FIG. 8, the display device 800 includes a display panel 810, a driving circuit 820, a working power supply 830, and a control circuit 840.

[0147] In the embodiments of the present disclosure, the display panel 810 and the driving circuit 820 can refer to the display panel 310 and the driving circuit 320 described above.

[0148] In the embodiments of the present disclosure, the driving circuit 820 is electrically connected to the working power supply 830, and the driving circuit 820 outputs the first scan signal based on the working power supply voltage VGNH of the working power supply 830.

[0149] In the embodiments of the present disclosure, the control circuit 840 is electrically connected to the driving circuit 820 and the working power supply 830. The control circuit 840 compensates the working power supply voltage VGHN provided by the working power supply 830 based on the working power supply voltage received by the driving circuit 820.

[0150] In the embodiments of the present disclosure, because the driving circuit pulls down the working power supply voltage provided by the working power supply 830, the working power supply voltage received by the driving circuit 820 has a pull-down noise. When the driving circuit 820 outputs a plurality of first scan signals, a plurality of shift registers of the driving circuit 820 pull down the working power supply voltage provided by the working power supply 830, so that the working power supply voltage provided by the working power supply 830 recovers slowly, and the working power supply voltage received by the driving circuit 820 is smaller than the working power supply voltage provided by the working power supply 830.

[0151] In the embodiments of the present disclosure, the control circuit 840 can monitor the working power supply voltage received by the driving circuit 820. In a case where the voltage value of the working power supply voltage received by the driving circuit 820 is less than the set voltage value, the control circuit 840 compensates the voltage value of the working power supply voltage provided by the working power supply 830, so that the voltage value of the working power supply voltage provided by the working power supply 830 is greater than the set voltage value.

[0152] For example, the control circuit 840 monitors the amplitude of the working power supply voltage received by the driving circuit 820, and compensates the working power supply voltage provided by the working power supply based on the amplitude, so that the amplitude of the working power supply voltage received by the driving circuit 820 is a preset voltage value.

[0153] For example, the preset voltage value is the set voltage value of the working power supply voltage provided by the working power supply 830. The amplitude is the maximum voltage value of the working power supply voltage received by the driving circuit 820.

[0154] For example, the set voltage value is 12V, and the voltage value of the working power supply voltage received by the driving circuit 820 fluctuates between 8V and 10V. The amplitude of the working power supply voltage received by the driving circuit 820 is 10V.

[0155] The control circuit 840 monitors that the amplitude of the working power supply voltage received by the driving circuit 820 is 10V. In response to the amplitude of the working power supply voltage received by the driving circuit 820 being less than the set voltage value 12V, the control circuit 840 compensates the working power supply voltage provided by the working power supply 830, so that the amplitude of the working power supply voltage received by the driving circuit 820 is 12V.

[0156] FIG. 9 shows timing diagrams of a scanning signal and a working power supply voltage according to another embodiment of the present disclosure.

[0157] As shown in FIG. 9, the power supply voltage VGHN in1 is the working power supply voltage received by the driving circuit 820 before the control circuit 840 compensates the working power supply voltage provided by the working power supply 830. The power supply voltage VGHN out is the working power supply voltage provided by the working power supply 830 after the control circuit 840 compensates the working power supply voltage provided by the working power supply 830. The power supply voltage VGHN in2 is the working power supply voltage received by the driving circuit 820 after the control circuit 840 compensates the working power supply voltage provided by the working power supply 830.

[0158] The amplitude of the power voltage VGHN in1 is less than the set voltage value. After compensation, the amplitude of the power voltage VGHN in2 is the set voltage value. In the case that the driving circuit 820 receives the power voltage VGHN in2, the amplitudes of the first scanning signal Ngate n+1 to the first scanning signal Ngate n+12 and the first scanning signal Ngate m+1 to the first scanning signal Ngate m+12 are also the preset voltage value.

[0159] In some embodiments, the control circuit 840 can monitor the minimum value of the working power voltage received by the driving circuit 820, and compensate the working power voltage provided by the working power 830 according to the difference between the set voltage value and the minimum value.

[0160] For example, the set voltage value is 12V, and the voltage value of the working power voltage received by the driving circuit 820 fluctuates between 8V and 10V. Among them, the minimum value of the working power voltage received by the driving circuit 820 is 8V. The control circuit 840 compensates the voltage value of the working power voltage provided by the working power 830 from 12V to 16V. After compensation, the voltage value of the working power voltage received by the driving circuit 820 fluctuates between 10V and 12V

[0161] In the embodiments of the present disclosure, the control circuit 840 only compensates the working power voltage provided by the working power 830 in the process of scanning the high brush area.

[0162] In the embodiments of the present disclosure, the compensation method can include linear compensation, curve compensation, and segmented compensation, etc.

[0163] FIG. 10 shows a schematic diagram of compensating the working power voltage according to an embodiment of the present disclosure.

[0164] As shown in FIG. 10, the power voltage VGHN in1_1 represents that before the control circuit compensates the working power voltage provided by the working power, the voltage value of the working power voltage received by the driving circuit can be considered as linearly changing. The power voltage VGHN in1_2 represents that before the control circuit compensates the working power voltage provided by the working power, the voltage value of the working power voltage received by the driving circuit can be considered as segmented changing. The power voltage VGHN in1_3 and the power voltage VGHN in1_4 represent that before the control circuit compensates the working power voltage provided by the working power, the voltage value of the working power voltage received by the driving circuit can be considered as curve changing. The control signal C1 and the control signal C2 can be used to control the local refresh.

[0165] When the control signal C1 is high and the control signal C2 is low, the voltage values of the power supply voltages VGHN in1_1, VGHN in1_2, VGHN in1_3 and VGHN in1_4 are preset voltage values. When the control signal C1 is switched from high to low and the control signal C2 is switched from low to high, the local refresh is started, at which time the voltage values of the power supply voltages VGHN in1_1, VGHN in1_2, VGHN in1_3 and VGHN in1_4 decrease.

[0166] For the power supply voltage VGHN in1_1, within the time period Δt, the voltage value of the power supply voltage VGHN in1_1 decreases linearly, and there is a voltage difference ΔV between the minimum voltage value of the power supply voltage VGHN in1_1 and the preset voltage value. Therefore, the voltage value of the working power supply voltage provided by the working power supply is compensated by the voltage difference ΔV.

[0167] For the power supply voltage VGHN in1_2, within the time period Δt1, there is a voltage difference ΔV1 between the minimum voltage value of the power supply voltage VGHN in1_2 and the preset voltage value. Within the time period Δt2, there is a voltage difference ΔV2 between the minimum voltage value of the power supply voltage VGHN in1_2 and the preset voltage value. Within the time period Δt3, there is a voltage difference ΔV3 between the minimum voltage value of the power supply voltage VGHN in1_2 and the preset voltage value. Therefore, the voltage value of the working power supply voltage provided by the working power supply is compensated in segments, and the voltage value of each segment is compensated by the voltage difference ΔV1, the voltage difference ΔV2 and the voltage difference ΔV3, respectively.

[0168] For the power supply voltage VGHN in1_3 and the power supply voltage VGHN in1_3, the decrease of the voltage value is fitted as a curve, and the compensation value is determined according to the curvature change of the curve, so as to perform curve compensation on the voltage value of the working power supply voltage provided by the working power supply.

[0169] In some embodiments, the control circuit 840 shown in FIG. 8 can also monitor the voltage value of the working power supply voltage received by the driving circuit 820 in real time, and compensate the working power supply voltage provided by the working power supply 830 based on the voltage value at each moment, so that the voltage value of the working power supply voltage received by the driving circuit 20 is the preset voltage value.

[0170] In the embodiment of the present disclosure, the control circuit 840 acquires the voltage value of the working power supply voltage received by the driving circuit 820 at each moment, and compensates the working power supply voltage output by the working power supply 830 at this moment based on the difference between the voltage value and the set voltage value, so that the voltage value of the working power supply voltage received by the driving circuit 820 at each moment can be determined as the preset voltage value, and the pull-down noise of the working power supply voltage received by the driving circuit 820 is eliminated.

[0171] In the embodiment of the present disclosure, when the control circuit 840 monitors that the working power supply voltage received by the driving circuit 820 has jitter, the control circuit 840 can output the reverse compensation voltage in real time, the compensation voltage offsets the in-plane noise, the working power supply voltage received by the driving circuit 820 has a completely flat waveform, and thus the first scanning signal also has a completely flat waveform, thereby solving the problems of display defects and uneven brightness.

[0172] FIG. 11 shows a structural schematic diagram of a display device according to another embodiment of the present disclosure.

[0173] As shown in FIG. 11, the display device 1100 includes a display panel 1110, a driving circuit 1120, a working power supply 1130, and a control circuit 1140.

[0174] In the embodiment of the present disclosure, the display panel 1110, the driving circuit 1120, and the working power supply 1130 can refer to the display panel 310, the driving circuit 320, and the working power supply 330 described above.

[0175] In the embodiment of the present disclosure, the driving circuit 1120 includes N-stage cascaded shift registers G1, G2, …, GN_1, GN, N is an integer greater than 1. The control circuit 1140 is electrically connected with the Nth-stage shift register GN.

[0176] The control circuit 1140 generates a voltage compensation signal in response to the working power supply voltage received by the Nth-stage shift register GN, and compensates the working power supply voltage provided by the working power supply 1130 based on the voltage compensation signal.

[0177] In the embodiments of the present disclosure, the control circuit 1140 can be connected to the Nth shift register GN through an external wire. In the in-plane working power supply voltage (the Nth shift register of the driving circuit 1120 receives the working power supply voltage), the Nth shift register GN receives the working power supply voltage with the largest jitter amplitude. In this case, the control circuit 1140 obtains the working power supply voltage received by the Nth shift register GN through the external wire. Based on the real-time change of the working power supply voltage received by the Nth shift register GN, the working power supply voltage output by the working power supply 1130 is compensated in real time. The voltage compensation signal can be a reverse compensation signal for the working power supply voltage received by the Nth shift register GN. Based on the reverse compensation signal, the in-plane working power supply voltage can be compensated and denoised.

[0178] FIG. 12 shows a structural schematic diagram of a control circuit according to an embodiment of the present disclosure.

[0179] As shown in FIG. 12, the control circuit 1240 includes an operational amplifier AP, a first resistor R1, and a second resistor R2.

[0180] In the embodiments of the present disclosure, the positive input end of the operational amplifier AP is electrically connected to a predetermined power supply DC, the negative input end of the operational amplifier AP is electrically connected to the second end of the first resistor R1, and the output end of the operational amplifier AP outputs a voltage compensation signal OUTPUT. The first end of the first resistor R1 is electrically connected to the Nth shift register GN, the first end of the second resistor R2 is electrically connected to the negative input end of the operational amplifier AP, and the second end of the second resistor R2 is electrically connected to the output end of the operational amplifier AP.

[0181] In the embodiments of the present disclosure, the working power supply voltage received by the Nth shift register GN is input to the negative input end of the operational amplifier AP through the first resistor R1. The predetermined power supply DC provides a direct current voltage with a set voltage value of the working power supply voltage. The direct current voltage is input to the negative input end of the operational amplifier AP, and the output end OUTPUT outputs a compensation voltage signal.

[0182] The ideal operational amplifier calculation formula is:

[0183] When R1 = R2: V OUTPUT = 2V DC -VGNH GN .

[0184] VGHN GN is the voltage value of the working power supply voltage received by the Nth shift register GN, V DC is the direct current voltage provided by the predetermined power supply DC, V OUTPUTThe voltage value of the compensation voltage signal output by the output terminal OUTPUT. The control circuit 1240 controls the operating power supply voltage output by the operating power supply to be V OUTPUT .

[0185] FIG. 13 shows a timing diagram of a scan signal and an operating power supply voltage according to another embodiment of the present disclosure.

[0186] As shown in FIG. 13, the power supply voltage VGHN in1 is the operating power supply voltage received by the driving circuit 1120 before the control circuit 1140 compensates the operating power supply voltage provided by the operating power supply 1130. The power supply voltage VGHN out is the operating power supply voltage provided by the operating power supply 1130 after the control circuit 1140 compensates the operating power supply voltage provided by the operating power supply 1130. The power supply voltage VGHN in2 is the operating power supply voltage received by the driving circuit 1120 after the control circuit 1140 compensates the operating power supply voltage provided by the operating power supply 1130.

[0187] The voltage value of the power supply voltage VGHN out is the same as the voltage value V OUTPUT of the compensation voltage signal output by the output terminal OUTPUT in FIG. 12. After the reverse compensation of the power supply voltage VGHN out, the voltage value of the power supply voltage VGHN in2 at each moment is the set voltage value. In the case where the driving circuit 1120 receives the power supply voltage VGHN in2, the voltage value of each of the first scan signal Ngate n+1 to the first scan signal Ngate n+12 and the first scan signal Ngate m+1 to the first scan signal Ngate m+12 is the preset voltage value.

[0188] FIG. 14 shows a flow diagram of a driving method according to an embodiment of the present disclosure.

[0189] As shown in FIG. 14, the driving method includes step S1410.

[0190] In the embodiments of the present disclosure, the driving method can be applied to the display device 300a, the display device 300b, the display device 800, and the display device 1100 described above.

[0191] In operation S1410, a first scan signal is output to a display panel, and a reset signal is output to the display panel based on m first clock signals of m first clock terminals.

[0192] In the embodiments of the present disclosure, the reset signal is used to control the initialization of a driving transistor by an initialization signal, and the first scan signal is used to control the writing of a data signal into the driving transistor in a plurality of pixel circuits.

[0193] In the embodiments of the present disclosure, the duration of the effective level of the first scanning signal is greater than or equal to a preset value, and the preset value is determined based on the duration of the effective level of the reset signal, the duration of the effective level of the reset signal is (1+m)K*H, m and K are positive integers, K is the number of pixel circuit rows driven by the reset signal respectively, and H is the ratio of the display frame rate to the total number of pixel circuit rows of the display panel.

[0194] In the embodiments of the present disclosure, step S1410 is similar to the operations performed by the display device 300a, the display device 300b, the display device 800, and the display device 1100 described above, and details are not described herein.

[0195] The block diagrams in the drawings represent the architectural, functional, and operational aspects of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations thereof, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0196] Those skilled in the art can understand that the features described in various embodiments of the present disclosure and / or claims can be combined and / or integrated in various combinations, even if such combinations are not explicitly described in the present disclosure. In particular, the features described in various embodiments of the present disclosure and / or claims can be combined and / or integrated in various combinations without departing from the spirit and teachings of the present disclosure. All such combinations and / or integrations fall within the scope of the present disclosure.

[0197] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications shall fall within the scope of the present disclosure.

Claims

1. A display device comprising: a display panel comprising a plurality of pixel circuits; a driving circuit electrically connected to the display panel and m first clock terminals, the driving circuit being configured to output a first scan signal to the display panel and output a reset signal to the display panel based on m first clock signals of the m first clock terminals, the first scan signal being used to control a data signal to be written to a driving transistor in the plurality of pixel circuits, and the reset signal being used to control an initialization signal to initialize the driving transistor; wherein a duration of an active level of the first scan signal is greater than or equal to a preset value, the preset value being determined based on a duration of an active level of the reset signal, the duration of the active level of the reset signal being (1+m)K*H, m and K being positive integers, K being a number of rows of pixel circuits driven by the reset signal, and H being a ratio of a display frame rate to a total number of rows of pixel circuits of the display panel.

2. The display device according to claim 1, wherein the driving circuit is further configured to output a second scan signal to the display panel, the second scan signal being used to control a data signal to be written to the plurality of pixel circuits; wherein the active level of the reset signal and the active level of the second scan signal are a first level, and for scanning of a row of pixel circuits in the display panel, a time when the reset signal switches from the first level to a second level is earlier than a time when the second scan signal switches from the first level to the second level by K*H.

3. The display device of claim 2, wherein the duration of the active level of the first scan signal is (1+2m)K*H, and the duration of the active level of the second scan signal is 1H.

4. The display device according to claim 1, wherein the active level of the first scan signal is the second level, and the active level of the reset signal is the first level; a time when the reset signal switches from the second level to the first level is earlier than a time when the first scan signal switches from the second level to the first level by K*H.

5. The display device according to claim 1, wherein the active level of the first scan signal is the second level, and the active level of the reset signal is the first level; a time when the first scan signal switches from the second level to the first level is earlier than a time when the reset signal switches from the first level to the second level by mK*H.

6. The display device according to claim 2, wherein a time when the second scan signal switches from the first level to the second level is earlier than a time when the first scan signal switches from the second level to the first level by (m*K-1)*H.

7. The display device according to claim 2, wherein the driving circuit is further configured to output a light-emitting control signal to the display panel, the light-emitting control signal being used to control a driving current to be written to a light-emitting element of the pixel circuit; wherein the active level of the light-emitting control signal is the first level, and a duration of a second level of the light-emitting control signal is (5m*K+4K)*H.

8. The display device according to claim 2, wherein the driving circuit is further electrically connected to a second clock terminal and a third clock terminal; the driving circuit is further configured to output the first scan signal under control of a second clock signal from the second clock terminal, and output the second scan signal under control of a third clock signal from the third clock terminal. A duration of an active level of the second clock signal is K times a duration of an active level of the third clock signal.

9. The display device according to claim 1, wherein The driving circuit is electrically connected to a working power supply, and the driving circuit is further configured to output the first scan signal based on a working power supply voltage of the working power supply. The display device further includes a control circuit electrically connected to the driving circuit and the working power supply, and the control circuit is configured to compensate the working power supply voltage provided by the working power supply based on the working power supply voltage received by the driving circuit.

10. The display device of claim 9, wherein, The control circuit is further configured to monitor an amplitude of the working power supply voltage received by the driving circuit, and compensate the working power supply voltage provided by the working power supply based on the amplitude, so that the amplitude of the working power supply voltage received by the driving circuit is a preset voltage value.

11. The display device of claim 9, wherein, The control circuit is further configured to monitor a minimum value of the working power supply voltage received by the driving circuit, and compensate the working power supply voltage provided by the working power supply according to a difference between the preset voltage value and the minimum value.

12. The display device of claim 9, wherein, The control circuit is further configured to monitor a voltage value of the working power supply voltage received by the driving circuit in real time, and compensate the working power supply voltage provided by the working power supply based on the voltage value at each moment, so that the voltage value of the working power supply voltage received by the driving circuit is a preset voltage value.

13. The display device of claim 12, wherein, The driving circuit includes N-stage cascaded shift registers, and N is an integer greater than 1; the control circuit is electrically connected to an Nth-stage shift register. The control circuit is further configured to generate a voltage compensation signal in response to the working power supply voltage received by the Nth-stage shift register, and compensate the working power supply voltage provided by the working power supply based on the voltage compensation signal.

14. The display device of claim 13, wherein, The control circuit includes an operational amplifier, a first resistor and a second resistor. The positive input terminal of the operational amplifier is electrically connected to a predetermined power supply, the negative input terminal of the operational amplifier is electrically connected to the second end of the first resistor, and the output terminal of the operational amplifier outputs the voltage compensation signal. The first end of the first resistor is electrically connected to the Nth-stage shift register, the first end of the second resistor is electrically connected to the negative input terminal of the operational amplifier, and the second end of the second resistor is electrically connected to the output terminal of the operational amplifier.

15. A driving method, comprising: outputting a first scan signal to a display panel, and outputting a reset signal to the display panel based on m first clock signals of m first clock terminals, the reset signal being used to control initialization of a driving transistor by an initialization signal, and the first scan signal being used to control writing of a data signal into the driving transistor in a plurality of pixel circuits of the display panel; The effective level of the first scanning signal lasts for a time period greater than or equal to a preset value, and the preset value is determined based on a time period of an effective level of a reset signal, wherein the time period of the effective level of the reset signal is (1+m)K*H, m and K are positive integers, K is a number of pixel circuit rows driven by the reset signal, and H is a ratio of a display frame rate to a total number of pixel circuits of the display panel.

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