Cell, module, and photovoltaic system

Abstract

The present disclosure provides a cell, a module, and a photovoltaic system. The cell comprises: a silicon substrate provided with a P region and an N region on the surface; a first passivation layer located in the P region; a second passivation layer located in the N region; a P-type doped layer disposed on the surface of the first passivation layer facing away from the silicon substrate; and an N-type doped layer disposed on the surface of the second passivation layer facing away from the silicon substrate, wherein the P-type doped layer has a band gap smaller than that of the N-type doped layer.

Description

Battery, assembly, and photovoltaic system

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to the Chinese patent application No. 202411260478.8, filed on September 6, 2024, and entitled "A solar cell, a battery assembly, and a photovoltaic system", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of solar cells, in particular to a solar cell, a battery assembly, and a photovoltaic system. BACKGROUND

[0004] With the increasing depletion of fossil fuels, solar energy has become the most common and clean renewable energy. Among them, a solar cell is a device that directly converts light energy into electrical energy by using the photovoltaic effect. The solar cell mainly includes a bifacial solar cell and a back contact solar cell.

[0005] In the prior art, the silicon substrate of the bifacial solar cell is provided with a P region on one side and an N region on the other side; the back surface of the back contact solar cell is provided with both a P region and an N region; in order to achieve the passivation effect of the cell, the P region of the bifacial solar cell and the back contact solar cell is provided with a first passivation layer and a P-type doped layer disposed on the first passivation layer, and the electrode of the P region is in contact with the P-type doped layer; the N region of the bifacial solar cell and the back contact solar cell is provided with a second passivation layer and an N-type doped layer disposed on the second passivation layer, and the electrode of the N region is in contact with the N-type doped layer. However, the P-type doped layer of the conventional solar cell has a large resistance relative to the N-type doped layer, and the P-type doped layer has poor conductivity, resulting in poor current transmission effect of the P region and low cell efficiency.

[0006] DISCLOSURE

[0007] The present disclosure provides a solar cell, aiming to solve the problem of poor current transmission effect of the P region and low cell efficiency of the prior art solar cell.

[0008] The present disclosure is implemented in this way, providing a solar cell, comprising:

[0009] a silicon substrate, the surface of the silicon substrate being provided with a P region and an N region;

[0010] a first passivation layer located in the P region, disposed on the surface of the silicon substrate;

[0011] a second passivation layer located in the N region, disposed on the surface of the silicon substrate;

[0012] a P-type doped layer, disposed on the side of the first passivation layer away from the silicon substrate;

[0013] The N-type doped layer is arranged on the side of the second passivation layer away from the silicon substrate.

[0014] The band gap width of the P-type doped layer is less than the band gap width of the N-type doped layer.

[0015] In some embodiments, the deposition temperature of the P-type doped layer is greater than the deposition temperature of the N-type doped layer.

[0016] In some embodiments, the diffusion temperature of the P-type doped layer is greater than the diffusion temperature of the N-type doped layer.

[0017] In some embodiments, the deposition temperature of the P-type doped layer is 595-630℃, and the deposition temperature of the N-type doped layer is 100-585℃.

[0018] In some embodiments, the diffusion temperature of the P-type doped layer is 750-950℃, and the diffusion temperature of the N-type doped layer is 100-900℃.

[0019] In some embodiments, the crystallization rate of the P-type doped layer is greater than the crystallization rate of the N-type doped layer.

[0020] In some embodiments, the band gap width of the P-type doped layer is 1.12-1.65eV, and the band gap width of the N-type doped layer is 1.1-1.6eV.

[0021] In some embodiments, the first passivation layer contains P-type dopants, and the second passivation layer contains N-type dopants, and the doping concentration of the P-type dopants in the first passivation layer is greater than the doping concentration of the N-type dopants in the second passivation layer.

[0022] In some embodiments, the thickness of the P-type doped layer is greater than the thickness of the N-type doped layer.

[0023] In some embodiments, the thickness of the first passivation layer is less than the thickness of the second passivation layer.

[0024] In some embodiments, the first passivation layer and the second passivation layer are both porous passivation layers, and the pore density of the first passivation layer is greater than the pore density of the second passivation layer.

[0025] In some embodiments, the first passivation layer and the second passivation layer are both porous passivation layers, and the average pore size of the pores of the first passivation layer is greater than the average pore size of the pores of the second passivation layer.

[0026] In some embodiments, the solar cell is a back contact solar cell, and the P region and the N region are located on the same side of the silicon substrate.

[0027] In some embodiments, the solar cell is a bifacial solar cell, and the P region and the N region are located on opposite sides of the silicon substrate, respectively.

[0028] The present disclosure also provides a battery assembly comprising the solar cell described above.

[0029] The present disclosure also provides a photovoltaic system comprising the battery assembly described above.

[0030] The solar cell provided by the present disclosure can improve the current transmission effect of the P region by reducing the band gap width of the P-type doped layer, so as to balance the current transmission effects of the P region and the N region, solve the problem of poor current transmission effect of the P region of the traditional solar cell, and make the P region and the N region of the solar cell achieve good current transmission effect, thereby effectively improving the battery efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0031] FIG. 1 is a schematic diagram of a solar cell provided by an embodiment of the present disclosure;

[0032] FIG. 2 is a schematic diagram of another solar cell provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present disclosure and do not limit the present disclosure.

[0034] The solar cell provided by the present embodiment can improve the current transmission effect of the P region by reducing the band gap width of the P-type doped layer, so as to balance the current transmission effects of the P region and the N region, solve the problem of poor current transmission effect of the P region of the traditional solar cell, and make the P region and the N region of the solar cell achieve good current transmission effect, thereby effectively improving the battery efficiency.

[0035] Please refer to FIG. 1 and FIG. 2, the present embodiment provides a solar cell, which comprises:

[0036] a silicon substrate 1, the surface of the silicon substrate 1 is provided with a P region 11 and an N region 12;

[0037] a first passivation layer 2 located in the P region 11, which is arranged on the surface of the silicon substrate 1;

[0038] a second passivation layer 3 located in the N region 12, which is arranged on the surface of the silicon substrate 1;

[0039] a P-type doped layer 4, which is arranged on the side of the first passivation layer 2 away from the silicon substrate 1;

[0040] The N-type doped layer 5 is arranged on the side of the second passivation layer 3 away from the silicon substrate 1.

[0041] The band gap width of the P-type doped layer 4 is less than the band gap width of the N-type doped layer 5.

[0042] In the embodiments of the present disclosure, the band gap width of the P-type doped layer 4 is set to be less than the band gap width of the N-type doped layer 5, which means that the band gap width of the N-type doped layer 5 is unchanged, and the band gap width of the P-type doped layer 4 is reduced, the resistance of the P-type doped layer 4 is reduced, and the conductivity of the P-type doped layer 4 is improved, so that the current transmission effect of the P region is improved, and the current transmission effects of the P region 11 and the N region 12 are balanced, thereby solving the problem of poor current transmission effect of the P region 11 of the traditional solar cell, and making the P region 11 and the N region 12 of the solar cell achieve good current transmission effect, and effectively improving the cell efficiency.

[0043] Of course, in some other embodiments, the band gap width of the P-type doped layer 4 can be greater than or equal to the band gap width of the N-type doped layer 5.

[0044] In the embodiments of the present disclosure, the P-type doped layer 4 includes one of P-type polysilicon, P-type microcrystalline silicon, P-type nanocrystalline silicon, and P-type amorphous silicon, or a mixture of the above materials; and the N-type doped layer includes one of N-type polysilicon, N-type microcrystalline silicon, N-type nanocrystalline silicon, and N-type amorphous silicon, or a mixture of the above materials. In the embodiments of the present disclosure, the P-type doped layer 4 is electrically connected to the silicon substrate 1 through the first passivation layer 2, and the N-type doped layer 5 is electrically connected to the silicon substrate 1 through the second passivation layer 3.

[0045] The band gap is the difference between the lowest point of the conduction band and the highest point of the valence band. It is also called the energy gap. The greater the band gap, the more difficult it is for electrons to be excited from the valence band to the conduction band, and the lower the intrinsic carrier concentration and the lower the conductivity. Therefore, by reducing the band gap width of the P-type doped layer 4, the conductivity of the P-type doped layer 4 can be improved, and thus the current transmission effect of the P region 11 can be improved, and the current transmission effects of the P region 11 and the N region 12 are balanced.

[0046] In the embodiments of the present disclosure, the silicon substrate 1 can be a P-type silicon substrate 1 or an N-type silicon substrate 1. The surface of the silicon substrate 1 can be a back light surface or a light surface of the solar cell.

[0047] Referring to Figure 1, as an embodiment of the invention, the solar cell is a back-contact solar cell, with P-region 11 and N-region 12 located on the same side of the silicon substrate 1. The silicon substrate 1 includes a front side 101 and a back side 102 opposite to the front side 101. The front side 101 of the silicon substrate 1 is the light-facing side of the back-contact solar cell, and the back side 102 of the silicon substrate 1 is the back-light-receiving side of the back-contact solar cell. Both P-region 11 and N-region 12 are located on the back side 102 of the silicon substrate 1.

[0048] There are multiple P-areas 11 and multiple N-areas 12, which are arranged alternately and at intervals. An isolation zone 13 is provided between adjacent P-areas 11 and N-areas 12. The isolation zone 13 can be a trench or a gap.

[0049] In this embodiment, an anti-reflection layer 10 is further provided on the front side 101 of the silicon substrate 1 to reduce sunlight reflection and improve battery efficiency. Optionally, the anti-reflection layer 10 can be a silicon oxide layer or a silicon nitride layer.

[0050] Referring to Figure 2, as another embodiment of the invention, the solar cell is a bifacial solar cell, with P-region 11 and N-region 12 located on opposite sides of the silicon substrate 1. The silicon substrate 1 includes a front side 101 and a back side 102 opposite to the front side 101. The front side 101 of the silicon substrate 1 is the light-facing side of the bifacial solar cell, and the back side 102 of the silicon substrate 1 is the back-facing side of the bifacial solar cell. One of the P-region 11 and the N-region 12 is located on the front side 101 of the silicon substrate 1, and the other is located on the back side 102 of the silicon substrate 1.

[0051] In Figure 2, P-region 11 is located on the front side 101 of the silicon substrate 1, and N-region 12 is located on the back side 102 of the silicon substrate 1. P-region 11 may completely cover the front side 101 of the silicon substrate 1, or it may only cover a portion of the front side 101. N-region 12 may completely cover the back side 102 of the silicon substrate 1, or it may only cover a portion of the back side 102. Multiple P-regions and N-regions 12 may be present. Preferably, P-region 11 covers a portion of the front side 101 of the silicon substrate 1, and an isolation region 13 is provided between adjacent P-regions 11; N-region 12 only covers a portion of the back side 102 of the silicon substrate 1, and an isolation region 13 is provided between adjacent N-regions 12, which can reduce parasitic light absorption. The isolation region 13 may be a trench or a gap.

[0052] In this embodiment, the P-type doped layer 4 and the N-type doped layer 5 have opposite doping polarities. The P-type doped layer 4 contains a P-type dopant, and the N-type doped layer 5 contains an N-type dopant. The P-type dopant is a Group IIIA element dopant, and the N-type dopant is a Group VA element dopant. For example, the P-type dopant can be a boron dopant, and the N-type dopant can be a phosphorus dopant.

[0053] As one embodiment of the present disclosure, the solar cell further comprises:

[0054] a first electrode 6, arranged in the P region 11 and in contact with the P-type doped layer 4;

[0055] a second electrode 7, arranged in the N region 12 and in contact with the N-type doped layer 5.

[0056] In the embodiment, the first electrode 6 is in contact with the P-type doped layer 4 to form an ohmic contact, and the second electrode 7 is in contact with the N-type doped layer 5 to form an ohmic contact. Preferably, the depth of the first electrode 6 into the P-type doped layer 4 is greater than the depth of the second electrode 7 into the N-type doped layer 5, which can increase the contact area of the first electrode 6 with the P-type doped layer 4, further improve the conductivity of the P region 11, and improve the cell efficiency.

[0057] As one embodiment of the present disclosure, the deposition temperature of the P-type doped layer 4 is greater than the deposition temperature of the N-type doped layer 5.

[0058] In the embodiment, the deposition temperature of the P-type doped layer 4 is the temperature of depositing intrinsic amorphous silicon of the P-type doped layer 4, and the deposition temperature of the N-type doped layer 5 is the temperature of depositing intrinsic amorphous silicon of the N-type doped layer 5. The deposition temperatures of the P-type doped layer 4 and the N-type doped layer 5 can be set according to actual needs, as long as the deposition temperature of the P-type doped layer 4 is greater than the deposition temperature of the N-type doped layer 5. By setting the deposition temperature of the P-type doped layer 4 to be greater than the deposition temperature of the N-type doped layer 5, the band gap width of the P-type doped layer 4 can be made smaller than the band gap width of the N-type doped layer 5, and the implementation is simple and conducive to reducing the implementation cost.

[0059] As one embodiment of the present disclosure, the deposition temperature of the P-type doped layer 4 is 595-630℃, and the deposition temperature of the N-type doped layer 5 is 100-585℃.

[0060] In the embodiment, the deposition temperature of the P-type doped layer 4 and the N-type doped layer 5 can be set according to actual needs, as long as the deposition temperature of the P-type doped layer 4 is greater than the deposition temperature of the N-type doped layer 5. For example, the deposition temperature of the P-type doped layer 4 can be one of 595°C, 598°C, 600°C, 605°C, 609°C, 610°C, 616°C, 619°C, 620°C, 628°C, and 630°C; and the deposition temperature of the N-type doped layer 5 can be one of 100°C, 150°C, 180°C, 200°C, 220°C, 260°C, 300°C, 350°C, 380°C, 400°C, 420°C, 450°C, 470°C, 500°C, 510°C, 536°C, 565°C, and 585°C. Of course, the deposition temperature of the P-type doped layer 4 can also be other values in the range of 595-630°C, and the deposition temperature of the N-type doped layer 5 can also be other values in the range of 100-585°C.

[0061] As an embodiment of the present disclosure, the diffusion temperature of the P-type doped layer 4 is greater than the diffusion temperature of the N-type doped layer 5.

[0062] The diffusion temperature of the P-type doped layer 4 is the temperature at which the intrinsic amorphous silicon of the P-type doped layer 4 diffuses to form the P-type doped layer; and the diffusion temperature of the N-type doped layer 5 is the temperature at which the intrinsic amorphous silicon of the N-type doped layer 5 diffuses to form the N-type doped layer. The diffusion temperature of the P-type doped layer 4 and the N-type doped layer 5 can be set according to actual needs, as long as the diffusion temperature of the P-type doped layer 4 is greater than the diffusion temperature of the N-type doped layer 5. By setting the diffusion temperature of the P-type doped layer 4 to be greater than the diffusion temperature of the N-type doped layer 5, the band gap width of the P-type doped layer 4 can be made smaller than the band gap width of the N-type doped layer 5, and the implementation is simple and conducive to reducing the implementation cost.

[0063] As an embodiment of the present disclosure, the diffusion temperature of the P-type doped layer 4 is 750-950°C, and the diffusion temperature of the N-type doped layer 5 is 100-900°C.

[0064] In this embodiment, the diffusion temperature of the P-type doped layer 4 and the N-type doped layer 5 can be set according to actual needs, as long as the diffusion temperature of the P-type doped layer 4 is greater than the diffusion temperature of the N-type doped layer 5. For example, the diffusion temperature of the P-type doped layer 4 can be one of 750°C, 762°C, 770°C, 780°C, 792°C, 800°C, 812°C, 820°C, 835°C, 860°C, 865°C, 872°C, 880°C, 890°C, 900°C, 910°C, 920°C, 930°C, 945°C, 950°C; and the diffusion temperature of the N-type doped layer 5 can be one of 100°C, 120°C, 140°C, 150°C, 160°C, 170°C, 190°C, 200°C, 240°C, 285°C, 300°C, 340°C, 380°C, 400°C, 466°C, 500°C, 550°C, 580°C, 600°C, 620°C, 700°C, 760°C, 800°C, 840°C, 880°C, 900°C. Of course, the diffusion temperature of the P-type doped layer 4 can also be other values in the range of 750-950°C, and the diffusion temperature of the N-type doped layer 5 can also be other values in the range of 100-900°C.

[0065] As an embodiment of the present disclosure, the crystallization rate of the P-type doped layer 4 is greater than the crystallization rate of the N-type doped layer 5.

[0066] In this embodiment, under the premise that the crystallization rate of the N-type doped layer 5 remains unchanged, by increasing the crystallization rate of the P-type doped layer 4, the crystallization rate of the P-type doped layer 4 is higher than that of the N-type doped layer 5, which can reduce the band gap width of the P-type doped layer 4, thereby improving the conductivity of the P-type doped layer 4 and facilitating the improvement of the photoelectric conversion efficiency of the battery.

[0067] In this embodiment, the crystallization rate of the P-type doped layer 4 and the crystallization rate of the N-type doped layer 5 both refer to the average crystallization rate, which can be obtained by measuring the crystallization rate of different regions in the P-type doped layer 4 and the N-type doped layer 5 respectively and averaging the measured multiple crystallization rates.

[0068] For example, the crystallization rate test can be performed on different thicknesses of the P-type doped layer 4 and the N-type doped layer 5 to obtain the average crystallization rate. In a specific example, the P-type doped layer 4 and the N-type doped layer 5 can be divided into five equal parts in the thickness direction, and the crystallization rate test can be performed on each part to obtain the average crystallization rate. In other examples, the P-type doped layer 4 and the N-type doped layer 5 can also be divided into other number of equal parts in the thickness direction to obtain the average crystallization rate of the P-type doped layer 4 and the N-type doped layer 5.

[0069] In some embodiments, the crystallization rate of the P-type doped layer 4 and the N-type doped layer 5 can be tested by Raman spectroscopy.

[0070] For example, the crystallization rate of the P-type doped layer 4 is 90% to 95%, and the crystallization rate of the N-type doped layer 5 is 85% to 90%.

[0071] As an embodiment of the present disclosure, the band gap width of the P-type doped layer 4 is 1.12 to 1.65 eV, and the band gap width of the N-type doped layer 5 is 1.1 to 1.6 eV.

[0072] In this embodiment, the band gap widths of the P-type doped layer 4 and the N-type doped layer 5 are set in the above ranges, respectively, so that the current transmission effect of the P region 11 and the N region 12 can be balanced, and the P-type doped layer 4 and the N-type doped layer 5 can be easily processed and prepared.

[0073] The band gap widths of the P-type doped layer 4 and the N-type doped layer 5 can be set according to actual needs, and only need to satisfy that the band gap width of the P-type doped layer 4 is greater than the band gap width of the N-type doped layer 5. For example, the band gap width of the P-type doped layer 4 can be one of 1.12 eV, 1.15 eV, 1.17 eV, 1.19 eV, 1.2 eV, 1.35 eV, 1.4 eV, 1.46 eV, 1.50 eV, 1.58 eV, 1.6 eV, 1.61 eV, 1.63 eV, and 1.65 eV; and the band gap width of the N-type doped layer 5 can be one of 1.1 eV, 1.12 eV, 1.17 eV, 1.2 eV, 1.24 eV, 1.3 eV, 1.36 eV, 1.4 eV, 1.42 eV, 1.46 eV, 1.52 eV, 1.58 eV, and 1.6 eV. Of course, the band gap width of the P-type doped layer 4 can also be other values in the range of 1.2 to 1.65 eV, and the band gap width of the N-type doped layer 5 can also be other values in the range of 1.1 to 1.6 eV.

[0074] As an embodiment of the present disclosure, the first passivation layer 2 contains a P-type dopant, and the second passivation layer 3 contains an N-type dopant. The doping concentration of the P-type dopant of the first passivation layer 2 is greater than the doping concentration of the N-type dopant of the second passivation layer 3.

[0075] In this embodiment, since the doping concentration of the P-type dopant of the first passivation layer 2 is greater than the doping concentration of the N-type dopant of the second passivation layer 3, that is, by increasing the doping concentration of the P-type dopant of the first passivation layer 2, the resistivity of the first passivation layer 2 is reduced, and the conductivity of the first passivation layer 2 is improved, the current transmission effect of the P region 11 can be further improved, and the battery efficiency is further improved.

[0076] As an embodiment of the present disclosure, the doping concentration of the P-type dopant of the first passivation layer 2 is 1 x 1019 ~8x10 21 atoms / cm 3 ; the doping concentration of the N-type dopant of the second passivation layer 3 is 5x10 18 ~5x10 21 atoms / cm 3 .

[0077] In this embodiment, the doping concentrations of the first passivation layer 2 and the second passivation layer 3 can be set according to actual needs, as long as the doping concentration of the P-type dopant of the first passivation layer 2 is greater than the doping concentration of the N-type dopant of the second passivation layer 3.

[0078] wherein the doping concentration of the P-type dopant is the average value or the peak value of the doping concentration of the P-type dopant, and the doping concentration of the N-type dopant is the average value or the peak value of the doping concentration of the N-type dopant; wherein the peak value is the maximum doping concentration value. In the comparison of the doping concentrations, the average values of the doping concentrations are compared at the same time or the peak values of the doping concentrations are compared at the same time. It can be understood that the average value of the doping concentration of the P-type dopant of any region of the first passivation layer 2 is greater than the average value of the doping concentration of the N-type dopant of any region of the second passivation layer 3; or the peak value of the doping concentration of the P-type dopant of any region of the first passivation layer 2 is greater than the peak value of the doping concentration of the N-type dopant of any region of the second passivation layer 3.

[0079] In the embodiments of the present disclosure, the doping concentration of the P-type dopant can be the doping concentration of the activated P-type dopant, and the doping concentration of the N-type dopant can be the doping concentration of the activated N-type dopant, which can be measured by Spreading Resistance Profile (SRP) or Electrochemical Capacitance-Voltage (ECV). Of course, the doping concentration of the P-type dopant can also be the sum of the doping concentration of the activated P-type dopant and the doping concentration of the unactivated P-type dopant, and the doping concentration of the N-type dopant can also be the sum of the doping concentration of the activated N-type dopant and the doping concentration of the unactivated N-type dopant, which can be measured by Secondary Ion Mass Spectrometry (SIMS).

[0080] As an embodiment of the present disclosure, the first passivation layer 2 and the second passivation layer 3 are both porous passivation layers, and the pore density of the first passivation layer 2 is greater than the pore density of the second passivation layer 3.

[0081] In the embodiment, the holes on the first passivation layer 2 vertically penetrate the first passivation layer 2, and the holes on the second passivation layer 3 vertically penetrate the second passivation layer 3. The P-type doped layer 4 contacts the silicon substrate 1 through the holes on the first passivation layer 2, and the N-type doped layer 5 contacts the silicon substrate 1 through the holes on the second passivation layer 3, which is conducive to reducing current loss and improving battery conversion efficiency. Since the hole density of the first passivation layer 2 is greater than the hole density of the second passivation layer 3, that is, the number of holes per unit area of the first passivation layer 2 is greater than the number of holes per unit area of the second passivation layer 3, the resistance of the first passivation layer 2 can be reduced, the resistance of the first passivation layer 2 is less than the resistance of the second passivation layer 3, the conductivity of the first passivation layer 2 is improved, the conductivity of the P region 11 is improved, and the implementation is simple.

[0082] The holes of the first passivation layer 2 and the second passivation layer 3 can be prepared by one of chemical etching, dry etching, thermal diffusion impact, etc., which is prepared according to actual use needs, and is not specifically limited here. When observing the first passivation layer 2 and the second passivation layer 3 from the top view angle, the first passivation layer 2 and the second passivation layer 3 present a porous structure, and when observing the first passivation layer 2 and the second passivation layer 3 from the cross-sectional view angle, the first passivation layer 2 and the second passivation layer 3 show a multi-channel structure.

[0083] As an embodiment of the present disclosure, the first passivation layer 2 and the second passivation layer 3 are both porous passivation layers, and the average pore diameter of the holes of the first passivation layer 2 is greater than the average pore diameter of the holes of the second passivation layer 3.

[0084] In the embodiment, the pore diameters of the holes of the first passivation layer 2 can be equal or not equal, and similarly, the pore diameters of the holes of the second passivation layer 3 can be equal or not equal. The average pore diameter of the holes of the first passivation layer 2 can be understood as the average pore diameter of all holes of the first passivation layer 2 or the average pore diameter of all holes in a unit area, and the average pore diameter of the holes of the second passivation layer 3 can be understood as the average pore diameter of all holes of the second passivation layer 3 or the average pore diameter of all holes in a unit area. By setting the average pore diameter of the holes of the first passivation layer 2 to be greater than the average pore diameter of the holes of the second passivation layer 3, the resistance of the first passivation layer 2 can be reduced, the resistance of the first passivation layer 2 is less than the resistance of the second passivation layer 3, the conductivity of the first passivation layer 2 is improved, the conductivity of the P region 11 is improved, and the implementation is simple.

[0085] As an optional embodiment of the present disclosure, the hole diameter of the first passivation layer 2 and the second passivation layer 3 is less than 10 um, and the average hole diameter of the first passivation layer 2 and the second passivation layer 3 is greater than the average hole diameter of the second passivation layer 3.

[0086] As an embodiment of the present disclosure, the thickness of the first passivation layer 2 is less than the thickness of the second passivation layer 3.

[0087] In this embodiment, the thickness of the first passivation layer 2 is less than the thickness of the second passivation layer 3, that is, by thinning the thickness of the first passivation layer 2, the setting of the hole is facilitated, the tunneling effect of the first passivation layer 2 is improved, the conductive effect of the P region 11 is improved, and the battery transmission effect of the P region 11 can be further improved.

[0088] As an embodiment of the present disclosure, the materials of the first passivation layer 2 and the second passivation layer 3 can be the same or different. For example, the first passivation layer 2 and the second passivation layer 3 can be one or a combination of silicon oxide, silicon oxynitride, and silicon nitride. When the materials of the first passivation layer 2 and the second passivation layer 3 are different, the material resistivity of the first passivation layer 2 is less than that of the second passivation layer 3, which facilitates the realization of different resistivities of the first passivation layer 2 and the second passivation layer 3; when the materials of the first passivation layer 2 and the second passivation layer 3 are the same, the resistivity of the first passivation layer 2 can be less than that of the second passivation layer 3 by changing the doping concentration, processing technology, etc.

[0089] As an embodiment of the present disclosure, the thickness of the P-type doped layer 4 is greater than the thickness of the N-type doped layer 5.

[0090] In this embodiment, the thickness of the P-type doped layer 4 is greater than the thickness of the N-type doped layer 5, which can ensure that the P-type doped layer 4 has good electrode burn-through resistance and the P region 11 has good passivation effect. Of course, in some other embodiments, the thickness of the P-type doped layer 4 can be less than or equal to the thickness of the N-type doped layer 5.

[0091] As an embodiment of the present disclosure, it further comprises:

[0092] The first back passivation layer 8 is arranged on the side of the P-type doped layer 4 away from the silicon substrate 1;

[0093] The second back passivation layer 9 is arranged on the side of the N-type doped layer 5 away from the silicon substrate 1.

[0094] The first back passivation layer 8 and the second back passivation layer 9 can each include at least one of an aluminum oxide film layer, a silicon oxide film layer, a silicon nitride film layer, a silicon carbide film layer, and a silicon oxynitride film layer, or a combination of multiple thereof, for example, in some embodiments, the first back passivation layer 8 and the second back passivation layer 9 can include an aluminum oxide film layer and a silicon nitride film layer stacked in sequence, which is not limited in particular herein.

[0095] In this embodiment, the first back passivation layer 8 and the second back passivation layer 9 can further improve the battery passivation effect and improve the battery efficiency.

[0096] The battery assembly provided by the embodiments of the present disclosure includes the solar cell provided by the above embodiments. It should be noted that the battery assembly has the same or similar beneficial effects as the solar cell, and the related parts between the two can be referred to each other, and will not be repeated here to avoid repetition.

[0097] The photovoltaic system provided by the embodiments of the present disclosure includes the battery assembly provided by the above embodiments. It should be noted that the photovoltaic system has the same or similar beneficial effects as the solar cell, and the related parts between the two can be referred to each other, and will not be repeated here to avoid repetition.

[0098] The solar cell provided by the embodiments of the present disclosure can improve the conduction effect of the P-type doped layer 4 by setting the band gap width of the P-type doped layer 4 to be smaller than the band gap width of the N-type doped layer 5, i.e., by reducing the band gap width of the P-type doped layer 4, so as to improve the current transmission effect of the P region, balance the current transmission effects of the P region and the N region, solve the problem of poor current transmission effect of the P region of the conventional solar cell, and make the P region and the N region of the solar cell achieve good current transmission effects, thereby effectively improving the battery efficiency.

[0099] The above are only preferred embodiments of the present disclosure, and are not used to limit the present disclosure. Any modification, equivalent replacement and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A solar cell, comprising: a silicon substrate, a surface of the silicon substrate being provided with a P region and an N region; a first passivation layer located at the P region, the first passivation layer being provided on the surface of the silicon substrate; a second passivation layer located at the N region, the second passivation layer being provided on the surface of the silicon substrate; a P-type doped layer provided on a side of the first passivation layer away from the silicon substrate; and an N-type doped layer provided on a side of the second passivation layer away from the silicon substrate; wherein a band gap width of the P-type doped layer is less than a band gap width of the N-type doped layer. The deposition temperature of the P-type doped layer is greater than the deposition temperature of the N-type doped layer. The diffusion temperature of the P-type doped layer is greater than the diffusion temperature of the N-type doped layer. The deposition temperature of the P-type doped layer is 595-630℃, and the deposition temperature of the N-type doped layer is 100-585℃. The diffusion temperature of the P-type doped layer is 750-950℃, and the diffusion temperature of the N-type doped layer is 100-900℃. The crystallization rate of the P-type doped layer is greater than the crystallization rate of the N-type doped layer. The band gap width of the P-type doped layer is 1.12-1.65eV, and the band gap width of the N-type doped layer is 1.1-1.6eV.

2. The solar cell of claim 1, wherein, The first passivation layer contains P-type dopants, and the second passivation layer contains N-type dopants, the doping concentration of the P-type dopants in the first passivation layer being greater than the doping concentration of the N-type dopants in the second passivation layer.

3. The solar cell of claim 1, wherein, The thickness of the P-type doped layer is greater than the thickness of the N-type doped layer.

4. The solar cell of claim 2, wherein, The thickness of the first passivation layer is less than the thickness of the second passivation layer.

5. The solar cell of claim 3, wherein, Both the first passivation layer and the second passivation layer are porous passivation layers, and the pore density of the first passivation layer is greater than the pore density of the second passivation layer.

6. The solar cell of claim 1, wherein, Both the first passivation layer and the second passivation layer are porous passivation layers, and the average pore size of the pores of the first passivation layer is greater than the average pore size of the pores of the second passivation layer.

7. The solar cell of claim 1, wherein, The solar cell is a back contact solar cell, and the P region and the N region are located on the same side of the silicon substrate.

8. The solar cell of claim 1, wherein, The solar cell is a bifacial solar cell, and the P region and the N region are located on opposite sides of the silicon substrate, respectively.

9. The solar cell of claim 1, wherein, 15.A battery assembly, comprising the solar cell according to any one of claims 1-14.

10. The solar cell of claim 1, wherein, 16.A photovoltaic system, comprising the battery assembly according to claim 15.

11. The solar cell of claim 1, wherein, ​ 12. The solar cell of claim 1, wherein, ​ 13. The solar cell of claim 1, wherein, ​ 14. The solar cell of claim 1, wherein, ​ ​ ​

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