Information processing method and apparatus

Abstract

An information processing method and an apparatus. The number and positions of zero elements in puncturing information columns of an LDPC base graph, so that the number of zero elements in first x rows of at least one puncturing information column decreases from top to bottom. In this way, the probability that variable nodes corresponding to two or more puncturing information columns participate in information transfer can be reduced, thereby helping to reduce the probability of invalid updates and thus improving performance of an LDPC code.

Description

Information processing method and apparatus

[0001] The present application claims priority to the Chinese patent application No. 202411233742.9, filed on September 4, 2024, and entitled "Information processing method and apparatus", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of communication, and more particularly, to an information processing method and apparatus. BACKGROUND

[0003] Low-density parity check (LDPC) code is one of the most mature and widely used channel coding schemes. In current LDPC codes, there are a lot of invalid information updates in the decoding process, which slows down the decoding convergence speed and increases the number of decoding iterations, thereby causing the throughput of the decoder to decrease. Especially when the number of decoding iterations is limited (especially small number of decoding iterations), the invalid information update will cause the decoding convergence to slow down significantly, resulting in poor decoding performance. SUMMARY

[0004] Embodiments of the present application provide an information processing method and apparatus to improve the performance of LDPC codes.

[0005] In a first aspect, embodiments of the present application provide an information processing method, which can be applied to the encoding side, such as an encoding device, a module (such as a circuit, a chip or a chip system (such as a modem chip, also known as a baseband chip, or a system on chip (SoC) chip or system in package (SIP) chip containing a modem core), or a logical node, a logical module or software capable of implementing all or part of the encoding device. The encoding device can be a terminal or a network device.

[0006] Taking the case that the method is applied to the encoding device, in the method, the encoding device obtains a first input bit sequence; encodes the first input bit sequence according to an LDPC base graph to obtain a coded bit sequence, wherein an element in the LDPC base graph is a zero element or a non-zero element, the LDPC base graph includes at least one puncturing information column, each puncturing information column in the at least one puncturing information column includes at least one non-zero element, and in a matrix region constituted by the at least one puncturing information column of the first x rows of the LDPC base graph, the number of zero elements is distributed from more to less in the order of row number from small to large, and x is an integer greater than 8.

[0007] The arrangement of zero elements of the punctured information columns of the base graph used by the encoding side can affect the performance of the LDPC code, such as the decoding performance. In the above method, the number and position of the zero elements in the punctured information columns of the LDPC base graph are limited, so that the number of zero elements in the first x rows of at least one punctured information column satisfies the distribution from more to less from top to bottom, which can reduce the probability of the case that two or more than two variable nodes corresponding to the punctured information columns participate in information transmission, thereby helping to reduce the probability of invalid update, thereby improving the performance of the LDPC code.

[0008] In a possible design, the matrix region includes at least one first row, and the first row has one non-zero element.

[0009] Based on this design, the probability of invalid update can be further reduced.

[0010] In a possible design, the columns where the non-zero elements of the first y rows of the matrix region are located are the same as the columns where the non-zero elements of the first y-1 rows of the matrix region are located, y being an integer greater than 1; and / or, the columns where the non-zero elements of the first r rows of the matrix region are located are one column more than the columns where the non-zero elements of the first r-1 rows of the matrix region are located, r being an integer greater than 1.

[0011] Based on this design, the matrix region further satisfies that each row has no non-zero element corresponding to a variable node that does not normally perform information update or each row has one non-zero element corresponding to a variable node that does not normally perform information update, under the premise that the number of zero elements is distributed from more to less. This design can avoid the case that two or more than two variable nodes corresponding to the punctured information columns participate in information transmission, thereby avoiding invalid update.

[0012] In a possible design, the LDPC base graph further includes at least one punctured check column; and in a part constituted by the matrix region and the at least one punctured check column of the first x rows of the LDPC base graph, the number of zero elements is distributed from more to less in the order of row number from small to large.

[0013] In some scenarios, puncturing of check bits can occur. For example, in the scenario of an extremely high code rate, encoding or decoding is performed using the core matrix of the LDPC base graph, and puncturing of check bits can occur during rate matching. For these scenarios, embodiments of the present application design the punctured information columns and the punctured check columns of the LDPC base graph to satisfy the distribution of the number of zero elements from more to less in the order of row number from small to large, which can reduce the probability of invalid update caused by the punctured check columns.

[0014] In a possible design, the number of the at least one punctured information column is 1 or 2. Alternatively, the number of the at least one punctured information column is greater than or equal to 3.

[0015] In a second aspect, embodiments of this application provide an information processing method, which can be applied to a decoding side, such as a decoding device, a module (e.g., a circuit, a chip or a chip system (e.g., a modem chip, also known as a baseband chip, or a SoC chip or a SIP chip containing a modem core) in the decoding device, or a logic node, a logic module or software capable of implementing all or part of the decoding device. The decoding device can be a network device or a terminal. The same terms or features in the second aspect or its implementation as in the first aspect or its implementation can refer to the first aspect or its implementation, and the technical effects of the second aspect or its implementation can refer to the technical effects in the first aspect or its implementation, which will not be repeated in the second aspect.

[0016] For example, in the method, the decoding device obtains a second input bit sequence; and decodes the second input bit sequence according to an LDPC base graph to obtain a decoded bit sequence, wherein an element in the LDPC base graph is a zero element or a non-zero element, the LDPC base graph includes at least one punctured information column, each of the at least one punctured information column includes at least one non-zero element, and in a matrix region constituted by the at least one punctured information column of the first x rows of the LDPC base graph, the number of zero elements is distributed from more to less in the order of row numbers from small to large, and x is an integer greater than 8.

[0017] In a possible design, the matrix region includes at least one first row, and the first row has one non-zero element.

[0018] In a possible design, the column where the non-zero element of the y-th row of the matrix region is located is the same as the column where the non-zero element of the y-1-th row of the matrix region is located, and y is an integer greater than 1.

[0019] In a possible design, the column where the non-zero element of the r-th row of the matrix region is located is one more than the column where the non-zero element of the r-1-th row of the matrix region is located, and r is an integer greater than 1.

[0020] In a possible design, the LDPC base graph further includes at least one punctured check column, and in a part constituted by the matrix region and the at least one punctured check column of the first x rows of the LDPC base graph, the number of zero elements is distributed from more to less in the order of row numbers from small to large.

[0021] In a possible design, the number of the at least one punctured information column is 1 or 2. Alternatively, the number of the at least one punctured information column is greater than or equal to 3.

[0022] In a third aspect, embodiments of the present application provide a communication apparatus, which can implement the functions of the first aspect or any of its possible designs. For example, the communication apparatus can include modules or units or means corresponding to the operations of the first aspect or any of its possible designs, which can be implemented in software, or in hardware, or in a combination of software and hardware.

[0023] In a fourth aspect, embodiments of the present application provide a communication apparatus, which can implement the functions of the second aspect or any of its possible designs. For example, the communication apparatus can include modules or units or means corresponding to the operations of the second aspect or any of its possible designs, which can be implemented in software, or in hardware, or in a combination of software and hardware.

[0024] In a fifth aspect, embodiments of the present application provide a communication apparatus, which can include an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory is configured to store part or all of the necessary computer programs or instructions for implementing the functions of the first aspect or any of its possible designs. The one or more processors can execute the computer programs or instructions, which, when executed, cause the communication apparatus to implement the method of the first aspect or any of its possible designs. The interface circuit is configured to implement the communication function within the communication apparatus and / or the communication function of the communication apparatus with other apparatuses or components.

[0025] In a possible design, the processor is configured to communicate with other apparatuses or components via the interface circuit.

[0026] In a possible design, the communication apparatus can further include the memory.

[0027] The communication apparatus can be a terminal, a communication module in a terminal, or a chip responsible for the communication function in a terminal, such as a modem chip or a SoC or SIP chip including a modem module.

[0028] The communication apparatus can also be a network device, a module (e.g., a circuit, a chip or a chip system, etc.) in a network device, or a logic node, a logic module or software capable of implementing all or part of a network device.

[0029] In a sixth aspect, embodiments of the present application provide a communication apparatus, which comprises an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory is configured to store part or all of the computer program or instructions necessary to implement the functions of the above-mentioned second aspect or any of its possible designs. The one or more processors can execute the computer program or instructions, which, when executed, cause the communication apparatus to implement the method in the above-mentioned second aspect or any of its possible designs. The interface circuit is configured to implement the communication function within the communication apparatus and / or the communication function of the communication apparatus with other apparatuses or components.

[0030] In a possible design of the above apparatus, the processor is configured to communicate with other apparatuses or components via the interface circuit.

[0031] In a possible design of the above apparatus, the communication apparatus further comprises the memory.

[0032] The above communication apparatus can be a terminal, or a communication module in a terminal, or a chip responsible for the communication function in a terminal, such as a modem chip or a SoC or SIP chip containing a modem module.

[0033] The above communication apparatus can also be a network device, a module (for example, a circuit, a chip or a chip system, etc.) in a network device, or a logic node, a logic module or software capable of implementing all or part of a network device.

[0034] In a seventh aspect, embodiments of the present application provide a communication system, which comprises at least one of the above-mentioned encoding device or decoding device.

[0035] In an eighth aspect, embodiments of the present application provide a computer readable storage medium, which stores computer readable instructions, when a computer reads and executes the computer readable instructions, the computer executes the method in any of the above-mentioned aspects or any of its possible designs.

[0036] In a ninth aspect, embodiments of the present application provide a computer program product, when a computer reads and executes the computer program product, the computer executes the method in any of the above-mentioned aspects or any of its possible designs.

[0037] In a tenth aspect, embodiments of the present application provide a computer program, when it is run on a computer, the method provided by any of the above-mentioned aspects or any of its possible designs is executed. BRIEF DESCRIPTION OF DRAWINGS

[0038] FIG. 1 is a schematic diagram of a network architecture to which embodiments of the present application can be applied.

[0039] FIG. 2 is a schematic diagram of a communication system 200 to which embodiments of the present application can be applied.

[0040] FIG. 3 is a Tanner graph of a check matrix H.

[0041] FIG. 4 is a schematic diagram of a base graph and a base matrix.

[0042] FIG. 5 is a schematic diagram of a structure of a check matrix of an LDPC code in a raptor-like structure.

[0043] FIG. 6 is a schematic diagram of information passing in a layered decoding algorithm.

[0044] FIG. 7 is a schematic diagram of a node update flow in a layered decoding algorithm.

[0045] FIG. 8 is a schematic flowchart of an information processing method 800 provided by the present application.

[0046] FIG. 9 is a simulation result of decoding performance of an LDPC code of the present application and a 5th generation mobile communication technology (5G) LDPC code. th

[0047] FIG. 10 is an exemplary block diagram of an apparatus provided by an embodiment of the present application.

[0048] FIG. 11 is a schematic diagram of a structure of a terminal provided by an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the embodiments of the present application, the following points are explained before the embodiments of the present application are introduced.

[0050] ​"System" and "network" can be used interchangeably. "At least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship of associated objects, which means that there can be three relationships, for example, A and / or B can represent the cases of A alone, A and B together, and B alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, "at least one of A, B, or C" includes A, B, C, AB, AC, BC, or ABC, and "at least one of A, B, and C" can also be understood to include A, B, C, AB, AC, BC, or ABC. In addition, unless otherwise specified, the ordinal numbers "first", "second", etc. mentioned in the embodiments of the present application are used to distinguish a plurality of objects, and are not used to limit the order, time sequence, priority or importance of the plurality of objects. The "protocol" referred to can refer to a standard protocol in the communication field, which can include a long term evolution (LTE) protocol, a new radio (NR) protocol, and related protocols applied in future communication systems, which are not limited by the present application. "Example", "for example", "exemplarily", "as (another) example" and the like are used to indicate as an example, illustration or explanation. Any embodiment or design scheme described as "example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. The terms "include", "contain", "have" and their variants mean "include but are not limited to", unless otherwise specifically emphasized. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b and c can represent: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple.

[0051] In the present application, "sending information" can be understood as a device sending information to another device, or it can also be understood as a logical module in a device sending information to another logical module. For example, "the encoding device sends information" can be understood as the encoding device sending information to another device (such as a decoding device), or it can be understood as a logical module 1 in the encoding device sending information to a logical module 2 in the encoding device.

[0052] In the present application, "receiving information" can be understood as a device receiving information from another device, or can also be understood as a logical module in a device receiving information from another logical module. For example, "decoding device receiving information" can be understood as the decoding device receiving information from another device (such as an encoding device), or can be understood as a logical module 1 in the decoding device receiving information from a logical module 2 in the decoding device.

[0053] In the present application, "sending information to (for example, a decoding device)" or related illustrations in the drawings can be understood as that the destination of the information is the decoding device. It can include directly or indirectly sending information to the terminal. "Receiving information from (for example, an encoding device)" or "receiving information from (for example, an encoding device)" or "receiving information sent by (for example, an encoding device)", or related illustrations in the drawings can be understood as that the source of the information is the encoding device, and can include directly or indirectly receiving information from the encoding device. The information can be processed as necessary between the source and the destination of the information sending, such as format change, etc., but the destination can understand the valid information from the source. Similar expressions in the present application can be similarly understood, and will not be described here.

[0054] In addition, the network architecture and service scenarios described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of network architecture and the appearance of new service scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0055] The communication system to which the embodiments of the present application can be applied will be described below.

[0056] Embodiments of the present application can be applied to various communication systems, including but not limited to a 5G system or NR system, an LTE system, a long term evolution-advanced (LTE-A) system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, and the like. It can also be applied to future communication systems. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), internet of things (IoT) communication system, narrow band-internet of things (NB-IoT), or other communication systems. In addition, it can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and 3rd generation partnership project (3GPP) related communication systems, without limitation.

[0057] A communication system suitable for embodiments of the present application can include one or more transmitting end devices and one or more receiving end devices. Optionally, one of the transmitting end device and the receiving end device can be a terminal, and the other can be a network device. Optionally, both the transmitting end device and the receiving end device can be terminals. Optionally, both the transmitting end device and the receiving end device can be network devices.

[0058] In the present application, the transmitting end device can be understood as a data or information transmitting end device, which can also be referred to as an encoding device. The receiving end device can be understood as a data or information receiving end device, which can also be referred to as a decoding device. The scheme of the present application is described below using the encoding device and the decoding device.

[0059] Exemplarily, FIG. 1 shows a schematic diagram of a network architecture to which embodiments of the present application can be applied.

[0060] Figure 1 shows a possible, non-limiting, schematic illustration of a system. As shown in Figure 1, the communication system 10 includes a radio access network (RAN) 100 and a core network (CN) 200. The RAN 100 includes at least one RAN node (e.g., 110a and 110b in Figure 1, collectively referred to as 110) and at least one terminal (e.g., 120a-120j in Figure 1, collectively referred to as 120). Other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 1), etc., can also be included in the RAN 100. The terminals 120 are wirelessly connected to the RAN nodes 110. The RAN nodes 110 are connected to the core network 200 through wireless or wired means. The core network devices in the core network 200 and the RAN nodes 110 in the RAN 100 can be different physical devices, respectively, or can be the same physical device that integrates the core network logical functions and the radio access network logical functions.

[0061] The RAN 100 can be a 3rd generation partnership project (3GPP) related cellular system, e.g., a 4G, 5G mobile communication system, or a future-oriented evolved system. The RAN 100 can also be an open radio access network (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. The RAN 100 can also be a communication system that integrates two or more of the above systems.

[0062] The RAN nodes 110, which can also be referred to as access network devices, RAN entities, or access nodes, etc., form part of the communication system to help terminals to access wirelessly. The RAN nodes 110 in the communication system 10 can be of the same type or of different types. In some scenarios, the roles of the RAN nodes 110 and the terminals 120 are relative, e.g., the network element 120i in Figure 1 can be a helicopter or a drone, which can be configured as a mobile base station. For a terminal 120j that accesses the RAN 100 through the network element 120i, the network element 120i is a base station; but for the base station 110a, the network element 120i is a terminal. The RAN nodes 110 and the terminals 120 are sometimes referred to as communication apparatuses, e.g., the network elements 110a and 110b in Figure 1 can be understood as communication apparatuses with base station functions, and the network elements 120a-120j can be understood as communication apparatuses with terminal functions.

[0063] In a possible scenario, the RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a WiFi system, etc. The RAN node can be a macro base station (such as 110a in FIG. 1), a micro base station or an indoor station (such as 110b in FIG. 1), a relay node or a donor node, or a wireless controller in a CRAN scenario. Optionally, the RAN node can also be a server, a wearable device, a vehicle or a vehicle-mounted device, etc. For example, the access network device in vehicle to everything (V2X) technology can be a road side unit (RSU). All or part of the functions of the RAN node in this application can also be implemented by software functions running on hardware, or by virtualized functions instantiated on a platform (such as a cloud platform). The RAN node can also be provided with a communication module, circuit or chip for performing corresponding communication functions, and program instructions for performing corresponding communication functions. The RAN node in this application can also be a logical node, a logical module or software that can implement all or part of the functions of the RAN node.

[0064] In another possible scenario, multiple RAN nodes cooperate to assist a terminal to implement wireless access, and different RAN nodes respectively implement part of the functions of a base station. For example, the RAN node can be a central unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU), etc. The CU and the DU can be separately arranged, or can be included in the same network element, such as a baseband unit (BBU). The RU can be included in a radio frequency device or a radio frequency unit, such as a remote radio unit (RRU), an active antenna processing unit (AAU), or a remote radio head (RRH).

[0065] The CU (or CU-CP and CU-UP), DU or RU can also have different names in different systems, but those skilled in the art can understand their meanings. For example, in an ORAN system, the CU can also be referred to as an O-CU (open CU), the DU can also be referred to as an O-DU, the CU-CP can also be referred to as an O-CU-CP, the CU-UP can also be referred to as an O-CU-UP, and the RU can also be referred to as an O-RU. For the convenience of description, the CU, CU-CP, CU-UP, DU and RU are taken as examples for description in this application. Any one of the CU (or CU-CP, CU-UP), DU and RU in this application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0066] In embodiments of the present application, the access network device can also be referred to as a network device.

[0067] A terminal can be a device or module with corresponding communication functions and can access the above communication system. The terminal can also be referred to as a terminal device, a user equipment (UE), a mobile station, a mobile terminal, etc. The terminal can be widely used in various scenarios, such as device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-type communication (MTC), internet of things (IOT), virtual reality, augmented reality, industrial control, autonomous driving, remote medical treatment, smart power grid, smart furniture, smart office, smart wear, smart transportation, smart city, etc. The terminal can be a mobile phone, a tablet computer, a computer with wireless transceiver function, a wearable device, a vehicle, a drone, a helicopter, an airplane, a ship, a robot, a mechanical arm, a smart home device, a transport vehicle with wireless communication function, a communication module, etc. Embodiments of the present application do not limit the device form of the terminal. The terminal is usually provided with a communication module, circuit or chip for executing corresponding communication functions. The terminal is also configured with program instructions for executing corresponding communication functions.

[0068] Unless otherwise specified, the apparatus for implementing the functions of the terminal or network device in this application can refer to the terminal or network device itself, or can refer to an apparatus capable of supporting the terminal or network device to implement the functions, such as a chip system or a chip, specifically, a SoC or a modem. The apparatus can be installed in the terminal or network device. In embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0069] It should also be noted that some embodiments in this document take 5G system as an example to introduce specific scheme details. It can be understood that when the scheme is used in other communication systems, for example, LTE system, or future communication system, the messages, channels or information in the scheme can be replaced by messages, channels or information capable of realizing corresponding functions in other communication systems, and the present application does not limit this.

[0070] Embodiments of the present application can be applied to various communication scenarios. Specifically, for example, point-to-point connection between network device and terminal, multi-hop or multi-relay transmission of network device and terminal, dual connectivity (DC) or multi-connection of multiple network devices and terminals, or multi-hop multi-connection of multiple network devices and terminals, etc.

[0071] In addition, embodiments of the present application can be applied to various application scenarios, such as high throughput scenario, high reliability scenario, low latency scenario, high reliability low latency scenario or low power consumption scenario. Among them, the high throughput scenario may, for example, be an enhanced mobile broadband (eMBB) scenario, etc., the high reliability low latency scenario may, for example, be an ultra reliable low latency communication (URLLC) scenario, etc., and the low power consumption scenario may, for example, be an M2M scenario, an MTC scenario or an IoT scenario, etc.

[0072] Embodiments of the present application provide technical solutions that can be applied to channel encoding / decoding between communication devices. Channel encoding / decoding between communication devices can include channel encoding / decoding between network devices and terminal devices, channel encoding / decoding between network devices and network devices, and channel encoding / decoding between terminal devices and terminal devices. Among them, the term "channel encoding" can also be referred to as "encoding", "network encoding", "source channel joint encoding", etc., and the term "channel decoding" can also be referred to as "decoding", "network decoding", "source channel joint decoding", etc.

[0073] FIG. 2 is a schematic diagram of a communication system 200 to which embodiments of the present application can be applied.

[0074] As shown in FIG. 2, at the encoding side, the information data is subjected to operations such as cyclic redundancy check (CRC) calculation, code block segmentation, channel coding, rate matching, interleaving, and modulation, and the processed information data is sent out. At the decoding side, the information is received, and the received information data is subjected to operations such as demodulation, deinterleaving, de-rate matching, channel decoding, code block merging, and transport block CRC, to obtain the processed information data. The processing at the encoding side can be performed by, for example, an encoding device, a module (such as a circuit, a chip or a chip system (such as a modem chip, or a SoC chip or a SIP chip containing a modem core, etc.), or a logical node, a logical module or software capable of implementing all or part of the encoding device) in the encoding device. The processing at the decoding side can be performed by, for example, a decoding device, a module (such as a circuit, a chip or a chip system (such as a modem chip, or a SoC chip or a SIP chip containing a modem core, etc.), or a logical node, a logical module or software capable of implementing all or part of the decoding device) in the decoding device.

[0075] The encoding side can perform corresponding encoding according to the structure of the LDPC base graph provided by the embodiments of the present application. The decoding side can perform corresponding decoding according to the structure of the LDPC base graph provided by the embodiments of the present application. The encoding and / or decoding in FIG. 2 can be implemented in a hardware manner, or in a software manner. In a case where the demand for encoding / decoding throughput is high, a hardware accelerator (HAC) can be used for implementation.

[0076] In order to facilitate understanding of the embodiments of the present application, several concepts or terms related to the embodiments of the present application are briefly described. The concepts or terms described below are described based on the concepts or terms defined in the protocol, but it does not mean that the embodiments of the present application can only be applied to the existing system. The concepts or terms related to the embodiments of the present application can be applied to future systems. And the specific names of the concepts or terms (such as concepts or terms related to functional description) can be adjusted as the future system develops.

[0077] 1. LDPC code

[0078] An LDPC code is a kind of linear block code, and its check matrix has a sparse characteristic. The proportion of non-zero elements in the check matrix of the LDPC code is extremely small, or in other words, the row weight and the column weight of the check matrix are very small numbers compared with the code length of the LDPC code. For an LDPC code with an information bit number K and a code length N, the dimension of the check matrix H is (N-K) x N, and the corresponding code word c can be defined by the check matrix H as follows: c = {c | Hc T = 0, c ∈ {0, 1} N}

[0079] .

[0080] In the check matrix H, each row corresponds to a check equation of the LDPC code, and the N-K check equations correspond to the N-K check nodes of the LDPC code; each column corresponds to a symbol of the LDPC code, and the N symbols correspond to the N variable nodes of the LDPC code. The non-zero element h i,j indicates that the ith check node and the jth variable node are connected. The number of non-zero elements in each row of the check matrix is the degree of the check node, and the number of non-zero elements in each column is the degree of the variable node. If the degrees of all check nodes are equal and the degrees of all variable nodes are equal, the LDPC code corresponding to the matrix is a regular code, otherwise it is an irregular code. Exemplarily, a check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 can be as follows:

[0081] wherein v0, v1, …, v9 represent variable nodes, and c0, c1, …, c4 represent check nodes.

[0082] The LDPC code can be represented by a graph model, and common graph models include Tanner graph, factor graph and tree graph, etc., wherein the Tanner graph is relatively simple and intuitive. The Tanner graph of the check matrix H described above can be as shown in FIG. 3, wherein the degrees in FIG. 3 correspond to the definition of the degrees in the check matrix H described above, and the degree of a node can be defined as the number of edges connected thereto.

[0083] 2. Quasi-cyclic low density parity check (QC-LDPC) code

[0084] The check matrix of the QC-LDPC code has a quasi-cyclic characteristic, and the check matrix H can be represented simply according to the quasi-cyclic structure.

[0085] The parity check matrix H of a QC-LDPC code can be derived from a base graph (BG) and shift value. The base graph can generally include m*n matrix entries, which can be represented in a matrix form of m rows and n columns, and the matrix entries are either 0 or 1. The entry represented as 0, sometimes also referred to as a zero entry, indicates that the entry can be replaced by a zero matrix of Z*Z, and the entry represented as 1, sometimes also referred to as a non-zero entry, indicates that the entry can be replaced by a circulant permutation matrix of Z*Z. That is, each matrix entry in the base graph represents either a zero matrix or a circulant permutation matrix. An example of each entry in a base graph of an LDPC code with QC structure of m=4 and n=26 is shown in 10a of FIG. 4. It should be noted that in this document, the row and column numbers of the base graph and the matrix are numbered from 0, which is merely for the convenience of description. For example, the 0th column represents the first column of the base graph and the matrix, the 1st column represents the second column of the base graph and the matrix, the 0th row represents the first row of the base graph and the matrix, and the 1st row represents the second row of the base graph and the matrix, and so on. It can be understood that the row and column numbers can also be numbered from 1, and the corresponding row and column numbers are obtained by adding 1 to the row and column numbers shown in this document. For example, if the row and column numbers are numbered from 1, the 1st column represents the first column of the base graph and the matrix, the 2nd column represents the second column of the base graph and the matrix, the 1st row represents the first row of the base graph and the matrix, and the 2nd row represents the second row of the base graph and the matrix, and so on.

[0086] If the entry in the i-th row and the j-th column of the base graph is a non-zero entry, and the shift value is P i,j , P i,j is an integer greater than or equal to 0, then the non-zero entry in the i-th row and the j-th column can be replaced by a corresponding circulant permutation matrix of Z*Z of P i,j . The circulant permutation matrix can be obtained by performing P i,j times of right or left cyclic shift on a unit matrix of Z*Z. It can be seen that each zero entry in the base graph can be replaced by a zero matrix of Z*Z, and each non-zero entry can be replaced by a corresponding circulant permutation matrix of Z*Z of the shift value, and thus the parity check matrix of the LDPC code can be obtained. Z is a positive integer, which can also be referred to as a lifting factor, sometimes also referred to as a lifting size or a lifting factor, etc. Z can be determined according to the code block size supported by the system and / or the size of the information data. It can be seen that the size of the parity check matrix H is (m*Z)*(n*Z).

[0087] P i,jP i,j may be based on an extension factor Z, and different extension factors Z can result in different P i,j for non-zero elements in the same position i,j . To simplify implementation, a system also defines a base matrix of m rows and n columns. Each element in the base matrix corresponds to the position of each element in the base graph. Zero elements in the base graph remain in the same position in the base matrix, and can be represented by -1 or a null value. Non-zero elements in the i-th row and j-th column of the base graph remain in the same position in the base matrix, and can be represented as V i,j = mod(V i,j , Z) (mod(A, B) represents A modulo B). In embodiments of the present application, the base matrix can also be referred to as an offset matrix of the base graph matrix. As shown in 10b of FIG. 4, a base matrix corresponding to the base graph 10a is shown.

[0088] For example, as shown in FIG. 4, the extension factor Z = 4. Each zero element is replaced by a 4*4 all-zero matrix 11a. If P 2,4 = 0, the non-zero element in the 2nd row and 4th column is replaced by an identity matrix 11b. If P 0,0 = 1, the non-zero element in the 0th row and 0th column is replaced by a 4*4 cyclic shift matrix 11c, which is obtained by shifting the identity matrix 11b to the right by 1. If P 2,3 = 2, the non-zero element in the 2nd row and 3rd column is replaced by a 4*4 cyclic shift matrix 11d, which is obtained by shifting the identity matrix 11b to the right by 2. If P 1,3 = 3, the non-zero element in the 1st row and 3rd column is replaced by a 4*4 cyclic shift matrix 11e, which is obtained by shifting the identity matrix 11b to the right by 3. It should be noted that the above examples are merely illustrative and are not limiting.

[0089] Generally, an LDPC code can be obtained based on a base graph and / or a base matrix. Optimization of the positions of zero elements and non-zero elements in the base graph or base matrix can determine the upper limit of the performance of the LDPC code, and the error floor of the LDPC code can be determined based on the offset values in the base matrix. Improving the coding and decoding performance and reducing the error floor are one of the goals of determining the base graph and base matrix.

[0090] FIG. 5 is a structural diagram of a base graph of an LDPC code using a raptor-like structure. The base graph is composed of four parts:

[0091] 1) a core matrix H core in the upper left corner;

[0092] 2) an all-zero matrix Hzero ;

[0093] 3) the extended matrix H in the lower left corner rex ;

[0094] 4) the diagonal matrix H in the lower right corner diag .

[0095] The systematic bits in FIG. 5 can also be referred to as information bits. Sometimes, the check bits and the incremental check bits can also be collectively referred to as check bits. With a raptor-like structure, the core matrix H core is taken as the basis for the codeword extension of the diagonal matrix H diag in the lower right corner, and incremental check bits are added to support flexible code length and code rate. In actual use, the first a rows and the first b columns of the base graph can be intercepted according to the code length and / or the code rate. As the code rate decreases and / or the code length increases, a and b gradually increase, and the area of the base graph used also gradually expands. For example, in the case of an extremely high code rate, the core part of the base graph can be used for encoding or decoding. For another example, in the case of a low code rate or a large code length, the entire base graph can be used for encoding or decoding.

[0096] 3, puncturing, punctured information columns, and punctured check columns

[0097] Puncturing is a mode in molding. In an LDPC code, puncturing a column of a check matrix or a base graph can mean not transmitting the bit corresponding to the column.

[0098] The column corresponding to the information bit can be referred to as an information column, the column corresponding to the punctured bit can be referred to as a punctured column, and the column corresponding to the check bit can be referred to as a check column. In an LDPC code, the information column and / or the check column can be punctured. The punctured information column can be referred to as a punctured information column or an information punctured column, and the punctured check column can be referred to as a punctured check column or a check punctured column.

[0099] In the current LDPC code, the non-zero elements of the first two columns of the base graph are large in number, that is, the column weight of the first two columns is large. These two columns have many connection relationships and can fully exchange information with each check node, and are usually the bits that are most easily decoded correctly. Usually, in order to increase the code rate, the information bits corresponding to the first two columns are punctured when transmitting the encoded bits. Although the two information bits are punctured, the check bits and the punctured bits are fully connected because the punctured bits participate in encoding. In decoding, the log-likelihood ratio (LLR) of the punctured bits is initialized to 0, and through full iteration of information transmission between the variable nodes and the check nodes, the punctured information bits can still be decoded correctly and recovered.

[0100] 4, layered decoding of 5G LDPC

[0101] 5G LDPC decoding adopts row-wise layered decoding method, and variable node Q j Update and check node information update. At the first iteration, the variable node Q j The channel LLR value is initialized by assigning, wherein the LLR of the variable node corresponding to the two columns of the punctured row is initialized to 0.

[0102] In the row-wise layered decoding algorithm, the check matrix is divided into L layers according to the rows, M is the number of rows of the check matrix, and Z is the lifting value, that is, each layer corresponds to a row of the base matrix, and Z rows of the extended matrix. During decoding, it is updated layer by layer, and after completing the update of each layer, the variable node Q j is updated once, so that in one iteration, the information of the layer updated first can be directly transmitted to the subsequent layer, and the information interaction does not have to wait for the next iteration. Through the rapid interaction of information, the decoding convergence speed can be effectively accelerated.

[0103] Figure 6 is a schematic diagram of information transmission in the layered decoding algorithm.

[0104] As shown in Figure 6, in one iteration, the check node update of layer 0 is performed first, and the variable node connected thereto is updated; then the check node of layer 1 is updated according to the latest variable node, and then the variable node connected to the check node of layer 1 is updated; in this way, each layer is updated in turn, and when the check node of layer L-1 and the variable node connected thereto are updated, the current iteration is completed, and the next iteration is started from layer 0.

[0105] Figure 7 is a schematic diagram of node update flow in the layered decoding algorithm.

[0106] Figure 7 takes the check matrix H with code length 10 and code rate 1 / 2 mentioned above as an example to illustrate the node update flow in one iteration. In Figure 7, the check matrix is divided into 5 layers according to the rows, and each layer contains a row, that is, each layer corresponds to a check node. In one iteration, the node update flow is as follows:

[0107] 1) First, the check node of row 0 in layer 0 is updated;

[0108] 2) Then, the variable nodes connected to row 0 (i.e. the variable nodes corresponding to columns 0, 1, 2, and 3) are updated;

[0109] 3) Then, the check node of row 1 in layer 1 is updated;

[0110] 4) Then, the variable nodes connected to row 1 (i.e. the variable nodes corresponding to columns 0, 4, 5, and 6) are updated;

[0111] 5) Then update the check node of row 2 in layer 2;

[0112] 6) Then update the variable nodes connected to row 2 (i.e., the variable nodes corresponding to columns 1, 4, 7, and 8);

[0113] 7) Then update the check node of row 3 in layer 3;

[0114] 8) Then update the variable nodes connected to row 3 (i.e., the variable nodes corresponding to columns 2, 5, 6, and 9);

[0115] 9) Then update the check node in row 3 of layer 4;

[0116] 10) Then update the variable nodes that are connected to row 4 (i.e., the variable nodes corresponding to columns 3, 7, 8, and 9).

[0117] When updating rows and columns hierarchically, the Min-Sum (MS) algorithm is often used to update row and column information.

[0118] For example, the row update formula that satisfies the minimum sum algorithm can be as follows:

[0119] Where α is the correction factor coefficient, with a value range of [0,1], and Ra ij To verify the magnitude of the information transmitted from node i to variable node j, Rs ij To verify the sign of the information passed from node i to variable node j, R ij Let V(i) be the set of variable nodes connected to the i-th row, and i be the corresponding verification node in the current row. Q ji The information passed from variable node j to check node i is initialized as channel LLR. For variable nodes corresponding to the punched column, the initial LLR is 0.

[0120] In calculating the R value passed from check node i to its connected variable node j. ij First, calculate Ra. ij We need to remove the value corresponding to the current j from the amplitudes of the set V(i) of all variable nodes connected to the verification node i, and determine the minimum value among the remaining amplitudes. Taking the verification node C0 in Figure 3 as an example, the verification node C0 is connected to variable nodes V0, V1, V2, and V6. Here, the set V(C0) = {V0, V1, V2, V6}. When calculating the values ​​passed from the verification node C0 to V0... At this time, it is necessary to calculate the amplitude for V1, V2, and V6, and determine a minimum value among them, which is then passed to the verification node C0 for V1. At this time, the amplitudes for V0, V2 and V6 need to be calculated, and a minimum value is determined among them.

[0121] It should be understood that the above formula 1 is for illustration only, and is only to help those skilled in the art to understand the embodiments of the application, and is not intended to limit the embodiments of the application to the specific formula shown.

[0122] The above describes the related terms involved in the embodiments of the application, which will not be explained hereinafter.

[0123] In the current LDPC code, the first two columns of information columns of the LDPC base graph are punctured columns. The information bits corresponding to the two punctured columns participate in the encoding process, but the information bits corresponding to the two punctured columns after encoding are not transmitted. When decoding, the channel LLR of the two punctured columns is initialized to zero, and all bit information can be recovered through the iteration process of LDPC decoding. However, in the current LDPC base graph, the influence of the distribution of zero elements in the punctured columns on the decoding performance is not considered, and inappropriate distribution may cause invalid update of information in LDPC decoding, which slows down the decoding convergence speed, increases the number of decoding iterations, and thus causes the throughput of the decoder to decrease. Especially when the number of decoding iterations is limited (especially small number of decoding iterations), the invalid update of information will cause the decoding convergence to slow down significantly, resulting in poor decoding performance.

[0124] To solve the above problems, the present application provides an information processing method and device to improve the decoding performance.

[0125] The method embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0126] FIG. 8 is a schematic flowchart of an information processing method 800 provided by the present application.

[0127] It can be understood that the present application takes the encoding device and the decoding device as an example to illustrate the execution subject of the interaction, but the present application does not limit the execution subject of the interaction. For example, the method executed by the encoding device in the present application can also be implemented by a module in the encoding device, or a logical node, a logical module or software capable of realizing all or part of the function of the encoding device; the method executed by the decoding device in the present application can also be implemented by a module in the decoding device, or a logical node, a logical module or software capable of realizing all or part of the function of the decoding device. The module in the encoding device and / or the decoding device can be, for example, a circuit, a chip or a chip system (such as a modem chip, also known as a baseband chip, or a SoC chip or a SIP chip containing a modem core). The encoding device can be a terminal device or a network device, and the decoding device can be a network device or a terminal device.

[0128] The method 800 can include at least part of the following contents.

[0129] Step 801, the encoding device acquires a first input bit sequence.

[0130] Exemplarily, the first input bit sequence can be an information bit sequence to be encoded. If the encoding device needs to communicate with the decoding device, i.e., the encoding device needs to send a signal to the decoding device, the encoding device needs to acquire an information bit sequence corresponding to the signal to be sent to the decoding device. Wherein, the encoding device acquiring the information bit sequence can refer to that the encoding device source encodes the source symbol to generate the information bit sequence. The encoding device acquiring the information bit sequence can also refer to that the encoding device receives the information bit sequence from other communication devices.

[0131] Step 802, the encoding device encodes the first input bit sequence according to the LDPC base graph to obtain an encoded bit sequence.

[0132] In the encoding process, the encoding device can use the LDPC base graph for encoding, or further obtain a base graph actually used for encoding based on the LDPC base graph. Exemplarily, the encoding device can perform row transformation and / or column transformation on the LDPC base graph to obtain the base graph actually used. Exemplarily, the encoding device can use part or all of the LDPC base graph for encoding according to the code rate and / or code length, and detailed description can be referred to FIG. 5.

[0133] Step 803, the encoding device sends first information to the decoding device, and correspondingly, the decoding device receives the first information from the encoding device.

[0134] Wherein, the first information is obtained based on the encoded bit sequence. Exemplarily, the encoding device can further process the encoded bit sequence to obtain the first information, and specific operations can be referred to the operations of the encoding side in FIG. 2, and then sent to the decoding device.

[0135] It should be noted that, since channel noise can be introduced in the transmission process of information, the information received by the decoding device can be different from the information output or sent by the encoding device, and thus the bit sequence to be decoded obtained therefrom can also be different from the encoded bit sequence output by the encoding device.

[0136] Step 804, the decoding device acquires a second input bit sequence.

[0137] Exemplarily, the decoding device can process the received first information to obtain the bit sequence to be decoded, i.e., the second input bit sequence, and specific operations can be referred to the operations of the decoding side in FIG. 2.

[0138] Step 805, the decoding device decodes the second input bit sequence according to the LDPC base graph to obtain a decoded bit sequence.

[0139] In the decoding process, the decoding device can use the LDPC base graph to decode, or further obtain a base graph actually used for decoding based on the LDPC base graph. For example, the decoding device can perform row transformation and / or column transformation on the LDPC base graph to obtain the base graph actually used. For example, the decoding device can use part or all of the LDPC base graph to decode according to the code rate and / or the code length. For details, refer to FIG. 5.

[0140] In an embodiment of the present application, the LDPC base graph includes at least one punctured information column, such as one punctured information column, two punctured information columns, three punctured information columns, or more than three punctured information columns. The at least one punctured information column has the following two properties.

[0141] Property 1: Each punctured information column in the at least one punctured information column includes at least one non-zero element.

[0142] That is, the elements in each punctured information column in the at least one punctured information column cannot all be zero elements. If the elements in a certain punctured information column are all zero elements, that is, the variable node corresponding to the column has no connection with all the check nodes, the variable node cannot transmit information, and the information bit value corresponding to the column cannot be decoded, resulting in decoding error. Each punctured information column of the LDPC base graph in the embodiment of the present application includes at least one non-zero element, which can reduce the probability that the information bit value corresponding to the punctured information column cannot be decoded.

[0143] Property 2: In a matrix region constituted by at least one punctured information column in the first x rows of the LDPC base graph, the number of zero elements is distributed from more to less in the order of row numbers from small to large, x is an integer greater than 8.

[0144] That is, in the first x rows of the LDPC base graph, the number of zero elements of the at least one punctured information column is distributed from more to less from top to bottom. It should be noted that the number of zero elements distributed from more to less can refer to the trend of the number changing from more to less, and there can be the same number of zero elements in adjacent rows in the process of changing from more to less.

[0145] Suppose that in the first few layers of layered decoding, the elements in the punctured information column are mostly non-zero elements, and in the last few layers, the elements in the punctured information column are zero elements. At the beginning of the initial decoding iteration, since the elements in the punctured information column are mostly non-zero elements in the first few layers of layered decoding, the variable node corresponding to the punctured information column will participate in information transmission. However, the channel LLR of the punctured information column is initialized to 0, and if there are two or more variable nodes corresponding to the punctured information column participating in information transmission, it can be known from formula 1 that the minimum value of the amplitude calculated at this time is 0, that is, all the updated R ijAll are 0, and the information transmission of the layer is invalid transmission, which wastes the number of decoding iterations. Moreover, if the elements in the punctured information column are zero elements in the later layers of hierarchical decoding, the variable nodes corresponding to the punctured information column do not participate in the message transmission, and the information thereof is not updated. Such a structure will lead to a large number of invalid iterations and greatly reduce the convergence speed. Embodiments of the present application design the number and position of zero elements in the punctured information column of the LDPC base graph, so that the number of zero elements in the first x rows of at least one punctured information column satisfies a distribution from more to less from top to bottom, which can reduce the probability of invalid update in decoding iteration.

[0146] In some implementations, the above matrix region includes at least one first row, wherein the first row has one non-zero element. When the row of the above matrix region has one non-zero element, the layer has a variable node corresponding to a punctured information column participating in the transmission of information, that is, even if the channel LLR of the punctured information column is initialized as 0, it can be known from formula 1 that the minimum value of the amplitude calculated for the variable node corresponding to the punctured information column where the non-zero element is located is not necessarily 0, that is, the variable node corresponding to the punctured information column where the non-zero element is located can be normally updated. Therefore, based on this implementation, the probability of invalid update in decoding iteration can be further reduced. ij

[0147] In some implementations, the column where the non-zero element of the first y rows of the above matrix region is located is the same as the column where the non-zero element of the first y-1 rows of the above matrix region is located, and / or the column where the non-zero element of the first r rows of the above matrix region is located is one more than the column where the non-zero element of the first r-1 rows of the above matrix region is located, y and r are integers greater than 1. That is, the above matrix region further satisfies that each row does not have a non-zero element corresponding to a variable node that does not normally update information or each row has one non-zero element corresponding to a variable node that does not normally update information, under the premise that the number of zero elements is distributed from more to less. This implementation can avoid having two or more variable nodes corresponding to punctured information columns participating in the transmission of information, thereby avoiding invalid updates in decoding iteration.

[0148] For example, the LDPC base graph includes 4 punctured information columns, the above matrix region is a region composed of the first 9 rows of the 4 punctured information columns, and the element distribution of the matrix region is shown in Table 1, wherein "0" represents a zero element and "1" represents a non-zero element. When y=3, the column where the non-zero element of the first 3 rows is located is column 2, and the column where the non-zero element of the first y-1=2 rows is also located is column 2. When r=4, the column where the non-zero element of the first r-1=3 rows is located is column 2, and the column where the non-zero element of the first 4 rows is located is column 1 and column 2, which is one more than column 1 compared with the column where the non-zero element of the first r-1=3 rows is located.

[0149] Table 1 ​

[0150] In some implementations, the LDPC base graph of the embodiments of the present application further includes at least one punctured check column, and in the part composed of the above matrix area and at least one punctured check column of the first x rows of the LDPC base graph, the number of zero elements is distributed from more to less in the order of row numbers from small to large. In some scenarios, puncturing of check bits may occur. For example, in the scenario of very high code rate, encoding or decoding is performed using the core matrix of the LDPC base graph, and puncturing of check bits may occur during rate matching. For these scenarios, the embodiments of the present application design the punctured information column and the punctured check column of the LDPC base graph to satisfy that the number of zero elements is distributed from more to less in the order of row numbers from small to large as a whole, so as to reduce the probability of invalid update caused by the punctured check column.

[0151] Further, the punctured information column and the punctured check column of the LDPC base graph can further satisfy that the at least one row has one non-zero element.

[0152] Further, the punctured information column and the punctured check column of the LDPC base graph can further satisfy that the non-zero elements of the first y rows are located in the same column as the non-zero elements of the first y-1 rows, and / or the non-zero elements of the first r rows are located in one more column than the non-zero elements of the first r-1 rows, y and r being integers greater than 1.

[0153] The technical solutions of the embodiments of the present application will be described below in conjunction with specific examples.

[0154] Example 1

[0155] Taking the core matrix of the LDPC base graph as 5 rows, the punctured information column as the first 3 columns, and x = 9 as an example, the first 9 rows of the LDPC base graph can be as shown in Table 2, where "-1" represents a zero element and a non-negative value represents a non-zero element.

[0156] Table 2

[0157] As can be seen from Table 2, in the matrix area composed of the first 9 rows and the first 3 columns of the LDPC base graph, the number of zero elements (i.e. -1) gradually decreases from 3 to 0. At the beginning of the initial iteration:

[0158] 1) The first layer (i.e. row 0) has no punctured information column participating in message passing, so there is no LLR with a value of 0, and the variable nodes corresponding to other non-punctured columns can successfully perform message passing.

[0159] 2) The second layer (i.e. row 1) has column 2 participating in message passing, at this time the LLR of the variable node corresponding to column 2 is 0, which will cause the LLR of the variable node corresponding to other non-punctured columns R ijis 0, but for the variable node corresponding to column 2, since the LLRs of the variable nodes corresponding to other non-punctured columns are not 0, the minimum value obtained is also not 0, thus the R ij is not 0, the variable node corresponding to column 2 can be successfully updated, and after the update, the Q ij of the variable node corresponding to column 2 is updated from 0 to another value. ji For the update of the subsequent layer, such as the fourth layer, the Q ji of the variable node corresponding to column 2 can be normally updated with the variable nodes corresponding to other non-punctured columns.

[0160] 3) Similarly, the third layer (i.e., row 2) can successfully update the variable node corresponding to column 1.

[0161] 4) When message passing of the fourth layer (i.e., row 3) is performed, since the variable node corresponding to column 2 has been normally updated, the Q ji of the current row is 0, the variable node corresponding to column 0 can be successfully updated.

[0162] 5) When message passing of the fifth layer to the ninth layer (i.e., row 4 to row 8) is performed, the Q ji of the first three columns of punctured information columns have been updated to non-0 values, at this time, row and column update can be normally performed.

[0163] As can be seen from the example, by constraining the number of non-zero elements of the punctured information column of the LDPC base graph, invalid update in initial decoding iteration can be avoided, thereby accelerating decoding convergence.

[0164] Example 2

[0165] Taking the core matrix of the LDPC base graph as 4 rows, the punctured information column as the first column, and x = 9 as an example, the first 9 rows of the LDPC base graph can be as shown in Table 3, wherein "-1" represents a zero element, and a non-negative value represents a non-zero element.

[0166] Table 3

[0167] As can be seen from Table 3, in the matrix region composed of the first 9 rows and the first column of the LDPC base graph, the number of zero elements (i.e., -1) is reduced from 1 to 0. At the beginning of the initial iteration:

[0168] 1) The first layer (i.e., row 0) has no punctured information column participating in message passing, thus no LLR with a value of 0 appears, and the variable nodes corresponding to other non-punctured columns of the current layer can successfully perform message passing.

[0169] 2) The second layer (i.e., row 1) has the variable node corresponding to column 0 participating in message passing, at this time, the LLR of the variable node corresponding to column 0 is 0, which will cause the R ijis 0, but for the variable node corresponding to column 0, since the LLRs of the variable nodes corresponding to other non-punctured columns are not 0, the minimum value obtained is also not 0, thus the R ij is not 0, the variable node corresponding to column 0 can be successfully updated, and after the update, the Q ij of the variable node corresponding to column 0 is also updated from 0 to other values. ji

[0170] 3) For the update of the subsequent layers, the Q ji of the variable node corresponding to column 0 can be normally updated with the variable nodes corresponding to other non-punctured columns.

[0171] Example 3

[0172] Taking the core matrix of the LDPC base graph as 4 rows, the punctured information column as the first column (i.e., column 0), the punctured check column as the 25th column (i.e., column 25), and x = 9 as an example, the first 9 rows of the LDPC base graph can be as shown in Table 4, where "-1" represents a zero element, and a non-negative value represents a non-zero element.

[0173] Table 4

[0174] As can be seen from Table 4, in the part composed of the first 9 rows, the first column and the 25th column of the LDPC base graph, the number of zero elements (i.e., -1) is reduced from 2 to 0. At the beginning of the initial iteration:

[0175] 1) The first layer (i.e., row 0) has no punctured information column participating in message passing, thus no LLR with a value of 0 appears, and the variable nodes corresponding to other non-punctured columns in this layer can successfully perform message passing.

[0176] 2) The second layer (i.e., row 1) has the variable node corresponding to column 25 participating in information passing, at this time, the LLR of the variable node corresponding to column 25 is 0, which will cause the R ij of the variable nodes corresponding to other non-punctured columns to be 0, but for the variable node corresponding to column 25, since the LLRs of the variable nodes corresponding to other non-punctured columns are not 0, the minimum value obtained is also not 0, thus the R ij of the variable node corresponding to column 25 is not 0, the variable node corresponding to column 25 can be successfully updated, and after the update, the Q ij of the variable node corresponding to column 25 is also updated from 0 to other values. ji

[0177] 3) The third layer (i.e., row 2) has the variable nodes corresponding to columns 0 and 25 participating in information passing, since the variable node corresponding to column 25 has been normally updated, the Q ji of this row is only 0, and the variable node corresponding to column 0 can be successfully updated.

[0178] ​​4) For the update of the subsequent layer, the Q of the variable node corresponding to column 0 and column 25 ji The variable nodes corresponding to other non-punctured columns can be normally updated.

[0179] Compared with the prior art, the number of zero elements of the punctured information column of the first x rows of the LDPC code is designed from top to bottom from more to less, which can avoid invalid update in the initial decoding iteration, thereby accelerating the decoding convergence. In the same number of iterations, the same or better decoding performance can be obtained than the prior art.

[0180] The performance of the LDPC code of the embodiment of the present application is described below in combination with simulation results.

[0181] FIG. 9 is a simulation result of the decoding performance of the LDPC code of the present application and the 5G LDPC code.

[0182] As can be seen from FIG. 9, the base graph of the present application can obtain a 0.2 dB gain compared with the BG1 of the 5G LDPC code in five decoding iterations. In this way, the base graph provided by the embodiment of the present application can achieve better decoding performance in the same number of iterations compared with the 5G LDPC code.

[0183] The method embodiments provided by the present application are described in detail above in combination with FIGS. 1 to 9, and the device embodiments of the present application will be described below in combination with FIGS. 10 and 11.

[0184] It can be understood that, in order to implement the functions in the above embodiments, the devices in FIGS. 10 and 11 include corresponding hardware structures and / or software modules for performing various functions. Those skilled in the art should easily realize that, in combination with the units and method steps of the examples described in the embodiments disclosed in the present application, the present application can be realized in the form of hardware or a combination of hardware and computer software.

[0185] FIG. 10 shows a possible exemplary block diagram of a communication device involved in the embodiments of the present application. As shown in FIG. 10, the communication device 1300 can include modules or units corresponding to the above-described method embodiments. In one possible design, the communication device 1300 includes a processing unit 1302 and a communication unit 1303. Optionally, the communication device 1300 can further include a storage unit 1301 for storing device program code and / or data.

[0186] The communication device 1300 can be an encoding side device in the above-described embodiments, for example, an encoding device, a module (such as a circuit, a chip or a chip system (such as a modem chip, or a SoC chip or a SIP chip containing a modem core), or a logic node, a logic module or software capable of implementing all or part of the decoding device. The encoding device can be a terminal or a network device.

[0187] For example, in an embodiment, the processing unit 1302 is configured to: obtain a first input bit sequence; encode the first input bit sequence according to an LDPC base graph to obtain an encoded bit sequence, wherein an element in the LDPC base graph is a zero element or a non-zero element, the LDPC base graph includes at least one puncturing information column, each of the at least one puncturing information column includes at least one non-zero element, and in a matrix region formed by the at least one puncturing information column of the first x rows of the LDPC base graph, the number of zero elements increases from small to large along the row number, and x is an integer greater than 8.

[0188] In a possible design of the present disclosure, the matrix region includes at least one first row, and the first row has one non-zero element.

[0189] In a possible design of the present disclosure, the column where the non-zero element of the y-th row of the matrix region is located is the same as the column where the non-zero element of the (y-1)-th row of the matrix region is located, and y is an integer greater than 1.

[0190] In a possible design of the present disclosure, the column where the non-zero element of the r-th row of the matrix region is located is one more than the column where the non-zero element of the (r-1)-th row of the matrix region is located, and r is an integer greater than 1.

[0191] In a possible design of the present disclosure, the LDPC base graph further includes at least one puncturing check column, and in a part formed by the matrix region and the at least one puncturing check column of the first x rows of the LDPC base graph, the number of zero elements increases from small to large along the row number.

[0192] In a possible design, when the communication apparatus 1300 is an encoding device or a module in an encoding device, the function of the processing unit 1302 can be implemented by one or more processors. Specifically, the processor can include a modem chip, or a SoC chip or a SIP chip including a modem core. The function of the communication unit 1303 can be implemented by a transceiver circuit.

[0193] In a possible design, when the communication apparatus 1300 is a circuit or chip responsible for communication functions in an encoding device, such as a modem chip or a SoC chip or a SIP chip including a modem core, the function of the processing unit 1302 can be implemented by a circuit system including one or more processors or processor cores in the above chip. The function of the communication unit 1303 can be implemented by an interface circuit or a data transceiver circuit on the above chip.

[0194] The communication apparatus 1300 can be a decoding-side apparatus in the above-described embodiments, for example, a decoding device, a module (e.g., a circuit, a chip or a chip system (such as a modem chip, also known as a baseband chip, or a SoC chip or a SIP chip containing a modem core) in the decoding device, or a logic node, a logic module or software capable of implementing all or part of the decoding device. The decoding device can be a terminal or a network device.

[0195] For example, in an embodiment, the processing unit 1302 is configured to: obtain a second input bit sequence; and decode the second input bit sequence according to an LDPC base graph to obtain a decoded bit sequence, wherein an element in the LDPC base graph is a zero element or a non-zero element, the LDPC base graph includes at least one punctured information column, each of the at least one punctured information column includes at least one non-zero element, and in a matrix region formed by the at least one punctured information column of the first x rows of the LDPC base graph, the number of zero elements increases from small to large along the row number, and x is an integer greater than 8.

[0196] In a possible design, the matrix region includes at least one first row, and the first row has one non-zero element.

[0197] In a possible design, the column where the non-zero element of the y-th row of the matrix region is located is the same as the column where the non-zero element of the (y-1)-th row of the matrix region is located, and y is an integer greater than 1.

[0198] In a possible design, the column where the non-zero element of the r-th row of the matrix region is located is one more than the column where the non-zero element of the (r-1)-th row of the matrix region is located, and r is an integer greater than 1.

[0199] In a possible design, the LDPC base graph further includes at least one punctured check column, and in a part formed by the matrix region and the at least one punctured check column of the first x rows of the LDPC base graph, the number of zero elements increases from small to large along the row number.

[0200] In a possible design, when the communication apparatus 1300 is a decoding device or a module in the decoding device, the function of the processing unit 1302 can be implemented by one or more processors. Specifically, the processor can include a modem chip, or a SoC chip or a SIP chip containing a modem core. The function of the communication unit 1303 can be implemented by a transceiver circuit.

[0201] In one possible design, when the communication device 1300 is a circuit or a chip responsible for communication functions in a decoding device, such as a modem chip or a SoC chip including a modem core or a SIP chip, the functions of the processing unit 1302 can be implemented by circuitry including one or more processors or processor cores in the chip. The functions of the communication unit 1303 can be implemented by interface circuitry or data transceiver circuitry on the chip.

[0202] It can be understood that the division of units in the above apparatus is only a logical division of functions, one function unit can correspond to one function, or two or more functions can be integrated into one function unit. In actual implementation, all or part of the units can be integrated into one physical entity, or distributed in different physical entities. In addition, the above function units can be implemented in the form of hardware, or in the form of software, or in the form of hardware combined with software. Whether a certain function is implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for specific applications, but such implementation should not be considered beyond the scope of the present application.

[0203] In one example, the functional units in any of the above apparatuses can be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASICs), or one or more central processing units (CPUs), one or more microcontroller units (MCUs), one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms.

[0204] In one example, the storage unit 1301 can include random access memory, flash memory, read only memory, programmable read only memory, electrically erasable programmable memory, and / or registers, etc.

[0205] FIG. 11 is a structural schematic diagram of a terminal 1000 provided by an embodiment of the present application, which can correspond to the terminal shown in FIG. 1, and is used to implement the operations of the terminal in the above embodiments. As shown in FIG. 11, the terminal includes one or more antennas 1010, a radio frequency processing system 1020, and a processor system 1030.

[0206] In the downlink or sidelink direction, the radio frequency processing system 1020 receives radio frequency signals through the antenna 1010 and sends the signals after radio frequency processing to the processor system 1030 for further processing. In the uplink or sidelink direction, the processor system 1030 sends the terminal side information after signal processing to the radio frequency processing system 1020, and the radio frequency processing system 1020 sends the signals after radio frequency processing through the antenna 1010.

[0207] In one example, the radio frequency processing system 1020, as a communication interface for the terminal to communicate with the outside, can include a radio frequency front end 1021 (RFFE) and a radio frequency transceiver 1022. The RFFE 1021 is mainly used for one or more of shaping, passband selection, or gain processing of RF signals received by the antenna or RF signals to be sent through the antenna, and can include one or more of radio frequency switches, duplexers, filters, power amplifiers, antenna tuning, and low-noise amplifiers. Components, etc. The RFFE 1021 can be a circuit system composed of a plurality of discrete devices, or can be integrated and packaged in one or more chips. The radio frequency transceiver 1022 is used to process the RF signals received by the RFFE into baseband / intermediate frequency signals for the processor system 1030 to process next, and to process the baseband / intermediate frequency signals provided by the processor system 1030 into RF signals to send to the RFFE 1021. The baseband / intermediate frequency signals transmitted between the radio frequency transceiver 1022 and the processor system 1030 can be digital signals or analog signals. The radio frequency transceiver 1022 can be implemented by one or more chips, which are usually referred to as radio frequency chips (RFIC).

[0208] In one example, the processor system 1030 can include one or more processors for processing signals and for executing appropriate instructions to carry out one or more communication protocols. Optionally, the processor system 1030 can further include a memory 1036. In one example, the one or more processors include at least one baseband processor 1031 (also referred to as a modem processor). The memory 1036 is used for storing data and / or computer program instructions. Optionally, the processor system 1030 can further include one or more application processors 1032 for implementing processing for an operating system of the terminal and for application layers. Optionally, the processor system 1030 can further include one or more of a voice subsystem 1033, a multimedia subsystem 1034, or an interface circuit 1035. The voice subsystem 1033 is used for processing voice signals, the multimedia subsystem 1034 is used for processing multimedia related operations, such as video codec, image processing, etc., and the interface circuit 1035 is used for communicating with other terminal components, such as a display 1040, input devices 1050, a memory 1060, etc. The above components in the processor system 1030 can communicate with each other through a bus or a communication interface circuit.

[0209] In one example, the processor system 1030 can be packaged as a processor chip, such as a SoC chip or a SIP chip. In one example, the processor system 1030 can be a system of multiple chips, for example, the baseband processor 1031 can be packaged separately as a chip, or packaged with part or all of the circuitry of the radio frequency processing system as a chip.

[0210] In one example, the memory 1036 can be an on-chip memory, i.e., located on the chip of the processor system 1030. In one example, the memory 1060 can be an off-chip memory, i.e., located off the chip of the processor system 1030.

[0211] In one example, the baseband processor 1031 can include one or more processor cores 10311 and interface circuit 10314. The one or more processor cores 10311 are configured to process signals and perform one or more communication protocols. Optionally, the baseband processor 1031 can also include a memory 10312 configured to store at least part of corresponding computer program instructions and / or data. In one example, the one or more processor cores 10311 implement the above-mentioned operations (e.g., steps 801-803 or steps 803-805 in FIG. 8) in the method embodiments by executing the computer program instructions stored in the memory 10312. In the present disclosure, the memory 10312 configured to store corresponding computer program instructions and / or data can mean that the memory 10312 is configured to store all corresponding computer program instructions and / or data for execution by the processor core 10311; or can mean that the memory 10312 is configured to store part of corresponding computer program instructions and / or data, which includes computer program instructions and / or data currently required for execution by the processor core 10311, and the memory 10312 can store different parts of computer program instructions and / or data for execution by the processor core 10311 multiple times to implement the above-mentioned operations in the method embodiments. The interface circuit 10314 is configured as a communication interface to communicate with other components, such as transmitting signals with the radio frequency processing system 1020, communicating with other subsystems and related components of the processor system 1030 through a bus, such as transmitting data control signals with the application processor 1032, and transmitting data or computer program instructions with the memory 1036 or the memory 1060. Optionally, in order to reduce the load of the processor core, the baseband signal processing circuit 10313 can also be configured to perform at least part of the processing of the baseband signal, including one or more of demodulation, modulation, encoding or decoding of the signal.

[0212] In one example, the communication apparatus provided in the present application can be the terminal 1000, the communication module including the processor system 1030 and the radio frequency system 1020, the processor system 1030, or the baseband processor 1031.

[0213] The processor, processor system, application processor, baseband processor, processor circuit, or processor core can be collectively referred to as a processor, which can include one or a combination of a central processing unit (CPU), a digital signal processor (DSP), a microprocessor unit (MPU), a microcontroller unit (MCU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an artificial intelligence processor (AI processor), or a neural processing unit (NPU).

[0214] The above memory can include one or more of the following storage media: random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), phase-change memory (PCM), resistive RAM (ReRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FRAM), cache, register, read-only memory (ROM), flash memory, erasable programmable ROM (EPROM), hard disk, etc. In an example, computer program instructions for implementing the above embodiments can be stored on a non-volatile memory, such as at least part of the above memory 1060 (e.g., one or more of ROM, flash memory, EPROM, or hard disk). During terminal operation, the corresponding computer program instructions can be loaded in whole or in part into a memory with faster transmission speed to the processor, such as at least part of the above memory 1036 and / or memory 10312 (e.g., one or more of RAM, SRAM, DRAM, PCM, RERAM, MRAM, FRAM, cache, or register), for execution by the processor to implement the steps in the above method embodiments.

[0215] In an example, the radio frequency transceiver 1022 and the radio frequency front end 1021 can also be packaged in one chip. In an example, the radio frequency transceiver 1022, the radio frequency front end 1021, and the baseband processor 1031 can also be packaged in one chip.

[0216] The present application also provides a computer readable storage medium having stored thereon computer instructions for implementing the method performed by the encoding device or the decoding device in the above method embodiments.

[0217] The present application also provides a computer program product containing instructions that, when executed by a computer, implement the method performed by the encoding device or the decoding device in the above method embodiments.

[0218] The present application also provides a computer program that, when executed by a computer, implements the method performed by the encoding device or the decoding device in the above method embodiments.

[0219] The application also provides a communication system comprising at least one of the encoding device or the decoding device in the embodiments above.

[0220] The explanations and beneficial effects of the related content in any of the above provided devices can refer to the corresponding method embodiments provided above, which will not be repeated here.

[0221] Those skilled in the art will understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, etc.) containing computer-usable program code.

[0222] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus produce the functions specified in the flowchart one or more flows and / or block diagram one or more blocks.

[0223] These computer program instructions can also be stored in a computer-readable memory that can direct the computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including instruction means, which implements the functions specified in the flowchart one or more flows and / or block diagram one or more blocks.

[0224] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable data processing apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable data processing apparatus provide steps for implementing the functions specified in the flowchart one or more flows and / or block diagram one or more blocks.

[0225] In various embodiments of the present application, the terms and / or descriptions among different embodiments are consistent and can be referred to each other if there is no special description and logical conflict. The technical features among different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0226] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. It is to be understood that the foregoing description is exemplary of the application only and is intended to provide an overview for understanding the nature and character of the application as it is claimed. It is to be understood that the foregoing description is exemplary of the application only and is intended to provide an overview for understanding the nature and character of the application as it is claimed. It is to be understood that the foregoing description is exemplary of the application only and is intended to provide an overview for understanding the nature and character of the application as it is claimed. It is to be understood that the foregoing description is exemplary of the application only and is intended to provide an overview for understanding the nature and character of the application as it is claimed. It is to be understood that the foregoing description is exemplary of the application only and is intended to provide an overview for understanding the nature and character of the application as it is claimed. It is to be understood that the foregoing description is exemplary of the application only and is intended to provide an overview for understanding the nature and character of the application as it is claimed.

Claims

1. An information processing method characterized by comprising: The method comprises: obtaining a first input bit sequence; encoding the first input bit sequence according to a low-density parity-check (LDPC) base graph to obtain an encoded bit sequence, wherein elements in the LDPC base graph are zero elements or non-zero elements, the LDPC base graph comprises at least one punctured information column, each of the at least one punctured information column comprises at least one non-zero element, and in a matrix region constituted by the at least one punctured information column of the first x rows of the LDPC base graph, the number of zero elements is distributed from more to less in ascending order of row number, and x is an integer greater than 8.

2. The method of claim 1, wherein the matrix region comprises at least one first row, and the first row has one non-zero element.

3. The method of claim 1 or 2, wherein the column where the non-zero element of the first y rows of the matrix region is located is the same as the column where the non-zero element of the first y-1 rows of the matrix region is located, and y is an integer greater than 1.

4. The method of any one of claims 1 to 3, wherein the column where the non-zero element of the first r rows of the matrix region is located is one more than the column where the non-zero element of the first r-1 rows of the matrix region is located, and r is an integer greater than 1.

5. The method of any one of claims 1 to 4, wherein the LDPC base graph further comprises at least one punctured check column; and in a part constituted by the matrix region and the at least one punctured check column of the first x rows of the LDPC base graph, the number of zero elements is distributed from more to less in ascending order of row number.

6. The method of any one of claims 1 to 5, wherein the number of the at least one punctured information column is 1 or 2, or the number of the at least one punctured information column is greater than or equal to 3.

7. An information processing method characterized by comprising: The method comprises: obtaining a second input bit sequence; decoding the second input bit sequence according to a low-density parity-check (LDPC) base graph to obtain a decoded bit sequence, wherein elements in the LDPC base graph are zero elements or non-zero elements, the LDPC base graph comprises at least one punctured information column, each of the at least one punctured information column comprises at least one non-zero element, and in a matrix region constituted by the at least one punctured information column of the first x rows of the LDPC base graph, the number of zero elements is distributed from more to less in ascending order of row number, and x is an integer greater than 8.

8. The method of claim 7, wherein the matrix region comprises at least one first row, and the first row has one non-zero element.

9. The method of claim 7 or 8, wherein the column where the non-zero element of the first y rows of the matrix region is located is the same as the column where the non-zero element of the first y-1 rows of the matrix region is located, and y is an integer greater than 1.

10. The method of any one of claims 7 to 9, wherein the column where the non-zero element of the first r rows of the matrix region is located is one more than the column where the non-zero element of the first r-1 rows of the matrix region is located, and r is an integer greater than 1.

11. The method of any one of claims 7-10, wherein the LDPC base graph further comprises at least one punctured check column; the at least one punctured check column of the LDPC base graph has a number of zero elements that is greater than or equal to 3.

12. The method of any one of claims 7-11, wherein the number of the at least one punctured information column is 1 or 2, or the number of the at least one punctured information column is greater than or equal to 3. a module or unit for performing the method of any one of claims 1-12. a computer program or instructions stored in the storage medium, which when executed, implement the method of any one of claims 1-12.

13. A communications device, characterized by a computer program, which when executed, implement the method of any one of claims 1-12.

14. A computer-readable storage medium, characterized in that, comprising:

15. A computer program product, characterised in that, an encoding device for performing the method of any one of claims 1-6; and 16. A communication system, characterized by a decoding device for performing the method of any one of claims 7-12. a communication interface circuit for enabling communication within the communication apparatus and / or between the communication apparatus and other apparatuses or components, and one or more processors for executing computer programs or instructions to implement the method of any one of claims 1-12. ​ ​ 17. A communications device, characterized by ​

Images