Circuitry implementing an artificial neuron of a spiking neural network and a method of operation of an artificial neuron

Abstract

A circuit for implementing artificial neurons of a spiking neural network able to resolve both excitatory and inhibitory synaptic signals. The circuit has multiple synaptic inputs each for receiving input spike signals of a single bit value. A pair of train generators is associated with each synaptic input, each train generator of the pair having a separate weighting associated with it where one of the weighting is of a zero value. Each train generator of the pair is configured to generate a spike train of a length dependent on its associated weighting in response to a synaptic input signal received at the pair's associated synaptic input. The circuit also includes a counter configured to count each spike received from each of the first spike train generators towards a potential threshold value, and to count away from the potential threshold value with each spike received from each of the second spike train generators.

Description

[0001] Circuitry Implementing an Artificial Neuron of a Spiking Neural Network and a Method of Operation of an Artificial Neuron

[0002] There is interest in developing Spiking Neural Networks (SNNs), a type of artificial neural network, for various applications due in part to their potentially lower power consumption compared to conventional artificial neural networks, and ability to perform continuous learning (Hebbian based learning) during operation.

[0003] The following describe known implementations of SNNs on a Field Programmable Gate Array (FPGA):

[0004] Spiker: an FPGA-optimized Hardware accelerator for Spiking Neural Networks, 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Nicosia, Cyprus, 2022, pp. 14-19, doi: 10.1109 / ISVLSI54635.2022.00016; A. Carpegna, A. Savino and S. Di Carlo.

[0005] Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator; Daniel Neil et al; IEEE Transactions On Very Large Scale Integration (Vlsi) Systems, page 2621; Vol. 22, No. 12, December 2014.

[0006] Energy Efficient Parallel Neuromorphic Architectures with Approximate

[0007] Arithmetic on FPGA; Wang, Qian et al; Neurocomputing 221 (2017) 146-158. A Fast and Energy-Efficient SNN Processor With Adaptive Clock / Event-Driven Computation Scheme and Online Learning; Sixu Li et al IEEE Transactions On Circuits And Systems — I: Regular Papers, Vol. 68, No. 4, April 2021.

[0008] The characteristics of a biological neuron are mimicked through use of CORDIC algorithms and arithmetic operations including: adding, subtracting, and multiplication. These processes are implemented using digital signal processing logic elements (DSP slices). However, a typical FPGA comprises relatively few DSP slices; consequently, implementing a SNN with a useful number of neurons requires multiple FPGAs to provide the necessary number of DSP slices.

[0009] Other efforts to implement SNNs have looked at novel application-specific integrated circuits (ASIC); however these require increasing amounts of expensive rare earth elements and complex processing to produce; moreover, this approach leads to a dedicated device function, limiting flexibility.

[0010] This invention was conceived as a result of endeavour to improve upon circuits for implementing artificial neurons of a spiking neural network, particularly, but not exclusively, that operating according to a Leaky Integrate and Fire (LIF) model; and for the purpose of more effective implementation of SNNs on embedded electronic hardware devices, such as, but not limited to, a silicon CMOS (Complementary Metal

[0011] Oxide Semiconductor) FPGA. According to an aspect of the invention there is provided a circuit for implementing an artificial neuron of a spiking neural network, the circuit comprising: a first synaptic input for receiving input spike signals of a single bit value; a first spike train generator means configured to generate, in response to each input spike signal received at the first synaptic input, a spike train comprising n weighting spikes, where n is an integer indicative of a synaptic weight value associated with the first synaptic input; a membrane potential counter configured to count each weighting spike received from the first spike train generator towards a potential threshold value; and an output spike generator configured to generate an output spike signal of a single bit value in response to the membrane potential counter reaching the potential threshold value.

[0012] Through applying a weight using a spike train, the circuit can resolve weighting values to large bit vectors needed to enable a high degree of network decision making accuracy, whilst obviating the need to implement CORDIC algorithms or carry out arithmetic functions, e.g. multiplication and addition, on multiple-bit numbers. The reduced complexity of the computation enables a simpler circuit design with reduced power consumption and requirement for DSP slices.

[0013] In contrast to the prior art, the invention enables implementation of a neuron circuit for a SNN with a relatively small number of flip-flops and look-up tables, for example, in the region of fifty each. As FPGAs typically comprise many more flip-flops and lookup tables compared with DSP slices, the resources of a FPGA can be used more efficiently so allowing implementation of a SNN comprising many, e.g. >l*105, neuron circuits on a single FPGA. The circuit may comprise a second spike train generator means configured to generate, in response to each input spike signal received at the first synaptic input, a spike train comprising k weighting spikes, and where n is an integer indicative of an excitatory synaptic weight value associated with the first synaptic input; k is an integer indicative of an inhibitory synaptic weight value associated with the first synaptic input; and in which the membrane potential counter is configured to count away from the potential threshold value with each weighting spike received from the second spike generator means.

[0014] This arrangement allows implementation of an artificial neuron able to resolve both excitatory and inhibitory synaptic signals.

[0015] The circuit may comprise a second synaptic input for receiving input spike signals of a single bit value; a third spike train generator means configured to generate, in response to each input spike signal received at the second synaptic input, a spike train comprising 1 weighting spikes, where 1 is an integer indicative of a synaptic weight value associated with the second synaptic input.

[0016] This is arrangement allows for multiple input synapses per neuron, each having a weighting value that is independent from the others. The circuit may comprise a fourth spike train generator means configured to generate, in response to each input spike signal received at the second synaptic input, a spike train comprising p weighting spikes, and where:

[0017] 1 is an integer indicative of an excitatory synaptic weight value associated with the second synaptic input; and p is an integer indicative of an inhibitory synaptic weight value associated with the second synaptic input; and in which the membrane potential counter is configured to count away from the potential threshold value with each weighting spike received from either the second spike generator means and fourth spike generator means. This arrangement allows each synapse to provide either an inhibitory or excitatory input.

[0018] Each spike train generator means may comprise a spike generator configured to generate spikes, and a synaptic counter configured to count, in response to a received input synaptic signal, to the synaptic weight value associated with its associated synaptic input; and in which the spike train generator means is configured to output spikes from the spike generator whilst the synaptic counter is counting to the synaptic weight value. This provides a simple method of implementing the spike generator means.

[0019] Each of the first, second, third of fourth spike train generator means (e.g. spike train generator sub-circuit) may comprise: a synaptic counter, and a spike generator configured to generate spikes; the synaptic counter configured to count, in response to a (or each) received spike signal of a single bit value, towards the synaptic weight value of the received synaptic input signal; and the spike train generator means configured to output spikes from the spike generator whilst the synaptic counter is counting to the synaptic weight value.

[0020] In one implementation an output of the synaptic counter is used to turn the spike generator on only whilst it is counting to the synaptic weight. In another implementation, the output of the synaptic counter is used to control a switch at the output of the spike generator to control whether spikes from the spike generator reach the counter.

[0021] The circuit may further include a refractory timer that comprises a Linear Feedback Shift Register (LFSR), configured to limit a frequency that synaptic output spike signals are outputted from a synaptic output of the circuit. The refractory time may be configured to prevent the output of an output spike signal for a period of time immediately following the output of an earlier output spike signal through the synaptic output. This implements a refectory period, making the functioning of the neuron more aligned with that of biological neurons.

[0022] The use of a LFSR avoids the need for cascaded logic found in a binary counter, reducing the critical timing path and so speeding up the circuit as well as requiring less logic.

[0023] The circuit may comprise a leakage timer having an output configured to periodically move a count value of the membrane potential counter away from the potential threshold value. This provides a more biologically plausible design in the sense of being aligned with the behaviour of biological neurons. This could be implemented using a shift register, a counter or LFSR depending on the leakage period length required.

[0024] Each weighting spike is favourably a single bit integer value.

[0025] The circuit may be an integrated circuit. The circuit may be fabricated using a CMOS process. The circuit may be carried on an integrated circuit chip. There may be provided an FPGA integrated circuit chip configured to implement a SNN including one or more of the circuits described herein.

[0026] The invention may also be expressed in terms of a method and thus according to a second aspect of the invention, there is provided a method of operation of an artificial neuron of a spiking neural network; the method comprising: generating a train of weighting spike signals in response to each synaptic input signal received at a first synaptic input of the artificial neuron, wherein the number of weighting spikes in each train is indicative of a first weight value associated with the first synaptic input; using a counter means to count the total number of weighting spike signals generated; and in response to the counter means reaching a threshold value, generating an output synaptic signal at a synaptic output of the artificial neuron.

[0027] The function of counting with respect to a threshold value may include refractory behaviour to impose a configurable limit on the frequency of output spikes within a time period in response to saturation of weighting spikes. The function of counting with respect to a threshold value may include leakage behaviour to require a configurable volume of weighting spikes within a time period to trigger an output synaptic signal.

[0028] The invention will now be described by way of example with reference to the following Figures in which:

[0029] Figure 1 is a representation of a simple artificial spiking neural network (SNN);

[0030] Figure 2 is a diagram illustrating functional features of a circuit implementing an artificial neuron of a SNN, having a single synaptic input; and

[0031] Figure 3 illustrates functional features of a variant circuit implementing an artificial neuron of a SNN having multiple synaptic inputs and configurable to apply either excitatory and or inhibitory synaptic weightings; and

[0032] Figure 4 illustrates a fragment of the circuit of Fig 3 associated with one of the synaptic inputs to illustrate the features of the first and second spike train generator sub-circuits in greater detail.

[0033] Figure 1 is a schematic of an artificial spiking neural network comprising artificial neurons N arranged in layers comprising: an input layer, at least one hidden layer and an output layer. As is conventional, information is passed between the neurons in the network in the form of binary spikes or pulses.

[0034] The following describe circuit configurations suitable to implement an artificial neuron of a SNN in hardware. Figure 2 illustrates functional features of a circuit 1 implementing an artificial neuron configured to function as a spiking neuron operating according to a leaky integrate and fire model (LIF).

[0035] Multiples of the circuit 1 can be interconnected to provide a SNN. Such a network can be physically manifested through suitable configuration of a FPGA.

[0036] A primary advantage of the circuit 1 is that it can be implemented in hardware using only flip-flops and look up tables; this allows for efficient use of the available resources of a typical FPGA.

[0037] The circuitry 1 comprises a synaptic input 2, a spike train generator sub-circuit 3, a counter 4, leakage timer 5, refractory timer 6, and an output spike generator 7, one or more synaptic outputs 9, and an edge detector 10.

[0038] The circuit 1 is configured to receive synaptic input spikes, each of a single bit value (e.g. STD logic in VHDL IEEE library) through synaptic input 2, e.g. from an input to the SNN or from a synaptic output of another artificial neuron in the SNN. In response to each synaptic input spike received through the input 2 the spike train generator 3 generates a spike train 8 of weighting spikes 8A. The number of weighting spikes 8A of the spike train 8 equates to the value of a synaptic weight w associated with the synaptic input, w is a multi-bit binary value. For example, if w=4, each spike train generated consists of four weighting spikes; if w’=93. each spike train consists of ninety three weighting spikes; Fig 2 illustrates an example where w=5. Note that, although preferred, it is not necessary that the number of weighting spikes equals the weight value so long as it is indicative.

[0039] It should be noted that the indicative behaviour described above encompasses proportionality, but with no mandate for linearly proportional or any other mathematical form of proportionality.

[0040] The synaptic weight value w is a pre-configured value that may be determined through training of the network. Depending on the design of the SNN, it may be up-dated from time-to-time whilst the model is running, using principles of continuous learning, for example, Spike Time Dependent Plasticity (STDP) or it may remain constant for the duration of running.

[0041] For the duration that the weighting value remains unchanged, the spike train generator 3 generates a separate spike train 8 comprising the same number of spikes 8A each time a synaptic input spike is received at the input 2.

[0042] Each weighting spike 8A of the spike train 8 is a single bit value. The temporal spacing between weighting spikes 8A within a train 8 may correspond with the clock rate of the processing system.

[0043] Each spike 8A of each spike train 8 outputted by the spike train generator 3 is received at an input 4A of the counter 4. The counter 4 counts each spike 8A received at its input from an initial value Vinitiai (typically zero) towards a threshold value Vth, corresponding to a potential threshold value of the artificial neuron. Vth is a multi -bit binary value; a bit width of between 4 and 32 bits for Vth is likely to allow for sufficient differentiation between the strength of connections between neuron circuits of the SNN to enable good prediction accuracy for many applications.

[0044] In response to the counter 4 reaching Vth, the output spike generator 7 produces an output synaptic spike signal at the circuit’s 1 one or more synaptic outputs 9i-9n, and the counter is reset to Vinitiai . Each output synaptic spike signal is typically a single bit value (e.g. STD logic in VHDL IEEE library).

[0045] The spike train generator sub-circuit 3 comprises a synaptic counter 3A, a weighting spike generator 3B and a store 3C holding the value of the synaptic weight, w.

[0046] Each input synaptic spike received at synaptic input 2 is detected by the edge detector 10 which, in response, initiates the synaptic counter 3 A to start counting from a set initial value, e.g. zero, towards the synaptic weight value w. Whilst counting, the synaptic counter 3A provides an engage signal to the spike generator 3B causing it to generate a weighting spike for each count of the synaptic counter 3A. In this way a train 8 of weighting spikes 8A is generated. It will be appreciated by to those skilled in the art that there are various other ways the synaptic counter 3A and spike generator 3B could be configured to perform the task. For example, assuming the counter 3 A and spike generator 3B operate to count and generate spikes simultaneously on the same clock signal, the spike generator 3B could continuously generate spikes, and the counter 3A function to control a switch at the output of the generator 3B whilst it is counting; alternatively the counter 3B could be configured to send an activation pulse to the spike generator 3B on each count to w, which the spike generator 3B responds to by generating a weighting spike.

[0047] Note that total time required to generate a train 8 of weighting spikes in response to receiving a synaptic input spike at input 2 will typically be at least an order of magnitude shorter than the expected time interval between synaptic spikes received at the synaptic input 2. As such it is not expected that a second synaptic input spike will ever be received at input 2 before the synaptic counter has counted to w.

[0048] The leakage timer 5 and refractory timer 6 enable the circuit 1 to function in a manner aligned to a LIF model to more closely resemble a biological neuron.

[0049] The leakage timer 5, which may, for example, be implemented by a shift register, a counter or LFSR depending of the period length desired, is configured to periodically move the count value of the counter 4 away from the threshold value Vth back towards the initial value Vinitiai . Thus in absence of trains 8 of spikes received at the counter 4, the count value will move towards Vinitiai over time. For example, the leakage timer 5 may be configured to periodically decrement the counter value by one. More complicated instances of leakage timer 5 are envisageable that decrement the counter value by differing amounts over time and / or operated non-periodically, although the additional complication required to enact is likely to make them less preferred. The refractory timer 6 is configured to implement a refractory period to limit the frequency that output synaptic spike signals are outputted from the circuit 1 at synaptic outputs 91-9n.

[0050] The refractory timer 6 is implemented by a Linear Feedback Shift Register (LFSR), favourably of Galois type. The LFSR has an input (tap) 6A configured to receive an output signal from the counter 4 produced in response to reaching Vth that enables the output spike generator 7. In response to said signal being received at 6A, the refractory timer 6 holds the counter value at Vinitiai for a pre-determined period.

[0051] Figures 3 and 4 illustrate a variant circuit 100 for implementing an artificial neuron of a SNN, having multiple synaptic inputs Sym - Synnand able to apply either excitatory and inhibitory weight values to synaptic signals received at any one of its synaptic inputs Sym - Synn.

[0052] Circuit 100 comprises: multiple edge detectors 110, one per synaptic input; multiple first spike train generator sub-circuits 30i-30n, one per synaptic input; multiple second spike train generator sub-circuits 1 li-l In, one per synaptic input; a combiner network 150, counter 40, leak timer 50, refractory timer 60, an output spike generator 70, and one or more synaptic outputs 90.

[0053] With reference to Fig 4, which shows a fragment 200 of circuit 100, each of the first spike train generator sub-circuits 30i-30n comprises a synaptic counter 30A, a spike generator 30B and a store 30C; and each second spike train generator sub-circuits 111-

[0054] 1 In comprises a synaptic counter 11 A, a spike generator 1 IB and a store 11C.

[0055] Each pair of first and second spike train generator sub-circuits, 30i: 11 i , 302: 112 to 30n: l ln are connected to their respective synaptic inputs Sym - Synnthrough an edge detector 110. Each first spike train generator sub-circuit 30i-30nand second spike train generator sub-circuit l l i-l In functions in the same manner as train generator subcircuit 3 of Fig 2 to generate a train 8, 12 of weighting spikes 8A, 12A corresponding to the synaptic weight value held in its respective store 30C 11C. The numeral 8 is assigned to spike trains from the first spike train generator sub-circuits 30 and numeral 12 to spike trains from the second spike train generator sub-circuits 11.

[0056] The store 30C of each first spike train generator sub-circuit 3 holds an excitatory synaptic weight value, weXcit, associated with it respective synaptic input 2. The store 30C of each second spike train generator sub-circuit 11 holds an inhibitory synaptic weight value winhib associated with its respective synaptic input. For each pair of weXcit and w’inhib weights associated with an individual synaptic input of the multiple synaptic inputs Sym - Synn, one is assigned a value zero, and the other a non-zero integer value depending on whether the synaptic input is to have an excitatory or inhibitory affect. This determination will typically be made during a training phase of the SNN.

[0057] In the non-limiting example illustrated in Fig 3, weights w7exand v>nsare non-zero values whereas u7inb and w’ / iinb are assigned a value of zero. Consequently each signal received at either Sym and Synnwill cause their respective first spike train generator sub-circuits 30i, 30nto generate spike trains 8 with one or more spikes, whereas the second spike train generator sub-circuits 111 , 1 In associated with Sym and Synnwill not generate a spike train in response to a synaptic input signal received at their respective inputs. In contrast, w2nm\, has a non-zero integer value and w2eXcit a zero value meaning the first spike train generator sub-circuit 302 associated with second input Sy does not generate spike trains whereas the second spike train generator subcircuit I I2 generates a spike train 12 in response to each synaptic input signal received at the second synaptic input Sym.

[0058] The counter 40 has two inputs 40A 40B. A first of the inputs 40 A is connected, through a combining network 150, to the output of each of the first the spike train generators 30i 30nto receive all spikes 8A outputted from all of first spike train generators 30i 30nassociated with all synaptic inputs Sym and Synn. A second input 40B of the counter 40 is connected, through the combining network 150, to the output of each of the second spike train generators 111 - 1 In to receive all spikes 12A of spike trains 12 outputted from all of the second spike train generators H i - l ln associated with all synaptic inputs Sym and Synn.

[0059] The counter 40 is configured to incrementally move a counter value from the reset value, V initial , towards the threshold value, Vth, in response to each spike 8A received through input 40A, and to incrementally move the counter value away from Vth in response to each spike 12A received through second input 40B. As such, each synaptic input signal received by the circuit 100 will either move the counter towards the threshold Vth or away from the threshold by an amount dependent upon the weighting value, w, associated with synaptic input Sym and Synnand whether the signal was received at a synaptic input designated as having a excitatory or inhibitory effect. .

[0060] In this example, the counter 40 moves the count away from Vth in response to each synaptic input signal received at Sym and Synn, and towards Vth in response to each synaptic input signal received at Sy .

[0061] For simplicity, in this example, the combining network 150 is implemented by a set of OR gates though any other suitable arrangement of logic circuitry could be used instead.

[0062] Note that in practice the likelihood of synaptic input spike signals being received at multiple synaptic inputs simultaneously is very low and thus it is highly unlikely that weighting spikes derived from multiple synaptic inputs would be received at either an OR gate of the combiner 150 or an input 40 A 40B of the counter 40 simultaneously.

[0063] In response to the counter 40 reaching Vth, the output spike generator 70 produces an synaptic output spike signal at the circuit’s 100 one or more synaptic outputs 90i-90n, and the counter is reset to Vinitiai . Each output synaptic spike signal is of a single bit value .

[0064] The leakage timer 50 and refractory timer 60 function in the same manner of their corresponding counterparts 5, 6 of circuit 1. Although described in relation to a circuit implementing an artificial neuron operating according to a LIF model, it will be appreciated that the invention may be applicable to implementing artificial neurons working according to other spiking neuron models, including but not limited to perfect integrate and fire, adaptive integrate and fire, the adaptive threshold neuron model, and the fractional order leaky integrate and fire.

[0065] The number of synaptic inputs and outputs of each artificial neuron will depend on the architecture of the neural network and the neuron’s position within the network. It will be appreciated that neurons within the network may have different numbers of synaptic inputs and different numbers of synaptic outputs.

[0066] Although likely to be less preferred in most applications due to its more limited functionality, a possible variant to the circuit 100 may comprise only a single spike train generator sub-circuit per synaptic input. This arrangement may be of use where the neuron is only required to process excitatory inputs.

[0067] The store(s) that hold the weights may be physically located separately from the remainder of the circuit, and for neural networks comprising many neuron circuits, the stores associated will all neurons may be collated. For example, where implemented on an FPGA the stores may be implemented using Block RAM. This is likely to be preferred implementation for neural networks comprising hundreds or thousands of neuron circuits. As such the store(s) could be considered as outside of circuit 1, 100 and instead function to provide an input to its respective spike train generator subcircuit.

Claims

Claim1. A circuit for implementing an artificial neuron of a spiking neural network, the circuit comprising: a first synaptic input for receiving input spike signals of a single bit value; a first spike train generator means configured to generate, in response to each input spike signal received at the first synaptic input, a spike train comprising n weighting spikes, where n is an integer indicative of a synaptic weight value associated with the first synaptic input; a membrane potential counter configured to count each weighting spike received from the first spike train generator towards a potential threshold value; and an output spike generator configured to generate an output spike signal of a single bit value in response to the membrane potential counter reaching the potential threshold value; wherein the circuit further comprising a second spike train generator means configured to generate, in response to each input spike signal received at the first synaptic input, a spike train comprising k weighting spikes, and where n is an integer indicative of an excitatory synaptic weight value associated with the first synaptic input; the k is an integer indicative of an inhibitory synaptic weight value associated with the first synaptic input; andin which the membrane potential counter is configured to count away from the potential threshold value with each weighting spike received from the second spike generator means.

2. A circuit according to claim 1 comprising a second synaptic input for receiving input spike signals of a single bit value; a third spike train generator means configured to generate, in response to each input spike signal received at the second synaptic input, a spike train comprising I weighting spikes, where I is an integer indicative of a synaptic weight value associated with the second synaptic input; and wherein the membrane potential counter is configured to count each weighting spike received from both the first spike train generator and the second train generator towards the potential threshold value.

3. A circuit according to claim 2 comprising a fourth spike train generator means configured to generate, in response to each input spike signal received at the second synaptic input, a spike train comprising p weighting spikes, whereI is an integer indicative of an excitatory synaptic weight value associated with the second synaptic input; p is an integer indicative of an inhibitory synaptic weight value associated with the second synaptic input; andin which the membrane potential counter is configured to count away from the potential threshold value with each weighting spike received from both the second spike generator means and fourth spike generator means; and wherein, the value of one of n and k is zero and the other is non-zero; and wherein the value of one of I and p is zero and the other is non-zero.

4. A circuit according to any previous claim in which each spike train generator means comprises a spike generator configured to generate spikes, and a synaptic counter configured to count, in response to a received input synaptic signal, to the synaptic weight value associated with its associated synaptic input; and in which the spike train generator means is configured to output spikes from the spike generator whilst the synaptic counter is counting to the synaptic weight value.

5. A circuit according to any previous claim further comprising a refractory timer comprising a Linear Feedback Shift Register (LFSR) configured to prevent an output spike signal output from the neuron circuit within a configurable period immediately following output of a preceding output spike signal output from the neuron circuit.

6. A circuit according to any previous claim comprising a leakage timer having an output configured to periodically move a count value of the membrane potential counter away from the potential threshold value.

7. An integrated circuit chip configured to implement the circuit of any previous claim.

8. An FPGA integrated circuit configured to implement a SNN including one or more of the circuits of any previous claim.

9. A method of operation of an artificial neuron of a spiking neural network; the method comprising: generating a train of weighting spike signals in response to each synaptic input signal received at a first synaptic input of the artificial neuron, wherein the number of weighting spikes in each train is indicative of a first weight value associated with the first synaptic input; using a counter means counting the total number of weighting spike signals generated; and in response to the counter means reaching a threshold value, generating an output synaptic signal at a synaptic output of the artificial neuron.

10. A method according to claim 9, wherein the artificial neuron further comprises a second synaptic input; the method also comprising: in response to each synaptic input signal received at the second synaptic input generating a train of weighting spike signals comprising a number of weighting spikesindicative of a second weight value associated with the second synaptic input; the first and second weight values being different; counting the total number of spikes signals generated in response to synaptic input signals received at both first and second synaptic inputs; and in response to the counter means reaching a threshold value, generating an output synaptic signal at a synaptic output of the artificial neuron11. A method according to claim 10 wherein the first weight value is an excitatory synaptic weight value and the second weight value is an inhibitory synaptic weight value; and in which the method comprises counting towards the threshold value with each weighting spike signal generated from a synaptic input signal received at the first synaptic input; and counting away from the threshold value with each weighting spike signal generated from a synaptic input signal received at the second synaptic input.

12. A method according to any claim 9-11 further comprising applying a refractory period by not counting weighting spikes generated for a period of time immediately following generation of an output synaptic signal.

13. A method according to any claim 9-12 comprising, during counting of weighting spikes, periodically adjusting a count value away from the threshold value to implement a leak function.

14. A circuit for implementing an artificial neuron of a spiking neural network, the circuit comprising: a first synaptic input for receiving input spike signals of a single bit value; a first spike train generator means configured to generate, in response to each input spike signal received at the first synaptic input, a spike train comprising n weighting spikes, where n is an integer indicative of a synaptic weight value associated with the first synaptic input; a membrane potential counter configured to count each weighting spike received from the first spike train generator towards a potential threshold value; and an output spike generator configured to generate an output spike signal of a single bit value in response to the membrane potential counter reaching the potential threshold value.

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