Register value processing device and register value processing method

Abstract

Provided is a register value processing device capable of enhancing usefulness of a register value. Thus, a register value processing device is provided with: a register value acquisition unit (52) that repeatedly acquires a register value (r) that is stored in a prescribed register included in a processor; and a report data creation unit (54) that creates report data (DS) on the basis of the acquired register value (r).

Description

Register value processing device and register value processing method

[0001] The present invention relates to a register value processing device and a register value processing method.

[0002] As background art in this technical field, the following non-patent document 1 shows the configuration of a typical CPU (Central Processing Unit). As shown in non-patent document 1, a control unit included in a CPU can access main memory via an address bus and a data bus. On the other hand, the control unit can access memory called a "register," which is faster than main memory, without going through the address bus and data bus. Registers generally use flip-flop circuits and operate at high speed, but have a small memory capacity and tend to be rewritten frequently. Some registers are used for specific purposes, and by referencing their information, it may be possible to diagnose the state of a computer.

[0003] Computer Course: Advanced Edition, Part 2: CPU Calculation Methods are Surprisingly Simple, Speed ​​is the Key to Competitiveness [online], [Retrieved August 21, 2024], Internet <URL: https: / / jp.fujitsu.com / family / familyroom / syuppan / family / webs / serial-comp2 / index2.html >

[0004] However, there are cases where a host computer and a monitoring computer are connected via a network or the like, and the monitoring computer is required to inquire about register values, which are the contents stored in registers in the host computer. However, as the frequency of inquiries increases, the processing load of sending and receiving IP packets and the like via the network increases. This invention has been made in consideration of the above-mentioned circumstances, and it is an object of the present invention to provide a register value processing device and a register value processing method that can increase the usefulness of register values.

[0005] In order to solve the above problem, the register value processing device of the present invention is characterized by comprising a register value acquisition unit that repeatedly acquires register values, which are values ​​stored in a specified register included in a processor, and a report data creation unit that creates report data based on the acquired register values.

[0006] According to the present invention, the usefulness of register values ​​can be increased.

[0007] It is a block diagram of an information processing system according to a first embodiment. It is a block diagram of a computer. It is a block diagram of a CPU included in the computer. It is a functional block diagram of a register information processing unit in a host computer. It is a sequence diagram of the first embodiment. It is an explanatory diagram of the operation of a report data creation unit in a second embodiment. It is a diagram showing an example of transition of a register value in a third embodiment.

[0008] [First Embodiment] <Configuration of First Embodiment> The first embodiment will be described below. Fig. 1 is a block diagram of an information processing system 100 according to the first embodiment. The information processing system 100 includes a host computer 110 (register value processing device, computer) and a monitoring computer 120, which communicate bidirectionally via a network 130. The host computer 110 is primarily used to execute various application programs, and the monitoring computer 120 monitors the host computer 110 via the network 130.

[0009] FIG. 2 is a block diagram of a computer 980. The host computer 110 and the monitoring computer 120 shown in FIG. 1 each include one or more computers 980 shown in FIG. 2. In FIG. 2, the computer 980 includes a CPU 981 (processor), a storage unit 982, a communication port 983, an input / output port 984, and a media port 985. The storage unit 982 includes a RAM 982a, a ROM 982b, and an SSD (Solid State Drive) 982c. The communication port 983 is connected to a communication circuit 986. The input / output port 984 is connected to an input / output device 987. The media port 985 reads and writes data from a recording medium 988.

[0010] The ROM 982b stores an IPL (Initial Program Loader) and other programs executed by the CPU 981. The SSD 982c stores an operating system, application programs, various data, and other programs. The CPU 981 executes the operating system, application programs, and other programs loaded from the SSD 982c into the RAM 982a to implement various functions.

[0011] The communication circuit 986 communicates with the network 130 (see FIG. 1 ) via DCO (Digital Coherent Optics). To this end, the communication circuit 986 includes a DSP (Digital Signal Processor) 10 therein, and the DSP 10 (processor) includes a register group 12 therein. The register group 12 stores various data for the DSP 10. In particular, the register group 12 includes a register that stores noise information for the DSP 10 (for example, the number of occurrences per unit time of noise above a predetermined level).

[0012] Fig. 3 is a block diagram of a CPU 981 included in a computer 980. In Fig. 3, the CPU 981 includes an internal bus 20, an arithmetic register 22, an arithmetic unit 24, a control unit 26, an instruction register 28, an instruction recorder 30, a register group 32, and an address register 34. The CPU 981 is also connected to a RAM 982a via a control bus 42, an address bus 44, and a data bus 46.

[0013] The register group 32 includes a plurality of registers having various functions. When accessing the RAM 982a, the control unit 26 writes the address of the access destination in the address register 34. The control unit 26 also transmits a signal distinguishing between writing and reading to the RAM 982a via the control bus 42. The control unit 26 also inputs and outputs data to be written and read from the RAM 982a via the data bus 46.

[0014] On the other hand, when the control unit 26 accesses the register group 32, it does so without going through the address register 34, the control bus 42, the address bus 44, or the data bus 46. This allows the control unit 26 to write / read data to / from the register group 32 at higher speeds than when writing / reading data to / from the RAM 982a.

[0015] 2, the DSP 10 included in the communication circuit 986 has a register set 12. Therefore, the CPU 981 and the DSP 10 have in common the fact that they both perform "processing for inputting and outputting data to and from a register set (or a single register)." Therefore, in this specification, the CPU 981 and the DSP 10 may be collectively referred to as a "processor."

[0016] 4 is a functional block diagram of the register information processing unit 50 in the host computer 110. In FIG. 4, each block in the register information processing unit 50 mainly represents a function realized by the operating system, application programs, etc. in the host computer 110. That is, the register information processing unit 50 includes a register value acquisition unit 52, a report data creation unit 54, and a data reporting unit 56.

[0017] The register value acquisition unit 52 acquires the register value r, which is the stored content, from a register belonging to either the register group 32 in the CPU 981 (see FIG. 3) or the register group 12 in the communication circuit 986 (see FIG. 2). The report data creation unit 54 creates report data DS to be transmitted to, for example, the monitoring computer 120, based on the acquired register value r. Note that the report data DS in this embodiment is a combination of the acquired register values ​​r in the order in which they were acquired. The data reporting unit 56 transmits the report data DS to the request source (e.g., the monitoring computer 120) via the network 130 based on a request from the request source.

[0018] <Operation of First Embodiment> Next, the operation of the first embodiment will be described. Fig. 5 is a sequence diagram of the first embodiment. First, the "register" in the diagram refers to a predetermined register in the register group 32 (see Fig. 3) in the CPU 981 of the host computer 110, or a predetermined register in the register group 12 (see Fig. 2) in the DSP 10 of the communication circuit 986. The contents stored in the register, i.e., the register value r, is updated as needed by hardware processing of the CPU 981 or the DSP 10 (step S2).

[0019] The register value acquisition unit 52 of the register information processing unit 50 acquires the register value r, for example, periodically (step S4, register value acquisition step). The report data creation unit 54 then creates report data DS each time the register value r is acquired (step S6, report data creation step). The monitoring computer 120 also transmits a report request to the data reporting unit 56 of the host computer 110, for example, periodically, requesting the transmission of report data DS (step S8). Upon receiving the report request, the data reporting unit 56 then transmits the latest report data DS at that time to the monitoring computer 120 (step S10).

[0020] As in the above example, it is assumed that the register value r is noise information (the number of times noise above a predetermined level occurs per unit time) of the DSP 10 in the communication circuit 986. In this case, the monitoring computer 120 can monitor the quality of the communication environment of the host computer 110 based on the report data DS.

[0021] [Second Embodiment] Next, a second embodiment will be described. Note that in the description of each embodiment, parts corresponding to parts of the other embodiments described above will be assigned the same reference numerals, and their description may be omitted. The configuration and operation of the second embodiment are similar to those of the first embodiment described above, but the operation of the report data creation unit 54 differs from that of the first embodiment. Therefore, the operation of the report data creation unit 54 will be described. First, in the first embodiment described above, the report data DS was obtained by combining the acquired register values ​​r in the order in which they were acquired. However, it would be more preferable if the data volume of the report data DS could be further compressed. Therefore, in this embodiment, the data volume of the report data DS is compressed using the procedure shown in FIG. 6.

[0022] 6 is a diagram illustrating the operation of the report data creation unit 54 in the second embodiment. The register value r1 shown in FIG. 2 is the register value r acquired by the register value acquisition unit 52 at a certain acquisition timing (step S4 in FIG. 5). The register value r2 is the register value r acquired by the register value acquisition unit 52 at the acquisition timing immediately thereafter. The register values ​​r1 and r2 are both 32-bit data, and the bit strings separated into octets (8 bits) starting from the most significant bit are called the first, second, third, and fourth octets p1, p2, p3, and p4 (partial bit strings).

[0023] In register value r2, underlined bits are bits that have been changed with respect to register value r1. That is, in the illustrated example, the contents of the first and fourth octets p1 and p4 of register value r2 are different from those of register value r1. Difference data DD is data that represents the difference between register values ​​r1 and r2, and has a change position field DD1 and a change content field DD2.

[0024] The change position field DD1 is 4-bit data, and the first to fourth bits correspond to the first to fourth octets p1 to p4, respectively. In the change position field DD1, the bits corresponding to the changed octets among the first to fourth octets p1 to p4 of the register values ​​r1 and r2 are set to "1," and the other bits are set to "0." In the example of Figure 6, changes have occurred in the first and fourth octets p1 and p4, so the first and fourth bits of the change position field DD1 are set to "1," and the other bits are set to "0."

[0025] The contents of the changed octet are stored in the change contents field DD2. In the example of Fig. 6, the contents of the first and fourth octets p1 and p4 of the register value r2 are stored in the change contents field DD2. If there is no change in the contents of the register values ​​r1 and r2, the change position field DD1 will be "0000" and the change contents field DD2 will be omitted.

[0026] The report data creation unit 54 (see FIG. 4) in this embodiment creates differential data DD each time it acquires a register value r, and creates report data DS by concatenating the created differential data DD. This allows the report data DS to be generated with a particular focus on octets where changes have occurred, thereby reducing the amount of data in the report data DS compared to the first embodiment.

[0027] [Third Embodiment] Next, a third embodiment will be described. In the third embodiment, the method by which the report data creation unit 54 creates the report data DS is also different from that in the first embodiment. Other than that, the configuration and operation of the information processing system in the third embodiment are the same as those in the first embodiment described above.

[0028] 7 is a diagram showing an example of the transition of the register value r in the third embodiment. In FIG. 7, the horizontal axis is time t, and the vertical axis is the register value r. In FIG. 7, the black circles and black rectangles represent the register values ​​r at each time acquired by the register value acquisition unit 52 (see FIG. 4). In this embodiment, a period repeated at a predetermined cycle TP is called an "acquisition period." In FIG. 7, a certain acquisition period C N and the previous acquisition period C N-1 10 shows an example of the transition of the register value r in

[0029] The report data creation unit 54 N-1 Based on the register value r in N-1 Calculate the fluctuation reference value B. N-1 For example, the acquisition period C N-1 The average value of the register value r in N-1 does not necessarily mean that the acquisition period C N-1 For example, the average value α and standard deviation σ are calculated for a predetermined number of past register values ​​r, and the average value of only the register values ​​r that fall within the range of "α±3σ" is used as the fluctuation reference value B. N-1 It may also be possible to use the following.

[0030] The report data creation unit 54 uses the previous fluctuation reference value B N-1 Corresponding to this acquisition period C NRecording suppression range E in N Here, the recording suppression range E N is a range in which the recording of the register value r is suppressed (for example, the recording is completely omitted). N-1 If the value is close to the fluctuation reference value B, N-1 The recording of the register value r can be suppressed by regarding it as "equal to" the acquisition period C shown in FIG. N In the range, the register value r indicated by the black circle is the value to be recorded, and the black rectangle is the recording suppression range E N , and therefore are suppressed from being recorded (e.g., omitted from being recorded).

[0031] In addition, the recording suppression range E N The highest value of EH N and the lowest value EL N When a predetermined constant f satisfies "0<f<1", "EH N = (1 + f) B N-1 " and "EL N = (1 - f) B N-1 The report data creation unit 54 in this embodiment can calculate the data for each acquisition period (for example, C N ), the recording suppression range (for example, E N ) and the fluctuation reference value (e.g., B N ) are recorded, and the recorded contents are used as report data DS. As a result, in this embodiment as well, the amount of data in the report data DS can be reduced compared to the first embodiment.

[0032] [Modifications] The present invention is not limited to the above-described embodiment, and various modifications are possible. The above-described embodiment is provided as an example to facilitate understanding of the present invention, and is not necessarily limited to an embodiment including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to delete part of the configuration of each embodiment, or to add or replace other configurations. Furthermore, the control lines and information lines shown in the figures are those considered necessary for explanation, and do not necessarily represent all control lines and information lines necessary for the product. In reality, it is possible to consider that almost all components are interconnected. Possible modifications of the above-described embodiment include, for example, the following.

[0033] (1) In the above embodiments, the CPU 981 and the DSP 10 are used as examples of a "processor." However, the "processor" of the present invention is not limited to these. Devices such as an ASIC (Application Specific Integrated Circuit) and an FPGA (Field Programmable Gate Array) that have registers for storing physical quantities and other information and perform various processes based on the information stored in the registers are also included in the category of a "processor."

[0034] (2) Since the hardware of the host computer 110 in the above embodiment can be realized by a general-purpose computer, the processes corresponding to the above-mentioned block diagrams and sequence diagrams, as well as programs that execute the various processes described above, may be stored on a storage medium (a computer-readable storage medium on which a program is recorded) or distributed via a transmission path.

[0035] (3) In the above embodiment, the processes corresponding to the block diagrams and sequence diagrams, as well as the various other processes described above, are described as software processes using programs. However, some or all of these processes may be replaced with hardware processes using ASICs, FPGAs, etc.

[0036] [Effects] (1) According to the above-described embodiments, the register value processing device includes a register value acquisition unit 52 that repeatedly acquires a register value r, which is a value stored in a predetermined register included in the processor (981, 10), and a report data creation unit 54 that creates report data DS based on the acquired register value r. As a result, by referring to the report data DS, it is possible to know the trend of the register value r and increase the usefulness of the register value r.

[0037] (2) Furthermore, it is more preferable that the register value r includes a plurality of partial bit strings (p1 to p4), and the report data creation unit 54 creates the report data DS by accumulating a change position field DD1 that indicates which of the plurality of partial bit strings (p1 to p4) has changed, and a change content field DD2 that indicates the content of the partial bit string (p1 to p4) in which the change has occurred. This allows the report data DS to be created by focusing on the partial bit string (p1 to p4) in which the change has occurred, thereby reducing the amount of data in the report data DS.

[0038] (3) The report data creation unit 54 also N The fluctuation reference value B is calculated based on the register value r acquired by the register value acquisition unit 52 in each of the above. N and a function for calculating one acquisition period C N In the previous acquisition period (C N-1 ) Fluctuation reference value B N-1 A recording suppression range E including N and a function for determining whether the register value r is within the recording suppression range E N a function of suppressing recording of the register value r when the register value r falls within the recording suppression range E N It is more preferable to provide a function for recording the register value r as report data DS when the register value r is outside the recording suppression range E. N Since the recording of the register value r belonging to the register r can be suppressed, the amount of data in the report data DS can be reduced.

[0039] 10 DSP (processor) 50 Register information processing unit 52 Register value acquisition unit 54 Report data creation unit 100 Information processing system 110 Host computer (register value processing device, computer) 980 Computer 981 CPU (processor) r Register value DS Report data S4 Step (register value acquisition step) S6 Step (report data creation step) DD1 Change position field DD2 Change content field B N , B N-1 Fluctuation reference value C N Acquisition period E N Recording suppression range p1 to p4 1st to 4th octets (partial bit string)

Claims

1. A register value processing device comprising: a register value acquisition unit that repeatedly acquires register values, which are values ​​stored in a specified register included in a processor; and a report data creation unit that creates report data based on the acquired register values.

2. The register value processing device described in claim 1, characterized in that the register value includes a plurality of partial bit strings, and the report data creation unit creates the report data by accumulating a change position field that indicates which of the plurality of partial bit strings has changed, and a change content field that is the content of the partial bit string in which the change has occurred.

3. The register value processing device described in claim 1, characterized in that the report data creation unit has the following functions: a function to calculate a fluctuation reference value based on the register value acquired by the register value acquisition unit in each of multiple acquisition periods; a function to determine a recording suppression range in one of the acquisition periods, which is a range that includes the fluctuation reference value in the previous acquisition period; a function to suppress recording of the register value if the register value falls within the recording suppression range; and a function to record the register value as the report data if the register value falls outside the recording suppression range.

4. A register value processing method characterized by having a computer execute a register value acquisition step of repeatedly acquiring register values, which are values ​​stored in a specified register included in a processor, and a report data creation step of creating report data based on the acquired register values.

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