Information processing method and electronic control device

Abstract

In a multi-core environment according to the present embodiment, at least one of a plurality of processor cores disposes each of data blocks in any of a shared memory and a plurality of local memories on the basis of additional information included in the data block. Each data block comprises an accumulation of one or more referenced data items referred to by a program executed by the same processor core at the same execution cycle, and the additional information allows identification of said same processor core and said same execution cycle.

Description

Information processing method and electronic control device

[0001] The present invention relates to an information processing method and an electronic control device.

[0002] Conventionally, multiprocessor systems (multicore environments) have been known in which a plurality of processors (processor cores) can be combined and operated in parallel with each other. For example, Patent Document 1 listed below proposes a crossbar switch for a multiprocessor system, which can interconnect all processors with any memory in any configuration and exchange data between them.

[0003] Japanese Patent Application Publication No. 03-211656

[0004] However, the above-mentioned conventional techniques have a problem in that they do not take into consideration the relationship between the location of data referenced by a processor core that executes a program and the processing load of that processor core in a multi-core environment.

[0005] In one aspect, the present invention has been made in consideration of these circumstances, and its purpose is to provide an information processing method and electronic control device that reduces the processing load on a processor core executing a program in a multi-core environment by controlling whether the data referenced by the processor core is placed in shared memory or multiple local memories.

[0006] In order to solve the above-mentioned problems, one aspect of the present invention provides an information processing method in a multi-core environment in which multiple processor cores are interconnected, each of which can communicate with a shared memory and each of which has a local memory, and which causes at least one of the multiple processor cores to execute a process of placing each of multiple referenced data, which is data referenced in a program executed by one of the multiple processor cores, in the shared memory or one of the multiple local memories, wherein at least one of the multiple processor cores executes the following steps: acquiring a data block, which is formed by accumulating one or more of the multiple referenced data so that the referenced data does not exceed a reference data size, and a program that references each of the one or more referenced data included in the data block is executed by the same processor core among the multiple processor cores and with the same execution period, and which includes, as additional information, common core identification information that identifies the same processor core as a common core and common execution period information that identifies the same execution period as a common execution period; and placing the data block in the shared memory or one of the multiple local memories based on the additional information.

[0007] According to the present invention, in a multi-core environment, an information processing method and an electronic control device can be provided that reduce the processing load on a processor core by controlling whether the data referenced by the processor core executing a program is placed in shared memory or multiple local memories.

[0008] 1 is a block diagram showing a schematic configuration of a data allocation system including an electronic control device according to an embodiment; FIG. 1 shows an example of a data block (A) according to an embodiment, and tag information (B) included in the data block; FIG. 2 is a schematic diagram showing an example of a software configuration of an electronic control device according to an embodiment; FIG. 3 shows a table (A) organizing an example of a common core and a common execution period identified by the respective tag information for a plurality of data blocks, and FIG. 4 shows the state of a shared memory and each local memory after an electronic control device according to an embodiment arranges each of the plurality of data blocks illustrated in the table; FIG. 4 shows a table (A) showing an example of a plurality of CPU cores provided in an electronic control device, each classified as an ASIL core or a QM core, and FIG. 5 shows an example of tag information (B) including safety level information in addition to common core identification information and common execution period information; FIG. 5 shows a table (A) organizing an example of a plurality of programs that are enabled or disabled for each region, and FIG. 6 shows an example of tag information (B) including valid region information in addition to common core identification information and common execution period information. 8 shows a table (A) that organizes examples of common cores, common execution periods, and common execution regions (configurations) identified by the respective tag information for multiple data blocks, and (B) shows the state of the shared memory and each local memory after an electronic control device according to an embodiment allocates each of the multiple data blocks illustrated in the table. An example of an outline of the processing procedure of the electronic control device according to an embodiment is shown. An example of the details of the processing procedure of the data block allocation process of FIG.

[0009] An embodiment according to one aspect of the present invention (hereinafter also referred to as "the present embodiment") will be described below with reference to the drawings. However, the present embodiment described below is merely an example of the present invention in all respects. Needless to say, various improvements and modifications can be made without departing from the scope of the present invention. In other words, when implementing the present invention, specific configurations according to the embodiment may be appropriately adopted. Note that, although data appearing in the present embodiment are described in natural language, more specifically, they are specified using pseudo-language, commands, parameters, machine language, etc. that can be recognized by a computer.

[0010] §1 System Overview and Hardware Configuration of Electronic Control Device, etc. Figure 1 is a block diagram showing the overview of the configuration of a data allocation system Sys including an electronic control device (electronic control device 1) according to this embodiment. In the illustrated example, the data allocation system Sys includes the electronic control device 1, a tool 2, and a non-volatile memory 3, which is an example of a storage device external to the electronic control device 1. However, it is not essential for the data allocation system Sys to include the tool 2 and the non-volatile memory 3, and the tool 2 and the non-volatile memory 3 may be omitted from the data allocation system Sys.

[0011] The tool 2, also referred to as a diagnostic device, is a device that writes (in other words, stores) destination information 31 into the nonvolatile memory 3 via the CPU core 10 (in the illustrated example, CPU core 10(1)) of the electronic control unit 1. The destination information 31 is written into the nonvolatile memory 3 by the tool 2 via the CPU core 10(1), that is, the nonvolatile memory 3 stores the destination information 31. The destination information 31 is also referred to as configuration information (setting information), and in this embodiment, is information indicating a region RG such as "Japan (JPN)" or "United States (US)," and is used in memory allocation processing (in other words, memory assignment processing) by the electronic control unit 1. The method by which the electronic control unit 1 uses the destination information 31 will be described in detail below.

[0012] The electronic control unit 1 is an electronic control unit that includes a plurality of CPU cores 10 (processor cores) that are connected to each other and each of which can communicate with a shared memory 12 and each of which has a local memory 11. In other words, the electronic control unit 1 realizes a multi-core environment in which a plurality of CPU cores 10 that are connected to each other and each of which can communicate with the shared memory 12 and each of which has a local memory 11. In this embodiment, the electronic control unit 1 is realized, for example, as a microcomputer provided in an on-board control unit (ECU, Electronic Control Unit) of a vehicle VH (not shown).

[0013] 1 shows an example of the hardware configuration of an electronic control device 1. The electronic control device 1 shown in FIG. 1 includes a plurality of CPU cores 10, a plurality of local memories 11 each corresponding to one of the CPU cores 10, a shared memory 12, a ROM (Read Only Memory) 13, a clock oscillator 14, and a bus 15. The CPU cores 10, the local memories 11, the shared memory 12, the ROM 13, and the clock oscillator 14 are electrically connected to one another via the bus 15.

[0014] Each of the multiple CPU cores 10 is an example of a "processor core" of the present invention and is capable of executing various programs PG. In this embodiment, an example is described in which the electronic control unit 1 includes three processor cores, CPU cores 10(0), 10(1), and 10(2), as the multiple CPU cores 10. However, this is not limiting, and the number of processor cores included in the electronic control unit 1 may be two, four, or more. Furthermore, the electronic control unit 1 may realize a multi-core environment by using multiple chips each including multiple processor cores. In this embodiment, when there is no need to particularly distinguish between the CPU cores 10(0), 10(1), and 10(2), they may be simply referred to as "CPU cores 10."

[0015] Each of the multiple local memories 11 is an example of the "local memory" of the present invention, and each of the multiple local memories 11 is a local memory corresponding to each of the multiple CPU cores 10. As described above, in this embodiment, the electronic control unit 1 includes local memories 11(0), 11(1), and 11(2) corresponding to the CPU cores 10(0), 10(1), and 10(2), respectively. In this embodiment, when there is no need to particularly distinguish between the local memories 11(0), 11(1), and 11(2), they may be simply referred to as "local memories 11." Each local memory 11 is realized, for example, by a RAM (Random Access Memory).

[0016] The shared memory 12 is an example of the "shared memory" of the present invention, is capable of communicating with each of the multiple CPU cores 10, and is realized, for example, by a RAM. The ROM 13 stores a program (placement control program 131) for causing the electronic control device 1 (particularly, at least one of the multiple CPU cores 10) to execute an information processing method PM. The information processing method PM causes at least one of the multiple CPU cores 10 to execute information processing (the memory placement process of FIG. 8 ), which will be described later, for placing each of the multiple referenced data RD in either the shared memory 12 or one of the multiple local memories 11. The placement control program 131 is a program for causing at least one of the multiple CPU cores 10 to execute the information processing, and includes a series of instructions for the information processing. At least one of the multiple CPU cores 10 executes the placement control program 131 read from the ROM 13 using the RAM (either the shared memory 12 or one of the multiple local memories 11) as a work area, thereby executing the above-mentioned information processing. The clock oscillator 14 is a circuit that generates a clock (synchronization signal), and is also called a clock oscillation circuit or a clock generator.

[0017] In the electronic control device 1, at least one of the multiple CPU cores 10 places each of multiple referenced data RD in either the shared memory 12 or multiple local memories 11. Each referenced data RD is data referenced in each of various programs PG executed by one of the multiple CPU cores 10. In other words, each referenced data RD is data referenced by one of the multiple CPU cores 10 executing the program PG. In this embodiment, the referenced data RD is referenced in the program PG executed by one of the CPU cores 10(0), 10(1), or 10(2), in other words, it is referenced by one of the CPU cores 10(0), 10(1), or 10(2) executing the program PG.

[0018] In this embodiment, various programs PG that reference each piece of referenced data RD are executed at a predetermined execution cycle EC, and are executed repeatedly at the execution cycle EC, for example. That is, each of the multiple referenced data RD is referenced by one of the multiple CPU cores 10 at the predetermined execution cycle EC. In this embodiment, various programs PG are executed at, for example, one of execution cycles EC(1) (high execution cycle), EC(2) (medium execution cycle), and EC(3) (low execution cycle). The execution cycle EC(1) is faster (in other words, shorter) than the execution cycle EC(2), and the execution cycle EC(2) is faster than the execution cycle EC(3). The execution cycle EC may be understood as, for example, an execution priority, and it may be understood that the shorter the execution cycle EC, the higher the execution priority. In this embodiment, an example will be described in which the execution period EC of the program PG is one of three types: execution period EC(1), execution period EC(2), and execution period EC(3). However, it is not essential that there are three types of execution period EC. There may be two types of execution period EC of the program PG, or there may be four or more types of execution period EC.

[0019] The following describes an example in which the CPU core 10(0) of the multiple CPU cores 10 allocates each of the multiple referenced data RD in either the shared memory 12 or the multiple local memories 11. Hereinafter, the CPU core 10 that executes such allocation may be particularly referred to as the "allocation processing execution core PPC." In other words, in this embodiment, an example in which the CPU core 10(0) is the allocation processing execution core PPC will be described. However, it is not essential that the CPU core 10(0) allocates each referenced data RD in memory (either the shared memory 12 or the multiple local memories 11). In other words, it is not essential that the CPU core 10(0) be the allocation processing execution core PPC. A CPU core 10 other than the CPU core 10(0) may also be the allocation processing execution core PPC. Furthermore, the multiple referenced data RD may each be allocated in memory by, for example, the CPU core 10 that executes the program PG that references each referenced data RD. For example, among a plurality of referenced data RD, a "certain referenced data RD" referenced in a certain program PG may be allocated to memory by the CPU core 10 that executes the certain program PG. Furthermore, a data block DB, which will be described in detail below, may be allocated to memory by a common core CC identified by the common core identification information ICC of the certain data block DB, for example, and the common core CC may be used as the allocation processing execution core PPC.

[0020] The placement process execution core PPC (for example, the CPU core 10(0)) executes memory placement processing to place each of the multiple referenced data RD in either the shared memory 12 or the multiple local memories 11. In this embodiment, the placement process execution core PPC executes memory placement processing in units of data blocks DB.

[0021] FIG. 2A shows an example of a data block DB including tag information TI and one or more pieces of referenced data RD. FIG. 2B also shows an example of tag information TI. The data block DB accumulates one or more (e.g., multiple) pieces of referenced data RD so that the data size does not exceed a reference data size SS. In particular, the data block DB accumulates "one or more pieces of referenced data RD" that satisfy the following conditions so that the data size does not exceed the reference data size SS. That is, the data block DB accumulates "one or more pieces of referenced data RD" that satisfy the following conditions: (1) the programs PG that reference each piece of referenced data RD are executed by the same CPU core 10 among multiple CPU cores 10, and (2) with the same execution cycle EC. In this embodiment, the "same CPU core 10" related to condition (1) above is referred to as a "common core CC." In addition, the "same execution cycle EC" related to condition (2) above is referred to as a "common execution cycle CEC." The data block DB includes, as tag information TI, common core identification information ICC that identifies the common core CC and common execution cycle information ICE that identifies the common execution cycle CEC. The data block DB is configured so that the total data size of the tag information TI and one or more referenced data RD does not exceed the reference data size SS. As illustrated in FIG. 2A, the tag information TI may be tagged at the beginning of the data block DB. However, the location of the tag information TI in the data block DB is not particularly limited. In addition to the tag information TI, the data block DB includes N referenced data RD, where "N" is an integer greater than or equal to 1. In the illustrated example, the data block DB includes referenced data RD(1), RD(2), RD(3), ... RD(N). For example, the number (N) of referenced data RD included in the data block DB is adjusted so that the data size of the data block DB does not exceed the reference data size SS.

[0022] As described above, the various programs PG that reference one or more pieces of referenced data RD included in the data block DB are each executed by the same CPU core 10 among the multiple CPU cores 10. In this embodiment, the programs are executed by one of the CPU cores 10(0), 10(1), and 10(2). That is, the one or more pieces of referenced data RD included in the data block DB are all referenced by the same CPU core 10, specifically, by the common core CC indicated by the tag information TI (particularly, the common core identification information ICC) of the data block DB. For example, the one or more pieces of referenced data RD included in the data block DB whose common core CC is CPU core 10(0) are each referenced by one of the various programs PG executed by CPU core 10(0). Furthermore, the various programs PG that reference one or more pieces of referenced data RD included in the data block DB are each executed in the same execution cycle EC. In this embodiment, the programs are executed in one of the execution cycles EC(1), EC(2), and EC(3). That is, all of the one or more referenced data RD included in the data block DB are referenced in the same execution cycle EC, specifically, in the common execution cycle CEC indicated by the tag information TI (particularly, the common execution cycle information ICE) of the data block DB. For example, if the common core CC is CPU core 10(0) and the common execution cycle CEC is execution cycle EC(1), the one or more referenced data RD included in the data block DB are each referenced in one of the various programs PG executed by CPU core 10(0) in execution cycle EC(1).

[0023] FIG. 2B shows an example of tag information TI implemented as 8-bit information. Each bit stores a "0" or a "1." In the illustrated example, bits 0 to 2 represent common execution cycle information ICE. For example, if the common execution cycle CEC is execution cycle EC(1) (execution cycle (high)), bits 0 and 1 store a "0," and bit 2 stores a "1." Additionally, bits 3 to 5 store common core identification information ICC. For example, if the common core CC is CPU core 10(0), bits 3 and 4 store a "0," and bit 5 stores a "1." Configuring the tag information TI as a bit string including (A) a plurality of bits each indicating, for each of the multiple CPU cores 10, whether it is a common core CC (1) or not a common core CC (0), and (B) a plurality of bits each indicating, for each of the multiple types of execution cycles EC, whether it is a common execution cycle CEC (1) or not a common execution cycle CEC (0), provides the following advantages: Namely, the data size of the tag information TI can be reduced. Furthermore, reading of the tag information TI is simplified, and the placement processing execution core PPC can easily determine the common core CC and the common execution cycle CEC from the tag information TI.

[0024] In a multi-core environment, the time required for a processor core to read data varies depending on the location of the data, i.e., the memory in which the data is located. Specifically, the time is fastest when the data is located in a local memory of a processor core, followed by when the data is located in shared memory. The time required for a processor core to read data is longest (slowest) when the data is located in a local memory of a processor core other than the processor core in question. For example, for CPU core 10(0), the time required to read data stored in local memory 11(0) is faster than the time required to read data stored in shared memory 12. Furthermore, the time required for CPU core 10(0) to read data stored in shared memory 12 is usually faster than the time required to read data stored in local memory 11(1) or local memory 11(2), although this depends on the congestion of bus 15. This is because the methods (methods) used by CPU core 10(0) to access each memory are different. The CPU core 10(0) accesses the local memory 11(0) using a method such as DSPR (Data Scratch Pad RAM), while accessing the shared memory 12 using a method such as SRI (Shared Resource Interconnection). The CPU core 10(0) also accesses the local memory 11(1) or the local memory 11(2) using a method such as SPB (System Peripheral Bus). Depending on the method, the time required for the CPU core 10(0) to read the referenced data RD stored in each memory varies, and the time required to access each memory also varies. The longer the time required for reading and the time required for access, the greater the processing load. In particular, the faster the execution period EC of a program PG, the greater the number of accesses to the memory in which the referenced data RD referenced in the program PG is stored, and therefore the greater the processing load of the CPU core 10(0).If the processing load exceeds 100%, for example, the processing will fail.

[0025] Therefore, from the viewpoint of processing load, it is desirable that the referenced data RD referenced in a program PG executed by a certain CPU core 10 among the multiple CPU cores 10 be allocated in the local memory 11 of that certain CPU core 10. In particular, the shorter the execution period EC of a program PG executed by a certain CPU core 10, the more desirable it is that the referenced data RD referenced in that program PG be allocated in the local memory 11 of that certain CPU core 10. This can also be rephrased as follows. That is, it is desirable that the referenced data RD referenced by a certain CPU core 10 among the multiple CPU cores 10 be allocated in the local memory 11 of that certain CPU core 10. In particular, the more frequently a certain CPU core 10 references the referenced data RD, that is, the shorter the execution period EC of the program PG that references that referenced data RD, the more desirable it is that the referenced data RD be allocated in the local memory 11 of that certain CPU core 10.

[0026] Therefore, the placement process execution core PPC handles the referenced data RD in units of data block DBs in the memory placement process for placing each of the multiple referenced data RD in either the shared memory 12 or the multiple local memories 11. Specifically, the placement process execution core PPC accumulates "one or more referenced data RD, all of which are referenced by the same common core CC with the same common execution cycle CEC," and places the data block DB, which includes tag information TI that can identify the common core CC and the common execution cycle CEC, in the shared memory 12 or one of the multiple local memories 11 based on the tag information TI.

[0027] The placement process execution core PPC achieves the following effects by treating the referenced data RD as a unit of data block DB. That is, the placement process execution core PPC can efficiently handle "one or more referenced data RD" collectively, using a data block DB as a unit, which is made up of an accumulation of "one or more referenced data RD" that are all referenced by the same common core CC with the same common execution cycle CEC. The placement process execution core PPC can, for example, collectively allocate "multiple referenced data RD" that are all referenced by the same common core CC with the same common execution cycle CEC" to either the shared memory 12 or multiple local memories 11.

[0028] In particular, the placement process execution core PPC places the data block DB in one of the shared memory 12 and the multiple local memories 11 based on tag information TI that can identify the common core CC and the common execution cycle CEC. As described above, it is desirable that referenced data RD referenced by a certain CPU core 10 (in other words, referenced in a program PG executed by the certain CPU core 10) be placed in the local memory 11 of the certain CPU core 10. In particular, the referenced data RD referenced in a program PG executed by a certain CPU core 10 is more desirably placed in the local memory 11 of the certain CPU core 10 the shorter the execution cycle EC of the program PG. Therefore, the placement process execution core PPC can reduce the processing load on the common core CC, for example, by placing the data block DB in the local memory 11 of the common core CC indicated by the tag information TI. By using the tag information TI, the placement process execution core PPC can place "one or more referenced data RD" referenced by the same common core CC at the same common execution cycle CEC in an appropriate memory (either the shared memory 12 or one of the multiple local memories 11). By using the tag information TI, the placement process execution core PPC can place "one or more referenced data RD" included in the data block DB in, for example, a memory that can reduce the processing load on the common core CC. The electronic control device 1 outlined above will be described in detail below using Figures 3 to 9.

[0029] §2 Software Configuration of Electronic Control Unit Figure 3 schematically illustrates an example of the software configuration of the electronic control unit 1 according to this embodiment. A CPU core 10 (e.g., CPU core 10(0)) operating as a placement processing execution core PPC loads a placement control program 131 stored in ROM 13 into RAM and interprets and executes the instructions contained in the loaded placement control program 131, thereby controlling each component. As shown in Figure 3, this allows the electronic control unit 1 to operate as a computer including a block generation unit 110, a block acquisition unit 120, and a block placement unit 130 as software modules. In other words, in this embodiment, each software module of the electronic control unit 1 is implemented by the CPU core 10 operating as the placement processing execution core PPC.

[0030] The block generation unit 110 generates one or more data block DBs from multiple referenced data RDs. For example, the block generation unit 110 generates multiple data block DBs from multiple referenced data RDs. For example, the block generation unit 110 generates one or more "data block DBs in which the CPU core 10(0) is the common core CC and the execution period EC(1) is the common execution period CEC" from a group of "referenced data RDs referenced in programs PG executed by the CPU core 10(0) with the execution period EC(1)" among the multiple referenced data RDs. In a similar manner, the block generation unit 110 generates one or more "data block DBs in which the same CPU core 10 is the common core CC and the same execution period EC is the common execution period CEC" from a group of "referenced data RDs referenced in programs PG executed by the same CPU core 10 among the multiple CPU cores 10 with the same execution period EC" among the multiple referenced data RDs. The block generation unit 110 adjusts, for example, the number (N) of referenced data RD included in the data block DB so that the data size of the data block DB does not exceed the reference data size SS.

[0031] The block acquisition unit 120 acquires a data block DB. In this embodiment, the block acquisition unit 120 acquires a data block DB generated by the block generation unit 110. For example, the block acquisition unit 120 acquires one or more (for example, multiple) data block DBs generated by the block generation unit 110. Note that the electronic control unit 1 does not necessarily have to include the block generation unit 110, and it is not essential for the electronic control unit 1 to generate one or more data block DBs from multiple referenced data RDs. The block acquisition unit 120 may acquire a data block DB from outside the electronic control unit 1. However, by including the block generation unit 110, the electronic control unit 1 can generate a data block DB that accumulates "one or more referenced data RDs executed by the same CPU core 10 and at the same execution period EC" from multiple referenced data RDs. The electronic control unit 1 can then handle multiple referenced data RDs as units of the corresponding data block DBs, i.e., it can handle "one or more referenced data RDs" collectively as an efficiency point.

[0032] The block arrangement unit 130 arranges the data block DB acquired by the block acquisition unit 120 in either the shared memory 12 or the multiple local memories 11, based on the tag information TI included in the data block DB. In the example shown in Figure 3, the block arrangement unit 130 includes a block sorting unit 132, an arrangement position determination unit 134, and a counting unit 136.

[0033] The block sorting unit 132 sorts the plurality of data block DBs acquired by the block acquisition unit 120 in order of the earliest common execution period CEC specified by the common execution period information ICE included in each data block DB.

[0034] The placement position determination unit 134 determines a placement position for each of the multiple data block DBs sorted by the block sorting unit 132 in descending order of common execution period CEC, i.e., determines whether to place the data block DB in the shared memory 12 or the multiple local memories 11. The block placement unit 130 places the data block DB in the placement position (memory) determined by the placement position determination unit 134. In this embodiment, the placement position determination unit 134 determines the placement positions of each of the multiple data block DBs in descending order of common execution period CEC. In other words, the block placement unit 130 places the multiple data block DBs in either the shared memory 12 or the multiple local memories 11 in descending order of common execution period CEC. In the example shown in FIG. 3 , the placement position determination unit 134 includes a common core identification unit 1342, a common execution period identification unit 1344, and a capacity determination unit 1346.

[0035] The common core identification unit 1342 identifies the common core CC by referring to the tag information TI (particularly, the common core identification information ICC) of each data block DB. The common execution cycle identification unit 1344 identifies the common execution cycle CEC by referring to the tag information TI (particularly, the common execution cycle information ICE) of each data block DB. The capacity determination unit 1346 determines, for each data block DB, whether an overflow will occur in the memory (either the shared memory 12 or one of the multiple local memories 11) if the data block DB is allocated to the memory. For example, the capacity determination unit 1346 determines the free space of each memory and determines whether the free space is equal to or greater than the reference data size SS. If the free space is equal to or greater than the reference data size SS, the capacity determination unit 1346 may determine that an overflow will not occur even if the data block DB is allocated to the memory. The capacity determination unit 1346 may calculate the total data size of the data block DBs allocated to each memory by multiplying the allocation number counter CT (the number of data block DBs allocated to each memory) by the reference data size SS for each memory. The capacity determination unit 1346 may determine the free space of each memory from the calculated "total data size of the data block DBs allocated to each memory" and a predetermined maximum capacity for each memory. The allocation number counter CT will be described in detail later.

[0036] The placement position determination unit 134 determines the placement positions of each of a plurality of data block DBs in ascending order of common execution cycle CEC, specifically, in descending order of common execution cycle CEC confirmed by the common execution cycle identification unit 1344. In this embodiment, the placement position determination unit 134 first determines the placement positions of data block DBs whose common execution cycle CEC is execution cycle EC(1), then determines the placement positions of data block DBs whose common execution cycle CEC is execution cycle EC(2). Finally, the placement position determination unit 134 determines the placement position of data block DBs whose common execution cycle CEC is execution cycle EC(3).

[0037] As described above, in a multi-core environment, it is desirable that referenced data RD referenced in a program PG executed by a certain processor core be allocated to the local memory of that certain processor core. In particular, the shorter the execution period EC of a program PG executed by a certain processor core, the more desirable it is that referenced data RD referenced in that program PG be allocated to the local memory of that certain processor core. Therefore, for a data block DB whose common execution period CEC is execution period EC(1), the allocation position determination unit 134 determines the local memory 11 of the "common core CC identified by the common core identification information ICC of that data block DB" as the allocation position. In other words, the allocation position determination unit 134 determines the allocation position of a data block DB whose common execution period CEC is execution period EC(1) to be the local memory 11 of the "common core CC identified by the common core identification unit 1342 for that data block DB." For example, the placement position determination unit 134 determines the placement position of a data block DB whose common execution period CEC is execution period EC(1) and whose common core CC is CPU core 10(0) to be local memory 11(0) of CPU core 10(0). After completing placement of all data block DBs whose common execution period CEC is execution period EC(1) in local memory 11 of the common core CC identified by the common core identification information ICC of each data block DB, the block placement unit 130 then performs memory placement processing for a data block DB whose common execution period CEC is execution period EC(2).

[0038] The placement position determination unit 134 determines a placement position for a data block DB whose common execution period CEC is execution period EC(2) through a first placement position determination process. In the first placement position determination process, the placement position determination unit 134 determines whether the data block DB can be placed in the local memory 11 included in the common core CC identified by the common core identification information ICC of the data block DB, using the determination result of the capacity determination unit 1346. If the capacity determination unit 1346 determines that "an overflow will not occur in the local memory 11 included in the common core CC," the placement position determination unit 134 determines the local memory 11 included in the common core CC as the placement position. If the capacity determination unit 1346 determines that "an overflow will occur in the local memory 11 included in the common core CC," the placement position determination unit 134 determines "a memory other than the local memory 11 included in the common core CC" as the placement position, such as the shared memory 12.

[0039] As described above, first, a data block DB having a common execution period CEC of EC(1) is placed in each local memory 11, with the CPU core 10 corresponding to that local memory 11 being the common core CC. Therefore, if an attempt is made to place a data block DB having a common execution period CEC of EC(2) in the local memory 11 provided with the common core CC identified by the common core identification information ICC of that data block DB, an overflow may occur. Therefore, the placement position determination unit 134 executes a first placement position determination process to determine the placement position of the data block DB having a common execution period CEC of EC(2) in a memory where an overflow will not occur. When the block placement unit 130 completes placement of all data block DBs whose common execution cycle CEC is execution cycle EC(2) in "local memory 11 provided in the common core CC identified by the common core identification information ICC of each data block DB" or in shared memory 12, it then performs memory placement processing for data block DBs whose common execution cycle CEC is execution cycle EC(3).

[0040] The placement position determination unit 134 determines the placement position of a data block DB whose common execution period CEC is execution period EC(3) through a second placement position determination process. In the second placement position determination process, the placement position determination unit 134 first determines whether the data block DB can be placed in the local memory 11 included in the common core CC identified by the common core identification information ICC of the data block DB, using the determination result of the capacity determination unit 1346. If the capacity determination unit 1346 determines that "an overflow will not occur in the local memory 11 included in the common core CC," the placement position determination unit 134 determines the local memory 11 included in the common core CC as the placement position. If the capacity determination unit 1346 determines that "an overflow will occur in the local memory 11 included in the common core CC," the placement position determination unit 134 then determines whether the data block DB can be placed in the shared memory 12, using the determination result of the capacity determination unit 1346. When the capacity determination unit 1346 determines that "an overflow will not occur in the shared memory 12," the placement position determination unit 134 determines the placement position to be the shared memory 12. When the capacity determination unit 1346 determines that "an overflow will occur in the shared memory 12," the placement position determination unit 134 determines the placement position to be the local memory 11 provided in a CPU core 10 other than the common core CC.

[0041] The placement position determination unit 134 may determine the placement position of the "local memory 11 provided in the CPU core 10 other than the common core CC" having the smallest placement number counter CT among multiple "local memories 11 provided in the CPU core 10 other than the common core CC." With this configuration, the block placement unit 130 can place a data block DB whose common execution period CEC is EC(3) in the "local memory 11 provided in the CPU core 10 other than the common core CC" having the smallest placement number counter CT, i.e., the "local memory 11 provided in the CPU core 10 other than the common core CC" having the largest free space. Therefore, the block placement unit 130 can easily and reliably prevent memory overflow caused by the data block DB. For example, the placement position determination unit 134 may determine the placement position of a data block DB determined to cause an overflow if placed in the local memory 11 provided in the common core CC, as follows: In other words, the placement position determination unit 134 may determine the placement position to be the memory with the smallest placement number counter CT among the shared memory 12 and "among the multiple local memories 11, the local memories 11 other than the local memories 11 provided in the common core CC."

[0042] The counting unit 136 counts up the number of data block DBs (arrangement number counter CT) arranged by the block arrangement unit 130 for each of the shared memory 12 and the multiple local memories 11. For example, for each of the shared memory 12 and the multiple local memories 11, the counting unit 136 counts up the arrangement number counter CT by "1" each time each of the multiple data block DBs is arranged in either the shared memory 12 or the multiple local memories 11.

[0043] As described above, in the electronic control device 1 (particularly, the placement process execution core PPC), the block acquisition unit 120 acquires multiple data block DBs. The block placement unit 130 places the multiple data block DBs acquired by the block acquisition unit 120 in either the shared memory 12 or multiple local memories 11 in descending order of common execution period CEC, which is identified by common execution period information ICE included in each data block DB. In particular, the block placement unit 130 places the multiple data block DBs in the local memory 11 included in the common core CC identified by the common core identification information ICC of each data block DB in descending order of common execution period CEC, within a range that does not exceed the data size that can be stored in the local memory 11. For the multiple data block DBs that cannot be placed in the local memory 11 included in the common core CC, the block placement unit 130 places the data block DBs in either the shared memory 12 or "the local memory 11 included in the CPU core 10 other than the common core CC, among the multiple local memories 11."

[0044] 4A is a table showing an example of the common core CC and common execution period CEC identified by the tag information TI of each data block DB for multiple (eight in the illustrated example) data block DBs. FIG. 4B shows the state of each local memory 11 and shared memory 12 after the placement process execution core PPC (particularly the block placement unit 130) has placed each of the multiple data block DBs shown in FIG. 4A. In FIG. 4A, the common core CC identified by the tag information TI of data block DB (1) of block No. 1, data block DB (4) of block No. 4, data block DB (5) of block No. 5, and data block DB (6) of block No. 6 is all "CPU core 10(0)." The common core CC identified by the tag information TI of data block DB (2) of block No. 2 and data block DB (3) of block No. 3 is "CPU core 10(1)." The common core CC identified by the tag information TI of data block DB(7) of block No. 7 is "CPU core 10(1)." The common core CC identified by the tag information TI of data block DB(3) of block No. 3 and data block DB(8) of block No. 8 is "CPU core 10(2)." Furthermore, the common execution cycle CEC of data block DB(5) is slower than the common execution cycles CEC of data blocks DB(1), DB(4), and DB(6), specifically, the execution cycle CEC(3) (execution cycle (low)). The block allocation unit 130 executes the above-described memory allocation process for each of data blocks DB(1) to DB(8), and thereby allocates the data block DBs shown in FIG. 4B in each local memory 11 and shared memory 12.

[0045] As described above, the block allocation unit 130 allocates multiple data blocks DB in the local memory 11 provided in the common core CC in descending order of common execution period CEC, without exceeding the data size that can be stored in the local memory 11. Therefore, the block allocation unit 130 allocates data blocks DB(1), DB(4), DB(5), and DB(6), all of which have the common core CC "CPU core 10(0)," in the following order in the local memory 11(0), without exceeding the data size that can be stored in the local memory 11(0). In other words, the block allocation unit 130 allocates data blocks DB(1), DB(6), DB(4), and DB(5) in the local memory 11(0) in this order. As a result, data block DB(5) cannot be allocated to local memory 11(0) (if allocated, local memory 11(0) will overflow), so the block allocation unit 130 allocates data block DB(5) to either the shared memory 12 or "one of the multiple local memories 11 other than local memory 11(0)." In the example shown in Figure 4(B), the block allocation unit 130 allocates data block DB(5) to the shared memory 12.

[0046] Therefore, the block placement unit 130 can place the referenced data RD referenced in a program PG executed by a certain CPU core 10 among the multiple CPU cores 10 in the local memory 11 of that CPU core 10, within a range not exceeding the data size that can be stored in that local memory 11. In particular, the shorter the execution period EC of a program PG executed by a certain CPU core 10, the more preferentially the block placement unit 130 can place the referenced data RD referenced in that program PG in the local memory 11 of that CPU core 10. By controlling the placement position of the referenced data RD (particularly the data block DB) as described above, the block placement unit 130 can reduce the processing load on the CPU core 10 (processor core) that executes the program PG in a multi-core environment.

[0047] (Considerations on Tag Information TI (Additional Information)) The placement process execution core PPC described above uses the common core identification information ICC and common execution cycle information ICE included in the tag information TI of each data block DB to place each data block DB in either the shared memory 12 or the multiple local memories 11. For example, the placement process execution core PPC places multiple data block DBs in the local memory 11 of the common core CC identified by the common core identification information ICC of each data block DB in order of earliest common execution cycle CEC identified by the common execution cycle information ICE of each data block DB, within a range not exceeding the data size that can be stored in the local memory 11. However, the tag information TI may include additional information in addition to the common core identification information ICC and the common execution cycle information ICE. The placement process execution core PPC may use the additional information in addition to the common core identification information ICC and the common execution cycle information ICE to place each data block DB in the shared memory 12 or the multiple local memories 11. An example of additional information included in the tag information TI will be described below.

[0048] (Example 1 of Additional Information—Safety Level Information) As described above, the electronic control unit 1 is realized, for example, as a microcomputer included in the ECU of the vehicle VH. Therefore, each of the multiple CPU cores 10 of the electronic control unit 1 may be pre-classified as an ASIL core that satisfies any of the Automotive Safety Integrity Levels (ASIL) ASIL-D to ASIL-A defined by the ISO 26262 standard in functional safety activities, or as a Quality Management (QM) core that does not satisfy ASIL-A. For example, in the example shown in FIG. 5A , the electronic control unit 1 includes four CPU cores 10 (CPU cores 10(0), 10(1), 10(2), and 10(3)), and each CPU core 10 is classified as an ASIL core or a QM core as follows: That is, the CPU core 10(0) and the CPU core 10(1) are each classified as an ASIL core, and the CPU core 10(2) and the CPU core 10(3) are each classified as a QM core.

[0049] Since each of the multiple CPU cores 10 included in the electronic control device 1 is classified as an ASIL core or a QM core, the tag information TI may include, as additional information, safety level information ISL indicating whether the common core CC is classified as an ASIL core or a QM core. For example, FIG. 5B shows an example of tag information TI implemented as 8-bit information, similar to FIG. 2B. In the illustrated example, bits 0 to 2 represent common execution cycle information ICE, and each bit indicates, for each of the multiple execution cycles EC, whether it is a common execution cycle CEC (1) or not a common execution cycle CEC (0). Furthermore, bits 3 to 6 represent common core identification information ICC, and each bit indicates, for each of the multiple CPU cores 10, whether it is a common core CC (1) or not a common core CC (0). The seventh bit is safety level information ISL, and for example, a value of "1" indicates that the common core CC is classified as an ASIL core, and a value of "0" indicates that the common core CC is classified as a QM core. Explaining this based on the example shown in FIG. 5A, in the tag information TI of the data block DB in which the common core CC is CPU core 10(0) or CPU core 10(1), the safety level information ISL (the seventh bit in the example shown in FIG. 5B) is "1." In the tag information TI of the data block DB in which the common core CC is CPU core 10(2) or CPU core 10(3), the safety level information ISL is "0."

[0050] When the tag information TI includes safety level information ISL, the placement processing execution core PPC (e.g., the block placement unit 130) may use the safety level information ISL to control the placement position of each data block DB as follows. That is, the block placement unit 130 may not place, among the multiple data block DBs, a data block DB for which the safety level information ISL indicates that the common core CC is classified as an ASIL core, in a memory, among the shared memory 12 and the multiple local memories 11, in which a data block DB for which the safety level information ISL indicates that the common core CC is classified as a QM core is placed. The block placement unit 130 may not place, among the multiple data block DBs, a data block DB for which the safety level information ISL indicates that the common core CC is classified as a QM core, in a memory, among the shared memory 12 and the multiple local memories 11, in which a data block DB for which the safety level information ISL indicates that the common core CC is classified as an ASIL core is placed.

[0051] That is, the block allocating unit 130 may prevent the referenced data RD referenced by the CPU core 10 classified as an ASIL core from being allocated to the local memory 11 of the CPU core 10 classified as a QM core, and may also prevent the referenced data RD referenced by the CPU core 10 classified as a QM core from being allocated to the local memory 11 of the CPU core 10 classified as an ASIL core. In other words, the block allocating unit 130 may control the allocation position of the referenced data RD (particularly the data block DB) so as to prevent the CPU core 10 classified as an ASIL core from accessing the local memory 11 of the CPU core 10 classified as a QM core, and to prevent the CPU core 10 classified as a QM core from accessing the local memory 11 of the CPU core 10 classified as an ASIL core.

[0052] 5A , for example, when a certain data block DB is to be stored in a local memory 11 other than the local memory 11 included in the “common core CC identified by the tag information TI of the block DB,” the block allocation unit 130 executes the following process. That is, when the common core CC is classified as an ASIL core (that is, the common core CC is CPU core 10(0) or CPU core 10(1)), the block allocation unit 130 stores the certain data block DB in the local memory 11(1) or local memory 11(0), and does not store the certain data block DB in either the local memory 11(2) or local memory 11(3) included in the CPU core 10(2) or CPU core 10(3), which are classified as QM cores. Furthermore, if the common core CC is classified as a QM core (that is, the common core CC is CPU core 10(2) or CPU core 10(3)), the block placement unit 130 stores the data block DB in local memory 11(3) or local memory 11(2), and does not store the data block DB in either local memory 11(0) or local memory 11(1) of CPU core 10(0) or CPU core 10(1), which are classified as ASIL cores. Through this control, the placement processing execution core PPC can place the referenced data RD (particularly the data block DB) in the shared memory 12 or one of the multiple local memories 11 so as to satisfy the requirements of the functional safety activities (functional safety requirements) described above.

[0053] For example, the block placement unit 130 (particularly, the placement position determination unit 134) may include a "safety level identification unit that identifies whether the common core CC is classified as an ASIL core or a QM core by referring to the tag information TI (particularly, the safety level information ISL) of each data block DB" (not shown). The block placement unit 130 may use the identification result by the safety level identification unit to place each data block DB in the shared memory 12 or one of the multiple local memories 11.

[0054] (Example 2 of Additional Information - Valid Region Information) The ECU software (program PG) complies with different standards depending on the region RG. For example, the standard complies with different standards depending on the region RG in which a vehicle VH equipped with the ECU is sold (where the vehicle VH is driven). However, for various reasons, software having all functions may be prepared in advance, and each function (software) may be enabled or disabled by rewriting the configuration information depending on the destination (region RG), such as the sales region of the vehicle VH. In other words, the validity or invalidity of each of the various programs PG executed by any of the multiple CPU cores 10 is predetermined for each region RG, in other words, whether or not the program PG is executed. Note that the region RG is not limited to a "country," but may be a "state" or "region," etc., as long as the program PG complies with the same standard.

[0055] 6A is a table showing an example of multiple programs PG that are enabled (executed) or disabled (not executed) for each region RG. In the example shown in FIG. 6A, all of the prepared programs PG(A), PG(B), PG(C), and PG(D) are enabled in the United States (region RG(US)), meaning that all of these programs PG are executed in the United States. However, in Japan (region RG(JPN)), programs PG(A) and PG(C) are enabled (executed), but programs PG(B) and PG(D) are disabled (not executed).

[0056] Whether or not a program PG that references referenced data RD is executed is predefined for each region RG. Accordingly, the data block DB may accumulate the following "one or more referenced data RD." That is, the data block DB may accumulate "one or more referenced data RD" that each satisfy at least one of the following conditions: "referenced in a program PG executed in a common region RG (e.g., region RG(X))" and "referenced in a program PG that is not executed in another common region RG (e.g., region RG(Y))." That is, the "one or more referenced data RD" accumulated in the data block DB may satisfy at least one of the following conditions: "executed in a common region RG" and "not executed in another common region RG." In the above-mentioned condition, the "common region RG (in which various programs PG that reference each of the "one or more referenced data RD" are executed)" is referred to as the "common execution region CRA" in this embodiment. For example, the block generation unit 110 may generate one or more data block DBs "in which the same CPU core 10 is the common core CC, the same execution cycle EC is the common execution cycle CEC, and the region RG(X) is the common execution region CRA" from a group of "referenced data RD referenced in a program PG executed in a region RG(X) by the same CPU core 10 with the same execution cycle EC" among a plurality of referenced data RDs. As an example, the block generation unit 110 may generate one or more data block DBs "in which the CPU core 10(0) is the common core CC, the execution cycle EC(1) is the common execution cycle CEC, and Japan is the common execution region CRA" from a group of "referenced data RD referenced in a program PG executed in Japan by the CPU core 10(0) with the execution cycle EC(1)" among a plurality of referenced data RDs.The block generation unit 110 may generate one or more "data block DBs in which the CPU core 10(0) is the common core CC, the execution period EC(1) is the common execution period CEC, and Japan is the common execution region CRA" from a group of "referenced data RDs that are all referenced in a program PG that is executed in Japan by the CPU core 10(0) with an execution period EC(1) and is not executed in the United States" among the multiple referenced data RDs.

[0057] Furthermore, in accordance with the fact that whether or not a program PG that references referenced data RD is executed is specified in advance for each region RG, tag information TI may include valid region information IVA as additional information. The valid region information IVA indicates the "region RG" (i.e., the common execution region CRA) in which a program PG that references each of "one or more referenced data RD" accumulated in the data block DB is "executed." In particular, the valid region information IVA according to this embodiment indicates, for each region RG, whether or not a program PG that references each of "one or more referenced data RD" accumulated in the data block DB is executed.

[0058] 6B shows an example of tag information TI that includes valid region information IVA in addition to common core identification information ICC and common execution cycle information ICE. For example, FIG. 6B shows an example of tag information TI implemented as 8-bit information, similar to FIG. 2B. In the illustrated example, bits 0 to 2 represent common execution cycle information ICE, and bits 3 to 5 represent common core identification information ICC. Bits 6 to 7 represent valid region information IVA, and each bit indicates, for each of multiple regions RG, whether a program PG that references one or more referenced data RD accumulated in the data block DB is an "executed region RG" (1) or a "non-executed region RG" (0). For example, if a program PG that references each of the "one or more referenced data RD" accumulated in the data block DB is valid (executed) in the United States (region RG(US)), a "1" is stored in the sixth bit, and if it is invalid (not executed) in the United States, a "0" is stored in the sixth bit. Similarly, if a program PG that references each of the "one or more referenced data RD" accumulated in the data block DB is valid (executed) in Japan (region RG(JPN)), a "1" is stored in the seventh bit, and if it is invalid (not executed) in Japan, a "0" is stored in the seventh bit.

[0059] If the tag information TI includes valid region information IVA, the allocation processing execution core PPC may use the valid region information IVA to control the allocation position of each data block DB. For example, the allocation processing execution core PPC may include a destination information acquisition unit (not shown), which may acquire destination information 31 by referring to the non-volatile memory 3. The block allocation unit 130 may then use the region RG indicated by the destination information 31 acquired by the destination information acquisition unit to determine whether to allocate each data block DB in memory (either the shared memory 12 or one of the multiple local memories 11) or not. That is, if the valid region information IVA of a data block DB indicates that "the program PG that references each of the 'one or more referenced data RD' is executed in the region RG indicated by the destination information 31," the block allocation unit 130 may allocate the data block DB in memory. If the valid region information IVA of a data block DB indicates that "a program PG that references each of the one or more referenced data RDs will not be executed in the region RG indicated by the destination information 31," the block allocation unit 130 may not allocate the data block DB in memory. In other words, the block allocation unit 130 may allocate, among multiple data block DBs, only the data block DBs whose valid region information IVA indicates that "a program PG that references each of the one or more referenced data RDs included in the data block DB will be executed in the region RG indicated by the destination information 31."

[0060] The placement process execution core PPC may execute the above-described process using the valid region information IVA when the destination information 31 in the non-volatile memory 3 is updated (rewritten) by the tool 2. That is, when the region RG indicated by the destination information 31 is changed, the placement process execution core PPC may determine whether to place each data block DB in memory based on the "changed region RG." Specifically, when the valid region information IVA of a data block DB indicates that "a program PG that references each of the 'one or more referenced data RD' will be executed in the changed region RG," the placement process execution core PPC may place the data block DB in memory. When the valid region information IVA of a data block DB indicates that "a program PG that references each of the 'one or more referenced data RD' will not be executed in the changed region RG," the placement process execution core PPC may not place the data block DB in memory. As described above, the tool 2 writes the destination information 31 to the non-volatile memory 3 via the CPU core 10 of the electronic control unit 1, so that the electronic control unit 1 can recognize that the destination information 31 has been updated. Therefore, the placement processing execution core PPC of the electronic control unit 1 may execute the above-described processing based on the changed region RG, for example, when the electronic control unit 1 is started for the first time after the destination information 31 has been updated (for example, when the ignition power of the vehicle VH equipped with the electronic control unit 1 (ECU) is turned on for the first time).

[0061] 7A is a table showing an example of the common core CC, common execution cycle CEC, and common execution area CRA (config) identified by the tag information TI of each data block DB for multiple (eight in the illustrated example) data block DBs. Figure 7B shows the state of each local memory 11 and shared memory 12 after the placement processing execution core PPC (particularly, the block placement unit 130) places each of the multiple data block DBs shown in Figure 7A. In Figure 7A, the config (common execution area CRA) represents a combination of "0 or 1" stored in the sixth and seventh bits of the tag information TI shown in Figure 6B. For example, the common execution region CRA of data blocks DB(1), DB(2), DB(5), and DB(8) is "11," indicating that a "1" is stored in the seventh bit and a "1" is stored in the sixth bit of the tag information TI illustrated in FIG. 6B. In other words, a common execution region CRA of "11" indicates that both Japan and the United States are common execution region CRAs. Therefore, a program PG that references each of the "one or more referenced data RD" accumulated in a data block DB with a common execution region CRA of "11" is executed in both Japan and the United States. The common execution region CRA of data blocks DB(3), DB(4), and DB(7) is "01," indicating that a "0" is stored in the seventh bit and a "1" is stored in the sixth bit of the tag information TI illustrated in FIG. 6B. In other words, a common execution region CRA of "01" indicates that the United States is a common execution region CRA and Japan is not a common execution region CRA. Therefore, a program PG that references each of "one or more referenced data RD" accumulated in a data block DB with a common execution region CRA of "01" is not executed in Japan, but is executed in the United States. The common execution region CRA of "10" in data block DB(6) indicates that a "1" is stored in the seventh bit and a "0" is stored in the sixth bit of the tag information TI illustrated in Figure 6(B). In other words, the common execution region CRA of "10" indicates that Japan is a common execution region CRA, but the United States is not a common execution region CRA.Therefore, a program PG that references each of the "one or more referenced data RD" accumulated in a data block DB whose common execution area CRA is "10" is executed in Japan but not in the United States.

[0062] For example, when the destination information 31 is updated to "Japan," the placement processing execution core PPC places only the following data block DBs in memory (the shared memory 12 and any of the multiple local memories 11) out of the eight data block DBs illustrated in FIG. 7A. That is, the placement processing execution core PPC places only the data block DBs whose common execution region CRA indicates that "the program PG that references each of the one or more referenced data RDs is executed in Japan." In other words, the placement processing execution core PPC places only the data block DBs whose common execution region CRA is Japan in memory. The placement processing execution core PPC places only the data block DBs whose common execution region CRA (config) is "11" or "10" out of the eight data block DBs illustrated in FIG. 7A in the shared memory 12 or any of the multiple local memories 11. Specifically, the placement process execution core PPC places only the data blocks DB(1), DB(2), DB(5), DB(6), and DB(8) in the shared memory 12 and one of the multiple local memories 11. The placement process execution core PPC places the data blocks DB(1), DB(2), DB(5), DB(6), and DB(8) in the local memory 11 provided in the common core CC of each data block DB in order of the earliest common execution period CEC, without exceeding the data size that can be stored in the local memory 11. Of the eight data block DBs illustrated in (A) of Figure 7, the placement process execution core PPC does not place the data blocks DB(3), DB(4), and DB(7) in memory for which the common execution area CRA (config) is "01". In other words, when the destination information 31 is updated to "Japan", the placement processing execution core PPC does not place in memory the data block DB which is made up of an accumulation of "one or more referenced data RD" which is referenced in the program PG which is executed only in the United States.

[0063] As described above, the allocation process execution core PPC does not allocate, for each region RG, referenced data RD referenced in an invalid (non-executed) program PG in memory. By performing this process, the allocation process execution core PPC can reduce memory consumption (the shared memory 12 and each of the multiple local memories 11), for example, to the minimum necessary.

[0064] For example, the block placement unit 130 (particularly, the placement position determination unit 134) may include an "execution region identification unit that identifies a common execution region CRA by referencing the tag information TI (particularly, the valid region information IVA) of each data block DB" (not shown). The block placement unit 130 may use the results of the identification by the execution region identification unit and the region RG indicated by the destination information 31 to determine whether or not to place each data block DB in memory. For example, the block placement unit 130 places, among multiple data block DBs, only data block DBs whose common execution region CRA is the "region RG indicated by the destination information 31" in memory.

[0065] §3 Operation Example (Overall Overview) Figure 8 is a flowchart illustrating an example of the processing procedure of the electronic control device 1 (particularly, the placement processing execution core PPC) according to this embodiment. The processing procedure described below is an example of the processing procedure of an information processing method PM that causes the placement processing execution core PPC (e.g., CPU core 10(0)) to execute the process of "placing each of the multiple referenced data RD in the shared memory 12 or one of the multiple local memories 11." However, the processing procedure described below is merely an example, and each step may be modified as much as possible. Furthermore, steps may be omitted, replaced, or added to the processing procedure described below as appropriate depending on the embodiment.

[0066] (Steps S110 and S120) In step S110, the placement processing execution core PPC operates as the block placement unit 130 (particularly, the counting unit 136) and clears to "0" the placement number counters CT for the shared memory 12 and the multiple local memories 11. In step S120, the placement processing execution core PPC operates as the block acquisition unit 120 and acquires a data block DB, for example, acquires multiple data block DBs.

[0067] (Step S130) In step S130, the placement process execution core PPC operates as the block placement unit 130 (particularly, the block sort unit 132) and arranges the multiple data block DBs acquired in step S120 in order of earliest common execution period CEC. For example, the placement process execution core PPC references the common execution period information ICE included in each data block DB and identifies the common execution period CEC for each data block DB from the common execution period information ICE. Based on the identified common execution period CEC of each data block DB, the placement process execution core PPC arranges the multiple data block DBs in order of earliest common execution period CEC.

[0068] (Step S140) In step S140, the placement process execution core PPC operates as the block placement unit 130 and sequentially executes data block placement processing on the multiple data block DBs arranged in step S130 in descending order of common execution cycle CEC. In the data block placement processing, the placement process execution core PPC places the data block DBs in memory (the shared memory 12 or any of the multiple local memories 11) based on the tag information TI of the data block DBs. The placement process execution core PPC places the multiple data block DBs in memory in descending order of common execution cycle CEC based on the tag information TI of each data block DB.

[0069] (Step S150) In step S150, the placement process execution core PPC operates as the block placement unit 130 and determines whether placement of all data block DBs is complete, that is, whether data block placement processing has been executed for all data block DBs. If it determines that placement of all data block DBs is complete (Yes in step S150), the placement process execution core PPC terminates processing. If it determines that placement of all data block DBs is not complete (No in step S150), the placement process execution core PPC returns to step S140 and executes data block placement processing for data block DBs for which data block placement processing has not been executed. An example of the details of the processing procedure for the data block placement processing (step S140) will be further described below with reference to FIG. 9.

[0070] (Detailed Example of Data Block Placement Processing) (Steps S1410 and S1420) In step S1410, the placement processing execution core PPC operates as the common core identification unit 1342 and identifies the common core CC by referring to the common core identification information ICC in the data block DB. In step S1420, the placement processing execution core PPC operates as the common execution period identification unit 1344 and identifies the common execution period CEC by referring to the common execution period information ICE in the data block DB.

[0071] (Step S1430) In step S1430, the placement process execution core PPC operates as the block placement unit 130 and determines which of the multiple types of execution periods EC the common execution period CEC identified in step S1420 is. In this embodiment, the placement process execution core PPC determines whether the common execution period CEC is execution period EC(1), execution period EC(2), or execution period EC(3). If it determines that the common execution period CEC is execution period EC(1), the placement process execution core PPC proceeds to step S1440. If it determines that the common execution period CEC is execution period EC(2), the placement process execution core PPC proceeds to step S1460. If it determines that the common execution period CEC is execution period EC(3), the placement process execution core PPC proceeds to step S1480.

[0072] (Steps S1440 and S1450) In step S1440, the placement process execution core PPC operates as the block placement unit 130 and places the data block DB whose common execution period CEC is execution period EC(1) in the local memory 11 provided in the common core CC identified for the data block DB in step S1410. In step S1450, the placement process execution core PPC operates as the counting unit 136 and counts up by "1" the placement number counter CT of the memory (local memory 11 provided in the common core CC) in which the data block DB was placed in step S1440.

[0073] (Step S1460) In step S1460, the placement processing execution core PPC operates as the block placement unit 130 and determines placement positions for data block DBs whose common execution period CEC is execution period EC(2) by a first placement position determination process. The placement processing execution core PPC places the data block DBs whose common execution period CEC is execution period EC(2) at the placement positions determined by the first placement position determination process.

[0074] In the first placement position determination process, the placement process execution core PPC determines whether the data block DB can be placed in the local memory 11 included in the common core CC identified for the data block DB in step S1410. Specifically, the placement process execution core PPC determines whether an overflow will occur in the local memory 11 included in the common core CC if the data block DB is placed in the local memory 11 included in the common core CC. If it determines that an overflow will not occur, the placement process execution core PPC determines the local memory 11 included in the common core CC as the placement position. If it determines that an overflow will occur, the placement process execution core PPC determines a memory other than the local memory 11 included in the common core CC as the placement position, such as the shared memory 12.

[0075] (Step S1470) In step S1470, the placement process execution core PPC operates as the counting unit 136 and counts up by "1" the placement number counter CT of the memory into which the data block DB was placed in step S1460.

[0076] (Step S1480) In step S1480, the placement processing execution core PPC operates as the block placement unit 130 and determines placement positions for data block DBs whose common execution period CEC is execution period EC(3) by using a second placement position determination process. The placement processing execution core PPC places the data block DBs whose common execution period CEC is execution period EC(3) at the placement positions determined by the second placement position determination process.

[0077] In the second placement position determination process, the placement process execution core PPC first determines whether the data block DB can be placed in the local memory 11 included in the common core CC identified for the data block DB in step S1410. Specifically, the placement process execution core PPC determines whether an overflow will occur in the local memory 11 if the data block DB is placed in the local memory 11 included in the common core CC. If it determines that an overflow will not occur, the placement process execution core PPC determines whether the data block DB can be placed in the shared memory 12. Specifically, the placement process execution core PPC determines whether an overflow will occur in the shared memory 12 if the data block DB is placed in the shared memory 12. If it determines that an overflow will not occur, the placement process execution core PPC determines the shared memory 12 as the placement position. When it is determined that "an overflow will occur," the placement process execution core PPC determines the local memory 11 provided in the CPU core 10 other than the common core CC as the placement location.

[0078] (Step S1490) In step S1490, the placement process execution core PPC operates as the counting unit 136 and counts up by "1" the placement number counter CT of the memory into which the data block DB was placed in step S1480.

[0079] 8 and 9, the placement process execution core PPC places multiple data block DBs in the local memory 11 provided in the common core CC in descending order of common execution cycle CEC, without exceeding the data size that can be stored in the local memory 11. Then, the placement process execution core PPC places, of the multiple data block DBs, any data block DB that cannot be placed in the local memory 11 provided in the common core CC in either the shared memory 12 or "the local memory 11 provided in a CPU core 10 other than the common core CC, of ​​the multiple local memories 11."

[0080] The placement process execution core PPC may determine the placement position of a data block DB that cannot be placed in the local memory 11 provided in the common core CC, among the multiple data block DBs, by using the placement number counter CT of each memory. That is, the placement process execution core PPC may place the data block DB that cannot be placed in the local memory 11 provided in the common core CC in the memory with the smallest placement number counter CT. For example, in the second placement position determination process, the placement process execution core PPC may place the data block DB in the "local memory 11 provided in the CPU core 10 other than the common core CC" with the smallest placement number counter CT, among the multiple "local memories 11 provided in the CPU cores 10 other than the common core CC."

[0081] As described above, the tag information TI of each data block DB may include additional information in addition to the common core identification information ICC and the common execution period information ICE, and the placement processing execution core PPC may use such additional information in the data block placement processing.

[0082] For example, each of the multiple CPU cores 10 may be pre-classified as an ASIL core or a QM core. The tag information TI may include, as additional information, safety level information ISL indicating whether the common core CC is classified as an ASIL core or a QM core. The placement processing execution core PPC may not allocate, among the multiple data block DBs, a data block DB for which the safety level information ISL indicates that the common core CC is classified as an ASIL core, in a memory, among the shared memory 12 and the multiple local memories 11, in which a data block DB for which the safety level information ISL indicates that the common core CC is classified as a QM core is allocated. The placement processing execution core PPC may not allocate, among the multiple data block DBs, a data block DB for which the safety level information ISL indicates that the common core CC is classified as an ASIL core, in a memory, among the shared memory 12 and the multiple local memories 11, in which a data block DB for which the safety level information ISL indicates that the common core CC is classified as an ASIL core is allocated.

[0083] For example, whether a program PG that references referenced data RD is executed may be specified in advance for each region RG. Accordingly, the data block DB may be configured so that the "one or more referenced data RD" accumulated in the data block DB further satisfies the following condition. That is, the data block DB may be configured so that the "one or more referenced data RD accumulated in the data block DB" satisfy at least one of the following conditions: "The programs PG that reference each of the one or more referenced data RD are executed in a common region RG (e.g., region RG(X))" and "They are not executed in another common region RG (e.g., region RG(Y))." The data block DB may, for example, accumulate "one or more referenced data RD that are each referenced in a program PG executed in region RG(X) by the same CPU core 10 at the same execution period EC." The tag information TI may include, as additional information, valid region information IVA indicating, for each region RG, whether a program PG referencing each of "one or more referenced data RD" accumulated in the data block DB will be executed. When the region RG is changed, the allocation processing execution core PPC may allocate, in memory (the shared memory 12 or any of the multiple local memories 11), a data block DB whose valid region information IVA indicates that "a program PG referencing each of "one or more referenced data RD" will be executed in the changed region." When the region RG is changed, the allocation processing execution core PPC may not allocate, in memory, a data block DB whose valid region information IVA indicates that "a program PG referencing each of "one or more referenced data RD" will not be executed in the changed region."

[0084] The placement process execution core PPC may generate the data block DB acquired in step S120, or may generate one or more data block DBs from multiple referenced data RD. For example, the placement process execution core PPC may first extract a group of "referenced data RD referenced in a program PG executed by the same CPU core 10 in the same execution cycle EC" from the multiple referenced data RD. The placement process execution core PPC may accumulate "one or more referenced data RD" included in the extracted group so that the accumulated data does not exceed the reference data size SS, and may generate the data block DB by adding tag information TI that can identify the same CPU core 10 and the same execution cycle EC.

[0085] [Features] As described above, the electronic control device 1 according to this embodiment includes a plurality of CPU cores 10, each of which can communicate with the shared memory 12 and each of which has a local memory 11. In the electronic control device 1, the plurality of CPU cores 10 are connected to each other.

[0086] The electronic control device 1 includes a block acquisition unit 120 that acquires a data block DB, and a block allocation unit 130 that allocates the data block DB acquired by the block acquisition unit 120 in one of the shared memory 12 and multiple local memories 11 based on tag information TI (additional information) included in the data block DB. The data block DB is configured by accumulating one or more referenced data RD so that the data size does not exceed a standard data size SS. The referenced data RD is referenced in a program PG executed by one of multiple CPU cores 10 of the electronic control device 1. The program PG that references each of the one or more referenced data RD included in the data block DB is executed by the same CPU core 10 among the multiple CPU cores 10 and at the same execution cycle EC. The tag information TI includes common core identification information ICC and common execution cycle information ICE. The common core identification information ICC identifies, as a common core CC, the "same CPU core 10" that executes the program PG that references each of the one or more referenced data RD included in the data block DB. The common execution cycle information ICE specifies, as a common execution cycle CEC, the "same execution cycle EC" of the programs PG that reference each of one or more pieces of referenced data RD included in the data block DB.

[0087] The information processing method PM according to this embodiment causes at least one of a plurality of CPU cores 10 (a placement processing execution core PPC) to execute a process of placing each of a plurality of referenced data RD in either a shared memory 12 or a plurality of local memories 11 in a multi-core environment (e.g., an electronic control unit 1). In the multi-core environment, the plurality of CPU cores 10, each of which can communicate with the shared memory 12 and each of which has a local memory 11, are interconnected. The information processing method PM causes the placement processing execution core PPC to execute steps S120 and S140 illustrated in FIG. 8 . In step S120, the placement processing execution core PPC acquires a data block DB. In step S140, the placement processing execution core PPC allocates the data block DB acquired in step S120 in either the shared memory 12 or a plurality of local memories 11 based on tag information TI included in the data block DB.

[0088] The electronic control unit 1 (information processing method PM) handles the referenced data RD in units of data block DBs each consisting of an accumulation of "one or more referenced data RD." Therefore, the electronic control unit 1 (information processing method PM) can efficiently handle "one or more referenced data RD" collectively, using data block DBs each consisting of an accumulation of "one or more referenced data RD" that are all referenced by the same common core CC with the same common execution cycle CEC. The electronic control unit 1 (information processing method PM) can collectively allocate "multiple referenced data RD" that are all referenced by the same common core CC with the same common execution cycle CEC" to either the shared memory 12 or one of the multiple local memories 11.

[0089] In particular, the electronic control unit 1 (information processing method PM) allocates the data block DB in either the shared memory 12 or the multiple local memories 11 based on tag information TI that can identify the common core CC and the common execution cycle CEC. Therefore, the electronic control unit 1 (information processing method PM) can reduce the processing load on the common core CC, for example, by allocating the data block DB in the local memory 11 of the common core CC indicated by the tag information TI. By using the tag information TI, the electronic control unit 1 (information processing method PM) can allocate "one or more referenced data RD referenced by the same common core CC with the same common execution cycle CEC" in an appropriate memory, for example, in a memory that can reduce the processing load on the common core CC.

[0090] §4 Modifications Although the embodiments of the present invention have been described above in detail, the above description is merely an example of the present invention in every respect. It goes without saying that various improvements and modifications can be made without departing from the scope of the present invention. For example, the following modifications are possible. Note that, in the following, the same reference numerals are used for components similar to those in the above embodiment, and descriptions of similar points to those in the above embodiment are omitted where appropriate. The following modifications can be combined as appropriate.

[0091] 1...Electronic control device, 10...CPU core (processor core), 11...Local memory, 12...Shared memory, 120...Block acquisition unit, 130...Block placement unit, CC...Common core, CEC...Common execution cycle, DB...Data block, EC...Execution cycle, ICC...Common core identification information, ICE...Common execution cycle information, ISL...Safety level information, IVA...Valid area information, PG...Program, PM...Information processing method, RD...Referenced data, RG...Area, SS...Reference data size, TI...Tag information (additional information)

Claims

1. An information processing method in a multi-core environment in which multiple processor cores are interconnected, each capable of communicating with a shared memory and each equipped with a local memory, and which causes at least one of the multiple processor cores to execute a process of placing each of multiple referenced data, which is data referenced in a program executed by one of the multiple processor cores, in the shared memory or one of the multiple local memories, wherein at least one of the multiple processor cores executes the following steps: acquiring a data block formed by accumulating one or more of the multiple referenced data so that the size does not exceed a standard data size, and a program that references each of the one or more referenced data included in the data block is executed by the same processor core among the multiple processor cores and with the same execution cycle, and the data block includes, as additional information, common core identification information that identifies the same processor core as a common core and common execution cycle information that identifies the same execution cycle as a common execution cycle; and placing the data block in the shared memory or one of the multiple local memories based on the additional information.

2. The information processing method of claim 1, wherein at least one of the multiple processor cores acquires the multiple data blocks in the acquiring step, and at least one of the multiple processor cores allocates the multiple data blocks acquired in the acquiring step in the shared memory and the local memory of the common core identified by the common core identification information from among the multiple local memories in order of earliest common execution period identified by the common execution period information, within a range not exceeding the data size that can be stored in the local memory of the common core, and allocates any of the multiple data blocks that cannot be allocated to the local memory of the common core in the shared memory or one of the multiple local memories that is provided to a processor core other than the common core.

3. The information processing method of claim 2, wherein in the placing step, at least one of the multiple processor cores counts up the number of data blocks to be placed in each of the shared memory and the multiple local memories each time each of the multiple data blocks is placed in either the shared memory or the multiple local memories, and places, among the multiple data blocks, a data block that cannot be placed in the local memory provided by the common core in the shared memory and, among the multiple local memories other than the local memory provided by the common core, the memory with the smallest counted-up number.

4. Each of the plurality of processor cores is pre-classified as either an ASIL core that satisfies any one of the Automotive Safety Integrity Levels (ASIL) ASIL-D to ASIL-A defined in the ISO 26262 standard in functional safety activities, or a QM (Quality Management) core that does not satisfy ASIL-A, and the additional information further includes safety level information indicating whether the common core is classified as the ASIL core or the QM core, and in the placing step, at least one of the plurality of processor cores does not place, among the plurality of data blocks, a data block for which the safety level information indicates that the common core is classified as the ASIL core in the shared memory or the plurality of local memories in which a data block for which the safety level information indicates that the common core is classified as the QM core is placed, and 4. The information processing method according to claim 2 or 3, wherein a data block for which the safety level information indicates that the common core is classified as the QM core is not placed in the shared memory or the plurality of local memories in which a data block for which the safety level information indicates that the common core is classified as the ASIL core is placed.

5. The information processing method of claim 1 or 2, wherein whether or not the program is to be executed is predetermined for each region, and the one or more referenced data accumulated in the data block satisfy at least one of the conditions that the programs referencing each of them are to be executed in a common region and that they are not to be executed in another common region, and the additional information includes valid region information indicating, for each region, whether or not the programs referencing each of the one or more referenced data accumulated in the data block will be executed, and when the region is changed, in the placing step, at least one of the multiple processor cores: places the data block in either the shared memory or the multiple local memories if the valid region information of the data block indicates that the programs referencing each of the one or more referenced data will be executed in the changed region, and does not place the data block in either the shared memory or the multiple local memories if the valid region information of the data block indicates that the programs referencing each of the one or more referenced data will not be executed in the changed region.

6. An information processing method according to claim 1 or 2, wherein at least one of the plurality of processor cores further executes a step of generating one or more of the data blocks from the plurality of referenced data, and in the acquiring step, at least one of the plurality of processor cores acquires the data block generated in the generating step.

7. An electronic control device including a plurality of processor cores, each capable of communicating with a shared memory and each equipped with a local memory, the plurality of processor cores being interconnected; wherein each of the plurality of processor cores is a data block formed by accumulating one or more pieces of referenced data, the data being data referenced in a program executed by one of the plurality of processor cores, so that the data block does not exceed a standard data size; and a program that references each of the one or more pieces of referenced data included in the data block is executed by the same processor core among the plurality of processor cores and with the same execution cycle; and the data block includes, as additional information, common core identification information that identifies the same processor core as a common core and common execution cycle information that identifies the same execution cycle as a common execution cycle; and a block placement unit that places the data block acquired by the block acquisition unit in the shared memory or one of the plurality of local memories based on the additional information.

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