Nitride semiconductor device

Abstract

A nitride semiconductor device (1) comprises: a substrate (10); an electron transit layer (22) that is provided above the substrate (10); an electron supply layer (23) that contains Al and that is provided above the electron transit layer (22); a gap layer (27) that contains GaN as the main component thereof and that is provided above the electron supply layer (23); a p-type semiconductor layer (28) that is provided above the gap layer (27); and a gate electrode (32) that is provided above the p-type semiconductor layer (28) and that is electrically connected to the p-type semiconductor layer (28), wherein the Si concentration of an upper surface (23a) of the electron supply layer (23) in a range not overlapping with the p-type semiconductor layer (28) in a plan view of the substrate (10) is lower than the Si concentration of an upper surface (27a) of the gap layer (27) in a range overlapping with the p-type semiconductor layer (28) in the plan view of the substrate (10).

Description

Nitride Semiconductor Devices

[0001] The present disclosure relates to nitride semiconductor devices.

[0002] Nitride semiconductors, such as GaN and AlGaN, have a larger band gap and a higher breakdown field and saturated drift velocity than compound semiconductor materials such as Si semiconductors or GaAs, and are therefore being applied to electronic devices such as high-voltage power devices and high-speed, high-output transistors.

[0003] Patent Document 1 discloses a lateral field effect transistor (FET) formed using a GaN-based semiconductor material. The device disclosed in Patent Document 1 utilizes a two-dimensional electron gas (2DEG) generated near the heterointerface of AlGaN / GaN as a channel.

[0004] Patent No. 7113233

[0005] The device disclosed in Patent Document 1 has room for improvement in terms of reducing leakage current.

[0006] Therefore, the present disclosure provides a nitride semiconductor device capable of reducing leakage current.

[0007] A nitride semiconductor device according to one aspect of the present disclosure comprises a substrate, a first nitride semiconductor layer provided above the substrate, a second nitride semiconductor layer containing Al provided above the first nitride semiconductor layer, a third nitride semiconductor layer containing GaN as a main component provided above the second nitride semiconductor layer, a p-type fourth nitride semiconductor layer provided above the third nitride semiconductor layer, and a first electrode provided above the fourth nitride semiconductor layer and electrically connected to the fourth nitride semiconductor layer, wherein the Si concentration in an upper surface of the second nitride semiconductor layer within a range that does not overlap with the fourth nitride semiconductor layer in a planar view of the substrate is lower than the Si concentration in an upper surface of the third nitride semiconductor layer within a range that overlaps with the fourth nitride semiconductor layer in a planar view of the substrate.

[0008] According to the present disclosure, leakage current can be reduced.

[0009] FIG. 1 is a cross-sectional view of a nitride semiconductor device according to the first embodiment. FIG. 2A is a cross-sectional view for illustrating a step of a method for manufacturing a nitride semiconductor device according to the first embodiment. FIG. 2B is a cross-sectional view for illustrating a step of a method for manufacturing a nitride semiconductor device according to the first embodiment. FIG. 2C is a cross-sectional view for illustrating a step of a method for manufacturing a nitride semiconductor device according to the first embodiment. FIG. 2D is a cross-sectional view for illustrating a step of a method for manufacturing a nitride semiconductor device according to the first embodiment. FIG. 2E is a cross-sectional view for illustrating a step of a method for manufacturing a nitride semiconductor device according to the first embodiment. FIG. 2F is a cross-sectional view for illustrating a step of a method for manufacturing a nitride semiconductor device according to the first embodiment. FIG. 2G is a cross-sectional view for illustrating a step of a method for manufacturing a nitride semiconductor device according to the first embodiment. FIG. 2H is a cross-sectional view for illustrating a step of a method for manufacturing a nitride semiconductor device according to the first embodiment. FIG. 3 is an enlarged cross-sectional view of a main portion of a nitride semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view of a nitride semiconductor device according to a first modification of the first embodiment. FIG. 5 is a cross-sectional view for illustrating an effect of the nitride semiconductor device according to the first modification of the first embodiment. FIG. 6 is a cross-sectional view of a nitride semiconductor device according to a second modification of the first embodiment. Fig. 7 is a cross-sectional view of a nitride semiconductor device according to a third modification of the first embodiment. Fig. 8 is an enlarged cross-sectional view of a main portion of a nitride semiconductor device according to a fourth modification of the first embodiment. Fig. 9 is a cross-sectional view of a nitride semiconductor device according to a second embodiment. Fig. 10 is a cross-sectional view of a nitride semiconductor device according to a second modification of the second embodiment.

[0010] (Findings that Form the Basis of the Present Disclosure) The present inventors have found that the conventional nitride semiconductor devices described in the "Background Art" section have the following problems.

[0011] In the nitride semiconductor device disclosed in Patent Document 1, a recess is formed in an AlGaN layer by dry etching, and then a p-type nitride semiconductor layer is formed by epitaxial growth. In this case, impurities such as Si adhere to the surface of the AlGaN layer before the p-type nitride semiconductor layer is formed. The impurities adhered to the surface diffuse into the AlGaN layer during crystal growth of the p-type nitride semiconductor layer. As the impurities diffused into the AlGaN layer pile up on the surface, leakage current tends to flow between the gate and drain and / or between the gate and source via the surface portion of the AlGaN layer.

[0012] Therefore, an object of the present disclosure is to provide a nitride semiconductor device capable of reducing leakage current.

[0013] A nitride semiconductor device according to a first aspect of the present disclosure comprises: a substrate; a first nitride semiconductor layer provided above the substrate; a second nitride semiconductor layer containing Al provided above the first nitride semiconductor layer; a third nitride semiconductor layer containing GaN as a main component provided above the second nitride semiconductor layer; a p-type fourth nitride semiconductor layer provided above the third nitride semiconductor layer; and a first electrode provided above the fourth nitride semiconductor layer and electrically connected to the fourth nitride semiconductor layer, wherein the Si concentration in an upper surface of the second nitride semiconductor layer within a range that does not overlap with the fourth nitride semiconductor layer in a planar view of the substrate is lower than the Si concentration in an upper surface of the third nitride semiconductor layer within a range that overlaps with the fourth nitride semiconductor layer in a planar view of the substrate.

[0014] This reduces the Si concentration at the top surface of the second nitride semiconductor layer due to unavoidable impurities, making it difficult for a leakage current path to form along the top surface of the second nitride semiconductor layer, thereby enabling the nitride semiconductor device according to this aspect to reduce leakage current.

[0015] A nitride semiconductor device according to a second aspect of the present disclosure is the nitride semiconductor device according to the first aspect, wherein the third nitride semiconductor layer is provided only in a region that overlaps with the fourth nitride semiconductor layer in a planar view of the substrate.

[0016] This allows impurities inevitably remaining on the upper surface of the third nitride semiconductor layer to be removed together with the third nitride semiconductor layer in an area that does not overlap with the fourth nitride semiconductor layer, thereby making it more difficult for a leakage current path to be formed along the upper surface of the second nitride semiconductor layer, thereby further reducing the leakage current.

[0017] A nitride semiconductor device according to a third aspect of the present disclosure is the nitride semiconductor device according to the first aspect, wherein the third nitride semiconductor layer includes a thick film portion that overlaps the fourth nitride semiconductor layer in a planar view of the substrate, and a thin film portion that does not overlap the fourth nitride semiconductor layer in a planar view of the substrate, and the thin film portion has a thickness smaller than that of the thick film portion.

[0018] By leaving the third nitride semiconductor layer thin in the area that does not overlap with the fourth nitride semiconductor layer, electron traps such as surface states can be reduced, and current collapse can be suppressed.

[0019] A nitride semiconductor device according to a fourth aspect of the present disclosure is the nitride semiconductor device according to the third aspect, wherein the Si concentration in the upper surface of the thin film portion is lower than the Si concentration in the upper surface of the thick film portion.

[0020] This makes it possible to remove impurities that inevitably remain on the top surface of the third nitride semiconductor layer together with the surface portion of the third nitride semiconductor layer in the area that does not overlap with the fourth nitride semiconductor layer, thereby making it more difficult for a leakage current path to be formed along the top surface of the second nitride semiconductor layer, thereby further reducing the leakage current.

[0021] A nitride semiconductor device according to a fifth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to fourth aspects, wherein the third nitride semiconductor layer has a maximum film thickness of 10 nm or more.

[0022] This makes it possible to prevent impurities that inevitably remain on the upper surface of the third nitride semiconductor layer from diffusing into the second nitride semiconductor layer.

[0023] A nitride semiconductor device according to a sixth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to fifth aspects, wherein the third nitride semiconductor layer contains undoped GaN as a main component.

[0024] This allows GaN to suppress the diffusion of Si into the second nitride semiconductor layer, making it difficult for a leakage current path to be formed, thereby reducing the leakage current.

[0025] A nitride semiconductor device according to a seventh aspect of the present disclosure is the nitride semiconductor device according to any one of the first to fifth aspects, wherein the third nitride semiconductor layer contains p-type GaN as a main component.

[0026] As a result, GaN can suppress the diffusion of Si into the second nitride semiconductor layer, making it difficult for a leakage current path to be formed, thereby reducing the leakage current. Furthermore, by using p-type GaN, even if the film quality of the fourth nitride semiconductor layer deteriorates, the presence of a p-type third nitride semiconductor layer between the first electrode and the second nitride semiconductor layer can suppress a decrease in breakdown voltage.

[0027] A nitride semiconductor device according to an eighth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to seventh aspects, wherein the first electrode is a gate electrode, and the nitride semiconductor device further comprises a source electrode provided above the substrate and electrically connected to the first nitride semiconductor layer, and a drain electrode provided below the substrate.

[0028] This makes it possible to realize a vertical FET with high breakdown voltage and high output.

[0029] A nitride semiconductor device according to a ninth aspect of the present disclosure is the nitride semiconductor device according to the eighth aspect, comprising an n-type fifth nitride semiconductor layer provided above the substrate, and a p-type sixth nitride semiconductor layer provided above the fifth nitride semiconductor layer, wherein the first nitride semiconductor layer and the second nitride semiconductor layer are provided so as to cover an inner surface of a first opening that penetrates the sixth nitride semiconductor layer to reach the fifth nitride semiconductor layer, and an upper part of the sixth nitride semiconductor layer.

[0030] This allows the first nitride semiconductor layer including the channel to come into contact with the n-type fifth nitride semiconductor layer at the bottom of the first opening, thereby reducing the on-resistance.

[0031] A nitride semiconductor device according to a tenth aspect of the present disclosure is the nitride semiconductor device according to the ninth aspect, wherein the second nitride semiconductor layer has a recessed portion at a position overlapping the sixth nitride semiconductor layer in a planar view of the substrate, the third nitride semiconductor layer has a second opening at a position overlapping the recessed portion in a planar view of the substrate, and the fourth nitride semiconductor layer is provided in the recessed portion via the second opening.

[0032] This allows the threshold voltage of the FET to be adjusted by adjusting the depth of the recess, making it possible to easily realize, for example, a normally-off FET.

[0033] A nitride semiconductor device according to an eleventh aspect of the present disclosure is the nitride semiconductor device according to the tenth aspect, wherein the gate electrode is provided so as to overlap a bottom surface of the first opening and the recess portion in a plan view of the substrate.

[0034] This makes it possible to increase the contact area between the fourth nitride semiconductor layer and the gate electrode, thereby improving the controllability of the channel by the gate electrode.

[0035] A nitride semiconductor device according to a twelfth aspect of the present disclosure is the nitride semiconductor device according to the tenth aspect, wherein the gate electrode is provided at a position that overlaps the sixth nitride semiconductor layer but does not overlap the first opening in a planar view of the substrate.

[0036] This increases the distance between the gate electrode and the drain electrode, reducing the gate-drain parasitic capacitance Cgd, thereby enabling faster switching of the FET.

[0037] A nitride semiconductor device according to a thirteenth aspect of the present disclosure is the nitride semiconductor device according to the twelfth aspect, further comprising a second electrode provided at a position overlapping a bottom surface of the first opening in a plan view of the substrate and set to the same potential as the source electrode, wherein the third nitride semiconductor layer includes a first portion and a second portion electrically isolated from each other, the fourth nitride semiconductor layer includes a third portion and a fourth portion electrically isolated from each other, the first portion and the third portion being located between the gate electrode and the second nitride semiconductor layer, and the second portion and the fourth portion being located between the second electrode and the second nitride semiconductor layer.

[0038] This allows the electric field lines extending from the drain electrode to terminate at the fourth portion of the fourth nitride semiconductor layer and the sixth nitride semiconductor layer, thereby reducing the gate-drain parasitic capacitance Cgd and enabling faster switching of the FET.

[0039] A nitride semiconductor device according to a fourteenth aspect of the present disclosure is the nitride semiconductor device according to any one of the ninth to thirteenth aspects, further comprising: a p-type seventh nitride semiconductor layer provided in contact with the sixth nitride semiconductor layer within a third opening that passes through the third nitride semiconductor layer, the second nitride semiconductor layer, and the first nitride semiconductor layer to reach the sixth nitride semiconductor layer; and a third electrode electrically connected to the seventh nitride semiconductor layer.

[0040] As a result, the third electrode is in contact with the p-type seventh nitride semiconductor layer, rather than the p-type sixth nitride semiconductor layer, which may be subject to etching damage. Since the contact resistance can be reduced compared to when the third electrode is in contact with the sixth nitride semiconductor layer, charges accumulated in the sixth nitride semiconductor layer can be efficiently extracted to the third electrode via the seventh nitride semiconductor layer. This prevents a decrease in the 2DEG concentration due to residual charges, thereby preventing an increase in on-resistance.

[0041] A nitride semiconductor device according to a fifteenth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to seventh aspects, wherein the first electrode is a gate electrode, and the nitride semiconductor device further comprises a source electrode and a drain electrode disposed above the substrate and sandwiching the gate electrode therebetween, and electrically connected to the first nitride semiconductor layer.

[0042] This makes it possible to realize a lateral FET with a high switching speed.

[0043] A nitride semiconductor device according to a sixteenth aspect of the present disclosure is the nitride semiconductor device according to the fifteenth aspect, wherein the second nitride semiconductor layer has a recessed portion at a position overlapping the gate electrode in a planar view of the substrate, the third nitride semiconductor layer has a second opening at a position overlapping the recessed portion in a planar view of the substrate, and the fourth nitride semiconductor layer is provided in the recessed portion via the second opening.

[0044] This allows the threshold voltage of the FET to be adjusted by adjusting the depth of the recess, making it possible to easily realize, for example, a normally-off FET.

[0045] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0046] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0047] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0048] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or orthogonal, terms indicating the shape of elements, such as rectangular or trapezoidal, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0049] In this specification, the "thickness direction" of a substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction." The direction parallel to the main surface of the substrate may be referred to as the "lateral direction." A "vertical" device refers to a device in which the main path of a main current, such as a drain current or a forward current, is vertical, i.e., a device in which the main current passes vertically through the substrate. A "lateral" semiconductor device refers to a device in which the main path of a main current, such as a drain current or a forward current, is horizontal, i.e., a device in which the main current does not pass through the substrate.

[0050] Furthermore, the side on which the heterostructure is provided with respect to the substrate is considered to be "upper" or "upper side," and the opposite side is considered to be "lower" or "lower side." In this specification, the terms "upper" and "lower" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked structure. Furthermore, the terms "upper" and "lower" are used not only when two components are arranged with a gap between them and another component is present between them, but also when two components are arranged in close contact with each other and the two components are in contact.

[0051] In this specification, unless otherwise specified, the term "plan view" refers to a view perpendicular to the main surface of the substrate of the nitride semiconductor device, that is, a view of the main surface of the substrate from the front.

[0052] In addition, in this specification, "A and B overlap in a plan view" means that at least a part of A overlaps with at least a part of B. In other words, this includes cases where only a part of A overlaps with only a part of B, where all of A overlaps with B, where all of B overlaps with A, and where A and B completely overlap with each other.

[0053] In this specification, AlGaN refers to a ternary mixed crystal Al ｘ Ga １－ｘ Hereinafter, multi-element mixed crystals are abbreviated by the arrangement of the symbols of the respective constituent elements, such as AlInN, GaInN, etc. For example, AlInN, which is an example of a nitride semiconductor, ｘ Ga １－ｘ－ｙ In ｙ N (0<x<1, 0<y<1, and 0<x+y<1) is abbreviated as AlGaInN, where x, 1-xy, and y represent the composition ratios of Al, Ga, and In, respectively.

[0054] Furthermore, n-type and p-type indicate the conductivity types of semiconductors, and are conductivity types of opposite polarity. ＋ The n-type indicates a state in which a semiconductor is doped with a high concentration of n-type dopants, i.e., a heavily doped semiconductor. － The term "type" refers to a state in which a semiconductor is doped with a low concentration of n-type dopant, i.e., a so-called lightly doped state. ＋ Type and n － Both types are examples of n-type, and may be referred to as n-type without distinction. ＋ Type and p － The same is true for types.

[0055] Furthermore, "A contains B as a main component" means that B has the highest composition ratio among the elements constituting A. Furthermore, a layer made of A and a layer constituted by A mean that the layer contains substantially only A. However, the layer may contain other elements as impurities, such as elements that are unavoidable in the manufacturing process, at a rate of 1 at % or less.

[0056] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0057] First Embodiment [Configuration] First, an outline of a nitride semiconductor device according to a first embodiment will be described with reference to FIG.

[0058] Fig. 1 is a cross-sectional view of a nitride semiconductor device 1 according to this embodiment. In Fig. 1, components such as semiconductor layers, insulating layers, and electrodes other than the electron transit layer 22 are shaded with diagonal lines to indicate cross sections. This is also true for Fig. 2A and subsequent cross-sectional views.

[0059] The nitride semiconductor device 1 includes a normally-off vertical FET. In the nitride semiconductor device 1, for example, the source electrode 34 is grounded, and a positive potential is applied to the drain electrode 38. The potential applied to the drain electrode 38 is, for example, not limited to, 100 V or more and 1200 V or less. The nitride semiconductor device 1 performs modulation according to the potential applied to the gate electrode 32. For example, when 0 V or a negative potential (e.g., −5 V) is applied to the gate electrode 32, no current flows between the drain electrode 38 and the source electrode 34. In other words, the nitride semiconductor device 1 is in a non-conductive state (off). When a positive potential (e.g., +5 V) is applied to the gate electrode 32, a current flows from the drain electrode 38 to the source electrode 34. In other words, the nitride semiconductor device 1 is in a conductive state (on). The current flowing from the drain electrode 38 to the source electrode 34 when the device is on is called a drain current. The drain current flows through the substrate 10 in its thickness direction (i.e., vertical direction).

[0060] 1 , the nitride semiconductor device 1 includes a substrate 10, a drift layer 12, a block layer 14, a nitride semiconductor layer 21, a cap layer 27, a p-type semiconductor layer 28, a gate electrode 32, a source electrode 34, an ohmic electrode 35, and a drain electrode 38. The nitride semiconductor layer 21 includes an electron transit layer 22, an electron supply layer 23, and a 2DEG 24. The nitride semiconductor device 1 further includes an insulating layer 40 and a source wiring 50. The nitride semiconductor device 1 also includes a vertical conduction opening 20 and a source opening 30.

[0061] The nitride semiconductor device 1 is a device in which a semiconductor layer including a channel contains a nitride semiconductor as a main component. Specifically, the drift layer 12, the block layer 14, the electron transit layer 22, the electron supply layer 23, the cap layer 27, and the p-type semiconductor layer 28 each contain a nitride semiconductor as a main component.

[0062] Each of the components of the nitride semiconductor device 1 will be described in detail below.

[0063] The substrate 10 has a thickness of, for example, 300 μm and a carrier concentration of 5×10 １８ cm －３ n ＋ The substrate is made of GaN.

[0064] The substrate 10 does not have to be a nitride semiconductor substrate, but may be, for example, a Si substrate, a SiC substrate, or a ZnO substrate.

[0065] The drift layer 12 is an example of an n-type fifth nitride semiconductor layer provided above the substrate 10. The drift layer 12 is, for example, an n-type fifth nitride semiconductor layer having a thickness of 8 μm. － The drift layer 12 is a film made of GaN of the type. The donor concentration of the drift layer 12 is, for example, 1×10 １５ cm －３ 1x10 or more １７ cm －３ As an example, １６ cm －３ The carbon concentration (C concentration) of the drift layer 12 is, for example, 1×10 １５ cm －３ 5x10 or more１６ cm －３ The drift layer 12 is provided in contact with, for example, the upper surface (main surface) of the substrate 10 .

[0066] The block layer 14 is an example of a p-type sixth nitride semiconductor layer provided above the drift layer 12. The block layer 14 has a thickness of 400 nm and a carrier concentration of 1×10 １７ cm －３ The block layer 14 is a film made of p-type GaN, where p-type GaN is a p-type GaN film. The block layer 14 is provided in contact with the upper surface of the drift layer 12.

[0067] A vertical conduction opening 20 is provided in the block layer 14. The vertical conduction opening 20 is an example of a first opening that penetrates the block layer 14 and reaches the drift layer 12. A bottom surface 20a of the vertical conduction opening 20 is part of the upper surface of the drift layer 12. As shown in FIG. 1 , the bottom surface 20a is located below the lower surface of the block layer 14. The lower surface of the block layer 14 corresponds to the interface between the block layer 14 and the drift layer 12. The bottom surface 20a is, for example, parallel to the major surface of the substrate 10. When the nitride semiconductor device 1 is on, a drain current flows between the drain electrode 38 and the source electrode 34 through the bottom surface 20a of the vertical conduction opening 20.

[0068] In this embodiment, the vertical conductive opening 20 is formed so that the opening area increases as it becomes farther from the substrate 10. Specifically, the side surface 20b of the vertical conductive opening 20 is inclined obliquely. As shown in FIG. 1 , the cross-sectional shape of the vertical conductive opening 20 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

[0069] The inclination angle of the side surface 20b with respect to the bottom surface 20a is, for example, 20° to 80°, but may be 30° to 45°. The smaller the inclination angle, the closer the side surface 20b is to the c-plane, thereby improving the film quality of the electron transit layer 22 and other layers formed along the side surface 20b by crystal regrowth. On the other hand, the larger the inclination angle, the more effectively the vertical conduction opening 20 is prevented from becoming too large, thereby realizing a more compact nitride semiconductor device 1. The side surface 20b may be perpendicular to the bottom surface 20a.

[0070] The electron transit layer 22 is an example of a first nitride semiconductor layer provided above the substrate 10. Specifically, the electron transit layer 22 is also an example of a first regrowth layer, and is provided so as to cover the inner surface of the vertical conduction opening 20 and the upper side of the block layer 14. For example, a portion of the electron transit layer 22 is provided along the bottom surface 20 a and the side surface 20 b of the vertical conduction opening 20, and another portion of the electron transit layer 22 is provided on the upper surface 14 a of the block layer 14. The electron transit layer 22 is, for example, a film made of undoped GaN with a thickness of 150 nm. Note that although the electron transit layer 22 is assumed to be undoped, a portion of the electron transit layer 22 may be made n-type by, for example, Si doping.

[0071] The electron transit layer 22 is in contact with the drift layer 12 at the bottom surface 20 a and the side surface 20 b of the vertical conduction opening 20. The electron transit layer 22 is in contact with the block layer 14 at the side surface 20 b of the vertical conduction opening 20. The electron transit layer 22 is in contact with the top surface 14 a of the block layer 14.

[0072] The electron transit layer 22 has a channel region. Specifically, a 2DEG 24, which serves as a channel, is generated near the interface between the electron transit layer 22 and the electron supply layer 23. The 2DEG 24 is bent along the interface between the electron transit layer 22 and the electron supply layer 23, i.e., along the inner surface of the vertical conduction opening 20.

[0073] 1, an AlN layer having a thickness of about 1 nm is provided as a second regrown layer between the electron transit layer 22 and the electron supply layer 23. This suppresses alloy scattering, improves channel mobility, and makes it possible to reduce on-resistance. However, the AlN layer is not necessarily required.

[0074] The electron supply layer 23 is an example of a second nitride semiconductor layer containing Al and is provided above the electron transit layer 22. Specifically, the electron supply layer 23 is also an example of a third regrowth layer, and is provided so as to cover the inner surface of the vertical conduction opening 20 and the upper surface of the block layer 14. Specifically, the electron supply layer 23 is provided along the upper surface of the electron transit layer 22 so as to overlap the bottom surface 20 a and side surface 20 b of the vertical conduction opening 20 and the upper surface 14 a of the block layer 14 in a planar view of the substrate 10. The electron supply layer 23 is, for example, a film made of undoped AlGaN. The electron supply layer 23 is formed to a shape that conforms to the upper surface of the electron transit layer 22 and to a substantially uniform thickness.

[0075] The electron supply layer 23 has a larger band gap than the electron transit layer 22. Therefore, an AlGaN / GaN heterointerface is formed between the electron supply layer 23 and the electron transit layer 22. The electron supply layer 23 supplies electrons to a channel region (2DEG 24) formed in the electron transit layer 22.

[0076] The electron transit layer 22 and the electron supply layer 23 are both layers included in the nitride semiconductor layer 21 provided in the nitride semiconductor device 1. The nitride semiconductor layer 21 is an example of a nitride semiconductor layer provided above the block layer 14. Note that "provided above" means that at least a portion of the nitride semiconductor layer 21 is located above the block layer 14. In other words, at least a portion of the nitride semiconductor layer 21 is located above the block layer 14. In this embodiment, the nitride semiconductor layer 21 is provided so as to cover the inner surface of the vertical conduction opening 20 and the upper portion of the block layer 14.

[0077] The electron supply layer 23 has a recess 26. Specifically, the recess 26 is provided in a portion of the electron supply layer 23 that is located above the upper surface 14a of the block layer 14.

[0078] In this embodiment, the recessed portion 26 is provided at a position overlapping the upper surface 14a of the block layer 14 in a plan view of the substrate 10. Note that a part or all of the recessed portion 26 may overlap the end surface of the block layer 14 on the vertical conductive opening 20 side in a plan view of the substrate 10. The recessed portion 26 may be provided in range A1. That is, the recessed portion 26 may be provided at a position overlapping the block layer 14 in a plan view of the substrate 10. Note that the side surface of the recessed portion 26 is perpendicular to the bottom surface of the recessed portion 26, but may be inclined obliquely.

[0079] The thickness of the electron supply layer 23 is reduced in the portion overlapping the recessed portion 26 in plan view. This reduces the concentration of the 2DEG 24 directly below the recessed portion 26, thereby increasing the threshold voltage of the FET. For example, the threshold voltage can be increased above 0 V, making it easier to make the FET normally off. On the other hand, the thickness of the electron supply layer 23 is increased in the portion not overlapping the recessed portion 26 in plan view. This increases the concentration of the 2DEG 24 directly below the portion other than the recessed portion 26, thereby reducing the on-resistance. In this way, the provision of the recessed portion 26 makes it possible to achieve both a normally off state and reduced on-resistance.

[0080] If the thickness of the electron supply layer 23 is too large, dislocations and cracks may occur, which may increase the on-resistance or leakage current. Therefore, the thickness of the electron supply layer 23 is, for example, 70 nm or less when the Al composition ratio is 20%. This makes it possible to suppress increases in on-resistance and leakage current. The thickness of the electron supply layer 23 in the portion overlapping the recessed portion 26 in a plan view is, for example, half or less of the thickness of the portion other than the recessed portion 26, and can be, for example, 20 nm. This makes it possible to increase the threshold voltage of the FET above 0 V, thereby realizing a normally-off FET.

[0081] The cap layer 27 is an example of a third nitride semiconductor layer containing GaN as a main component, which is provided above the electron supply layer 23. For example, the cap layer 27 contains undoped GaN as a main component.

[0082] In the present embodiment, the cap layer 27 is provided only in a region that overlaps with the p-type semiconductor layer 28 in a plan view of the substrate 10. That is, the cap layer 27 is not provided in a range that does not overlap with the p-type semiconductor layer 28. Furthermore, the cap layer 27 is provided with an opening 27h, which is an example of a second opening, at a position that overlaps with the recess portion 26 in a plan view of the substrate 10.

[0083] The cap layer 27 includes a first portion 27A and a second portion 27B that are electrically isolated from each other. The first portion 27A is located between the gate electrode 32 and the electron supply layer 23. Specifically, the first portion 27A is provided between the upper surface 23a of the electron supply layer 23 and the lower surface of the p-type semiconductor layer 28, in contact with each other. The first portion 27A is not in contact with the inner surface of the recess 26, but is provided outside the recess 26. In other words, an opening 27h is provided in the first portion 27A to avoid contact with the inner surface of the recess 26. For example, the sidewall surface of the opening 27h provided in the first portion 27A is flush with the side surface of the recess 26 provided in the electron supply layer 23, and is inclined perpendicularly or obliquely with respect to the bottom surface of the recess 26.

[0084] The second portion 27B is located between the ohmic electrode 35 and the electron supply layer 23. Specifically, the second portion 27B is provided between and in contact with the upper surface 23a of the electron supply layer 23 and the lower surface of the p-type semiconductor layer 28. An end face of the second portion 27B is flush with an end face of the p-type semiconductor layer 28 and is perpendicular or obliquely inclined with respect to the upper surface 23a of the electron supply layer 23.

[0085] The p-type semiconductor layer 28 is an example of a p-type fourth nitride semiconductor layer provided above the cap layer 27. As shown in Fig. 1 , the p-type semiconductor layer 28 includes a threshold adjustment layer 28A and a p-type semiconductor layer 28B. The threshold adjustment layer 28A and the p-type semiconductor layer 28B are electrically isolated from each other.

[0086] The threshold adjustment layer 28A is an example of a third portion included in the p-type semiconductor layer 28. The threshold adjustment layer 28A is located between the gate electrode 32 and the electron supply layer 23. Specifically, the threshold adjustment layer 28A is provided between an upper surface 27a of the cap layer 27 and a lower surface of the gate electrode 32 so as to be in contact with each other. The threshold adjustment layer 28A is also provided in the recess portion 26 via an opening 27h provided in the cap layer 27. The threshold adjustment layer 28A is disposed at a distance from the source electrode 34 and the ohmic electrode 35 and is electrically isolated from them.

[0087] In the present embodiment, the threshold adjustment layer 28A is provided at a position overlapping the block layer 14 without overlapping the vertical conductive opening 20 in a plan view of the substrate 10. Specifically, the threshold adjustment layer 28A is provided at a position overlapping the upper surface 14a of the block layer 14 in a plan view of the substrate 10. That is, the threshold adjustment layer 28A is provided outside the vertical conductive opening 20. Note that the threshold adjustment layer 28A may also be provided at a position overlapping the inclined end face of the block layer 14 on the vertical conductive opening 20 side in a plan view of the substrate 10.

[0088] The provision of the threshold adjustment layer 28A raises the potential of the conduction band edge of the channel portion. This reduces the carrier concentration directly below the gate electrode 32, shifting the threshold voltage of the FET to the positive side. This makes it easy to realize the nitride semiconductor device 1 as a normally-off FET. Furthermore, although an example is shown in which the upper surface of the threshold adjustment layer 28A is flat, a recess corresponding to the recess portion 26 may be provided in the upper surface of the threshold adjustment layer 28A.

[0089] The p-type semiconductor layer 28B is an example of a fourth portion included in the p-type semiconductor layer 28. The p-type semiconductor layer 28B is located between the ohmic electrode 35 and the electron supply layer 23. Specifically, the p-type semiconductor layer 28B is provided between the upper surface 27a of the cap layer 27 and the lower surface of the gate electrode 32 so as to be in contact with each other. The p-type semiconductor layer 28B is disposed at a distance from the gate electrode 32 and is electrically isolated from it.

[0090] The threshold adjustment layer 28A and the p-type semiconductor layer 28B each have a thickness of 200 nm and a carrier concentration of 5×10 １７ cm －３ The threshold adjustment layer 28A and the p-type semiconductor layer 28B are films made of p-type GaN. The thicknesses and carrier concentrations of the threshold adjustment layer 28A and the p-type semiconductor layer 28B are merely examples and can be changed as appropriate. For example, the threshold adjustment layer 28A and the p-type semiconductor layer 28B may be films made of p-type AlGaN. The threshold adjustment layer 28A and the p-type semiconductor layer 28B are formed using the same material in the same process, but may also be formed in different processes. The threshold adjustment layer 28A and the p-type semiconductor layer 28B may differ from each other in at least one of thickness, composition, and carrier concentration.

[0091] The source opening 30 is an example of an opening that penetrates the nitride semiconductor layer 21 and reaches the block layer 14 outside the vertical conduction opening 20 in a plan view of the substrate 10. The source opening 30 is provided at a position away from both the gate electrode 32 and the threshold adjustment layer 28A in a plan view of the substrate 10. Since the source opening 30 penetrates the nitride semiconductor layer 21, the 2DEG 24 is exposed on a side surface 30b of the source opening 30.

[0092] A bottom surface 30a of the source opening 30 is part of the upper surface 14a of the block layer 14. The bottom surface 30a is, for example, parallel to the main surface of the substrate 10. In the example shown in FIG. 1 , the bottom surface 30a is located below the lower surface of the electron transit layer 22. The lower surface of the electron transit layer 22 corresponds to the interface between the electron transit layer 22 and the block layer 14.

[0093] As shown in FIG. 1 , the source opening 30 is formed so that the opening area increases with increasing distance from the substrate 10. Specifically, the side surface 30 b of the source opening 30 is obliquely inclined. For example, the cross-sectional shape of the source opening 30 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid. In this case, the inclination angle of the side surface 30 b relative to the bottom surface 30 a is, for example, in the range of 30° to 60°. The oblique inclination of the side surface 30 b increases the contact area between the source electrode 34 and the 2DEG 24, facilitating ohmic contact. The 2DEG 24 is exposed on the side surface 30 b of the source opening 30 and connected to the source electrode 34 at the exposed portion. The side surface 30 b may also be perpendicular to the bottom surface 30 a.

[0094] The provision of the source opening 30 can reduce the ohmic contact resistance between the 2DEG 24 functioning as a channel and the source electrode 34. That is, the on-resistance of the nitride semiconductor device 1 can be reduced.

[0095] Furthermore, the source electrode 34 and the block layer 14 are electrically connected at the bottom surface 30a of the source opening 30. As a result, the same potential as that applied to the source electrode 34 is supplied to the block layer 14. When a reverse voltage is applied to the pn junction formed by the block layer 14 and the drift layer 12, specifically when the drain electrode 38 has a higher potential than the source electrode 34, a depletion layer extends into the drift layer 12, thereby enabling the nitride semiconductor device 1 to withstand a high voltage.

[0096] The gate electrode 32 is an example of a first electrode provided above the p-type semiconductor layer 28 and electrically connected to the p-type semiconductor layer 28. Specifically, the gate electrode 32 is provided on an upper surface of the threshold adjustment layer 28A of the p-type semiconductor layer 28 and is electrically connected to the threshold adjustment layer 28A. The gate electrode 32 is not electrically connected to the p-type semiconductor layer 28B. In the present embodiment, the gate electrode 32 is provided at a position where it overlaps the block layer 14 but does not overlap the vertical conductive opening 20 in a plan view of the substrate 10. Specifically, the gate electrode 32 does not overlap the bottom surface 20a and the side surface 20b of the vertical conductive opening 20 in a plan view of the substrate 10 but overlaps the upper surface 14a of the block layer 14. The gate electrode 32 is disposed apart from the source electrode 34 and the ohmic electrode 35 and is electrically isolated from them.

[0097] The gate electrode 32 is formed using a conductive material such as a metal. For example, the gate electrode 32 may be formed using a material that forms an ohmic contact with a p-type nitride semiconductor such as p-type GaN, but is not limited thereto and may also be formed using a material that forms a Schottky contact with the p-type nitride semiconductor. For example, the gate electrode 32 may be formed using Pd, a Ni-based material, WSi, Au, or the like.

[0098] The source electrode 34 is provided above the substrate 10 and electrically connected to the electron transit layer 22. In this embodiment, the source electrode 34 is in contact with the electron transit layer 22 within the source opening 30. Specifically, the source electrode 34 is provided in contact with the bottom surface 30a and the side surface 30b of the source opening 30. The source electrode 34 is in direct contact with the 2DEG 24 at the side surface 30b of the source opening 30. This reduces the contact resistance between the source electrode 34 and the 2DEG 24, thereby reducing the on-resistance of the nitride semiconductor device 1.

[0099] The source electrode 34 is formed using a conductive material such as a metal. Examples of the material for the source electrode 34 include Ti / Al (a laminated structure of a Ti layer and an Al layer), which can be ohmically connected to an n-type nitride semiconductor such as n-type GaN by heat treatment.

[0100] The ohmic electrode 35 is an example of a second electrode provided at a position overlapping the bottom surface 20a of the vertical conductive opening 20 in a plan view of the substrate 10. The ohmic electrode 35 is provided on the upper surface of the p-type semiconductor layer 28B.

[0101] The ohmic electrode 35 is formed using a conductive material such as a metal. For example, the ohmic electrode 35 may be formed using a material that forms an ohmic connection with a p-type nitride semiconductor such as p-type GaN. For example, the ohmic electrode 35 may be formed using Pd, a Ni-based material, WSi, Au, or the like. The ohmic electrode 35 is formed using the same material and in the same process as the gate electrode 32, for example.

[0102] The ohmic electrode 35 is set to the same potential as the source electrode 34. Specifically, a source wiring 50 is connected to the ohmic electrode 35 through an opening provided in the insulating layer 40, as shown in FIG.

[0103] The drain electrode 38 is provided below the substrate 10. Specifically, the drain electrode 38 is provided in contact with the lower surface of the substrate 10.

[0104] The drain electrode 38 is formed using a conductive material such as a metal. As with the material of the source electrode 34, the material of the drain electrode 38 may be, for example, Ti / Al, which is a material that forms an ohmic contact with an n-type nitride semiconductor such as n-type GaN.

[0105] The insulating layer 40 is provided above the gate electrode 32. Specifically, the insulating layer 40 is provided so as to cover the gate electrode 32, the p-type semiconductor layer 28, the electron supply layer 23, the source electrode 34, and the ohmic electrode 35. The insulating layer 40 has a laminated structure of a plurality of insulating films. The plurality of insulating films may be made of, for example, SiN, SiO ２ , SiON, Al ２ O ３ The insulating layer 40 may have a single layer structure of one insulating film.

[0106] The source wiring 50 is provided above the insulating layer 40 and is connected to each of the source electrode 34 and the ohmic electrode 35 through an opening provided in the insulating layer 40. The source wiring 50 is formed using a conductive material such as a metal. For example, the source wiring 50 is a plated film made of Au.

[0107] [Manufacturing Method] Next, a method for manufacturing the nitride semiconductor device 1 according to this embodiment will be described with reference to Figures 2A to 2H. Figures 2A to 2H are cross-sectional views for explaining a step in the method for manufacturing the nitride semiconductor device 1 according to this embodiment. The cross-sectional configuration of the device during manufacturing changes in the order of Figures 2A to 2H.

[0108] First, as shown in FIG. 2A , a drift layer 12 and a block layer 14 are formed in this order by crystal growth above a substrate 10. Specifically, a nitride semiconductor is crystal-grown on the main surface of the substrate 10 by epitaxial growth, such as MOCVD (Metal Oxide Chemical Vapor Deposition) or HVPE (Hydride Vapor Phase Epitaxy). By adjusting growth conditions, such as raw materials, growth temperature, and growth time, the composition, film thickness, impurity concentration, and the like, can be adjusted to values ​​appropriate for each layer. For example, n-type GaN is crystal-grown as the drift layer 12, and then p-type GaN is crystal-grown as the block layer 14. Si, for example, is used as the n-type impurity, and Mg, for example, is used as the p-type impurity. For example, the drift layer 12 and the block layer 14 are formed consecutively in the same growth furnace without being exposed to the atmosphere during the process. Although the block layer 14 is formed by crystal growth, it may also be formed by, for example, implanting Mg into a deposited i-GaN film.

[0109] Next, as shown in FIG. 2B , a vertical conductive opening 20 is formed through the block layer 14. For example, a photosensitive photoresist is applied to the upper surface 14a of the block layer 14 and patterned into a predetermined shape by photolithography. The patterned photosensitive photoresist (i.e., a resist mask) has an opening at a position corresponding to the vertical conductive opening 20, exposing the upper surface 14a of the block layer 14. At this time, the side surface of the resist mask opening can be sloped by adjusting baking conditions such as the baking temperature of the resist mask. Then, the vertical conductive opening 20 is formed by removing a portion of the block layer 14 and the drift layer 12 in an area not covered by the resist mask by dry etching or the like. The side surface 20b of the vertical conductive opening 20 is inclined according to the slope of the side surface of the resist mask opening. After the vertical conductive opening 20 is formed, the resist mask is peeled off.

[0110] 2C , the electron transit layer 22, the electron supply layer 23, and the cap layer 27 are formed in this order by crystal growth (second crystal growth) so as to cover the vertical conduction opening 20 and the block layer 14. For example, undoped GaN is epitaxially grown as the electron transit layer 22 so as to entirely cover the bottom surface 20 a and the side surface 20 b of the vertical conduction opening 20 and the upper surface 14 a of the block layer 14, and then undoped AlGaN is successively grown as the electron supply layer 23, and undoped GaN is further successively formed as the cap layer 27. After forming the undoped GaN for the electron transit layer 22, undoped AlGaN may be formed before forming the undoped AlGaN for the electron supply layer 23.

[0111] 2D , an opening 27h penetrating the cap layer 27 and a recess 26 provided in the upper surface 23a of the electron supply layer 23 are formed. Specifically, similar to the formation of the vertical conduction opening 20, the opening 27h and the recess 26 are formed by forming a resist mask by photolithography and then dry etching. Because the opening 27h and the recess 26 are formed continuously using a single resist mask, the sidewall surface of the opening 27h and the side surface of the recess 26 are flush with each other. In this embodiment, the opening 27h and the recess 26 are formed at a position overlapping the upper surface 14a of the block layer 14 in a plan view of the substrate 10.

[0112] 2E , a p-type semiconductor layer 28 is formed by crystal growth (third crystal growth) so as to cover the recessed portion 26. For example, p-type GaN is grown as the p-type semiconductor layer 28 by epitaxial growth so as to cover the entire upper surface of the cap layer 27, including the inner surface of the recessed portion 26 and the sidewall surface of the opening 27 h.

[0113] 2F , portions of the p-type semiconductor layer 28 and the cap layer 27 are removed to separate the p-type semiconductor layer 28 into a threshold adjustment layer 28A and a p-type semiconductor layer 28B, and to separate the cap layer 27 into a first portion 27A and a second portion 27B. The removal of the portions of the p-type semiconductor layer 28 and the cap layer 27 is performed by forming a resist mask by photolithography and then performing dry etching, similar to the formation of the vertical conduction opening 20.

[0114] 2G, a source opening 30 is formed so as to penetrate the electron supply layer 23 and the electron transit layer 22. The source opening 30 is formed by forming a resist mask by photolithography and then performing dry etching, similar to the formation of the vertical conduction opening 20.

[0115] Next, as shown in FIG. 2H , the gate electrode 32, the source electrode 34, and the ohmic electrode 35 are formed. For example, a metal film is formed by sputtering or EB (Electron Beam) deposition using a metal material that can be ohmic-contacted to an n-type nitride semiconductor, and then the source electrode 34 is formed in a predetermined shape by etching or lift-off. Next, a metal film is formed by sputtering or EB deposition using a metal material that can be ohmic-contacted to a p-type nitride semiconductor, and then the gate electrode 32 and the ohmic electrode 35 are formed in a predetermined shape by etching or lift-off. In other words, the gate electrode 32 and the ohmic electrode 35 can be formed in the same process using the same material. This allows for simplification of the manufacturing process. Note that the gate electrode 32 and the ohmic electrode 35 may be formed in different processes using different materials.

[0116] Next, the nitride semiconductor device 1 shown in FIG. 1 is manufactured by forming an insulating layer 40, a source wiring 50, and a drain electrode 38. For example, first, the insulating layer 40 is formed by plasma CVD, atomic layer deposition (ALD), or the like so as to cover the gate electrode 32, the source electrode 34, the ohmic electrode 35, and the like. Then, openings that expose at least a portion of the ohmic electrode 35 and the source electrode 34 are formed in the insulating layer 40 by dry etching or the like. Next, the source wiring 50 is formed by plating or the like so as to contact the ohmic electrode 35 and the source electrode 34 within the formed opening. Also, although not shown, a gate wiring, a source pad, a gate pad, and the like connected to the gate electrode 32 are also formed. Finally, the drain electrode 38 is formed on the lower surface of the substrate 10 by sputtering, EB evaporation, or the like.

[0117] Through the above steps, the nitride semiconductor device 1 shown in Fig. 1 is manufactured. Note that the above-described manufacturing method is merely an example, and the order of steps and specific processing can be changed as appropriate.

[0118] [Characteristic Configuration] Next, the main characteristic configuration of the nitride semiconductor device 1 according to this embodiment will be described. Specifically, the cap layer 27 and the structure in its vicinity will be described with reference to Fig. 3. Fig. 3 is an enlarged cross-sectional view of a main part of the nitride semiconductor device 1 according to this embodiment. Note that the insulating layer 40 and the source wiring 50 are not shown in Fig. 3.

[0119] 3 shows areas A1 and A2 and areas B1 and B2. In a plan view of the substrate 10, both areas A1 and A2 are areas of the upper surface 23a of the electron supply layer 23 where the p-type semiconductor layer 28 is provided. Specifically, in area A1, a threshold adjustment layer 28A of the p-type semiconductor layer 28 and a first portion 27A of the cap layer 27 are provided. Note that the first portion 27A is provided in an area of ​​area A1 that does not overlap the recessed portion 26 in a plan view and is not provided within the recessed portion 26. In area A2, a p-type semiconductor layer 28B of the p-type semiconductor layer 28 and a second portion 27B of the cap layer 27 are provided. The second portion 27B is provided throughout the entire area A2.

[0120] In a plan view of the substrate 10, ranges B1 and B2 are ranges of the upper surface 23a of the electron supply layer 23 where the p-type semiconductor layer 28 is not provided. Neither the p-type semiconductor layer 28 nor the cap layer 27 is provided in ranges B1 and B2. Range B1 is a region between the threshold adjustment layer 28A and the first portion 27A of the cap layer 27, and the source opening 30. Range B2 is a region between the threshold adjustment layer 28A and the first portion 27A of the cap layer 27, and the p-type semiconductor layer 28B and the second portion 27B of the cap layer 27.

[0121] In the nitride semiconductor device 1, the Si concentration in the upper surface 23 a of the electron supply layer 23 in the ranges B1 and B2 is lower than the Si concentration in the upper surface 27 a of the cap layer 27 in the ranges A1 and A2. That is, in the ranges B1 and B2, pile-up of Si is suppressed along the upper surface 23 a of the electron supply layer 23. This makes it difficult for a leakage current path to be formed along the upper surface 23 a of the electron supply layer 23, thereby suppressing the leakage current in the nitride semiconductor device 1.

[0122] Si is present in a manufacturing environment, such as a clean room, in which the nitride semiconductor device 1 is manufactured, and is difficult to completely remove. Therefore, if a device (wafer) in the middle of manufacturing is exposed to the atmosphere in a clean room, Si may adhere to the device surface, and the Si adhered to the surface may penetrate into the device in subsequent processes. For example, after forming the electron supply layer 23 by crystal growth, the device must be transported from a growth furnace to an etching apparatus to form a recess 26 in the electron supply layer 23, and the device is exposed to the atmosphere. If Si adheres to the surface of the electron supply layer 23, heat generated during subsequent crystal growth processes, such as the formation of the p-type semiconductor layer 28 shown in FIG. 2E, will cause Si to diffuse into the electron supply layer 23. Ultimately, Si may pile up on the surface of the electron supply layer 23, potentially forming a path for leakage current.

[0123] The present inventors performed SIMS (Secondary Ion Mass Spectrometry) analysis on prototype nitride semiconductor devices and found that the degree of diffusion of Si attached to the surface into the layer differs between a nitride semiconductor layer mainly composed of GaN and a nitride semiconductor layer mainly composed of AlGaN. Specifically, it was found that the diffusion of Si is suppressed in a nitride semiconductor layer mainly composed of GaN compared to a nitride semiconductor layer mainly composed of AlGaN.

[0124] Therefore, in this embodiment, as shown in FIG. 2C , after the electron supply layer 23 is formed, the cap layer 27 containing GaN as its main component is formed continuously without exposure to the atmosphere. Therefore, during the subsequent exposure to the atmosphere, the electron supply layer 23 is not exposed, but the cap layer 27 is exposed. Therefore, Si adheres to the upper surface 27 a of the cap layer 27. The cap layer 27 contains GaN as its main component, and Si diffusion is suppressed more than in the electron supply layer 23 containing AlGaN as its main component. Therefore, diffusion of Si adhered to the upper surface 27 a of the cap layer 27 is suppressed within the cap layer 27, and the amount of Si that reaches the electron supply layer 23 is sufficiently reduced.

[0125] The maximum film thickness Dmax of the cap layer 27 is, for example, 10 nm or more. In this embodiment, the film thickness of the cap layer 27 is substantially uniform. That is, the film thickness of the cap layer 27 is 10 nm or more at any location. This sufficiently suppresses diffusion of Si attached to the upper surface 27 a of the cap layer 27 into the electron supply layer 23. Pile-up on the upper surface 23 a of the electron supply layer 23 is also suppressed, thereby suppressing leakage current.

[0126] For example, the Si concentration in the upper surface 27a of the cap layer 27 within the ranges A1 and A2 is 1×10 １７ cm －３ The Si concentration in the upper surface 27a of the cap layer 27 within the ranges A1 and A2 is 2×10 １７ cm －３ It may be 5×10 or more. １７ cm －３ The Si concentration in the upper surface 23 a of the electron supply layer 23 within the ranges B1 and B2 may be 1×10 １７ cm －３ Alternatively, the Si concentration in the upper surface 23 a of the electron supply layer 23 within the ranges B1 and B2 is less than 5×10 １７ cm －３ It may be 1×10 or less, １６ cm －３ It may be the following:

[0127] [Modifications] Next, a description will be given of several modifications of the first embodiment. In the following description, differences from the nitride semiconductor device 1 according to the first embodiment will be mainly described, and descriptions of commonalities will be omitted or simplified.

[0128] <Modification 1> Fig. 4 is a cross-sectional view of a nitride semiconductor device 2 according to Modification 1. The nitride semiconductor device 2 shown in Fig. 4 differs from the nitride semiconductor device 1 in that it includes a cap layer 127 instead of the cap layer 27.

[0129] The cap layer 127 has a different polarity from the cap layer 27. Specifically, the cap layer 127 contains p-type GaN as a main component. The cap layer 127 has, for example, the same composition and carrier concentration as the p-type semiconductor layer 28. By containing p-type GaN as a main component, the cap layer 127 can suppress a decrease in breakdown voltage even if the film quality of the p-type semiconductor layer 28 formed thereon deteriorates.

[0130] 5 is a cross-sectional view illustrating the effect of the nitride semiconductor device 2 according to Modification 1. Specifically, Fig. 5 shows a device in the middle of manufacture, corresponding to the step shown in Fig. 2E. That is, Fig. 5 shows the cross-sectional configuration at the point when the p-type semiconductor layer 28 has been formed so as to cover the recess portion 26 and the cap layer 127.

[0131] The p-type semiconductor layer 28 is provided along the shape of the vertical conductive opening 20 and is susceptible to process damage from the regrowth interface (specifically, the upper surface 27a of the cap layer 27). Process damage may cause cracks 28c as shown in FIG. 5 to form in the p-type semiconductor layer 28. If the gate electrode 32 is formed with the cracks 28c remaining, the gate electrode 32 and the 2DEG 24 may come close to each other, making it impossible to ensure sufficient breakdown voltage. This prevents the device from functioning as an FET, resulting in a decrease in yield.

[0132] In contrast, in the nitride semiconductor device 2 according to this modification, the cap layer 127 contains p-type GaN as a main component, and therefore the cap layer 127 can perform the same function as the p-type semiconductor layer 28. This makes it possible to ensure a sufficient breakdown voltage and increase the yield.

[0133] 6 is a cross-sectional view of a nitride semiconductor device 3 according to Modification 2. The nitride semiconductor device 3 shown in Fig. 6 differs from the nitride semiconductor device 1 in that it includes a cap layer 227, a p-type semiconductor layer 228, and a gate electrode 232 instead of the cap layer 27, the p-type semiconductor layer 28, the gate electrode 32, and the ohmic electrode 35.

[0134] The cap layer 227 and the p-type semiconductor layer 228 correspond to the cap layer 27 and the p-type semiconductor layer 28, respectively, and are different in that they are not separated inside and outside the range overlapping with the vertical conductive opening 20 in a planar view. Specifically, both the cap layer 227 and the p-type semiconductor layer 228 are provided along the upper surface 23a of the electron supply layer 23 so as to continuously cover from a position overlapping with the bottom surface 20a of the vertical conductive opening 20 to a position overlapping with the recess portion 26 in a planar view of the substrate 10. The cap layer 227 has an opening 27h provided at a position overlapping with the recess portion 26 in a planar view.

[0135] The gate electrode 232 corresponds to the gate electrode 32 and is different in that it is provided so as to overlap not only the recess portion 26 but also the bottom surface 20 a of the vertical conductive opening 20 in a plan view of the substrate 10. Specifically, the gate electrode 232 is provided along the upper surface of the p-type semiconductor layer 228 so as to continuously cover the area from a position overlapping the bottom surface 20 a of the vertical conductive opening 20 to a position overlapping the recess portion 26 in a plan view of the substrate 10. That is, a portion of the gate electrode 232 is provided so as to overlap the vertical conductive opening 20, and another portion of the gate electrode 32 is provided so as to overlap the upper surface 14 a of the block layer 14.

[0136] The recessed portion 26 in the electron supply layer 23 causes the electron supply layer 23 to have different thicknesses depending on the region. Specifically, within the region overlapping the upper surface 14a of the block layer 14 in a plan view of the substrate 10, the thickness of the region without the recessed portion 26 (thick-film region) is greater than the thickness of the region with the recessed portion 26 (thin-film region). The thickness of the region with the recessed portion 26 refers to the thickness of the region of the electron supply layer 23 that overlaps the bottom surface of the recessed portion 26 in a plan view of the substrate 10. Each thickness is expressed as a length in a direction perpendicular to the upper surface 14a of the block layer 14. The maximum thickness of the electron supply layer 23 within the region overlapping the upper surface 14a of the block layer 14 in a plan view of the substrate 10 is smaller than the thickness of the inclined portion of the electron supply layer 23 that is provided along the side surface 20b of the vertical conductive opening 20. The thickness of the inclined portion is expressed as a length in a direction perpendicular to the side surface 20b.

[0137] The thickness of the electron supply layer 23 affects the concentration of the 2DEG 24 generated by piezoelectric polarization. Specifically, the thinner the electron supply layer 23, the lower the concentration of the 2DEG 24. Therefore, the thickness of the electron supply layer 23 where the recessed portion 26 is provided is the smallest, and therefore the concentration of the 2DEG 24 directly below the recessed portion 26 is the lowest. As a result, if the 2DEG 24 disappears directly below the recessed portion 26, the FET is turned off. However, if the 2DEG 24 is generated directly below the recessed portion 26, the FET is also generated in other portions, and the FET is turned on. In other words, the threshold voltage of the FET is determined based on the thickness of the portion of the electron supply layer 23 where the recessed portion 26 is provided, and is not affected by the thickness of other portions.

[0138] Therefore, by increasing the thickness of the portion of the electron supply layer 23 where the recessed portion 26 is not provided, the concentration of the 2DEG 24 can be increased, thereby reducing the on-resistance. Even if the thickness of the portion where the recessed portion 26 is not provided is increased, the threshold voltage of the FET is not substantially affected. On the other hand, by adjusting the thickness of the portion where the recessed portion 26 is provided, a desired threshold voltage can be achieved. As described above, according to this embodiment, it is possible to achieve both a reduction in on-resistance and an improvement in the design freedom of the threshold voltage.

[0139] The concentration of the 2DEG 24 generated by piezoelectric polarization is affected not only by the thickness but also by the composition of the electron supply layer 23. Therefore, the threshold voltage of the FET can be adjusted by the thickness and composition of the portion where the recessed portion 26 is provided. For example, if the portion where the recessed portion 26 is provided is made of AlGaN, increasing the Al composition ratio enhances the polarization effect and increases the concentration of the 2DEG 24, thereby lowering the threshold voltage. On the other hand, decreasing the Al composition ratio reduces the polarization effect and decreases the concentration of the 2DEG 24, thereby increasing the threshold voltage.

[0140] In the present embodiment, the Al composition ratio of the electron supply layer 23 is uniform regardless of the region. That is, the Al composition ratio of the electron supply layer 23 in the region where the recessed portion 26 is provided and the Al composition ratio of the region where the recessed portion 26 is not provided are the same, and are, for example, 10% to 50%, but may also be 15% to 25%.

[0141] It should be noted that the on-resistance can be reduced by thickening the electron supply layer 23. However, on the other hand, there is a risk that misfit dislocations or cracks may occur due to the relaxation of stress caused by lattice mismatch. If misfit dislocations or cracks occur, the stress caused by strain is relaxed, thereby reducing piezoelectric polarization, or the cracks may become a path for leakage current. For this reason, the thickness of the portion of the electron supply layer 23 where the recessed portion 26 is not provided needs to be set to an upper limit value or less that prevents the occurrence of misfit dislocations or cracks.

[0142] The upper limit depends on the composition of the electron supply layer 23. For example, when the Al composition ratio is 20%, the upper limit of the thickness of the portion of the electron supply layer 23 where the recessed portion 26 is not provided is 70 nm. This makes it possible to suppress the occurrence of misfit dislocations and cracks. Note that the higher the Al composition ratio, the lower the upper limit of the thickness of the portion of the electron supply layer 23 where the recessed portion 26 is not provided tends to be. For example, when the Al composition ratio is 25%, the upper limit of the thickness is 45 nm, and when the Al composition ratio is 30%, the upper limit of the thickness is 22 nm.

[0143] The thickness of the portion where the recessed portion 26 is provided is, for example, half or less of the thickness of the portion where the recessed portion 26 is not provided, but may be one-third or less. The lower limit of the thickness of the portion where the recessed portion 26 is provided is, for example, 10 nm, but may be 5 nm. The thickness of the portion where the recessed portion 26 is provided can be, for example, 20 nm. This allows the threshold voltage of the FET to be greater than 0 V, thereby realizing a normally-off FET.

[0144] In this modification, the cap layer 227 may contain p-type GaN as a main component, similar to the cap layer 127 according to the modification 1. As in the modification 1, it is possible to ensure a sufficient breakdown voltage and increase the yield.

[0145] Furthermore, for example, the gate electrode 232 and the recess portion 26 may not overlap in a plan view of the substrate 10. For example, the gate electrode 232 may overlap only the bottom surface 20 a of the vertical conductive opening 20, or only the bottom surface 20 a and the side surface 20 b, and may not overlap the top surface of the block layer 14.

[0146] 7 is a cross-sectional view of a nitride semiconductor device 4 according to Modification 3. The nitride semiconductor device 4 shown in Fig. 7 differs from the nitride semiconductor device 1 in the structure in the vicinity of the source electrode 34. Specifically, the nitride semiconductor device 4 differs in that an opening 25 penetrating the nitride semiconductor layer 21 is provided, and that the nitride semiconductor device 4 further includes a p-type semiconductor layer 29 and an ohmic electrode 36.

[0147] The opening 25 is an example of a third opening that penetrates the cap layer 27, the electron supply layer 23, and the electron transit layer 22 to reach the block layer 14. A bottom surface 25a of the opening 25 is part of the upper surface of the block layer 14. As shown in FIG. 1 , the bottom surface 25a is located below the lower surface of the electron transit layer 22. The lower surface of the electron transit layer 22 corresponds to the interface between the electron transit layer 22 and the block layer 14. The bottom surface 25a is, for example, parallel to the main surface of the substrate 10. In this modification, the side surface 25b of the opening 25 is perpendicular to the bottom surface 25a, but may be inclined with respect to the bottom surface 25a.

[0148] In this modification, the opening 25 is formed after the cap layer 27 is formed in the step described with reference to Fig. 2C and before the p-type semiconductor layer 28 is formed in the step described with reference to Fig. 2E. It is noted that the formation of the opening 25 and the formation of the recessed portion 26 may be performed in any order. The formation of the opening 25 is performed by forming a resist mask by photolithography and then dry etching, similar to the formation of the recessed portion 26.

[0149] The p-type semiconductor layer 29 is an example of a p-type seventh nitride semiconductor layer provided in the opening 25 so as to be in contact with the block layer 14. Specifically, the p-type semiconductor layer 29 covers and is in contact with the bottom surface 25 a and the side surface 25 b of the opening 25, and is in contact with the block layer 14 at the bottom surface 25 a and parts of the side surface 25 b. The p-type semiconductor layer 29 also covers the upper surface of the nitride semiconductor layer 21. Specifically, the p-type semiconductor layer 29 overlaps the electron supply layer 23 in a plan view and covers and is in contact with part of the upper surface of the electron supply layer 23. More specifically, the p-type semiconductor layer 29 covers and is in contact with a part of the upper surface of the electron supply layer 23 that is located between the opening 25 and the source opening 30, of the upper surface of the electron supply layer 23.

[0150] The p-type semiconductor layer 29 has a thickness of 200 nm and a carrier concentration of 5×10 １７ cm －３ The p-type semiconductor layer 29 is a film made of p-type GaN, which has the same composition and carrier concentration as the p-type semiconductor layer 28. Note that the thickness and carrier concentration of the p-type semiconductor layer 29 are merely examples and can be changed as appropriate.

[0151] 2E is patterned into a predetermined shape to form the p-type semiconductor layer 29. That is, in the method for manufacturing the nitride semiconductor device 4 according to this modification, the p-type semiconductor layer 28 is a layer that serves as the base for the threshold adjustment layer 28A and the p-type semiconductor layers 28B and 29. The p-type semiconductor layer 28 is separated into the threshold adjustment layer 28A, the p-type semiconductor layer 28B, and the p-type semiconductor layer 29 by removing a portion of it.

[0152] The ohmic electrode 36 is an example of a third electrode electrically connected to the p-type semiconductor layer 29. The ohmic electrode 36 is also electrically connected to the source electrode 34. In this embodiment, the ohmic electrode 36 is in contact with and covers the upper surface of the p-type semiconductor layer 29 and the upper surface of the source electrode 34.

[0153] The ohmic electrode 36 can be made of a material that forms an ohmic contact with a p-type nitride semiconductor such as p-type GaN. For example, Pd, a Ni-based material, WSi, Au, or the like can be used as the material for forming the ohmic electrode 36. The ohmic electrode 36 is formed in the same process as the gate electrode 32 and the ohmic electrode 35.

[0154] Furthermore, in this modification, the source opening 30 does not penetrate the nitride semiconductor layer 21. A bottom surface 30 a of the source opening 30 is part of the upper surface of the electron transit layer 22. The bottom surface 30 a is located lower than the lower surface of the electron supply layer 23. The lower surface of the electron supply layer 23 corresponds to the heterointerface between the electron supply layer 23 and the electron transit layer 22. The bottom surface 30 a is located lower than the 2DEG 24 generated in the vicinity of the heterointerface. In other words, the 2DEG 24 is exposed on the side surface 30 b of the source opening 30.

[0155] The source opening 30 may penetrate the electron transit layer 22 or reach the blocking layer 14. The source opening 30 may be formed integrally with the opening 25. That is, the bottom surface 30a of the source opening 30 and the bottom surface 25a of the opening 25 may be continuous. When the source opening 30 is shallower than the opening 25, the edge of the bottom surface 30a of the source opening 30 may coincide with the upper end of the side surface 25b of the opening 25.

[0156] In the nitride semiconductor device 4 according to this modification, the opening 25 for exposing the block layer 14 is formed by dry etching. Therefore, etching damage may remain on the upper surface of the block layer 14 exposed as the bottom surface 25 a of the opening 25. Therefore, even if an ohmic electrode 36 is formed so as to be in direct contact with the block layer 14, it is difficult to achieve an ohmic connection to the block layer 14.

[0157] In contrast, in this modification, the ohmic electrode 36 is electrically connected to the block layer 14 via the p-type semiconductor layer 29. The surface of the p-type semiconductor layer 29 is formed by epitaxial growth and is free from etching damage. This allows for good ohmic contact between the ohmic electrode 36 and the p-type semiconductor layer 29, thereby reducing contact resistance. Furthermore, because the p-type semiconductor layer 29 and the block layer 14 are layers made of the same p-type nitride semiconductor, charge transfer is smooth.

[0158] Therefore, when the FET is turned off, charges accumulated in the block layer 14 near the side surface 20b of the vertical conductive opening 20 can be efficiently extracted to the ohmic electrode 36 via the p-type semiconductor layer 29 to the ohmic electrode 36 when the FET is turned on. Simply put, the potential of the block layer 14 is likely to return to a normal value (e.g., 0 V) ​​immediately after switching from off to on. This makes it possible to suppress a decrease in the concentration of the 2DEG 24 when the FET is turned on, and to suppress an increase in on-resistance. A highly reliable nitride semiconductor device 4 can be realized, with on / off switching being performed appropriately and with high switching accuracy.

[0159] In this embodiment, a pn junction is formed between the p-type semiconductor layer 29 and the p-type block layer 14 and the n-type drift layer 12, thereby forming a pn diode with the ohmic electrode 36 as the anode electrode and the drain electrode 38 as the cathode electrode. The FET may perform a free-wheeling operation, that is, an operation in which the source electrode 34 has a higher potential than the drain electrode 38 and a current (called a free-wheeling current) flows from the source electrode 34 to the drain electrode 38. The free-wheeling current may flow through a first path through the 2DEG 24 and a second path through the pn diode. The free-wheeling current is more likely to flow through the path with the lower resistance of the first or second path.

[0160] If the p-type semiconductor layer 29 is not provided and the source electrode 34 or the ohmic electrode 36 is in contact with the block layer 14, a good ohmic connection cannot be achieved, resulting in high contact resistance. For this reason, the main path for the return current is the first path. However, when the return current is caused to flow through the first path, the drive voltage applied between the drain and source also increases. This is because, in the case of return operation, a negative bias must be applied to the gate electrode 32 to suppress malfunction, and a drain voltage that is smaller (with a larger absolute value) than the negative bias is applied.

[0161] In contrast, in this modification, the contact resistance between the ohmic electrode 36 and the p-type semiconductor layer 29 is low, so the return current is more likely to flow through the second path. The second path is not affected by the negative bias applied to the gate electrode 32, and the drive voltage applied between the drain and source only needs to exceed the turn-on voltage of the pn diode, which is smaller than when the current flows through the first path. Therefore, the drive voltage can be reduced, and loss can be reduced.

[0162] In this modification, the nitride semiconductor device 4 may include the cap layer 127 according to the first modification instead of the cap layer 27. Furthermore, the nitride semiconductor device 4 may include the cap layer 227, the p-type semiconductor layer 228, and the gate electrode 232 according to the second modification instead of the cap layer 27, the p-type semiconductor layer 28, the gate electrode 32, and the ohmic electrode 35.

[0163] Furthermore, the ohmic electrode 36 and the source electrode 34 do not need to be in direct contact with each other, and may be electrically connected via a via, a wiring, etc. Alternatively, the ohmic electrode 36 and the source electrode 34 may be integrally formed using the same material.

[0164] <Modification 4> Fig. 8 is an enlarged cross-sectional view of a main portion of a nitride semiconductor device 5 according to Modification 4. The nitride semiconductor device 5 shown in Fig. 8 differs from the nitride semiconductor device 1 in that it includes a cap layer 327 instead of the cap layer 27. Note that the insulating layer 40 and the source wiring 50 are not shown in Fig. 8.

[0165] The cap layer 327 includes thick film portions 327A and 327B and a thin film portion 327C. The thick film portions 327A and 327B are portions of the cap layer 327 that overlap the p-type semiconductor layer 28 in a planar view of the substrate 10. The thin film portion 327C is a portion of the cap layer 327 that does not overlap the p-type semiconductor layer 28 in a planar view of the substrate 10.

[0166] The thick film portion 327A is provided within the range A1 and overlaps the threshold adjustment layer 28A in a plan view of the substrate 10. Specifically, the thick film portion 327A is provided between the threshold adjustment layer 28A and the upper surface 23a of the electron supply layer 23 and is in contact with each of them. An opening 27h is provided in the thick film portion 327A. The thick film portion 327A is substantially the same as the first portion 27A of the cap layer 27.

[0167] The thick film portion 327B is provided within the range A2 and overlaps the p-type semiconductor layer 28B in a plan view of the substrate 10. Specifically, the thick film portion 327B is provided between the p-type semiconductor layer 28B and the upper surface 23a of the electron supply layer 23 and is in contact with both. The thick film portion 327B is substantially the same as the second portion 27B of the cap layer 27.

[0168] The thin film portion 327C is provided within the ranges B1 and B2, and does not overlap either the threshold adjustment layer 28A or the p-type semiconductor layer 28B in a plan view of the substrate 10. Specifically, the thin film portion 327C is provided between the insulating layer 40 and the upper surface 23a of the electron supply layer 23, and is in contact with both.

[0169] The thickness D2 of the thin film portion 327C is smaller than the thickness D1 of the thick film portions 327A and 327B. For example, the thickness D2 is equal to or less than half the thickness D1, but is not limited to this.

[0170] In this modification, the Si concentration of each of the upper surface 327Aa of the thick film portion 327A and the upper surface 327Ba of the thick film portion 327B is lower than the Si concentration of the upper surface 23a of the electron supply layer 23. Furthermore, the Si concentration of the upper surface 327Ca of the thin film portion 327C is lower than the Si concentration of the upper surface 327Aa of the thick film portion 327A and the upper surface 327Ba of the thick film portion 327B. Si that adheres to the surface when the cap layer 327 is formed is removed when the thin film portion 327C is formed. Therefore, during the subsequent crystal growth of the p-type semiconductor layer 28, the Si is removed, suppressing Si diffusion and lowering the Si concentration.

[0171] In the nitride semiconductor device 5 according to this modification, the cap layer 327 is left thin in the areas B1 and B2 that do not overlap with the p-type semiconductor layer 28. This makes it possible to reduce electron traps such as surface states and suppress current collapse. The cap layer 327 having the thick portions 327A and 327B and the thin portion 327C is formed by partially leaving the cap layer 327 that is not covered with the p-type semiconductor layer 28 without completely removing it in the process described with reference to FIG. 2F .

[0172] <Others> For example, in the nitride semiconductor devices 1, 2, 3, 4, and 5, a first high-resistance layer having a higher resistance than the block layer 14 may be provided between the drift layer 12 and the block layer 14. The first high-resistance layer is, for example, a 100 nm thick film made of carbon-doped GaN (C—GaN). The carbon concentration of the first high-resistance layer is, for example, 3×10 １７ cm －３ That's all, but 1 x 10 １８ cm －３ The first high-resistance layer is provided in contact with each of the drift layer 12 and the block layer 14. The first high-resistance layer may contain n-type impurities such as Si. The concentration of the n-type impurities contained in the first high-resistance layer is lower than the carbon concentration and oxygen concentration of the first high-resistance layer, and may be, for example, 5×10 １６ cm －３ or less than or equal to 2×10 １６ cm －３or less. Providing the first high-resistance layer can suppress punch-through and increase the breakdown voltage of the nitride semiconductor devices 1, 2, 3, 4, and 5. When the first high-resistance layer is formed, the vertical conduction opening 20 penetrates the first high-resistance layer. This prevents the first high-resistance layer from being located on the path of the drain current when the FET is on, thereby suppressing an increase in on-resistance.

[0173] Furthermore, for example, in the nitride semiconductor devices 1, 2, 3, 4, and 5, a second high-resistance layer having a higher resistance than the block layer 14 may be provided between the block layer 14 and the electron transit layer 22. For example, the second high-resistance layer is an undoped GaN film with a thickness of 200 nm, but it may also be a carbon-doped GaN film. The second high-resistance layer is formed by crystal growth continuously from the formation of the block layer 14. When the second high-resistance layer is formed, the vertical conduction opening 20 penetrates the second high-resistance layer. By providing the second high-resistance layer, an npn parasitic transistor is not formed by the 2DEG 24, the p-type block layer 14, and the n-type drift layer 12, and malfunction of the nitride semiconductor devices 1, 2, 3, 4, and 5 can be suppressed.

[0174] The source opening 30 may not be provided. In this case, the source electrode 34 is provided on the upper surface of the electron supply layer 23.

[0175] Furthermore, for example, the distance between the bottom surface 20a of the vertical conductive opening 20 and the substrate 10 may be shorter than the distance between the block layer 14 and the substrate 10. This allows the electric field between the drain and the source to be dispersed also to the lower surface of the p-type semiconductor layer 28. This makes it possible to suppress the electric field concentration at the lower end of the block layer 14, thereby increasing the breakdown voltage of the FET.

[0176] Second Embodiment Next, a second embodiment will be described. The nitride semiconductor device according to the second embodiment is different from the first embodiment in that it is a lateral device. The following description will focus on the differences from the first embodiment, and description of the commonalities will be omitted or simplified.

[0177] [Configuration] FIG. 9 is a cross-sectional view of a nitride semiconductor device 401 according to this embodiment. The nitride semiconductor device 401 shown in FIG. 9 is a normally-off lateral FET. The nitride semiconductor device 401 performs modulation according to the potential applied to the gate electrode 432. For example, when 0 V or a negative potential is applied to the gate electrode 432, no current flows between the drain electrode 438 and the source electrode 434. That is, the nitride semiconductor device 401 is in a non-conductive state (off). When a positive potential is applied to the gate electrode 432, a current flows from the drain electrode 438 to the source electrode 434. That is, the nitride semiconductor device 401 is in a conductive state (on). The current flowing from the drain electrode 438 to the source electrode 434 when the device is on is called a drain current. The drain current flows in a direction parallel to the main surface of the substrate 410 (i.e., laterally) near the interface between the electron transit layer 422 and the electron supply layer 423. The main path of the drain current does not pass through the substrate 410.

[0178] 9 , the nitride semiconductor device 401 includes a substrate 410, a buffer layer 412, a back barrier layer 414, a nitride semiconductor layer 421, a cap layer 427, a threshold adjustment layer 428, a gate electrode 432, a source electrode 434, and a drain electrode 438. The nitride semiconductor layer 421 includes an electron transit layer 422, an electron supply layer 423, and a 2DEG 424. The nitride semiconductor device 401 further includes an insulating layer 440 and a source wiring 450.

[0179] The nitride semiconductor device 401 is a nitride semiconductor device in which a semiconductor layer including a channel contains a nitride semiconductor as a main component, specifically, a buffer layer 412, a back barrier layer 414, an electron transit layer 422, an electron supply layer 423, a cap layer 427, and a threshold adjustment layer 428 each contain a nitride semiconductor as a main component.

[0180] The substrate 410 is made of a nitride semiconductor. The shape of the substrate 410 in plan view is, for example, rectangular, but is not limited to this. The substrate 410 has, for example, a thickness of 300 μm and a carrier concentration of 5×10 １８ cm －３ n ＋The substrate is made of GaN.

[0181] The substrate 410 may be a Si substrate, a SiC substrate, a ZnO substrate, etc. The substrate 410 may also be an insulating substrate such as sapphire.

[0182] The buffer layer 412 is provided above the substrate 410. The buffer layer 412 is, for example, a 7 μm-thick film made of undoped GaN. The buffer layer 412 may be provided in contact with the upper surface of the substrate 410, or another nitride semiconductor layer may be provided between the buffer layer 412 and the substrate 410.

[0183] The buffer layer 412 may be an insulating layer or a semi-insulating layer. For example, the buffer layer 412 may be a film made of carbon-doped GaN (C—GaN). The carbon concentration of the buffer layer 412 is, for example, 3×10 １７ cm －３ That's all, but 1 x 10 １８ cm －３ The buffer layer 412 may contain n-type impurities such as Si. The concentration of the n-type impurities contained in the buffer layer 412 is lower than the carbon concentration and oxygen concentration of the buffer layer 412, and may be, for example, 5×10 １６ cm －３ or less than or equal to 2×10 １６ cm －３ It may be the following:

[0184] The back barrier layer 414 is provided above the buffer layer 412. The back barrier layer 414 is made of, for example, an undoped AlGaN layer.

[0185] The back barrier layer 414 may be an insulating layer or a semi-insulating layer. For example, the back barrier layer 414 may be a film made of carbon-doped AlGaN (C-AlGaN). The carbon concentration of the back barrier layer 414 is, for example, 3×10 １７ cm －３ That's all, but 1 x 10 １８ cm －３The back barrier layer 414 may be made up of two layers: an undoped layer that is not intentionally doped with impurities, and a layer that is doped with carbon.

[0186] The provision of the buffer layer 412 and the back barrier layer 414 can suppress so-called punch-through, in which electrons leak from the 2DEG 424 to the substrate 410. This can increase the breakdown voltage of the nitride semiconductor device 401. Note that at least one of the buffer layer 412 and the back barrier layer 414 does not necessarily have to be provided.

[0187] The electron transit layer 422 is an example of a first nitride semiconductor layer provided above the substrate 410. Specifically, the electron transit layer 422 is provided on the upper surface of the back barrier layer 414. The electron transit layer 422 is, for example, a film made of undoped GaN with a thickness of 150 nm. Note that although the electron transit layer 422 is assumed to be undoped, it may be partially doped with Si to be n-type.

[0188] The electron transit layer 422 has a channel region. Specifically, a 2DEG 424 that serves as a channel is generated near the interface between the electron transit layer 422 and the electron supply layer 423. The 2DEG 424 extends parallel to the major surface of the substrate 410 along the interface between the electron transit layer 422 and the electron supply layer 423.

[0189] 9, an AlN layer having a thickness of about 1 nm is provided between the electron transit layer 422 and the electron supply layer 423. This suppresses alloy scattering, improves channel mobility, and makes it possible to reduce on-resistance. Note that the AlN layer is not necessarily required.

[0190] The electron supply layer 423 is an example of a second nitride semiconductor layer containing Al and is provided above the electron transit layer 422. Specifically, the electron supply layer 423 is provided so as to cover the upper surface of the electron transit layer 422. The electron supply layer 423 is, for example, a film made of undoped AlGaN with a thickness of 50 nm or 60 nm. The electron supply layer 423 has a larger band gap than the electron transit layer 422. Therefore, an AlGaN / GaN heterointerface is formed between the electron supply layer 423 and the electron transit layer 422. The electron supply layer 423 supplies electrons to a channel region (2DEG 424) formed in the electron transit layer 422.

[0191] In this embodiment, the electron transit layer 422 and the electron supply layer 423 are both layers included in the nitride semiconductor layer 421 provided in the nitride semiconductor device 401. The nitride semiconductor layer 421 is provided above the substrate 410.

[0192] The electron supply layer 423 is provided with a recess 426. The recess 426 is a depression provided in the upper surface of the electron supply layer 423. By providing the recess 426, the electric field applied to the gate electrode 432 can be more easily concentrated at the end of the recess 426, thereby improving gate controllability. In addition, the thickness of the electron supply layer 423 can be increased in the portion where the recess 426 is not provided. This increases the concentration of the 2DEG 424, thereby reducing the on-resistance. Note that the recess 426 does not necessarily have to be provided.

[0193] The cap layer 427 is an example of a third nitride semiconductor layer that is provided above the electron supply layer 423 and contains GaN as a main component. For example, the cap layer 427 contains undoped GaN as a main component. Note that the cap layer 427 may contain p-type GaN as a main component, similar to the cap layer 127 according to the first modification.

[0194] In this embodiment, the cap layer 427 is provided only in a region overlapping the threshold adjustment layer 428 in a plan view of the substrate 10. That is, the cap layer 427 is not provided in a region that does not overlap the threshold adjustment layer 428. Specifically, the cap layer 427 is provided in a region A3 shown in FIG. 9 , but not in regions B3 and B4. Region B3 is the region between the threshold adjustment layer 428 and the source electrode 434, and region B4 is the region between the threshold adjustment layer 428 and the drain electrode 438. Note that the cap layer 427 is provided in a region within region A3 that does not overlap the recess portion 426 in a plan view, and is not provided within the recess portion 426. Furthermore, the cap layer 427 has an opening 427h, which is an example of a second opening, provided at a position that overlaps the recess portion 426 in a plan view of the substrate 10.

[0195] The threshold adjustment layer 428 is an example of a p-type fourth nitride semiconductor layer provided above the cap layer 427. Specifically, the threshold adjustment layer 428 is provided between the electron supply layer 423 and the gate electrode 432. In this embodiment, the threshold adjustment layer 428 is provided so as to fill the recess portion 426. The threshold adjustment layer 428 is disposed apart from each of the source electrode 434 and the drain electrode 438 and is electrically isolated from them.

[0196] The threshold adjustment layer 428 has a thickness of 200 nm and a carrier concentration of 5×10 １７ cm －３ The thickness and carrier concentration of the threshold adjustment layer 428 are merely examples and can be changed as appropriate.

[0197] The provision of the threshold adjustment layer 428 raises the potential of the conduction band edge of the channel portion. This reduces the carrier concentration directly below the gate electrode 432, shifting the threshold voltage of the FET to the positive side. This allows the nitride semiconductor device 401 to be easily realized as a normally-off FET. The threshold adjustment layer 428 may be a film made of p-type AlGaN.

[0198] The gate electrode 432 is an example of a first electrode that is provided above the threshold adjustment layer 428 and electrically connected to the threshold adjustment layer 428. Specifically, the gate electrode 432 is provided in contact with the upper surface of the threshold adjustment layer 428. The gate electrode 432 is formed using a conductive material such as a metal. For example, the gate electrode 432 may be made of a material that forms an ohmic contact with the p-type GaN layer, but is not limited to this, and may also be made of a material that forms a Schottky contact with the p-type GaN layer. For example, Pd, a Ni-based material, WSi, Au, etc. may be used.

[0199] The source electrode 434 and the drain electrode 438 are provided above the substrate 410 to sandwich the gate electrode 432. Specifically, the source electrode 434 is electrically connected to the electron transit layer 422 and is provided away from the threshold adjustment layer 428 and the gate electrode 432. The source electrode 434 is provided to sandwich the threshold adjustment layer 428 and the gate electrode 432 between itself and the drain electrode 438. The drain electrode 438 is electrically connected to the electron transit layer 422 and is provided away from the threshold adjustment layer 428 and the gate electrode 432.

[0200] The source electrode 434 and the drain electrode 438 are each formed using a conductive material such as a metal. Materials that can be ohmically connected to the n-type GaN layer by heat treatment, such as Ti / Al (a laminated structure of a Ti layer and an Al layer), can be used as materials for the source electrode 434 and the drain electrode 438. The source electrode 434 and the drain electrode 438 are formed, for example, using the same material in the same process.

[0201] At least one of the source electrode 434 and the drain electrode 438 may be provided so as to be in contact with the electron transit layer 422. Specifically, a source opening and a drain opening may be provided that penetrate the electron supply layer 423 and expose the electron transit layer 422.

[0202] The insulating layer 440 is provided above the gate electrode 432. Specifically, the insulating layer 440 is provided so as to cover the gate electrode 432, the threshold adjustment layer 428, the electron supply layer 423, the source electrode 434, and the drain electrode 438. The insulating layer 440 has a stacked structure of a plurality of insulating films. The plurality of insulating films may be made of, for example, SiN, SiO ２ , SiON, Al ２ O ３ The insulating layer 440 may have a single-layer structure of one insulating film.

[0203] The source wiring 450 is provided above the insulating layer 440 and is connected to each of the source electrodes 434 through an opening provided in the insulating layer 440. The source wiring 450 is formed using a conductive material such as a metal. For example, the source wiring 450 is a plated film made of Au.

[0204] In this embodiment, the source wiring 450 overlaps with the gate electrode 432 in a plan view of the substrate 410. The source wiring 450 extends from a position where it overlaps with the source electrode 434 in a plan view of the substrate 410, beyond the gate electrode 432, toward the drain electrode 438. The source wiring 450 functions as a source field plate that relieves the electric field applied between the gate and the drain. The source wiring 450 does not overlap with the drain electrode 438 in a plan view.

[0205] Although not shown in FIG. 9, a drain wiring electrically connected to the drain electrode 438 and a gate wiring electrically connected to the gate electrode 432 are provided above the insulating layer 440 .

[0206] [Manufacturing Method] The nitride semiconductor device 401 configured as above is manufactured by, for example, the following method.

[0207] First, a nitride semiconductor is crystal-grown on the main surface of the substrate 410 by epitaxial growth, such as MOVPE or HVPE. For example, a buffer layer 412, a back barrier layer 414, an electron transit layer 422, an electron supply layer 423, and a cap layer 427 are successively formed in this order on the main surface of the substrate 410. Then, a portion of the cap layer 427 and a portion of the electron supply layer 423 are removed by dry etching or the like to form an opening 427h in the cap layer 427 and a recess 426 in the electron supply layer 423. Then, a threshold adjustment layer 428 is formed by epitaxial growth, such as MOVPE or HVPE, so as to cover the recess 426. The threshold adjustment layer 428 is formed over the entire surface of the substrate 410, filling the opening 427h and the recess 426. Then, the threshold adjustment layer 428 and the cap layer 427 are patterned into a predetermined shape by dry etching or the like. As a result, the upper surface 423 a of the electron supply layer 423 is exposed.

[0208] Next, a metal film is formed by electron beam evaporation, sputtering, or the like so as to cover the threshold adjustment layer 428, and unnecessary portions are removed by etching, lift-off, or the like to form the gate electrode 432. Furthermore, a metal film is formed so as to cover the upper surface 423a of the electron supply layer 423, and unnecessary portions are removed by etching, lift-off, or the like to form the source electrode 434 and the drain electrode 438. Note that the formation of the gate electrode 432 and the formation of the source electrode 434 and the drain electrode 438 may be performed in any order. Furthermore, the source electrode 434 and the drain electrode 438 may be formed in different processes.

[0209] Next, the gate electrode 432, the source electrode 434, and the drain electrode 438 are formed, and then the insulating layer 440 is formed. The insulating layer 440 is formed by, for example, plasma CVD or atomic layer deposition. After the insulating layer 440 is formed, openings are formed in the insulating layer 440 by dry etching or the like to expose at least a portion of the source electrode 434 and the drain electrode 438. Thereafter, the source wiring 450 and the drain wiring (not shown) are formed so as to fill the openings. The source wiring 450 and the drain wiring are formed, for example, by sequentially depositing films of Ti, Al, Ni, etc. by sputtering or electron beam evaporation, followed by Au plating.

[0210] In this manner, it is possible to manufacture the nitride semiconductor device 401 shown in Fig. 9. The above-described method for manufacturing the nitride semiconductor device 401 is merely an example, and is not particularly limited.

[0211] [Characteristic Configuration] Next, the main characteristic configuration of the nitride semiconductor device 401 according to this embodiment will be described.

[0212] In the nitride semiconductor device 401 according to the present embodiment, the cap layer 427 contains GaN as a main component, as in the first embodiment. Therefore, the cap layer 427 can suppress the diffusion of Si. Therefore, the Si concentration in the upper surface 423 a of the electron supply layer 423 in the ranges B3 and B4 is lower than the Si concentration in the upper surface 427 a of the cap layer 427 in the range A3. That is, in the ranges B3 and B4, Si pile-up is suppressed along the upper surface 423 a of the electron supply layer 423. Since a leakage current path along the upper surface 423 a of the electron supply layer 423 is less likely to be generated, the leakage current in the nitride semiconductor device 401 can be suppressed.

[0213] The maximum film thickness of the cap layer 427 is, for example, 10 nm or more. In this embodiment, the film thickness of the cap layer 427 is substantially uniform. That is, the film thickness of the cap layer 427 is 10 nm or more at any location. This sufficiently suppresses diffusion of Si attached to the upper surface 427a of the cap layer 427 into the electron supply layer 423. Pile-up on the upper surface 423a of the electron supply layer 423 is also suppressed, thereby suppressing leakage current.

[0214] For example, the Si concentration in the upper surface 427a of the cap layer 427 within the range A3 is 1×10 １７ cm －３ The Si concentration in the upper surface 427a of the cap layer 427 within the range A3 is 2×10 １７ cm －３ It may be 5×10 or more. １７ cm －３ The Si concentration in the upper surface 423a of the electron supply layer 423 within the ranges B3 and B4 may be 1×10 １７ cm －３ Alternatively, the Si concentration in the upper surface 423a of the electron supply layer 423 within the ranges B3 and B4 is less than 5×10 １７ cm －３ It may be 1×10 or less, １６ cm －３ It may be the following:

[0215] <Modification> Next, a modification of the second embodiment will be described with reference to Fig. 10. In the following description, differences from the nitride semiconductor device 401 according to the second embodiment will be mainly described, and descriptions of commonalities will be omitted or simplified.

[0216] 10 is a cross-sectional view of a nitride semiconductor device 402 according to a modification of the second embodiment. The nitride semiconductor device 402 shown in FIG. 10 differs from the nitride semiconductor device 401 in that it includes a cap layer 527 instead of the cap layer 427.

[0217] The cap layer 527 includes a thick portion 527A and a thin portion 527C. The thick portion 527A is a portion of the cap layer 527 that overlaps with the threshold adjustment layer 428 in a planar view of the substrate 10. The thin portion 527C is a portion of the cap layer 527 that does not overlap with the threshold adjustment layer 428 in a planar view of the substrate 10.

[0218] The thick film portion 527A is provided within the range A3 and overlaps the threshold adjustment layer 428 in a plan view of the substrate 10. Specifically, the thick film portion 527A is provided between the threshold adjustment layer 428 and the upper surface 423a of the electron supply layer 423 and is in contact with each of them. An opening 427h is provided in the thick film portion 527A. The thick film portion 527A is substantially the same as the cap layer 427.

[0219] The thin film portion 527C is provided within ranges B3 and B4, and does not overlap the threshold adjustment layer 428 in a plan view of the substrate 10. Specifically, the thin film portion 527C is provided between the insulating layer 440 and the upper surface 423a of the electron supply layer 423, and is in contact with each of them.

[0220] The film thickness of the thin film portion 527C is smaller than the film thickness of the thick film portion 527A. For example, the film thickness of the thin film portion 527C is half or less of the film thickness of the thick film portion 527A, but is not limited to this.

[0221] In this modification, the Si concentration in the upper surface 527Aa of the thick film portion 527A is lower than the Si concentration in the upper surface 423a of the electron supply layer 423. Furthermore, the Si concentration in the upper surface 527Ca of the thin film portion 527C is lower than the Si concentration in the upper surface 527Aa of the thick film portion 527A. Si that adheres to the surface when the cap layer 527 is formed is removed when the thin film portion 527C is formed. Therefore, during the crystal growth of the threshold adjustment layer 428, which is performed later, the Si is removed, so that diffusion of Si is suppressed and the Si concentration is lowered.

[0222] In the nitride semiconductor device 402 according to this modification, the cap layer 527 is left thin in areas B3 and B4 that do not overlap with the threshold adjustment layer 428. This makes it possible to reduce electron traps such as surface states and suppress current collapse. The cap layer 527 having the thick portion 527A and the thin portion 527C is formed by leaving the portions of the cap layer 527 that are not covered with the threshold adjustment layer 428 partially intact without completely removing them.

[0223] While nitride semiconductor devices according to one or more aspects have been described above based on embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0224] For example, the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) gradually decreases from the substrate 10 side to the block layer 14 side. The donor concentration may be controlled by Si, which acts as a donor, or by carbon, which acts as an acceptor that compensates for Si. Alternatively, the drift layer 12 may have a stacked structure of multiple nitride semiconductor layers with different impurity concentrations. Specifically, the drift layer may be two-layered, with a layer with a low donor concentration disposed below the block layer and a layer with a high donor concentration disposed on the substrate side. By providing a vertical conductive opening 20 that penetrates the layer with a low donor concentration, current flows through the layer with a high donor concentration through the vertical conductive opening 20 when the transistor is on, thereby reducing the on-resistance. Conversely, when the transistor is off, a high electric field is maintained by the layer with a low donor concentration, thereby achieving both low on-resistance and high breakdown voltage.

[0225] The nitride semiconductor device may include a pn diode instead of or in addition to the FET. The pn diode has a pn junction between a p-type fourth nitride semiconductor layer and a 2DEG generated at a heterointerface between the second nitride semiconductor layer and the first nitride semiconductor layer. In this case, the nitride semiconductor device includes a first electrode serving as an anode electrode and a cathode electrode ohmically connected to the 2DEG. The pn diode may be a lateral diode or a vertical diode.

[0226] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

[0227] The nitride semiconductor device according to the present disclosure is useful as a power device used in, for example, power supply circuits of electrical equipment, inverter circuits, etc.

[0228] 1, 2, 3, 4, 5, 401, 402 Nitride semiconductor device 10, 410 Substrate 12 Drift layer 14 Block layer 14a, 23a, 27a, 327Aa, 327Ba, 327Ca, 423a, 427a, 527Aa, 527Ca Top surface 20 Vertical conduction opening 20a, 25a, 30a Bottom surface 20b, 25b, 30b Side surface 21, 421 Nitride semiconductor layer 22, 422 Electron transit layer 23, 423 Electron supply layer 24, 424 2DEG 25, 27h, 427h Opening 26, 426 Recessed portion 27, 127, 227, 327, 427, 527 Cap layer 27A First portion 27B Second portion 28, 28B, 29, 228 p-type semiconductor layer 28c crack 28A, 428 threshold adjustment layer 30 source opening 32, 232, 432 gate electrode 34, 434 source electrode 35, 36 ohmic electrode 38, 438 drain electrode 40, 440 insulating layer 50, 450 source wiring 327A, 327B, 527A thick film portion 327C, 527C thin film portion 412 buffer layer 414 back barrier layer

Claims

1. A nitride semiconductor device comprising: a substrate; a first nitride semiconductor layer provided above the substrate; a second nitride semiconductor layer containing Al provided above the first nitride semiconductor layer; a third nitride semiconductor layer containing GaN as a main component provided above the second nitride semiconductor layer; a p-type fourth nitride semiconductor layer provided above the third nitride semiconductor layer; and a first electrode provided above the fourth nitride semiconductor layer and electrically connected to the fourth nitride semiconductor layer, wherein the Si concentration in an upper surface of the second nitride semiconductor layer within an area not overlapping with the fourth nitride semiconductor layer in a planar view of the substrate is lower than the Si concentration in an upper surface of the third nitride semiconductor layer within an area overlapping with the fourth nitride semiconductor layer in a planar view of the substrate.

2. The nitride semiconductor device according to claim 1, wherein the third nitride semiconductor layer is provided only in a region that overlaps with the fourth nitride semiconductor layer in a plan view of the substrate.

3. The nitride semiconductor device according to claim 1, wherein the third nitride semiconductor layer includes a thick film portion that overlaps the fourth nitride semiconductor layer in a planar view of the substrate, and a thin film portion that does not overlap the fourth nitride semiconductor layer in a planar view of the substrate, and the film thickness of the thin film portion is smaller than the film thickness of the thick film portion.

4. The nitride semiconductor device according to claim 3, wherein the Si concentration in the upper surface of the thin film portion is lower than the Si concentration in the upper surface of the thick film portion.

5. The nitride semiconductor device according to any one of claims 1 to 4, wherein the third nitride semiconductor layer has a maximum film thickness of 10 nm or more.

6. The nitride semiconductor device according to any one of claims 1 to 4, wherein the third nitride semiconductor layer contains undoped GaN as a main component.

7. The nitride semiconductor device according to claim 1, wherein the third nitride semiconductor layer contains p-type GaN as a main component.

8. The nitride semiconductor device according to any one of claims 1 to 4, wherein the first electrode is a gate electrode, and the nitride semiconductor device further comprises: a source electrode provided above the substrate and electrically connected to the first nitride semiconductor layer; and a drain electrode provided below the substrate.

9. The nitride semiconductor device according to claim 8, comprising: an n-type fifth nitride semiconductor layer provided above the substrate; and a p-type sixth nitride semiconductor layer provided above the fifth nitride semiconductor layer, wherein the first nitride semiconductor layer and the second nitride semiconductor layer are provided so as to cover an inner surface of a first opening that penetrates the sixth nitride semiconductor layer to reach the fifth nitride semiconductor layer and an upper part of the sixth nitride semiconductor layer.

10. The nitride semiconductor device according to claim 9, wherein the second nitride semiconductor layer has a recessed portion at a position overlapping the sixth nitride semiconductor layer in a planar view of the substrate, the third nitride semiconductor layer has a second opening at a position overlapping the recessed portion in a planar view of the substrate, and the fourth nitride semiconductor layer is provided in the recessed portion via the second opening.

11. The nitride semiconductor device according to claim 10, wherein the gate electrode is provided so as to overlap the bottom surface of the first opening and the recessed portion in a plan view of the substrate.

12. The nitride semiconductor device according to claim 10, wherein the gate electrode is provided at a position overlapping the sixth nitride semiconductor layer but not overlapping the first opening in a plan view of the substrate.

13. The nitride semiconductor device according to claim 12, further comprising a second electrode provided at a position overlapping a bottom surface of the first opening in a plan view of the substrate and set to the same potential as the source electrode, wherein the third nitride semiconductor layer includes a first portion and a second portion electrically isolated from each other, the fourth nitride semiconductor layer includes a third portion and a fourth portion electrically isolated from each other, the first portion and the third portion being located between the gate electrode and the second nitride semiconductor layer, and the second portion and the fourth portion being located between the second electrode and the second nitride semiconductor layer.

14. The nitride semiconductor device according to claim 9, further comprising: a p-type seventh nitride semiconductor layer provided in contact with the sixth nitride semiconductor layer within a third opening that passes through the third nitride semiconductor layer, the second nitride semiconductor layer, and the first nitride semiconductor layer to reach the sixth nitride semiconductor layer; and a third electrode electrically connected to the seventh nitride semiconductor layer.

15. The nitride semiconductor device according to any one of claims 1 to 4, wherein the first electrode is a gate electrode, and the nitride semiconductor device further comprises a source electrode and a drain electrode disposed above the substrate and sandwiching the gate electrode therebetween, the source electrode and the drain electrode being electrically connected to the first nitride semiconductor layer.

16. The nitride semiconductor device according to claim 15, wherein the second nitride semiconductor layer has a recessed portion formed in a position overlapping the gate electrode in a planar view of the substrate, the third nitride semiconductor layer has a second opening formed in a position overlapping the recessed portion in a planar view of the substrate, and the fourth nitride semiconductor layer is provided in the recessed portion via the second opening.

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