Photodetector and electronic equipment

Abstract

A photodetector according to an embodiment of the present disclosure comprises: a photoelectric conversion unit in which a first electrode, a photoelectric conversion layer, and a second electrode are stacked in the stated order; a control circuit unit that acquires data and determines an imaging mode; and a voltage switching circuit unit that switches the voltage difference between the first electrode and the second electrode in accordance with the imaging mode determined by the control circuit unit.

Description

Photodetector and electronic equipment

[0001] The present disclosure relates to a photodetector and an electronic device including a photoelectric conversion layer using, for example, an organic material.

[0002] For example, Patent Document 1 discloses a solid-state imaging device having a photoelectric conversion section in which a first electrode, a photoelectric conversion layer, and a second electrode are stacked in this order, and which includes a charge storage electrode that is arranged spaced apart from the first electrode and opposite the photoelectric conversion layer via an insulating layer.

[0003] Japanese Patent Application Laid-Open No. 2017-157816

[0004] Incidentally, there is a demand for improvement in image quality in photodetection devices used as solid-state imaging devices and the like.

[0005] It would be desirable to provide photodetection devices and electronics that can improve image quality.

[0006] An optical detection device according to one embodiment of the present disclosure includes a photoelectric conversion unit in which a first electrode, a photoelectric conversion layer, and a second electrode are stacked in this order, a control circuit unit that acquires data and determines an imaging mode, and a voltage switching circuit unit that switches the voltage difference between the first electrode and the second electrode according to the imaging mode determined by the control circuit unit.

[0007] An electronic device according to an embodiment of the present disclosure includes the photodetector according to the embodiment of the present disclosure.

[0008] The photodetector and electronic device of the present disclosure include a control circuit that acquires data and determines an imaging mode, and a voltage switching circuit that switches the voltage difference between the first electrode and the second electrode in accordance with the imaging mode determined by the control circuit, thereby applying an appropriate electric field between the first electrode and the second electrode in accordance with the imaging mode.

[0009] FIG. 1 is a block diagram illustrating a schematic configuration of a photodetector according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional schematic diagram illustrating an example of the configuration of a unit pixel of the photodetector shown in FIG. 1. FIG. 3 is a plan schematic diagram illustrating an example of the configuration of a unit pixel of the photodetector shown in FIG. 1. FIG. 4 is an equivalent circuit diagram of a unit pixel constituting the photodetector shown in FIG. 1. FIG. 5 is a layout diagram illustrating an example of the arrangement of transistors constituting the lower electrode and control unit of the photodetector shown in FIG. 1. FIG. 6 is a timing chart illustrating an example of the operation of the photodetector shown in FIG. 1. FIG. 7 is a diagram illustrating a cross-section (A) of a photoelectric conversion unit of a unit pixel, and an example of the energy potential of each region of the photoelectric conversion unit during an accumulation period (B) and a transfer period (C) in low gain mode. FIG. 8 is a diagram illustrating a cross-section (A) of a photoelectric conversion unit of a unit pixel, and an example of the energy potential of each region of the photoelectric conversion unit during an accumulation period (B) and a transfer period (C) in high gain mode. FIG. 9 is a block diagram illustrating an example of a control system for a storage electrode voltage. FIG. 10 is a block diagram illustrating an example of the configuration of a photodetector illustrating a method for determining an imaging mode. 11 is a block diagram showing an example of a control system for a storage electrode voltage of a photodetector according to a first modification of the present disclosure. FIG. 12 is a block diagram showing an example of a configuration of a photodetector, illustrating a method for determining an imaging mode of the photodetector according to a second modification of the present disclosure. FIG. 13 is a diagram showing a cross section (A) of a photoelectric conversion unit of a unit pixel of a photodetector according to a third modification of the present disclosure, and an example of energy potential of each region of the photoelectric conversion unit during an accumulation period (B) and a transfer period (C) in low gain mode. FIG. 14 is a diagram showing a cross section (A) of a photoelectric conversion unit of a unit pixel of a photodetector according to a third modification of the present disclosure, and an example of energy potential of each region of the photoelectric conversion unit during an accumulation period (B) and a transfer period (C) in high gain mode. FIG. 15 is a diagram showing a cross section (A) of a photoelectric conversion unit of a unit pixel of a photodetector according to a fourth modification of the present disclosure, and an example of energy potential of each region of the photoelectric conversion unit during an accumulation period (B) and a transfer period (C) in low gain mode. Figure 16 is a diagram showing a cross section (A) of the photoelectric conversion section of a unit pixel of a photodetector device relating to variant example 4 of the present disclosure, and an example of the energy potential of each region of the photoelectric conversion section during the accumulation period (B) and transfer period (C) of high gain mode.FIG. 17 is a diagram showing an example of energy potentials in each region of a photoelectric conversion unit during an accumulation period (A), a transfer transition period (B), and a transfer period (C), illustrating an example of driving of the storage electrode of a photodetector according to Modification 5 of the present disclosure. FIG. 18 is a schematic diagram showing an example of a power supply configuration in the photodetector shown in FIG. 1. FIG. 19 is a schematic diagram showing another example of a power supply configuration in a photodetector according to Modification 6 of the present disclosure. FIG. 20 is a schematic diagram showing another example of a power supply configuration in a photodetector according to Modification 6 of the present disclosure. FIG. 21 is a schematic diagram showing another example of a power supply configuration in a photodetector according to Modification 6 of the present disclosure. FIG. 22 is a schematic diagram showing another example of a power supply configuration in a photodetector according to Modification 6 of the present disclosure. FIG. 23 is a schematic diagram showing another example of a power supply configuration in a photodetector according to Modification 6 of the present disclosure. FIG. 24 is a schematic diagram showing another example of a power supply configuration in a photodetector according to Modification 6 of the present disclosure. FIG. 25A is a cross-sectional schematic diagram showing an example of a configuration of a photodetector according to Variation 1 of the present disclosure. FIG. 25B is a schematic plan view illustrating an example of a pixel configuration of the photodetector shown in FIG. 25A. FIG. 26A is a schematic cross-sectional view illustrating an example of a configuration of a photodetector according to Other Modification 2 of the present disclosure. FIG. 26B is a schematic plan view illustrating an example of a pixel configuration of the photodetector shown in FIG. 26A. FIG. 27 is a schematic cross-sectional view illustrating an example of a configuration of a photodetector according to Other Modification 3 of the present disclosure. FIG. 28 is a schematic cross-sectional view illustrating another example of a configuration of a photodetector according to Other Modification 4 of the present disclosure. FIG. 29A is a schematic cross-sectional view illustrating another example of a configuration of a photodetector according to Other Modification 5 of the present disclosure. FIG. 29B is a schematic plan view illustrating an example of a pixel configuration of the photodetector shown in FIG. 29A. FIG. 30A is a schematic cross-sectional view illustrating another example of a configuration of a photodetector according to Other Modification 6 of the present disclosure. FIG. 30B is a schematic plan view illustrating an example of a pixel configuration of the photodetector shown in FIG. 30A. FIG. 31 is a schematic cross-sectional view illustrating another example of a configuration of a photodetector according to Other Modification 7 of the present disclosure. Fig. 32 is a functional block diagram showing an example of an electronic device (camera) using the photodetector shown in Fig. 1 etc. Fig. 33A is a schematic diagram showing an example of the overall configuration of a photodetection system using the photodetector shown in Fig. 31.Fig. 33B is a diagram showing an example of the circuit configuration of the light detection system shown in Fig. 33A. Fig. 34 is a diagram showing an example of a schematic configuration of an endoscopic surgery system. Fig. 35 is a block diagram showing an example of the functional configuration of a camera head and a CCU. Fig. 36 is a block diagram showing an example of the schematic configuration of a vehicle control system. Fig. 37 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.

[0010] An embodiment of the present disclosure will be described in detail below with reference to the drawings. The following description is a specific example of the present disclosure, and the present disclosure is not limited to the following aspects. Furthermore, the present disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc. of the components shown in the drawings. The description will be given in the following order. 1. Embodiment (Example of a photodetector that switches the voltage difference between the first electrode and the second electrode depending on the imaging mode) 2. Modifications 2-1. Modification 1 (Another example of a control system for storage electrode voltage) 2-2. Modification 2 (Another example of a method for determining an imaging mode) 2-3. Modification 3 (Another example of pixel driving) 2-4. Modification 4 (Another example of pixel driving) 2-5. Modification 5 (Another example of storage electrode driving) 2-6. Modification 6 (Example of a power supply configuration) 3. Other Modifications 4-1. Other Modification 1 (Another example of a photodetector configuration) 4-2. Other Modification 2 (Another example of a photodetector configuration) 4-3. Other modified examples 3 (other examples of the configuration of the photodetector) 4-4. Other modified examples 4 to 7 (other examples of the configuration of the photodetector) 4. Application examples 5. Application examples

[0011] 1 illustrates an example of a schematic configuration of a photodetector (photodetector 1) according to an embodiment of the present disclosure. The photodetector 1 is used as a CMOS (Complementary Metal Oxide Semiconductor) image sensor or the like used in electronic devices such as digital still cameras and video cameras.

[0012] The photodetector 1 is, for example, a CMOS image sensor that captures incident light (image light) from a subject via an optical lens system (not shown), converts the amount of incident light imaged on an imaging surface into an electrical signal for each pixel, and outputs the electrical signal as a pixel signal. The photodetector 1 has a pixel array section 100A as an imaging area on a semiconductor substrate 30, and also has, in a peripheral region of the pixel array section 100A, for example, a vertical drive circuit 111, a column signal processing circuit 112, a horizontal drive circuit 113, an output circuit 114, a control circuit 115, and input / output terminals 116.

[0013] The pixel array section 100A has, for example, a plurality of unit pixels P arranged two-dimensionally in a matrix. For example, pixel drive lines Lread (specifically, row selection lines and reset control lines) are wired to each unit pixel P for each pixel row, and vertical signal lines Lsig are wired to each pixel column. The pixel drive lines Lread transmit drive signals for reading signals from the pixels. One end of each pixel drive line Lread is connected to an output terminal of the vertical drive circuit 111 corresponding to each row.

[0014] The vertical drive circuit 111 is a pixel drive unit that includes a shift register, an address decoder, etc., and drives each unit pixel P of the pixel array unit 100A, for example, row by row. Signals output from each unit pixel P of a pixel row selected and scanned by the vertical drive circuit 111 are supplied to a column signal processing circuit 112 through each vertical signal line Lsig. The column signal processing circuit 112 is configured with an amplifier, a horizontal selection switch, etc., provided for each vertical signal line Lsig.

[0015] The horizontal drive circuit 113 is configured with a shift register, an address decoder, etc., and scans and sequentially drives each horizontal selection switch of the column signal processing circuit 112. By selective scanning by this horizontal drive circuit 113, signals of each pixel transmitted through each vertical signal line Lsig are output in sequence to horizontal signal lines 121 and transmitted to the outside of the semiconductor substrate 30 through the horizontal signal lines 121.

[0016] The output circuit 114 processes and outputs signals sequentially supplied from each of the column signal processing circuits 112 via the horizontal signal line 121. The output circuit 114 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, and the like, for example.

[0017] The circuit portion consisting of the vertical drive circuit 111, the column signal processing circuit 112, the horizontal drive circuit 113, the horizontal signal line 121, and the output circuit 114 may be formed directly on the semiconductor substrate 30, or may be disposed on an external control IC. Furthermore, these circuit portions may be formed on another substrate connected by a cable or the like.

[0018] The control circuit 115 receives a clock and data instructing an operation mode from outside the semiconductor substrate 30, and outputs data such as internal information of the photodetector 1. The control circuit 115 further has a timing generator that generates various timing signals, and controls the driving of peripheral circuits such as the vertical drive circuit 111, the column signal processing circuit 112, and the horizontal drive circuit 113 based on the various timing signals generated by the timing generator.

[0019] The input / output terminal 116 is used to exchange signals with the outside.

[0020] [Configuration of Unit Pixel] Fig. 2 shows a configuration of one pixel (unit pixel P) repeatedly arranged in an array in the pixel array section 100A of the photodetector 1 shown in Fig. 1. Fig. 3 schematically shows an example of the pixel configuration of the photodetector 1 shown in Fig. 1, and Fig. 2 shows a cross section taken along line II shown in Fig. 3. In the pixel array section 100A, as shown in Fig. 3, a pixel unit 1a consisting of four unit pixels P arranged in, for example, two rows and two columns serves as a repeating unit, and is repeatedly arranged in an array consisting of row and column directions.

[0021] The photodetector 1 is a so-called vertical spectroscopic photodetector element in which, for example, one photoelectric conversion unit 20 and two photoelectric conversion regions 32B and 32R are stacked vertically. The photoelectric conversion unit 20 is provided on the back surface (first surface 30A) side of the semiconductor substrate 30. The photoelectric conversion regions 32B and 32R are embedded in the semiconductor substrate 30 and stacked in the thickness direction of the semiconductor substrate 30.

[0022] The photoelectric conversion unit 20 and the photoelectric conversion regions 32B and 32R selectively detect light in different wavelength ranges and perform photoelectric conversion. For example, the photoelectric conversion unit 20 acquires a green (G) color signal. The photoelectric conversion regions 32B and 32R acquire blue (B) and red (R) color signals, respectively, due to differences in absorption coefficients. This allows the photodetector 1 to acquire multiple types of color signals in one pixel without using color filters.

[0023] In this embodiment, a case where electrons, among pairs of electrons and holes (excitons) generated by photoelectric conversion, are read out as signal charges (when an n-type semiconductor region is used as the photoelectric conversion layer) will be described. In addition, in the figures, a "+ (plus)" attached to "p" and "n" indicates that the p-type or n-type impurity concentration is high.

[0024] The surface (second surface 30B) of the semiconductor substrate 30 is provided with, for example, floating diffusions FD1 (region 36B within the semiconductor substrate 30), FD2 (region 37C within the semiconductor substrate 30), and FD3 (region 38C within the semiconductor substrate 30), transfer transistors Tr2 and Tr3, an amplifier transistor (modulation element) AMP, a reset transistor RST, and a selection transistor SEL. The second surface 30B of the semiconductor substrate 30 is further provided with a multilayer wiring layer 40 via a gate insulating layer 33. The multilayer wiring layer 40 has, for example, wiring layers 41, 42, and 43 stacked within an insulating layer 44. Around the pixel array section 100A of the semiconductor substrate 30, i.e., in the peripheral section 100B (see FIG. 18 ), the vertical drive circuit 111, column signal processing circuit 112, horizontal drive circuit 113, output circuit 114, control circuit 115, input / output terminals 116, and the like.

[0025] In the drawings, the first surface 30A side of the semiconductor substrate 30 is represented as a light incident side S1, and the second surface 30B side is represented as a wiring layer side S2.

[0026] The photoelectric conversion unit 20 has an oxide semiconductor layer 23 and a photoelectric conversion layer 24 containing an organic material stacked in this order from the lower electrode 21 side between an opposing lower electrode 21 and an upper electrode 25. The photoelectric conversion layer 24 is composed of a p-type semiconductor and an n-type semiconductor, and has a bulk heterojunction structure within the layer. The bulk heterojunction structure is a p / n junction surface formed by mixing a p-type semiconductor and an n-type semiconductor.

[0027] The photoelectric conversion unit 20 further includes an insulating layer 22 between the lower electrode 21 and the oxide semiconductor layer 23. The insulating layer 22 is provided, for example, over the entire surface of the pixel array unit 100A, and has an opening 22H above the readout electrode 21A that constitutes the lower electrode 21. The readout electrode 21A is electrically connected to the oxide semiconductor layer 23 through this opening 22H.

[0028] 1 shows an example in which the oxide semiconductor layer 23, the photoelectric conversion layer 24, and the upper electrode 25 are provided, for example, over the entire surface of the pixel array section 100A as a common layer for a plurality of unit pixels P, but the present invention is not limited to this. The oxide semiconductor layer 23, the photoelectric conversion layer 24, and the upper electrode 25 may be formed separately for each unit pixel P, for example.

[0029] Between the first surface 30A of the semiconductor substrate 30 and the lower electrode 21, for example, a layer having a fixed charge (fixed charge layer 26), a dielectric layer 27, and an interlayer insulating layer 28 are stacked in this order.

[0030] The photoelectric conversion regions 32B and 32R enable the vertical separation of light by utilizing the fact that the wavelength of light absorbed varies depending on the depth of incidence of the light in the semiconductor substrate 30 made of a silicon (Si) substrate, and each has a pn junction in a predetermined region of the semiconductor substrate 30.

[0031] A through electrode 34 is provided between the first surface 30A and the second surface 30B of the semiconductor substrate 30. An end (upper end) of the through electrode 34 on the light incident side S1 is electrically connected to the readout electrode 21A, and an end (lower end) on the wiring layer side S2 is connected to the connection portion 41A. The photoelectric conversion unit 20 is connected via the through electrode 34 to the gate Gamp of the amplifier transistor AMP and one source / drain region 36B of the reset transistor RST (reset transistor Tr1rst), which also serves as the floating diffusion FD1. This allows the photodetector 1 to efficiently transfer charge carriers (here, electrons) generated in the photoelectric conversion unit 20 provided on the first surface 30A side of the semiconductor substrate 30 to the second surface 30B side of the semiconductor substrate 30 via the through electrode 34, thereby improving its characteristics.

[0032] As described above, the lower end of the through electrode 34 is connected to the wiring (connection portion 41A) in the wiring layer 41, and the connection portion 41A and the gate Gamp of the amplifier transistor AMP are connected via a lower first contact 45. The connection portion 41A and the floating diffusion FD1 (region 36B) are connected, for example, via a lower second contact 46. The upper end of the through electrode 34 is connected to the readout electrode 21A, for example, via a pad portion 29A, an upper first contact 29B, a pad portion 29C, and an upper second contact 29F.

[0033] A protective layer 51 is provided above the photoelectric conversion unit 20. In the protective layer 51, for example, wiring 52 and a light-shielding film 53 are provided in the peripheral unit 100B, which electrically connect the upper electrode 25 to peripheral circuit units such as a vertical drive circuit 111, a column signal processing circuit 112, a horizontal drive circuit 113, an output circuit 114, a control circuit 115, and an input / output terminal 116. Optical members such as a planarization layer (not shown) and an on-chip lens 54 are further provided above the protective layer 51.

[0034] In the photodetector 1 of this embodiment, light incident on the photoelectric conversion unit 20 from the light incident side S1 is absorbed by the photoelectric conversion layer 24. The resulting excitons migrate to the interface between the electron donors and electron acceptors that make up the photoelectric conversion layer 24, where they undergo exciton dissociation, i.e., dissociation into electrons and holes. The charge carriers (electrons and holes) generated here are transported to different electrodes by diffusion due to differences in charge carrier concentration and by an internal electric field caused by the difference in work function between the anode (e.g., the upper electrode 25) and the cathode (e.g., the lower electrode 21), and are detected as photocurrent. The transport direction of the electrons and holes can also be controlled by applying a potential between the lower electrode 21 and the upper electrode 25.

[0035] The structure and materials of each part will be described in detail below.

[0036] The photoelectric conversion unit 20 is an organic photoelectric conversion element that absorbs, for example, green light corresponding to a part or all of a selective wavelength range (for example, 450 nm or more and 650 nm or less) and generates excitons.

[0037] The lower electrode 21 includes, for example, a read electrode 21A, a storage electrode 21B, a shield electrode 21C, and an overflow barrier (OFB) electrode 21D, which are arranged in parallel on the interlayer insulating layer 28.

[0038] The readout electrode 21A is for transferring charge carriers generated in the photoelectric conversion layer 24 to the floating diffusion FD1, and is provided for each pixel unit 1a made up of four unit pixels P arranged in two rows and two columns, as shown in Fig. 3. The readout electrode 21A is connected to the floating diffusion FD1 via, for example, an upper second contact 29F, a pad portion 29C, an upper first contact 29B, a pad portion 29A, a through electrode 34, a connection portion 41A, and a lower second contact 46.

[0039] The storage electrode 21B is used to store, for example, electrons as signal charges in the oxide semiconductor layer 23 from among the charge carriers generated in the photoelectric conversion layer 24. The storage electrode 21B is provided for each unit pixel P in an area directly facing the light-receiving surfaces of the photoelectric conversion regions 32B, 32R formed in the semiconductor substrate 30 and covering these light-receiving surfaces. The storage electrode 21B is preferably larger than the readout electrode 21A, allowing a larger number of charge carriers to be stored. The storage electrode 21B is connected to a voltage application unit 48 (see FIG. 5 ) via wiring such as an upper fourth contact 29H and a pad unit 29E.

[0040] The shield electrode 21C is intended to prevent leakage of accumulated charges between adjacent pixel units 1a, and is applied with, for example, a fixed potential. For example, as shown in Fig. 3, in a pixel unit 1a consisting of four unit pixels P arranged in two rows and two columns, the shield electrode 21C extends between adjacent pixel units 1a in the row direction (Y-axis direction) and column direction (X-axis direction). The shield electrode 21C further protrudes between adjacent unit pixels P within the pixel unit 1a.

[0041] The OFB electrode 21D is intended to prevent charge carriers stored in the oxide semiconductor layer 23 above the storage electrode 21B from flowing to the readout electrode 21A, and a variable voltage is applied to the OFB electrode 21D. The OFB electrode 21D is disposed between the readout electrode 21A and the storage electrode 212B. Wiring such as an upper third contact 29G and a pad portion 29D is connected to the OFB electrode 21D, and a variable voltage is applied to the OFB electrode 21D via these.

[0042] The lower electrode 21 is made of, for example, a conductive film having optical transparency. The lower electrode 21 preferably has a work function of 4.0 eV or more and 5.5 eV or less. The material for the lower electrode 21 is, for example, InP doped with tin (Sn). ２ O ３The ITO thin film may have high or low crystallinity (approaching amorphous). In addition to the above, the constituent material of the lower electrode 21 may be tin oxide (SnO ２ )-based materials, for example, ATO with Sb added as a dopant, and FTO with fluorine added as a dopant can be used. Zinc oxide (ZnO) or a zinc oxide-based material with a dopant added can also be used. Examples of ZnO-based materials include aluminum zinc oxide (AZO) with aluminum (Al) added as a dopant, gallium zinc oxide (GZO) with gallium (Ga) added, boron zinc oxide with boron (B) added, and indium zinc oxide (IZO) with indium (In) added. Furthermore, zinc oxide with indium and gallium added as dopants (IGZO, In-GaZnO ４ In addition, the lower electrode 21 may be made of CuI, InSbO ４ , ZnMgO, CuInO ２ , MgIN ２ O ４ , CdO, ZnSnO ３ or TiO ２ Alternatively, spinel oxides or YbFe ２ O ４ Oxides having such a structure may also be used.

[0043] Furthermore, when the lower electrode 21 does not need to be optically transparent (for example, when light is incident from the upper electrode 25 side and the photoelectric conversion regions 32R and 32B are not provided below the storage electrode 21B), a single metal or alloy having a small work function (for example, φ=3.5 eV to 4.5 eV) can be used. Specific examples include alkali metals (for example, lithium (Li), sodium (Na), and potassium (K)) and their fluorides or oxides, and alkaline earth metals (for example, magnesium (Mg) and calcium (Ca)) and their fluorides or oxides. Other examples include rare earth metals such as aluminum (Al), Al—Si—Cu alloys, zinc (Zn), tin (Sn), thallium (Tl), Na—K alloys, Al—Li alloys, Mg—Ag alloys, In, and ytterbium (Yb), or alloys thereof.

[0044] Furthermore, examples of materials for the lower electrode 21 include metals such as platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), aluminum (Al), silver (Ag), tantalum (Ta), tungsten (W), copper (Cu), titanium (Ti), indium (In), tin (Sn), iron (Fe), cobalt (Co), and molybdenum (Mo), alloys containing these metal elements, conductive particles made of these metals, conductive particles of alloys containing these metals, polysilicon containing impurities, carbon-based materials, oxide semiconductors, carbon nanotubes, and graphene. Other examples of materials for the lower electrode 21 include organic materials (conductive polymers) such as poly(3,4-ethylenedioxythiophene) / polystyrene sulfonate (PEDOT / PSS). Alternatively, the above materials may be mixed with a binder (polymer) to form a paste or ink, which may then be cured and used as an electrode.

[0045] The lower electrode 21 can be formed as a single layer or a laminated film made of the above materials. The film thickness of the lower electrode 21 in the lamination direction (hereinafter simply referred to as thickness) is, for example, 20 nm to 200 nm, and preferably 30 nm to 150 nm.

[0046] The insulating layer 22 serves to electrically separate the storage electrode 21B, the shield electrode 21C, and the OFB electrode 21D from the oxide semiconductor layer 23. The insulating layer 22 is provided, for example, on the interlayer insulating layer 28 so as to cover the lower electrode 21. An opening 22H is provided in the insulating layer 22 above the readout electrode 21A of the lower electrode 21, and the readout electrode 21A and the oxide semiconductor layer 23 are electrically connected via this opening 22H. The insulating layer 22 is made of, for example, silicon oxide (SiO ｘ ), silicon nitride (SiN ｘ The insulating layer 22 is made of a single layer film made of one of silicon oxynitride (SiON) and silicon oxynitride (SiON), or a laminated film made of two or more of these materials. The thickness of the insulating layer 22 is, for example, 20 nm to 500 nm.

[0047] The oxide semiconductor layer 23 is for accumulating charge carriers generated in the photoelectric conversion layer 24. The oxide semiconductor layer 23 can be formed using an oxide semiconductor containing at least one element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), and tin (Sn). In this embodiment, electrons among the charge carriers generated in the photoelectric conversion layer 24 are used as signal charges. For this reason, the oxide semiconductor layer 23 can be formed using an n-type oxide semiconductor material. Specifically, the oxide semiconductor layer 23 can be formed using an n-type oxide semiconductor material such as IGZO (In—Ga—Zn—O-based oxide semiconductor), gallium oxide (Ga ２ O ３ ), ZTO (Zn—Sn—O-based oxide semiconductor), IZO (In—Zn—O-based oxide semiconductor), ITO, indium gallium aluminum oxide (InGaAlO), indium gallium silicon oxide (InGaSiO), etc. The thickness of the oxide semiconductor layer 23 is, for example, 10 nm to 300 nm.

[0048] The photoelectric conversion layer 24 converts light energy into electrical energy. The photoelectric conversion layer 24 is configured, for example, by including two or more organic materials (p-type semiconductor materials or n-type semiconductor materials) that function as p-type or n-type semiconductors, respectively. The photoelectric conversion layer 24 has a junction surface (p / n junction surface) between a p-type semiconductor material and an n-type semiconductor material within the layer. The p-type semiconductor functions relatively as an electron donor, and the n-type semiconductor functions relatively as an electron acceptor. The photoelectric conversion layer 24 provides a site where excitons generated upon light absorption separate into electrons and holes. Specifically, the excitons separate into electrons and holes at the interface (p / n junction surface) between the electron donor and electron acceptor.

[0049] In addition to the p-type and n-type semiconductor materials, the photoelectric conversion layer 24 may also contain an organic material, a so-called dye material, that photoelectrically converts light in a predetermined wavelength range while transmitting light in other wavelength ranges. When the photoelectric conversion layer 24 is formed using three types of organic materials, i.e., a p-type semiconductor material, an n-type semiconductor material, and a dye material, the p-type and n-type semiconductor materials are preferably materials that are optically transparent in the visible range (e.g., 450 nm to 800 nm). The thickness of the photoelectric conversion layer 24 is, for example, 50 nm to 500 nm.

[0050] Examples of organic materials that can be used to form the photoelectric conversion layer 24 include quinacridone derivatives, naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, and fluoranthene derivatives. The photoelectric conversion layer 24 is formed by combining two or more of the above organic materials. Depending on the combination, the above organic materials function as p-type or n-type semiconductors.

[0051] The organic material constituting the photoelectric conversion layer 24 is not particularly limited. In addition to the above organic materials, for example, polymers of phenylene vinylene, fluorene, carbazole, indole, pyrene, pyrrole, picoline, thiophene, acetylene, diacetylene, and the like, or derivatives thereof, can be used. Alternatively, metal complex dyes, cyanine dyes, merocyanine dyes, phenylxanthene dyes, triphenylmethane dyes, rhodacyanine dyes, xanthene dyes, macrocyclic azaannulene dyes, azulene dyes, naphthoquinone dyes, anthraquinone dyes, condensed polycyclic aromatic compounds such as pyrene, linear compounds in which aromatic rings or heterocyclic compounds are condensed, quinoline having a squarylium group and a croconite methine group as a bonding chain, two nitrogen-containing heterocycles such as benzothiazole and benzoxazole, or cyanine-like dyes bonded by a squarylium group and a croconite methine group, can be used. Examples of the metal complex dye include dithiol metal complex dyes, metal phthalocyanine dyes, metal porphyrin dyes, and ruthenium complex dyes. Of these, ruthenium complex dyes are particularly preferred, but the invention is not limited to these.

[0052] The upper electrode 25 is made of, for example, a light-transmitting conductive film, similar to the lower electrode 21. The upper electrode 25 is made of, for example, InP doped with tin (Sn). ２ O ３ The crystallinity of the ITO thin film may be high or low (approaching amorphous). In addition to the above, the upper electrode 25 may also be made of tin oxide (SnO ２)-based materials, for example, ATO with Sb added as a dopant, and FTO with fluorine added as a dopant. Zinc oxide (ZnO) or a zinc oxide-based material with a dopant added thereto may also be used. Examples of ZnO-based materials include aluminum zinc oxide (AZO) with aluminum (Al) added as a dopant, gallium zinc oxide (GZO) with gallium (Ga) added, boron zinc oxide with boron (B) added, and indium zinc oxide (IZO) with indium (In) added. Furthermore, zinc oxide with indium and gallium added as dopants (IGZO, In-GaZnO ４ In addition, the upper electrode 25 may be made of CuI, InSbO ４ , ZnMgO, CuInO ２ , MgIN ２ O ４ , CdO, ZnSnO ３ or TiO ２ Alternatively, spinel oxides or YbFe ２ O ４ Oxides having such a structure may also be used.

[0053] Furthermore, if optical transparency is not required for the upper electrode 25, a single metal or alloy having a large work function (for example, φ=4.5 eV to 5.5 eV) can be used. Specific examples include Au, Ag, Cr, Ni, Pd, Pt, Fe, iridium (Ir), germanium (Ge), osmium (Os), rhenium (Re), tellurium (Te), and alloys thereof.

[0054] Furthermore, examples of materials for the upper electrode 25 include metals such as Pt, Au, Pd, Cr, Ni, Al, Ag, Ta, W, Cu, Ti, In, Sn, Fe, Co, and Mo, or alloys containing these metal elements, or conductive particles made of these metals, conductive particles of alloys containing these metals, polysilicon containing impurities, carbon-based materials, oxide semiconductors, carbon nanotubes, and graphene. Other examples of materials for the upper electrode 25 include organic materials (conductive polymers) such as PEDOT / PSS. Alternatively, the above materials may be mixed with a binder (polymer) to form a paste or ink, which may then be cured and used as an electrode.

[0055] The upper electrode 25 can be formed as a single layer or a laminated film made of the above materials. The thickness of the upper electrode 25 is, for example, 20 nm to 200 nm, preferably 30 nm to 150 nm.

[0056] In the photoelectric conversion unit 20, other layers such as a charge blocking layer and a work function adjustment layer may be provided between the lower electrode 21 and the photoelectric conversion layer 24 and between the photoelectric conversion layer 24 and the upper electrode 25. In addition, the photoelectric conversion layer 24 may have a pin bulk heterostructure in which a p-type blocking layer, a layer containing a p-type semiconductor and an n-type semiconductor (i-layer), and an n-type blocking layer are stacked in this order.

[0057] The fixed charge layer 26 covers the first surface 30A of the semiconductor substrate 30, and serves to reduce the interface state with the semiconductor substrate 30 and suppress the generation of dark current from the interface with the semiconductor substrate 30. The fixed charge layer 26 may be a film having a positive fixed charge or a film having a negative fixed charge. The fixed charge layer 26 is preferably formed using a semiconductor material or a conductive material having a wider band gap than the semiconductor substrate 30. This makes it possible to suppress the generation of dark current at the interface with the semiconductor substrate 30. The fixed charge layer 26 may be formed using, for example, hafnium oxide (HfO ｘ ), aluminum oxide (AlO ｘ ), zirconium oxide (ZrO ｘ ), tantalum oxide (TaOｘ ), titanium oxide (TiO ｘ ), lanthanum oxide (LaO ｘ ), praseodymium oxide (PrO ｘ ), cerium oxide (CeO ｘ ), neodymium oxide (NdO ｘ ), promethium oxide (PmO ｘ ), samarium oxide (SmO ｘ ), europium oxide (EuO ｘ ), gadolinium oxide (GdO ｘ ), terbium oxide (TbO ｘ ), dysprosium oxide (DyO ｘ ), holmium oxide (HoO ｘ ), thulium oxide (TmO ｘ ), ytterbium oxide (YbO ｘ ), lutetium oxide (LuO ｘ ), yttrium oxide (YO ｘ ), hafnium nitride (HfN ｘ ), aluminum nitride (AlN ｘ ), hafnium oxynitride (HfO ｘ N ｙ ) and aluminum oxynitride (AlO ｘ N ｙ ) etc.

[0058] The dielectric layer 27 is intended to prevent light reflection caused by the difference in refractive index between the semiconductor substrate 30 and the interlayer insulating layer 28. The dielectric layer 27 is preferably formed using a material having a refractive index between the refractive index of the semiconductor substrate 30 and the refractive index of the interlayer insulating layer 28. Examples of materials that can be used for the dielectric layer 27 include silicon oxide, TEOS, silicon nitride, and silicon oxynitride (SiON).

[0059] The fixed charge layer 26 and the dielectric layer 27 extend from the first surface 30A of the semiconductor substrate 30 to the side surface of the opening in which the through electrode 34 that penetrates the semiconductor substrate 30 is formed.

[0060] The interlayer insulating layer 28 is configured, for example, by a single layer film made of one of silicon oxide, silicon nitride, silicon oxynitride, etc., or a laminated film made of two or more of these materials.

[0061] The semiconductor substrate 30 is made of, for example, an n-type Si substrate, and has a p-well 31 in a predetermined region.

[0062] The photoelectric conversion regions 32B and 32R are each composed of a photodiode (PD) having a pn junction in a predetermined region of the semiconductor substrate 30. They utilize the fact that different wavelengths of light are absorbed depending on the depth of incidence of light in the Si substrate to enable vertical light separation. The photoelectric conversion region 32B selectively detects, for example, blue light and accumulates signal charges corresponding to the blue color, and is located at a depth that allows efficient photoelectric conversion of the blue light. The photoelectric conversion region 32R selectively detects, for example, red light and accumulates signal charges corresponding to the red color, and is located at a depth that allows efficient photoelectric conversion of the red light. Note that blue (B) corresponds to, for example, a wavelength range of 450 nm to 495 nm, and red (R) corresponds to, for example, a wavelength range of 620 nm to 750 nm. Each of the photoelectric conversion regions 32B and 32R may be capable of detecting light in some or all of the respective wavelength ranges.

[0063] The photoelectric conversion region 32B includes, for example, a p+ region that serves as a hole accumulation layer and an n region that serves as an electron accumulation layer. The photoelectric conversion region 32R includes, for example, a p+ region that serves as a hole accumulation layer and an n region that serves as an electron accumulation layer (having a p-n-p stacked structure). The n region of the photoelectric conversion region 32B is connected to the vertical transfer transistor Tr2. The p+ region of the photoelectric conversion region 32B bends along the transfer transistor Tr2 and connects to the p+ region of the photoelectric conversion region 32R.

[0064] The gate insulating layer 33 is configured, for example, as a single layer film made of one of silicon oxide, silicon nitride, silicon oxynitride, etc., or as a laminated film made of two or more of these materials.

[0065] The through electrode 34 is provided between the first surface 30A and the second surface 30B of the semiconductor substrate 30, and functions as a connector between the photoelectric conversion unit 20 and the gate Gamp of the amplifier transistor AMP and the floating diffusion FD1, and also serves as a transmission path for charge carriers generated in the photoelectric conversion unit 20. A reset gate Grst of the reset transistor RST is disposed next to the floating diffusion FD1 (one of the source / drain regions 36B of the reset transistor RST). This makes it possible to reset the charge carriers accumulated in the floating diffusion FD1 by the reset transistor RST.

[0066] The pad portions 29A, 29C, 29D, 29E, the upper first contact 29B, the upper second contact 29F, the upper third contact 29G, the upper fourth contact 29H, the lower first contact 45, the lower second contact 46, and the wiring 52 can be formed using, for example, a silicon material doped with impurities such as PDAS (Phosphorus Doped Amorphous Silicon), or a metal material such as aluminum (Al), tungsten (W), titanium (Ti), cobalt (Co), hafnium (Hf), and tantalum (Ta).

[0067] The protective layer 51 and the on-chip lens 54 are made of a light-transmitting material, and are formed of, for example, a single layer film made of any of silicon oxide, silicon nitride, silicon oxynitride, etc., or a laminated film made of two or more of these materials. The thickness of this protective layer 51 is, for example, 100 nm to 30,000 nm.

[0068] The light-shielding film 53 is provided, for example, together with the wiring 52, in the protective layer 51 so as to cover at least the region of the readout electrode 21A that is in direct contact with the oxide semiconductor layer 23, but not the storage electrode 21B. The light-shielding film 53 can be formed using, for example, tungsten (W), aluminum (Al), an alloy of Al and copper (Cu), or the like.

[0069] Fig. 4 is an equivalent circuit diagram of a unit pixel P constituting the photodetector 1 shown in Fig. 1. Fig. 5 is a schematic diagram showing the arrangement of the lower electrode 21 and transistors constituting the control unit of the photodetector 1 shown in Fig. 1.

[0070] The reset transistor RST (reset transistor TR1rst) resets the charge carriers transferred from the photoelectric conversion unit 20 to the floating diffusion FD1, and is configured, for example, by a MOS transistor. Specifically, the reset transistor TR1rst is configured by a reset gate Grst, a channel formation region 36A, and source / drain regions 36B and 36C. The reset gate Grst is connected to a reset line RST1, and one source / drain region 36B of the reset transistor TR1rst also serves as the floating diffusion FD1. The other source / drain region 36C constituting the reset transistor TR1rst is connected to a power supply line VDD.

[0071] The amplifier transistor AMP (amplifier transistor TR1amp) is a modulation element that modulates the amount of charge generated in the photoelectric conversion unit 20 into a voltage, and is configured, for example, by a MOS transistor. Specifically, the amplifier transistor AMP is configured with a gate Gamp, a channel formation region 35A, and source / drain regions 35B and 35C. The gate Gamp is connected to the readout electrode 21A and one source / drain region 36B (floating diffusion FD1) of the reset transistor TR1rst via a lower first contact 45, a connection portion 41A, a lower second contact 46, a through-electrode 34, etc. Furthermore, one source / drain region 35B shares an area with the other source / drain region 36C that constitutes the reset transistor TR1rst, and is connected to the power supply line VDD.

[0072] The select transistor SEL (select transistor TR1sel) is composed of a gate Gsel, a channel formation region 34A, and source / drain regions 34B and 34C. The gate Gsel is connected to a select line SEL1. One source / drain region 34B shares an area with the other source / drain region 35C that constitutes the amplifier transistor AMP, and the other source / drain region 34C is connected to a signal line (data output line) VSL1.

[0073] The transfer transistor TR2 (transfer transistor TR2trs) transfers signal charges corresponding to blue generated and accumulated in the photoelectric conversion region 32B to the floating diffusion FD2. Because the photoelectric conversion region 32B is formed deep below the second surface 30B of the semiconductor substrate 30, the transfer transistor TR2trs in the photoelectric conversion region 32B is preferably configured as a vertical transistor. The transfer transistor TR2trs is connected to a transfer gate line TG2. A floating diffusion FD2 is provided in the region 37C near the gate Gtrs2 of the transfer transistor TR2trs. Charge carriers accumulated in the photoelectric conversion region 32B are read out to the floating diffusion FD2 via a transfer channel formed along the gate Gtrs2.

[0074] The transfer transistor TR3 (transfer transistor TR3trs) transfers the signal charges corresponding to red that are generated and accumulated in the photoelectric conversion region 32R to the floating diffusion FD3, and is configured, for example, by a MOS transistor. The transfer transistor TR3trs is connected to a transfer gate line TG3. A floating diffusion FD3 is provided in the region 38C near the gate Gtrs3 of the transfer transistor TR3trs. The charge carriers accumulated in the photoelectric conversion region 32R are read out to the floating diffusion FD3 via a transfer channel formed along the gate Gtrs3.

[0075] Further provided on the second surface 30B side of the semiconductor substrate 30 are a reset transistor TR2rst, an amplifier transistor TR2amp, and a selection transistor TR2sel that constitute a control section of the photoelectric conversion region 32B. Further provided are a reset transistor TR3rst, an amplifier transistor TR3amp, and a selection transistor TR3sel that constitute a control section of the photoelectric conversion region 32R.

[0076] The reset transistor TR2rst is composed of a gate, a channel forming region, and source / drain regions. The gate of the reset transistor TR2rst is connected to a reset line RST2, and one of the source / drain regions of the reset transistor TR2rst is connected to a power supply line VDD. The other source / drain region of the reset transistor TR2rst also serves as a floating diffusion FD2.

[0077] The amplifier transistor TR2amp is composed of a gate, a channel forming region, and source / drain regions. The gate is connected to the other source / drain region (floating diffusion FD2) of the reset transistor TR2rst. One of the source / drain regions constituting the amplifier transistor TR2amp shares the same region with one of the source / drain regions constituting the reset transistor TR2rst and is connected to the power supply line VDD.

[0078] The selection transistor TR2sel is composed of a gate, a channel formation region, and source / drain regions. The gate is connected to a selection line SEL2. One of the source / drain regions constituting the selection transistor TR2sel is shared with the other source / drain region constituting the amplifier transistor TR2amp. The other source / drain region constituting the selection transistor TR2sel is connected to a signal line (data output line) VSL2.

[0079] The reset transistor TR3rst is composed of a gate, a channel forming region, and source / drain regions. The gate of the reset transistor TR3rst is connected to a reset line RST3, and one of the source / drain regions constituting the reset transistor TR3rst is connected to a power supply line VDD. The other source / drain region constituting the reset transistor TR3rst also serves as a floating diffusion FD3.

[0080] The amplifier transistor TR3amp is composed of a gate, a channel forming region, and source / drain regions. The gate is connected to the other source / drain region (floating diffusion FD3) constituting the reset transistor TR3rst. One of the source / drain regions constituting the amplifier transistor TR3amp shares the same region with one of the source / drain regions constituting the reset transistor TR3rst and is connected to the power supply line VDD.

[0081] The selection transistor TR3sel is composed of a gate, a channel formation region, and source / drain regions. The gate is connected to a selection line SEL3. One of the source / drain regions constituting the selection transistor TR3sel shares the same region with the other of the source / drain regions constituting the amplifier transistor TR3amp. The other of the source / drain regions constituting the selection transistor TR3sel is connected to a signal line (data output line) VSL3.

[0082] The reset lines RST1, RST2, and RST3, the selection lines SEL1, SEL2, and SEL3, and the transfer gate lines TG2 and TG3 are connected to vertical drive circuits that constitute the drive circuit, and the signal lines (data output lines) VSL1, VSL2, and VSL3 are connected to a column signal processing circuit 112 that constitutes the drive circuit.

[0083] [Signal Acquisition Operation of the Photodetector] In the unit pixel P of the photodetector 1, when light is incident on the photoelectric conversion unit 20 via the on-chip lens 54, the light passes through the photoelectric conversion unit 20 and the photoelectric conversion regions 32B and 32R in that order, and is photoelectrically converted into green, blue, and red light during the passage. The signal acquisition operation for each color will be described below.

[0084] (Acquisition of Green Signal by Photoelectric Conversion Unit 20) Of the light incident on the photodetector 1, first, green light (G) is selectively detected (absorbed) by the photoelectric conversion unit 20 and photoelectrically converted.

[0085] The photoelectric conversion unit 20 is connected to the gate Gamp of the amplifier transistor AMP and the floating diffusion FD1 via the through electrode 34. Therefore, electrons of the excitons generated in the photoelectric conversion unit 20 are extracted from the lower electrode 21 side, transferred to the second surface 30S2 side of the semiconductor substrate 30 via the through electrode 34, and accumulated in the floating diffusion FD1. At the same time, the amount of charge generated in the photoelectric conversion unit 20 is modulated into a voltage by the amplifier transistor AMP.

[0086] In addition, a reset gate Grst of the reset transistor RST is disposed next to the floating diffusion FD1, so that the charge accumulated in the floating diffusion FD1 is reset by the reset transistor RST.

[0087] Since the photoelectric conversion unit 20 is connected not only to the amplifier transistor AMP but also to the floating diffusion FD1 via the through electrode 34, the charge accumulated in the floating diffusion FD1 can be easily reset by the reset transistor RST.

[0088] On the other hand, if the through electrode 34 and the floating diffusion FD1 are not connected, it becomes difficult to reset the charge accumulated in the floating diffusion FD1, and a large voltage must be applied to extract the charge to the upper electrode 25. This may damage the photoelectric conversion layer 24. Furthermore, a structure that allows resetting in a short time increases dark noise, which is a trade-off, making this structure difficult to implement.

[0089] 6 shows an example of the operation of the photodetector 1. (A) shows the potential at the storage electrode 21B, (B) shows the potential at the floating diffusion FD1 (readout electrode 21A), and (C) shows the potential at the gate (Gsel) of the reset transistor TR1rst. In the photodetector 1, voltages are applied to the readout electrode 21A and the storage electrode 21B individually.

[0090] In the photodetector 1, during the accumulation period, a potential V1 is applied from the drive circuit to the readout electrode 21A, and a potential V2 is applied to the storage electrode 21B. Here, the relationship between potentials V1 and V2 is V2 > V1. As a result, the charge (signal charge; electrons) generated by photoelectric conversion is attracted to the storage electrode 21B and accumulated in the region of the semiconductor layer 18 facing the storage electrode 21B (accumulation period). Incidentally, the potential of the region of the semiconductor layer 18 facing the storage electrode 21B becomes more negative as the photoelectric conversion time elapses. Note that holes are sent from the upper electrode 25 to the drive circuit.

[0091] In the photodetector 1, a reset operation is performed in the latter half of the accumulation period. Specifically, at timing t1, the scanning unit changes the voltage of the reset signal from low to high. As a result, in the unit pixel P, the reset transistor TR1rst is turned on, and as a result, the voltage of the floating diffusion FD1 is set to the power supply voltage and the voltage of the floating diffusion FD1 is reset (reset period).

[0092] After the reset operation is completed, the charge is read out. Specifically, at timing t2, the drive circuit applies a potential V3 to the readout electrode 21A and a potential V4 to the storage electrode 21B. Here, the potentials V3 and V4 are set to V3 > V4. As a result, the charge stored in the region corresponding to the storage electrode 21B is read out from the readout electrode 21A to the floating diffusion FD1. That is, the charge stored in the semiconductor layer 18 is read out to the control unit (transfer period).

[0093] After the read operation is completed, the drive circuit again applies potential V1 to the read electrode 21A and potential V2 to the storage electrode 21B, causing the charges generated by photoelectric conversion to be attracted to the storage electrode 21B and stored in the region of the photoelectric conversion layer 24 facing the storage electrode 21B (storage period).

[0094] (Acquisition of Blue and Red Signals by Photoelectric Conversion Regions 32B and 32R) Next, of the light transmitted through the photoelectric conversion unit 20, blue light (B) is absorbed and photoelectrically converted in the photoelectric conversion region 32B, and red light (R) is absorbed and photoelectrically converted in the photoelectric conversion region 32R, respectively. In the photoelectric conversion region 32B, electrons corresponding to the incident blue light (B) are accumulated in the n-region of the photoelectric conversion region 32B, and the accumulated electrons are transferred to the floating diffusion FD2 by the transfer transistor Tr2. Similarly, in the photoelectric conversion region 32R, electrons corresponding to the incident red light (R) are accumulated in the n-region of the photoelectric conversion region 32R, and the accumulated electrons are transferred to the floating diffusion FD3 by the transfer transistor Tr3.

[0095] [Operation of Photoelectric Conversion Unit] Next, the charge accumulation operation and charge transfer operation of the unit pixel P in the photodetector 1 will be described. FIGS. 7 and 8 respectively show a cross section (A) of the photoelectric conversion unit 20 of the unit pixel P, and examples of the energy potential of each region of the photoelectric conversion unit 20 during an accumulation period (B) and a transfer period (C). The photodetector 1 has two imaging modes: a low-gain mode in which a first electric field is applied between the lower electrode 11 and the upper electrode 12, and a high-gain mode in which a second electric field is applied between the lower electrode 11 and the upper electrode 12. Here, the first electric field is stronger than the second electric field; hereinafter, the first electric field will be referred to as a "strong electric field" and the second electric field will be referred to as a "weak electric field." FIG. 7 shows an example of the energy potential of each region of the photoelectric conversion unit 20 during an accumulation period (B), a strong electric field, and a transfer period (C) in the low-gain mode. FIG. 8 shows an example of the energy potential of each region of the photoelectric conversion unit 20 during an accumulation period (B) and a transfer period (C) in the high-gain mode.

[0096] (Charge storage operation in low-gain mode) During the storage period, a higher voltage is supplied to the storage electrode 21B of the lower electrode 21 than to the shield electrode 21C and OFB electrode 21D. As a result, as shown in FIG. 7B , the energy potential height of the region corresponding to the storage electrode 21B becomes smaller than the energy potential of the regions corresponding to the adjacent shield electrode 21C and OFB electrode 21D, and charge carriers (e.g., electrons (e) as signal charges) are stored in the region corresponding to the storage electrode 21B. As an example, a voltage of 2.8 V, which is the same as that of the readout electrode 21A, is applied to the storage electrode 21B, and a voltage of −3 V is applied to the upper electrode 25.

[0097] (Charge Transfer Operation in Low Gain Mode) During the transfer period, a voltage higher than that of the shield electrode 21C and lower than that of the OFB electrode 21D is supplied to the storage electrode 21B. As a result, as shown in Fig. 7C, the energy potential height of the region corresponding to the storage electrode 21B becomes higher than the energy potential of the region corresponding to the adjacent OFB electrode 21D, and the charge carriers stored in the region corresponding to the storage electrode 21B flow to the region corresponding to the readout electrode 21A and are transferred to the floating diffusion FD1. As an example, a voltage of 0 V is applied to the storage electrode 21B, and a voltage of -3 V is applied to the upper electrode 25.

[0098] (Charge Accumulation Operation in High Gain Mode) During the accumulation period, as in the low gain mode, a higher voltage is supplied to the storage electrode 21B of the lower electrode 21 than to the shield electrode 21C and the OFB electrode 21D. However, in the high gain mode, a lower voltage is supplied than the voltage applied in the low gain mode. As a result, as shown in FIG. 8B , the energy potential height of the region corresponding to the storage electrode 21B is higher than the energy potential in the low gain mode, and fewer charge carriers are accumulated than in the low gain mode. As an example, a voltage of 1.2 V, the same as that applied to the readout electrode 21A, is applied to the storage electrode 21B, and a voltage of −3 V is applied to the upper electrode 25. Thus, in the high gain mode, the amount of accumulated charge is reduced compared to the low gain mode, but this is not a problem due to the high gain.

[0099] (Charge Transfer Operation in High Gain Mode) During the transfer period, as in the low gain mode, a voltage higher than that of the shield electrode 21C and lower than that of the OFB electrode 21D is supplied to the storage electrode 21B. As a result, as shown in Fig. 8C, the energy potential height of the region corresponding to the storage electrode 21B becomes higher than the energy potential of the region corresponding to the adjacent OFB electrode 21D, and the charge carriers stored in the region corresponding to the storage electrode 21B flow to the region corresponding to the readout electrode 21A and are transferred to the floating diffusion FD1. As an example, a voltage of 0 V is applied to the storage electrode 21B, and a voltage of -3 V is applied to the upper electrode 25.

[0100] In this way, the photodetector 1 changes the voltage difference (electric field) between the lower electrode 21 and the upper electrode 22 by changing the voltage of the storage electrode 21B constituting the photoelectric conversion unit 20 depending on the imaging mode. The photodetector 1 has two imaging modes: a low-gain mode and a high-gain mode. In the low-gain mode, a strong electric field is applied between the lower electrode 11 and the upper electrode 12 to accumulate a large amount of signal charge. Applying a strong electric field between the lower electrode 11 and the upper electrode 12 increases dark current, but the low gain reduces the effect on image quality. On the other hand, in the high-gain mode, since there is no need to accumulate a large amount of signal charge, a weaker electric field (weak electric field) is applied between the lower electrode 11 and the upper electrode 12 than in the low-gain mode. In this case, the dark current is reduced, so the effect on image quality is minimal even with a high gain. In other words, image quality can be improved. In particular, it is possible to suppress image quality degradation due to dark current in high-gain imaging modes during dark conditions or low illuminance.

[0101] In the charge accumulation operation and charge transfer operation in the high gain mode described above, the voltage applied to the storage electrode 21B is set to a lower voltage than the voltage applied in the low gain mode, but this is not limiting. In the photodetector 1 according to this embodiment, in the charge accumulation operation and charge transfer operation in the high gain mode described above, the voltage applied to at least one of the shield electrode 21C and the OFB electrode 21D may be switched to a voltage higher than the voltage applied in the low gain mode.

[0102] 9 shows an example of a control system for the voltage (storage electrode voltage) applied to the storage electrode in the above-described low gain mode and high gain mode. The control system for the storage electrode voltage includes, for example, a voltage switching circuit unit 132, voltage generation circuits 134, 135, and 136, a timing generation circuit 1311, and a drive circuit 1111.

[0103] The voltage switching circuit unit 132 corresponds to a specific example of a "voltage switching circuit unit" according to an embodiment of the present disclosure. The voltage switching circuit unit 132 switches the voltage (storage voltage) supplied to the storage electrode 21B in accordance with the supplied gain information.

[0104] The voltage generation circuit 134 generates a voltage to be supplied to the storage electrode 21B during the accumulation period in the low gain mode. The voltage generation circuit 135 generates a voltage to be supplied to the storage electrode 21B during the accumulation period in the high gain mode. The voltage generation circuit 136 controls the voltage (transfer voltage) to be supplied to the storage electrode 21B during the transfer period. The voltage generation circuits 134, 135, and 136 may be, for example, a charge pump circuit. The accumulation voltage and transfer voltage may be supplied from outside the sensor chip 100. As will be described later, the voltage generation circuits 134, 135, and 136 may share a power supply with another power supply for the sensor chip 100, use the power supply for the logic chip 200, or use dedicated power supplies (see FIGS. 18 to 24 ).

[0105] The timing generation circuit 1311 generates timing signals that control the accumulation period and the transfer period.

[0106] Based on the timing signal generated by the timing generation circuit 1311, the drive circuit 1111 switches between the storage voltage and the transfer voltage to be supplied to the storage electrode 21B and drives it.

[0107] [Method of Determining the Shooting Mode] Next, a method of determining the above-mentioned shooting mode will be described. Fig. 10 shows an example of the configuration of the photodetector 1 including the control system for the storage electrode voltage.

[0108] Applying a gain to a pixel output is accomplished by changing the slope of a ramp wave, which is a reference voltage in the single-slope ADC 117. For example, by reducing the slope of this ramp wave, it is possible to increase the code value after AD conversion even if the pixel output is small. The slope of this ramp wave is determined by gain information supplied from the control circuit unit 131. The gain information is generated by the control circuit unit 131 and is determined based on information such as a control signal from an external application processor or the like and the signal value of the pixel data.

[0109] The control signal from an external application processor or the like in gain determination is controlled, for example, by a user setting to brighten an image or a setting for high dynamic range (HDR). The signal value of the pixel data in gain determination is determined by determining whether the average value of the pixel output of the entire screen or the average value of the pixel output of a partial area of ​​the screen is within a certain threshold value. The gain is set based on this. This gain setting may be set, for example, based on information about a frame immediately before or before acquiring the pixel data, or based on information about the average value of multiple frames immediately before or before acquiring the pixel data.

[0110] The timing generation circuit 1311 shown in Fig. 9 is included in the control circuit unit 131 shown in Fig. 10. This control circuit unit 131 corresponds to a specific example of a "control circuit unit" according to an embodiment of the present disclosure. The drive circuit 1111 shown in Fig. 10 is included in the vertical drive circuit 111 shown in Fig. 10. As described above, the storage voltage supplied to the storage electrode 21B is switched between low gain and high gain based on the gain information and input to the drive circuit 1111, and appropriate voltages are applied to the storage electrode 21B during the storage period and the transfer period in synchronization with the pixel drive timing.

[0111] [Functions and Effects] The photodetector 1 of this embodiment is provided with a control circuit 131 that acquires data and determines the imaging mode, and a voltage switching circuit 132 that switches the voltage difference applied between the lower electrode 11 and the upper electrode 25 in accordance with the imaging mode determined by the control circuit 131. In this way, an appropriate electric field in accordance with the imaging mode is applied between the lower electrode 11 and the upper electrode 25. This will be described below.

[0112] In solid-state imaging devices with organic photoelectric conversion units, charge carriers are generally accumulated by applying a reverse bias to the organic photoelectric conversion film between the lower electrode and the upper electrode. The larger the voltage difference between the lower electrode and the upper electrode, the more signal charge can be stored, but at the same time, the dark current also increases. In this case, if the set gain is high, the dark current is amplified, significantly affecting image quality.

[0113] However, if the set gain is high, the converted signal is also amplified, so there is no need to store a large amount of signal charge in the pixel, and the voltage difference between the lower electrode and the upper electrode can be small.

[0114] In contrast to this, in the present embodiment, an appropriate electric field according to the imaging mode is applied between the lower electrode 11 and the upper electrode 25. Specifically, there are provided a control circuit 131 that acquires data and determines the imaging mode, and a voltage switching circuit 132 that switches the voltage difference applied between the lower electrode 11 and the upper electrode 25 according to the imaging mode determined by the control circuit 131, and the voltage difference between the lower electrode 11 and the upper electrode 25 is changed according to the imaging mode, thereby reducing an increase in dark current while accumulating sufficient signal charge.

[0115] As a result, the photodetector 1 of this embodiment can improve image quality, particularly by suppressing image quality degradation caused by dark current in high-gain imaging modes in the dark or at low illuminance.

[0116] Next, Modifications 1 to 6 of the present disclosure and other Modifications 1 to 7, as well as application examples and applied examples, will be described. In the following, the same components as those in the above embodiment will be assigned the same reference numerals, and their description will be omitted as appropriate.

[0117] 2. Modifications (2-1. Modification 1) FIG. 11 illustrates another example of a control system for the voltage (storage electrode voltage) applied to the storage electrode in the above-described low gain mode and high gain mode, as Modification 1 of the present disclosure.

[0118] The storage electrode voltage control system of this modification is configured so that, for example, the voltage to be supplied to the storage electrode 21B during the storage period in the high gain mode is supplied from outside the sensor chip. Except for this point, the storage electrode voltage control system of this modification has substantially the same configuration as the storage electrode voltage control system of the above embodiment.

[0119] Even with this configuration, a photodetector having a control system for the storage electrode voltage of this modified example can obtain the same effects as those of the above embodiment.

[0120] (2-2. Modification 2) FIG. 12 illustrates an example of the configuration of a light detection device (light detection device 1A) according to Modification 2 of the present disclosure.

[0121] The photodetector 1A of this modification includes a column AMP 118 and an ADC 119 instead of the single-slope ADC 117. Except for this point, the photodetector 1A of this modification has substantially the same configuration as the photodetector 1 of the above embodiment.

[0122] Gain application to pixel output is performed in the column AMP 118, which is located in the preceding stage of the ADC 119. The column AMP 118 may be a switched capacitor circuit or the like that determines the amplification factor based on a capacitance ratio. The ADC 119 may be a single-slope ADC, a pipeline ADC, a successive approximation ADC, or the like. The amplification factor of the column AMP 118 is determined by gain information supplied from the control circuit unit 131. The gain information is generated by the control circuit unit 131 and is determined based on information such as a control signal from an external application processor or the like and the signal value of pixel data.

[0123] The control signal from an external application processor or the like in gain determination is controlled, for example, by a user setting to brighten an image or a setting for HDR. The signal value of pixel data in gain determination is determined by determining whether the average value of pixel output for the entire screen or the average value of pixel output for a partial area of ​​the screen is within a certain threshold value. The gain is set based on this. This gain setting may be set, for example, based on information about a frame immediately before or before acquiring pixel data, or based on information about the average value of multiple frames immediately before or before acquiring pixel data.

[0124] Even with this configuration, the photodetector 1A of this modification can achieve the same effects as those of the above embodiment.

[0125] 13 shows an example of a cross section (A) of the photoelectric conversion unit 20 of a unit pixel P, explaining the charge accumulation operation and charge transfer operation of the unit pixel P in the low gain mode in the photodetector 1 according to Modification 3 of the present disclosure, and an example of the energy potential of each region of the photoelectric conversion unit 20 during an accumulation period (B) and a transfer period (C). FIG. 14 shows an example of a cross section (A) of the photoelectric conversion unit 20 of a unit pixel P, explaining the charge accumulation operation and charge transfer operation of the unit pixel P in the high gain mode, and an example of the energy potential of each region of the photoelectric conversion unit 20 during an accumulation period (B) and a transfer period (C).

[0126] (Charge storage operation in low-gain mode) During the storage period, a higher voltage is supplied to the storage electrode 21B of the lower electrode 21 than to the shield electrode 21C and OFB electrode 21D. As a result, as shown in Fig. 13B, the energy potential height of the region corresponding to the storage electrode 21B becomes smaller than the energy potential of the regions corresponding to the adjacent shield electrode 21C and OFB electrode 21D, and charge carriers are stored in the region corresponding to the storage electrode 21B. As an example, a voltage of 2.0 V is applied to the storage electrode 21B, and a voltage of -3 V is applied to the upper electrode 25.

[0127] (Charge transfer operation in low gain mode) During the transfer period, a higher voltage is supplied to the OFB electrode 21D than to the storage electrode 21B. As a result, as shown in Fig. 13C, the energy potential height of the region corresponding to the OFB electrode 21D becomes lower than the energy potential of the region corresponding to the storage electrode 21B, and the charge carriers stored in the region corresponding to the storage electrode 21B flow to the region corresponding to the readout electrode 21A and are transferred to the floating diffusion FD1.

[0128] (Charge Storage Operation in High Gain Mode) During the storage period, as in the low gain mode, a higher voltage is supplied to the storage electrode 21B of the lower electrode 21 than to the shield electrode 21C and OFB electrode 21D. However, in the high gain mode, a lower voltage is supplied than the voltage applied in the low gain mode. As a result, as shown in FIG. 14B, the energy potential height of the region corresponding to the storage electrode 21B becomes higher than the energy potential in the low gain mode, and fewer charge carriers are stored than in the low gain mode. As an example, a voltage of 1.2 V, the same as that of the readout electrode 21A, is applied to the storage electrode 21B, and a voltage of −3 V is applied to the upper electrode 25.

[0129] (Charge Transfer Operation in High Gain Mode) During the transfer period, as in the low gain mode, a higher voltage is supplied to the OFB electrode 21D than to the storage electrode 21B. As a result, as shown in Fig. 14C, the energy potential height of the region corresponding to the OFB electrode 21D becomes lower than the energy potential of the region corresponding to the storage electrode 21B, and the charge carriers stored in the region corresponding to the storage electrode 21B flow to the region corresponding to the readout electrode 21A and are transferred to the floating diffusion FD1.

[0130] Even with this configuration, the photodetector that performs the charge accumulation operation and charge transfer operation of this modified example can obtain the same effects as those of the above embodiment.

[0131] 15 shows an example of a cross section (A) of the photoelectric conversion unit 20 of a unit pixel P, explaining the charge accumulation operation and charge transfer operation of the unit pixel P in the low gain mode in the photodetector 1 according to Modification 4 of the present disclosure, and an example of the energy potential of each region of the photoelectric conversion unit 20 during an accumulation period (B) and a transfer period (C). FIG. 16 shows an example of a cross section (A) of the photoelectric conversion unit 20 of a unit pixel P, explaining the charge accumulation operation and charge transfer operation of the unit pixel P in the high gain mode, and an example of the energy potential of each region of the photoelectric conversion unit 20 during an accumulation period (B) and a transfer period (C).

[0132] (Charge storage operation in low-gain mode) During the storage period, a higher voltage is supplied to the storage electrode 21B of the lower electrode 21 than to the shield electrode 21C and OFB electrode 21D. As a result, as shown in Fig. 15B, the energy potential height of the region corresponding to the storage electrode 21B becomes lower than the energy potential of the regions corresponding to the adjacent shield electrode 21C and OFB electrode 21D, and charge carriers are stored in the region corresponding to the storage electrode 21B. As an example, a voltage of 2.8 V, which is the same as that of the readout electrode 21A, and a voltage of -3 V are applied to the upper electrode 25.

[0133] 15C, voltages are supplied to the storage electrode 21B and the OFB electrode 21D so that the energy potential height of the region corresponding to the storage electrode 21B is lower than that of the shield electrode 21C and higher than that of the OFB electrode 21D. As a result, the charge carriers stored in the region corresponding to the storage electrode 21B flow to the region corresponding to the readout electrode 21A and are transferred to the floating diffusion FD1. As an example, a voltage of 0.5 V is applied to the storage electrode 21B, a voltage lower than that of the readout electrode 21A and higher than that of the storage electrode 21B is applied to the OFB electrode 21D, and a voltage of −3 V is applied to the upper electrode 25.

[0134] (Charge Accumulation Operation in High Gain Mode) During the accumulation period, as in the low gain mode, a higher voltage is supplied to the storage electrode 21B of the lower electrode 21 than to the shield electrode 21C and OFB electrode 21D. However, in the high gain mode, a voltage lower than that applied in the low gain mode is supplied. As a result, as shown in FIG. 16B, the energy potential height of the region corresponding to the storage electrode 21B becomes higher than that in the low gain mode, and fewer charge carriers are accumulated than in the low gain mode. As an example, a voltage of 0.5 V is applied to the storage electrode 21B, a voltage lower than that of the readout electrode 21A but higher than that of the storage electrode 21B is applied to the OFB electrode 21D, and a voltage of −3 V is applied to the upper electrode 25.

[0135] Even with this configuration, the photodetector that performs the charge accumulation operation and charge transfer operation of this modified example can obtain the same effects as those of the above embodiment.

[0136] (2-5. Fifth Modification) FIG. 17 shows another example of driving the storage electrode 21B in the photodetector 1 as a fifth modification of the present disclosure.

[0137] In the above-described embodiment and modifications 3 and 4, the voltage of the storage electrode 21B in each imaging mode takes two values, one for the storage period and one for the transfer period, but this is not limitative. For example, as shown in FIG. 17, the voltage of the storage electrode 21B may take three values, one for the storage period (A), one for the transfer transition period (B), and one for the transfer period (C).

[0138] During the accumulation period, as in the above-described embodiment and modifications 3 and 4, a higher voltage is supplied to the storage electrode 21B of the lower electrode 21 than to the shield electrode 21C and OFB electrode 21D. As a result, as shown in Fig. 17A, the energy potential height of the region corresponding to the storage electrode 21B becomes smaller than the energy potential of the regions corresponding to the adjacent shield electrode 21C and OFB electrode 21D, and charge carriers are accumulated in the region corresponding to the storage electrode 21B. As an example, a voltage of 2.8 V, which is the same as that of the readout electrode 21A, and a voltage of -3 V are applied to the upper electrode 25.

[0139] During the transfer transition period, a voltage lower than the voltage applied to the storage electrode 21B during the storage period and higher than the voltages applied to the shield electrode 21C and OFB electrode 21D is supplied to the storage electrode 21B. As a result, as shown in Fig. 17B, the energy potential height of the region corresponding to the storage electrode 21B becomes higher than the energy potential height of the region corresponding to the storage electrode 21B during the storage period, and some of the stored charge carriers flow to the region corresponding to the readout electrode 21A and are transferred to the floating diffusion FD1. As an example, a voltage of 1 V is applied to the storage electrode 21B, and a voltage of -3 V is applied to the upper electrode 25.

[0140] During the transfer period, a voltage higher than that of the shield electrode 21C and lower than that of the OFB electrode 21D is supplied to the storage electrode 21B. As a result, as shown in Fig. 17C, the energy potential height of the region corresponding to the storage electrode 21B becomes higher than the energy potential of the region corresponding to the adjacent OFB electrode 21D, and all charge carriers stored in the region corresponding to the storage electrode 21B flow to the region corresponding to the readout electrode 21A and are transferred to the floating diffusion FD1. As an example, a voltage of 0 V is applied to the storage electrode 21B, and a voltage of -3 V is applied to the upper electrode 25.

[0141] In this modified example, the voltage of the storage electrode 21B takes three values: the storage period, the transfer transition period, and the transfer period. This prevents signal charges from flowing into adjacent unit pixels P during charge transfer. This makes it possible to further improve image quality compared to the above embodiment.

[0142] (2-6. Modification 6) Fig. 18 is a schematic diagram showing an example of the configuration of the power supply in the photodetector 1 according to the above embodiment. Figs. 19 to 24 are schematic diagrams showing an example of the configuration of the power supply in the photodetector (photodetectors 2, 2A to 2E) according to Modification 6 of the present disclosure.

[0143] The photodetector 1 shown in FIG. 18 includes a semiconductor substrate 30 (sensor chip 100) on which photoelectric conversion regions 32B and 32R, each formed of, for example, a photodiode (PD), are provided. The sensor chip 100 includes, for example, a pixel array section 100A and a peripheral section 100B. The peripheral section 100B includes, for example, a vertical drive circuit 111, a column signal processing circuit 112, a horizontal drive circuit 113, an output circuit 114, a control circuit 115, input / output terminals 116, a single-slope ADC 117, a control circuit section 131, a voltage switching circuit section 132, a reference voltage generation circuit 133, and voltage generation circuits 134, 135, and 136. An external power supply 310 is connected to the sensor chip 100.

[0144] The photodetector 2 shown in FIG. 19 has a stacked structure of a sensor chip 100 and a logic chip 200. The sensor chip 100 is provided with a pixel array unit 100A. The logic chip 200 is provided with, for example, a vertical drive circuit 111, a column signal processing circuit 112, a horizontal drive circuit 113, an output circuit 114, a control circuit 115, input / output terminals 116, a single-slope ADC 117, a control circuit unit 131, a voltage switching circuit unit 132, a reference voltage generation circuit 133, and voltage generation circuits 134, 135, and 136. An external power supply 310 is connected to the sensor chip 100, and an external power supply 320 is connected to the logic chip 200. The voltage generation circuits 134, 135, and 136 provided in the logic chip 200 generate a storage voltage to be supplied to the storage electrode 21B using a power supply voltage supplied to the logic chip 200 from the external power supply 320. The storage voltages generated in the voltage generation circuits 134, 135, and 136 pass through a voltage switching circuit unit 132 controlled by gain information and a drive circuit 1111 of a vertical drive circuit 111. The output of the drive circuit 1111 is input from the logic chip 200 to the sensor chip 100 and supplied to the storage electrodes 21B of each of a plurality of unit pixels P arranged two-dimensionally in the pixel array unit 100A.

[0145] 20 has a stacked structure of a sensor chip 100 and a logic chip 200, similar to the photodetector 2. The sensor chip 100 is provided with a pixel array unit 100A. The logic chip 200 is provided with, for example, a vertical drive circuit 111, a column signal processing circuit 112, a horizontal drive circuit 113, an output circuit 114, a control circuit 115, an input / output terminal 116, a single-slope ADC 117, a control circuit unit 131, a voltage switching circuit unit 132, a reference voltage generation circuit 133, and a voltage generation circuit 136. An external power supply 310 is connected to the sensor chip 100, and external power supplies 320, 334, and 335 are connected to the logic chip 200. In the photodetector 2A, a low-gain accumulation voltage is supplied as a dedicated voltage from the external power supply 334, and a high-gain accumulation voltage is supplied as a dedicated voltage from the external power supply 335.

[0146] 21 has a stacked structure of a sensor chip 100 and a logic chip 200, similar to the photodetector 2. The sensor chip 100 is provided with a pixel array unit 100A. The logic chip 200 is provided with, for example, a vertical drive circuit 111, a column signal processing circuit 112, a horizontal drive circuit 113, an output circuit 114, a control circuit 115, an input / output terminal 116, a single-slope ADC 117, a control circuit unit 131, a voltage switching circuit unit 132, a reference voltage generation circuit 133, and a voltage generation circuit 136. An external power supply 310 is connected to the sensor chip 100, and an external power supply 320 is connected to the logic chip 200. In the photodetector 2B, the low-gain accumulation voltage and the high-gain accumulation voltage are shared with other power supply voltages supplied from the external power supply 320 to the logic chip 200.

[0147] The photodetector 2C shown in FIG. 22 has a stacked structure of a sensor chip 100 and a logic chip 200, similar to the photodetector 2. The sensor chip 100 is provided with a pixel array unit 100A. The logic chip 200 is provided with, for example, a vertical drive circuit 111, a column signal processing circuit 112, a horizontal drive circuit 113, an output circuit 114, a control circuit 115, input / output terminals 116, a single-slope ADC 117, a control circuit unit 131, a voltage switching circuit unit 132, a reference voltage generation circuit 133, and voltage generation circuits 135 and 136. An external power supply 310 is connected to the sensor chip 100, and external power supplies 320 and 334 are connected to the logic chip 200. In the photodetector 2C, for example, a low-gain accumulation voltage is supplied as a dedicated voltage from the external power supply 334, and a high-gain accumulation voltage is generated in the voltage generation circuit 135 using the power supply voltage supplied to the logic chip 200 from the external power supply 320.

[0148] 22 shows an example in which the low-gain accumulation voltage is supplied from the external power supply 334 and the high-gain accumulation voltage is supplied from the voltage generation circuit 135, but the present invention is not limited to this. The photodetector 2C may also be configured such that the low-gain accumulation voltage is supplied from the voltage generation circuit 134 and the high-gain accumulation voltage is supplied from the external power supply 335.

[0149] 23 has a stacked structure of a sensor chip 100 and a logic chip 200, similar to the photodetector 2. The sensor chip 100 is provided with a pixel array unit 100A. The logic chip 200 is provided with, for example, a vertical drive circuit 111, a column signal processing circuit 112, a horizontal drive circuit 113, an output circuit 114, a control circuit 115, input / output terminals 116, a single-slope ADC 117, a control circuit unit 131, a voltage switching circuit unit 132, a reference voltage generation circuit 133, and a voltage generation circuit 136. An external power supply 310 is connected to the sensor chip 100, and an external power supply 320 is connected to the logic chip 200. In the photodetector 2D, the low-gain accumulation voltage is shared with other power supply voltages supplied from the external power supply 320 to the logic chip 200, and the high-gain accumulation voltage is generated in the voltage generation circuit 135 using the power supply voltage supplied from the external power supply 320 to the logic chip 200.

[0150] 23 shows an example in which the accumulation voltage for low gain is shared with other power supply voltages, and the accumulation voltage for high gain is supplied from the voltage generation circuit 135, but this is not limiting. The accumulation voltage for low gain may be supplied from the voltage generation circuit 134, and may be shared with other power supply voltages for high gain.

[0151] 24 has a stacked structure of a sensor chip 100 and a logic chip 200, similar to the photodetector 2. The sensor chip 100 is provided with a pixel array unit 100A. The logic chip 200 is provided with, for example, a vertical drive circuit 111, a column signal processing circuit 112, a horizontal drive circuit 113, an output circuit 114, a control circuit 115, an input / output terminal 116, a single-slope ADC 117, a control circuit unit 131, a voltage switching circuit unit 132, a reference voltage generation circuit 133, and a voltage generation circuit 136. An external power supply 310 is connected to the sensor chip 100, and an external power supply 320 is connected to the logic chip 200. In the photodetector 2E, the low-gain accumulation voltage is shared with other power supply voltages supplied from the external power supply 320 to the logic chip 200, and the high-gain accumulation voltage is supplied as a dedicated voltage from an external power supply 335.

[0152] 24 shows an example in which the low-gain accumulation voltage is shared with other power supply voltages and the high-gain accumulation voltage is supplied from the external power supply 335, but the present invention is not limited to this. The photodetector 2E may also be configured such that the low-gain accumulation voltage is supplied as a dedicated voltage from the external power supply 334 and the high-gain accumulation voltage is shared with other power supply voltages.

[0153] In any of the above configurations, the photodetector devices 2, 2A to 2E of this modification can obtain the same effects as those of the above embodiment.

[0154] 3. Other Modifications (3-1. Other Modification 1) FIG. 25A is a schematic diagram illustrating a cross-sectional configuration of a photodetector 3A according to another modification 1 of the present disclosure. FIG. 25B is a schematic diagram illustrating an example of the planar configuration of the photodetector 3A illustrated in FIG. 25A, where FIG. 25A illustrates a cross section taken along line II-II in FIG. 25B. The photodetector 3A is a stacked photodetector in which, for example, a photoelectric conversion region 32 and a photoelectric conversion unit (e.g., the photoelectric conversion unit 20 of the above-described embodiment) are stacked. In a pixel array section 100A of a photodetector (e.g., the photodetector 1) including this photodetector 3A, pixel units 3a each consisting of four unit pixels P arranged in two rows and two columns are repeated in an array formed in the row and column directions, as illustrated in FIG. 25B.

[0155] In the photodetector 3A of this modification, a color filter 55 that selectively transmits red light (R), green light (G), and blue light (B) is provided for each unit pixel P above the photoelectric conversion unit 20 (on the light incident side S1). Specifically, in a pixel unit 3a consisting of four unit pixels P arranged in two rows and two columns, two color filters (green color filters) that selectively transmit green light (G) are arranged diagonally, and one color filter (red color filter and blue color filter) that selectively transmit red light (R) and blue light (B) is arranged on each diagonal that is perpendicular to the diagonal. In the unit pixels (Pr, Pg, Pb) provided with color filters of each color, the corresponding color light is detected, for example, in the photoelectric conversion unit 20. That is, in the pixel array unit 100A, the unit pixels (Pr, Pg, Pb) that detect red light (R), green light (G), and blue light (B), respectively, are arranged in a Bayer pattern.

[0156] The photoelectric conversion unit 20 absorbs light corresponding to some or all of the wavelengths in the visible light region of 400 nm or more and less than 750 nm, for example, to generate excitons (electron-hole pairs), and is composed of a lower electrode 21, an insulating layer 22, an oxide semiconductor layer 23, a photoelectric conversion layer 24, and an upper electrode 25 stacked in this order.

[0157] The photoelectric conversion region 32 detects, for example, an infrared light region of 750 nm or more and 1300 nm or less.

[0158] In the photodetector 3A, light in the visible light region (red light (R), green light (G), and blue light (B)) that passes through the color filters 55 is absorbed by the photoelectric conversion units 20 of the unit pixels (Pr, Pg, Pb) that are provided with the respective color filters, while other light, for example, light in the infrared light region (for example, 750 nm or more and 1000 nm or less) (infrared light (IR)), passes through the photoelectric conversion units 20. The infrared light (IR) that passes through the photoelectric conversion units 20 is detected in the photoelectric conversion regions 32 of each of the unit pixels Pr, Pg, Pb, and signal charges corresponding to the infrared light (IR) are generated in each of the unit pixels Pr, Pg, Pb. In other words, the photodetector 3A is capable of simultaneously generating both visible light images and infrared light images.

[0159] Furthermore, the photodetector 3A can acquire a visible light image and an infrared light image at the same position in the XY plane, thereby achieving high integration in the XY plane.

[0160] (3-2. Other Modification 2) Figure 26A is a schematic diagram showing a cross-sectional configuration of a photodetector 3B according to Other Modification 2 of the present disclosure. Figure 26B is a schematic diagram showing an example of the planar configuration of the photodetector 3B shown in Figure 26A, and Figure 26A shows a cross section taken along line III-III shown in Figure 26B. In the above-described Other Modification 1, an example has been shown in which the color filter 55 is provided above the photoelectric conversion unit 20 (on the light incident side S1), but the color filter 55 may also be provided between the photoelectric conversion region 32 and the photoelectric conversion unit 20, for example, as shown in Figure 26A.

[0161] In the photodetector 3B, for example, the color filter 55 has a configuration in which a color filter (color filter 55R) that selectively transmits at least red light (R) and a color filter (color filter 55B) that selectively transmits at least blue light (B) are arranged diagonally opposite each other within the pixel unit 3a. The photoelectric conversion unit 20 (photoelectric conversion layer 24) is configured to selectively absorb light having a wavelength corresponding to, for example, green light (G). The photoelectric conversion region 32R selectively absorbs light having a wavelength corresponding to red light (R), and the photoelectric conversion region 32B selectively absorbs light having a wavelength corresponding to blue light (B). This makes it possible to obtain signals corresponding to red light (R) or blue light (B) in the photoelectric conversion regions 32 (photoelectric conversion regions 32R and 32B) arranged below the photoelectric conversion unit 20 and the color filters 55R and 55B, respectively. In the photodetector 3B of this modified example, the pixel density for each of the RGB colors is higher than that of a photoelectric conversion element having a typical Bayer array, thereby improving resolution. Additionally, in the photodetector 3B of this modified example, when the resolution is made uniform, the area of ​​the photoelectric conversion section can be enlarged, making it possible to improve the S / N ratio.

[0162] 27 is a schematic diagram illustrating a cross-sectional configuration of a photodetector 3C according to another modification 3 of the present disclosure. The photodetector 3C of this modification has two photoelectric conversion units 20, 80 and one photoelectric conversion region 32 stacked in the vertical direction.

[0163] The photoelectric conversion units 20 and 80 and the photoelectric conversion region 32 selectively detect light in different wavelength ranges and perform photoelectric conversion. For example, the photoelectric conversion unit 20 acquires a green (G) color signal. For example, the photoelectric conversion unit 80 acquires a blue (B) color signal. For example, the photoelectric conversion region 32 acquires a red (R) color signal. This makes it possible for the photodetector 3C to acquire multiple types of color signals in one pixel without using color filters.

[0164] The photoelectric conversion unit 80 is stacked, for example, above the photoelectric conversion unit 20, and has the same configuration as the photoelectric conversion unit 20. Specifically, the photoelectric conversion unit 80 has a lower electrode 81, an insulating layer 82, an oxide semiconductor layer 83, a photoelectric conversion layer 84, and an upper electrode 85 stacked in this order. Like the photoelectric conversion unit 20, the lower electrode 81 is made up of multiple electrodes (e.g., a readout electrode 81A and a storage electrode 81B) and is electrically isolated by the insulating layer 82. An interlayer insulating layer 87 is provided between the photoelectric conversion unit 80 and the photoelectric conversion unit 20.

[0165] A through electrode 86 is connected to the readout electrode 81A, which penetrates the interlayer insulating layer 87 and the photoelectric conversion unit 20 and is electrically connected to the readout electrode 21A of the photoelectric conversion unit 20. Furthermore, the readout electrode 81A is electrically connected to a floating diffusion FD provided in the semiconductor substrate 30 via the through electrodes 34 and 86, and can temporarily store charge carriers generated in the photoelectric conversion layer 84. Furthermore, the readout electrode 81A is electrically connected to an amplifier transistor AMP and the like provided in the semiconductor substrate 30 via the through electrodes 34 and 86.

[0166] (3-4. Other Modifications 4 to 7) FIG. 28 is a schematic diagram illustrating an example of a cross-sectional configuration of a photodetector according to Other Modification 4 of the present disclosure (photodetector 3D). FIG. 29A is a schematic diagram illustrating an example of a cross-sectional configuration of a photodetector according to Other Modification 5 of the present disclosure (photodetector 3E). FIG. 29B is a schematic diagram illustrating an example of a planar configuration of the photodetector 3E shown in FIG. 29A. FIG. 30A is a schematic diagram illustrating an example of a cross-sectional configuration of a photodetector according to Other Modification 6 of the present disclosure (photodetector 3F). FIG. 30B is a schematic diagram illustrating an example of a planar configuration of the photodetector 3F shown in FIG. 30A. FIG. 31 is a schematic diagram illustrating an example of a cross-sectional configuration of a photodetector according to Other Modification 7 of the present disclosure (photodetector 3G). Like the photodetector 1 according to the above embodiment, the photodetectors 3D to 3G are used as imaging elements such as CMOS image sensors used in electronic devices such as digital still cameras and video cameras. The photodetecting devices 3D to 3G of this modification differ from the above-described embodiment in that the lower electrode 21 for each unit pixel P is made up of two electrodes, a storage electrode 21B and a shield electrode 21C.

[0167] Similar to the photodetector 1, the photodetectors 3D to 3F have one photoelectric conversion unit 20 and two photoelectric conversion regions 32B and 32R stacked vertically for each unit pixel P. The photoelectric conversion unit 20 is provided on the back surface (first surface 30A) side of the semiconductor substrate 30. The photoelectric conversion regions 32B and 32R are embedded in the semiconductor substrate 30 and stacked in the thickness direction of the semiconductor substrate 30.

[0168] In the photodetecting devices 3D to 3F, the shield electrode 21C is provided to absorb the ambiguous accumulated charges existing between adjacent unit pixels P and prevent the signal charges from mixing.

[0169] The photodetector 3G of this modified example, like the photodetector 3C of the other modified example 3 described above, has two photoelectric conversion units 20, 80 and one photoelectric conversion region 32 stacked vertically, and has the same configuration as the photodetector 3C described above, except that the lower electrodes 21, 81 of the photoelectric conversion units 20, 80 consist of a single electrode and no insulating layers 22, 82 are provided between the lower electrodes 21, 81 and the oxide semiconductor layers 23, 83.

[0170] In the photodetector devices 3D to 3G, when electrons are used as signal charges, the reset voltage of the storage electrode 21B is lowered to set the energy potential higher in the high-gain mode. At the same time, the voltage of the shield electrode 21C is set to the same voltage as that of the storage electrode 21B or is changed by the same ratio. This lowers the electric field applied to the organic film (e.g., the photoelectric conversion layer 24, 84), thereby suppressing dark current. When holes are used as signal charges, the reset voltage of the storage electrode 21B is increased in the high-gain mode. At the same time, the voltage of the shield electrode 21C is set to the same voltage as that of the storage electrode 21B or is changed by the same ratio. This lowers the electric field applied to the organic film (e.g., the photoelectric conversion layer 24, 84), thereby suppressing dark current, just as in the case of using electrons as signal charges.

[0171] 4. Application Examples (Application Example 1) The above-described light detection device 1 can be applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, and other devices with imaging functions.

[0172] FIG. 32 is a block diagram showing an example of the configuration of the electronic device 1000.

[0173] As shown in FIG. 32 , electronic device 1000 includes an optical system 1001, a photodetector 1, and a DSP (Digital Signal Processor) 1002. DSP 1002, memory 1003, a display device 1004, a recording device 1005, an operation system 1006, and a power supply system 1007 are connected via a bus 1008, and is capable of capturing still and moving images.

[0174] The optical system 1001 is configured to have one or more lenses, and receives incident light (image light) from a subject and forms an image on the imaging surface of the photodetector 1 .

[0175] The photodetector 1 converts the amount of incident light imaged on the imaging surface by the optical system 1001 into an electrical signal for each pixel, and supplies the signal to the DSP 1002 as a pixel signal.

[0176] The DSP 1002 performs various signal processing on the signal from the photodetector 1 to acquire an image, and temporarily stores the image data in the memory 1003. The image data stored in the memory 1003 is recorded in the recording device 1005 or supplied to the display device 1004 to display the image. In addition, the operation system 1006 accepts various operations by the user and supplies operation signals to each block of the electronic device 1000, and the power supply system 1007 supplies the power necessary to drive each block of the electronic device 1000.

[0177] (Application Example 2) Fig. 33A is a schematic diagram showing an example of the overall configuration of a light detection system 2000 including the light detection device 1. Fig. 33B is a diagram showing an example of the circuit configuration of the light detection system 2000. The light detection system 2000 includes a light emitting device 2001 serving as a light source unit that emits infrared light L2, and a light detection device 2002 serving as a light receiving unit having a photoelectric conversion element. The light detection device 1 described above can be used as the light detection device 2002. The light detection system 2000 may further include a system control unit 2003, a light source driving unit 2004, a sensor control unit 2005, a light source side optical system 2006, and a camera side optical system 2007.

[0178] The photodetector 2002 can detect light L1 and light L2. Light L1 is external ambient light reflected by the object (measurement target) 2100 ( FIG. 33A ). Light L2 is light emitted by the light-emitting device 2001 and then reflected by the object 2100. Light L1 is, for example, visible light, and light L2 is, for example, infrared light. Light L1 can be detected by a photoelectric conversion unit in the photodetector 2002, and light L2 can be detected by a photoelectric conversion region in the photodetector 2002. Image information of the object 2100 can be obtained from light L1, and distance information between the object 2100 and the photodetector system 2000 can be obtained from light L2. The photodetector system 2000 can be mounted, for example, on an electronic device such as a smartphone or a mobile object such as a car. The light-emitting device 2001 can be configured, for example, by a semiconductor laser, a surface-emitting semiconductor laser, or a vertical-cavity surface-emitting laser (VCSEL). The method of detecting the light L2 emitted from the light-emitting device 2001 by the photodetector 2002 can be, for example, an iTOF system, but is not limited to this. In the iTOF system, the photoelectric conversion unit can measure the distance to the subject 2100, for example, by the time-of-flight (TOF) of light. The method of detecting the light L2 emitted from the light-emitting device 2001 by the photodetector 2002 can also be, for example, a structured light system or a stereo vision system. For example, in the structured light system, a predetermined pattern of light is projected onto the subject 2100, and the distance between the photodetector system 2000 and the subject 2100 can be measured by analyzing the distortion of the pattern. Furthermore, in the stereo vision system, for example, two or more cameras are used to acquire two or more images of the subject 2100 viewed from two or more different viewpoints, thereby measuring the distance between the photodetector system 2000 and the subject. The light emitting device 2001 and the light detecting device 2002 can be controlled synchronously by a system control unit 2003 .

[0179] 5. Application Example Application Example to an Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0180] FIG. 34 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0181] 34 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0182] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0183] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0184] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected by the optical system onto the image sensor. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0185] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0186] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0187] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies the endoscope 11100 with irradiation light when photographing the surgical site, etc.

[0188] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0189] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0190] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0191] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0192] The light source device 11203 may also be configured to supply light in a predetermined wavelength range compatible with special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, in what is known as narrow band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light onto the body tissue. Fluorescence observation may involve irradiating excitation light onto the body tissue and observing the fluorescence from the body tissue (autofluorescence observation), or irradiating the body tissue with excitation light corresponding to the fluorescent wavelength of a reagent such as indocyanine green (ICG) to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light compatible with such special light observation.

[0193] FIG. 35 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0194] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0195] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0196] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0197] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0198] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0199] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0200] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0201] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0202] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0203] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0204] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0205] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0206] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0207] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0208] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0209] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0210] The above describes an example of an endoscopic surgery system to which the technology disclosed herein can be applied. The technology disclosed herein can be applied to the imaging unit 11402 among the components described above. Applying the technology disclosed herein to the imaging unit 11402 improves detection accuracy.

[0211] Although an endoscopic surgery system has been described as an example here, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0212] (Application Example to Mobile Object) The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, construction machinery, or agricultural machinery (tractor).

[0213] FIG. 36 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0214] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 36, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0215] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0216] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0217] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0218] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0219] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0220] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0221] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0222] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0223] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 36, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0224] FIG. 37 is a diagram showing an example of the installation position of the imaging unit 12031.

[0225] In FIG. 37, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0226] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0227] 37 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0228] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0229] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0230] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0231] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0232] The foregoing has described an example of a mobile object control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the image capture unit 12031 of the above-described configuration. Specifically, the photodetection devices (e.g., photodetection device 1) according to the above-described embodiment, Modifications 1 to 6, and other Modifications 1 to 7 can be applied to the image capture unit 12031. By applying the technology according to the present disclosure to the image capture unit 12031, it is possible to obtain high-resolution captured images with little noise, thereby enabling high-precision control using the captured images in the mobile object control system.

[0233] The above describes the embodiment, Modifications 1 to 6, and Modifications 1 to 7, as well as application examples and applied examples. However, the present disclosure is not limited to the above-described embodiments, and various modifications are possible. For example, while the above-described embodiments use electrons as signal charges, the present disclosure is not limited to this. Note that when holes are used as signal charges, the voltage applied to the storage electrode 21B in the high gain mode is switched to a voltage higher than the voltage applied in the low gain mode.

[0234] In the above embodiment, the photodetector device is configured by stacking the photoelectric conversion unit 20 that detects green light and the photoelectric conversion regions 32B and 32R that detect blue light and red light, respectively. However, the present disclosure is not limited to this structure. For example, the photoelectric conversion unit may be configured to detect red light or blue light, or the photoelectric conversion region may be configured to detect green light.

[0235] Furthermore, the number and ratio of these photoelectric conversion units and photoelectric conversion regions are not limited, and two or more photoelectric conversion units may be provided, or multiple color signals may be obtained using only the photoelectric conversion units.

[0236] Furthermore, in the above-described embodiments, the four electrodes constituting the lower electrode 21 are the readout electrode 21A, the storage electrode 21B, the shield electrode 21C, and the OFB electrode 21D, but other electrodes such as an exhaust electrode may also be provided.

[0237] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0238] The present technology may also be configured as follows. According to the present technology configured as follows, an appropriate electric field according to the imaging mode is applied between the first electrode and the second electrode, thereby improving image quality. (1) A photodetector including: a photoelectric conversion unit in which a first electrode, a photoelectric conversion layer, and a second electrode are stacked in this order; a control circuit unit that acquires data and determines the imaging mode; and a voltage switching circuit unit that switches the voltage difference between the first electrode and the second electrode according to the imaging mode determined by the control circuit unit. (2) The photodetector according to (1), wherein the photoelectric conversion unit has a plurality of electrodes that are arranged spaced apart from each other as the first electrodes, and the voltage switching circuit unit switches the voltage applied to at least one of the plurality of electrodes according to the imaging mode. (3) The photodetector according to (2), wherein the imaging modes include a first imaging mode set to a first gain and a second imaging mode set to a second gain higher than the first gain. (4) The photodetector according to (3), wherein in the second imaging mode, a voltage difference between the first electrode and the second electrode is switched to a voltage that is smaller than that in the first imaging mode. (5) The photodetector according to (4), wherein the first electrode includes, as the plurality of electrodes, a storage electrode that accumulates charge carriers generated in the photoelectric conversion layer, a readout electrode that reads out the charge carriers, an overflow barrier electrode that creates an energy barrier between the storage electrode and the readout electrode, and a shield electrode that prevents leakage of accumulated charge between adjacent pixels. (6) The photodetector according to (5), wherein the photoelectric conversion unit further includes an insulating layer between the first electrode and the photoelectric conversion layer, the storage electrode, the overflow barrier electrode, and the shield electrode are disposed opposite the photoelectric conversion layer via the insulating layer, and the readout electrode is electrically connected to the photoelectric conversion layer through an opening provided in the insulating layer. (7) The photodetector according to (6), wherein the photoelectric conversion unit further includes an oxide semiconductor layer between the insulating layer and the photoelectric conversion layer.(8) The photodetector according to any one of (5) to (7), wherein the voltage switching circuit switches the voltage applied to the storage electrode depending on the imaging mode. (9) The photodetector according to any one of (5) to (8), wherein in the second imaging mode, the voltage applied to the storage electrode is switched to a voltage lower than the voltage applied to the storage electrode in the first imaging mode. (10) The photodetector according to any one of (6) to (8), wherein in the second imaging mode, the voltage applied to at least one of the overflow barrier electrode and the shield electrode is switched to a voltage higher than the voltage applied to at least one of the overflow barrier electrode and the shield electrode in the first imaging mode. (11) The photodetector according to any one of (4) to (10), wherein the first electrode includes, as the plurality of electrodes, a storage electrode that stores charge carriers generated in the photoelectric conversion layer and a shield electrode that prevents signal charges between adjacent pixels from mixing. (12) The photodetector according to (11), wherein the voltage switching circuit switches the voltage applied to the storage electrode depending on the imaging mode. (13) The photodetector according to (11) or (12), wherein, in the second imaging mode, if the charge carriers stored in the storage electrode are electrons, the voltage applied to the storage electrode is switched to a voltage lower than the voltage applied to the storage electrode in the first imaging mode, and if the charge carriers stored in the storage electrode are holes, the voltage applied to the storage electrode is switched to a voltage higher than the voltage applied to the storage electrode in the first imaging mode. (14) The photodetector according to any one of (11) to (13), wherein in the second imaging mode, if the charge carriers accumulated by the storage electrode are electrons, the voltage applied to the shield electrode is switched to a voltage higher than the voltage applied to the shield electrode in the first imaging mode, and if the charge carriers accumulated by the storage electrode are holes, the voltage applied to the shield electrode is switched to a voltage lower than the voltage applied to the shield electrode in the first imaging mode.(15) The photodetector according to any one of (8) to (14), wherein the voltage applied to the storage electrode is further switched between a storage period in which the charge carriers are stored and a transfer period in which the stored charge carriers are transferred to the readout electrode. (16) The photodetector according to (15), wherein the voltage applied to the storage electrode during the transfer period includes a first voltage applied at an early stage of the transfer period and a second voltage lower than the first voltage applied at a middle or later stage of the transfer period. (17) The photodetector according to any one of (1) to (16), further including a voltage generation circuit that supplies one or more types of voltages to the voltage switching circuit unit. (18) The photodetector according to (17), wherein the imaging modes include a first imaging mode set to a first gain and a second imaging mode set to a second gain higher than the first gain, and the voltage generation circuit has a first voltage generation circuit that supplies a predetermined voltage to the voltage switching circuit unit in the first imaging mode and a second voltage generation circuit that supplies a predetermined voltage to the voltage switching circuit unit in the second imaging mode. (19) The photodetector according to any one of (1) to (18), wherein one or more types of voltages are supplied to the voltage switching circuit unit from an external source. (20) An electronic device comprising a photodetector, the photodetector having: a photoelectric conversion unit in which a first electrode, a photoelectric conversion layer, and a second electrode are stacked in this order; a control circuit unit that acquires data and determines the imaging mode; and a voltage switching circuit unit that switches the voltage difference between the first electrode and the second electrode in accordance with the imaging mode determined by the control circuit unit.

[0239] This application claims priority based on Japanese Patent Application No. 2024-152733, filed on September 4, 2024, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0240] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A photodetector comprising: a photoelectric conversion unit in which a first electrode, a photoelectric conversion layer, and a second electrode are stacked in this order; a control circuit unit that acquires data and determines an imaging mode; and a voltage switching circuit unit that switches the voltage difference between the first electrode and the second electrode in accordance with the imaging mode determined by the control circuit unit.

2. The photodetector device according to claim 1, wherein the photoelectric conversion unit has a plurality of electrodes arranged spaced apart from one another as the first electrodes, and the voltage switching circuit unit switches the voltage applied to at least one of the plurality of electrodes depending on the imaging mode.

3. The optical detection device of claim 2, wherein the imaging modes include a first imaging mode set to a first gain and a second imaging mode set to a second gain higher than the first gain.

4. The photodetector according to claim 3, wherein in the second imaging mode, the voltage difference between the first electrode and the second electrode is switched to a voltage that is smaller than that in the first imaging mode.

5. The photodetector device according to claim 4, wherein the first electrode includes, as the plurality of electrodes, a storage electrode that stores charge carriers generated in the photoelectric conversion layer, a readout electrode that reads out the charge carriers, an overflow barrier electrode that creates an energy barrier between the storage electrode and the readout electrode, and a shield electrode that prevents leakage of stored charge between adjacent pixels.

6. The photodetector device of claim 5, wherein the photoelectric conversion unit further has an insulating layer between the first electrode and the photoelectric conversion layer, the storage electrode, the overflow barrier electrode and the shield electrode are arranged opposite the photoelectric conversion layer via the insulating layer, and the readout electrode is electrically connected to the photoelectric conversion layer via an opening provided in the insulating layer.

7. The photodetector according to claim 6, wherein the photoelectric conversion section further includes an oxide semiconductor layer between the insulating layer and the photoelectric conversion layer.

8. The photodetector according to claim 5, wherein said voltage switching circuit section switches the voltage applied to said storage electrode depending on said imaging mode.

9. The photodetector device according to claim 5, wherein in said second imaging mode, the voltage applied to said storage electrode is switched to a voltage lower than the voltage applied to said storage electrode in said first imaging mode.

10. The photodetector device of claim 6, wherein in the second imaging mode, the voltage applied to at least one of the overflow barrier electrode and the shield electrode is switched to a voltage higher than the voltage applied to at least one of the overflow barrier electrode and the shield electrode in the first imaging mode.

11. The photodetector device according to claim 4, wherein the first electrode includes, as the plurality of electrodes, a storage electrode for storing charge carriers generated in the photoelectric conversion layer, and a shield electrode for preventing signal charges between adjacent pixels from mixing.

12. The photodetector according to claim 11, wherein said voltage switching circuit section switches the voltage applied to said storage electrode depending on said imaging mode.

13. The photodetector device of claim 11, wherein in the second imaging mode, if the charge carriers stored by the storage electrode are electrons, the voltage applied to the storage electrode is switched to a voltage lower than the voltage applied to the storage electrode in the first imaging mode, and if the charge carriers stored by the storage electrode are holes, the voltage applied to the storage electrode is switched to a voltage higher than the voltage applied to the storage electrode in the first imaging mode.

14. The photodetector device of claim 11, wherein in the second imaging mode, if the charge carriers stored by the storage electrode are electrons, the voltage applied to the shield electrode is switched to a voltage higher than the voltage applied to the shield electrode in the first imaging mode, and if the charge carriers stored by the storage electrode are holes, the voltage applied to the shield electrode is switched to a voltage lower than the voltage applied to the shield electrode in the first imaging mode.

15. The photodetector device according to claim 8, wherein the voltage applied to the storage electrode is further switched between a storage period in which the charge carriers are stored and a transfer period in which the stored charge carriers are transferred to the readout electrode.

16. The photodetector device of claim 15, wherein the voltages applied to the storage electrode during the transfer period include a first voltage applied at the beginning of the transfer period and a second voltage lower than the first voltage applied from the middle of the transfer period onwards.

17. The photodetector according to claim 1, further comprising a voltage generating circuit that supplies one or more types of voltage to said voltage switching circuit section.

18. The photodetector device of claim 17, wherein the imaging modes include a first imaging mode set to a first gain and a second imaging mode set to a second gain higher than the first gain, and the voltage generation circuit has a first voltage generation circuit that supplies a predetermined voltage to the voltage switching circuit unit in the first imaging mode, and a second voltage generation circuit that supplies a predetermined voltage to the voltage switching circuit unit in the second imaging mode.

19. The photodetector according to claim 1, wherein one or more types of voltages are supplied to the voltage switching circuit section from the outside.

20. An electronic device comprising a photodetector, the photodetector having a photoelectric conversion unit in which a first electrode, a photoelectric conversion layer, and a second electrode are stacked in this order; a control circuit unit that acquires data and determines an imaging mode; and a voltage switching circuit unit that switches the voltage difference between the first electrode and the second electrode in accordance with the imaging mode determined by the control circuit unit.

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