Substrate for electronic device, field effect transistor, and method for manufacturing substrate for electronic device

Abstract

A substrate (1) for an electronic device comprises a first diamond single-crystal layer (2), and a second diamond single-crystal layer (4) on the first diamond single-crystal layer (2). In the first diamond single-crystal layer (2), the nitrogen concentration is less than 20 ppb, the boron concentration is less than 0.01 ppb, the plane orientation of a surface (2A) is (001) plane orientation ± 3.0° or less, and the surface roughness Ra of the surface (2A) is 30 nm or less. In the second diamond single-crystal layer (4), the nitrogen concentration is less than 20 ppb, the boron concentration is 2.0 ppb to less than 20 ppb, the plane orientation of a surface (4A) is (001) plane orientation ± 3.0° or less, the surface roughness Ra of the surface (4A) is 30 nm or less, and the thickness of the second diamond single-crystal layer (4) is 50 to 400 nm. The surface (4A) is hydrogen-terminated by being covered with hydrogen, and has an NO2 adsorption surface (6) formed thereon by adsorption of NO2.　

Description

Substrate for electronic device, field effect transistor, and method for manufacturing substrate for electronic device

[0001] The present invention relates to a substrate for an electronic device, a field effect transistor, and a method for manufacturing a substrate for an electronic device. This application claims priority to Japanese Patent Application No. 2024-155348, filed on September 9, 2024, the contents of which are incorporated herein by reference.

[0002] Non-Patent Document 1 discloses a field effect transistor 100 using diamond, having a structure as shown in Figure 23. This field effect transistor 100 has a single CVD-synthesized diamond single crystal layer 102 with a (001) plane orientation, and the nitrogen concentration of this diamond single crystal layer 102 is 1 x 10 １４ cm －３ (0.568 ppb), boron concentration is 6 x 10 １５ cm －３ The surface of the diamond single crystal layer 102 is mainly oriented in the (001) plane, and the surface of the diamond single crystal layer 102 is hydrogen-terminated by hydrogen plasma treatment. ２ is adsorbed and NO ２ An adsorption surface 104 is formed.

[0003] NO ２ A source electrode 106 is formed on the first region of the attraction surface 104, and NO ２ A gate insulating film 110B and a gate electrode 112 are formed on the second region of the adsorption surface 104. ２ A drain electrode 108 is formed on the third region of the adsorption surface 104, thereby forming a field-effect transistor 100. The gate insulating film 110B is a part of the insulating film 110, and the insulating film 110 has passivation layers 110C and 110A that cover the source electrode 106 and the drain electrode 108. Non-Patent Documents 2 and 3 also describe field-effect transistors with almost the same structure as that of Non-Patent Document 1.

[0004] However, the field effect transistors shown in Non-Patent Documents 1 to 3 all have the following problems.

[0005] (1) Generation of gate leakage current Figure 24 shows the gate-source voltage (V ＧＳ ) is changed from -3V to 12V, the drain-source voltage (V ＤＳ ) and drain current (I Ｄ ) is a graph showing a linear relationship between the drain-source voltage and the drain current (I Ｄ ) has been measured. In the structure shown in FIG. 23, this is the current that flows from the drain electrode 106 to the gate electrode 112 via the gate insulating film 110B, and is called gate leakage current. This is a phenomenon that occurs when, as shown by arrow (A) in FIG. 23, a gate-source voltage is applied when the drain-source voltage is near 0V, and current flows through the gate insulating film 110B, which should be an insulator. This gate leakage current further damages the gate insulating film 110B during operation, causing the characteristics of the field-effect transistor to deteriorate over time. This problem is reported in Non-Patent Document 2 and in Fig. 2(a) in the literature.

[0006] (2) Generation of drain leakage current In the field effect transistors shown in Non-Patent Documents 1 to 3, as shown in FIG. 25 in which the drain current is logarithmically plotted, the gate-source voltage (V ＧＳ ) in the range of 0V to 12V, the negative drain current (I Ｄ ) flows, but this current is called drain leakage current. As shown by arrow (B) in Figure 23, even if a reverse gate voltage is applied, the drain current does not become zero, so it is not possible to obtain the high ON / OFF current ratio required for power semiconductor applications. This problem is reported in Figure 5(a) of Non-Patent Document 2.

[0007] (3) Short operating lifespan Furthermore, the field effect transistors shown in Non-Patent Documents 1 to 3 have the problem of short operating lifespan, which is also related to the above (1) and (2). Figure 26 is a graph of the continuous operating performance of the field effect transistor published in Non-Patent Document 3, and this graph reports that the lifetime of the field effect transistor was only 14.3 hours. As described above, conventional technologies have the problem of short lifetime and could not be put to practical use. Patent Document 1 and Non-Patent Documents 4 and 5 do not provide a solution to these problems.

[0008] Japanese Patent No. 4908409

[0009] Makoto Kasu, Kazuyuki Hirama, Kazuya Harada, Toshiyuki Oishi, Japanese Journal of Applied Physics 55, 041301 (2016) M. Kasu, M. Kubovic, A. Aleksov, N. Teofilov, Y. Taniyasu, R. Sauer, E. Kohn, T. Makimoto, N. Kobayashi, "Influence of epitaxy on the surface conduction of diamond film", Diamond and Related Materials 13, 226-232 (2004) K. Funaki, H. Ishimatsu, S. Masutani, T. Oshima, M. Kakazu, T. Oishi, "Continuous operation of double NO2-doped hydrogen-terminated diamond MOSFETs", 2017 Spring Meeting of the Japan Society of Applied Physics, Lecture No. 15, p. 315-16, Proceedings of IEEE ELECTRON. DEVICE held in Yokohama, March 14-17, 2017 LETT., VOL. 44, NO.10, PP.1704-1707, 2023 Journal of Plasma and Nuclear Fusion Research, vol.76, no.9, pp.833-841, 2000

[0010] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a substrate for an electronic device, a field-effect transistor, and a method for manufacturing a substrate for an electronic device, which, when used in the manufacture of a field-effect transistor, can suppress the occurrence of gate leakage current and drain leakage current, improve output characteristics, and enable the manufacture of a device with a long operating life.

[0011] An electronic device substrate according to a first aspect of the present invention comprises a first diamond single crystal layer and a second diamond single crystal layer formed on a surface of said first diamond single crystal layer, wherein said first diamond single crystal layer has a nitrogen concentration of 1.0 ppb or more and a boron concentration of 5.0 ppb or more, the surface of said first diamond single crystal layer has a plane orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, and said surface of said first diamond single crystal layer has a surface roughness Ra of less than 30 nm, The second diamond single crystal layer has a nitrogen concentration of less than 0.1 ppb and a boron concentration of less than 5.0 ppb, the plane orientation of the surface of the second diamond single crystal has an absolute value of an inclination angle from the (001) plane orientation of 3.0° or less, the surface roughness Ra of the surface of the second diamond single crystal is 30 nm or less, the thickness of the second diamond single crystal layer is 50 nm or more and 1600 nm or less, the surface of the second diamond single crystal layer is hydrogen-terminated by being covered with hydrogen and has p-type conductivity, and the hydrogen-terminated surface of the second diamond single crystal layer is covered with NO ２ is adsorbed, and NO ２ It is characterized by having an adsorption surface formed thereon.

[0012] According to the first aspect, a very thin second diamond single crystal layer having a thickness of 50 nm or more and 1600 nm or less is formed on a first diamond single crystal layer having high concentrations of nitrogen and boron, and this second diamond single crystal layer has a nitrogen concentration of less than 0.1 ppb, a boron concentration of less than 5.0 ppb, a plane orientation mainly of (001), and a surface roughness Ra of 30 nm or less. Therefore, when a field effect transistor is manufactured using the electronic device substrate, for example, a channel, which is a region through which a current flows between the drain and source, can be formed in the second diamond single crystal layer. By forming a channel in this second diamond single crystal layer having an impurity concentration, surface roughness, and thickness that make it difficult for a gate leakage current to flow, it is possible to suppress the gate leakage current and also suppress the drain leakage current, thereby improving the output characteristics and extending the life of the field effect transistor. Furthermore, by specifying the impurity concentration, plane orientation, and surface roughness Ra of the first diamond single crystal layer as described above, it becomes easy to form the second diamond single crystal layer with high purity and precision as described above.

[0013] In the first aspect, more preferably, the first diamond single crystal layer has a nitrogen concentration of 2.0 ppb or more and 1000 ppb or less, and a boron concentration of 6.0 ppb or more and 50 ppb or less, and the surface roughness Ra of the surface of the first diamond single crystal layer is less than 20 nm; the second diamond single crystal layer has a nitrogen concentration of 0.01 ppb or more and less than 0.1 ppb, and a boron concentration of 0.01 ppb or more and less than 5.0 ppb, the surface roughness Ra of the surface of the second diamond single crystal is 20 nm or less, and the thickness of the second diamond single crystal layer may be 50 nm or more and 400 nm or less.

[0014] A substrate for electronic devices according to a second aspect of the present invention comprises a first diamond single crystal layer and a second diamond single crystal layer formed on a surface of said first diamond single crystal layer, wherein said first diamond single crystal layer has a nitrogen concentration of 0.1 ppb or more and a boron concentration of 1.0 ppb or more, the surface of said first diamond single crystal layer has a plane orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, and said surface of said first diamond single crystal layer has a surface roughness Ra of 30 nm or less, The second diamond single crystal layer has a nitrogen concentration of less than 0.1 ppb and a boron concentration of less than 1.0 ppb, the plane orientation of the surface of the second diamond single crystal has an absolute value of an inclination angle from the (001) plane orientation of 3.0° or less, the surface roughness Ra of the surface of the second diamond single crystal is 30 nm or less, the thickness of the second diamond single crystal layer is 50 nm or more and 400 nm or less, the surface of the second diamond single crystal layer is hydrogen-terminated by being covered with hydrogen and has p-type conductivity, and further, the hydrogen-terminated surface of the second diamond single crystal layer is coated with NO ２ is adsorbed, and NO ２ It is characterized by having an adsorption surface formed thereon.

[0015] According to the second aspect, a very thin second diamond single crystal layer having a thickness of 50 nm or more and 400 nm or less is formed on a first diamond single crystal layer having a high concentration of nitrogen and boron, and the nitrogen concentration of this second diamond single crystal layer is less than 0.1 ppb, the boron concentration is less than 1.0 ppb, the plane orientation is mainly (001) plane orientation, and the surface roughness Ra is 30 nm or less. Therefore, when a field effect transistor is manufactured using the electronic device substrate, for example, a channel, which is a region through which a current flows between the drain and source, can be formed in the second diamond single crystal layer. By forming a channel in the second diamond single crystal layer having an impurity concentration, surface roughness, and thickness that make it difficult for a gate leakage current to flow, it is possible to suppress the gate leakage current and also suppress the drain leakage current, thereby improving the output characteristics and extending the life of the field effect transistor. Furthermore, by specifying the impurity concentration, plane orientation, and surface roughness Ra of the first diamond single crystal layer as described above, it becomes easy to form the second diamond single crystal layer with high purity and precision as described above.

[0016] In the second aspect, more preferably, the first diamond single crystal layer has a nitrogen concentration of 0.2 ppb or more and 1000 ppb or less, and a boron concentration of 2.0 ppb or more and 50 ppb or less, and the surface roughness Ra of the surface of the first diamond single crystal layer is less than 20 nm; the second diamond single crystal layer has a nitrogen concentration of 0.01 ppb or more and less than 0.1 ppb, and a boron concentration of 0.01 ppb or more and less than 1.0 ppb, and the surface roughness Ra of the surface of the second diamond single crystal is 20 nm or less, and the thickness of the second diamond single crystal layer may be 50 nm or more and 200 nm or less.

[0017] A substrate for electronic devices according to a third aspect of the present invention comprises a first diamond single crystal layer and a second diamond single crystal layer formed on a surface of the first diamond single crystal layer, wherein the first diamond single crystal layer has a nitrogen concentration of less than 20 ppb and a boron concentration of less than 0.01 ppb, the surface of the first diamond single crystal layer has a plane orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, and the surface of the first diamond single crystal layer has a surface roughness Ra of 30 nm or less. The second diamond single crystal layer has a nitrogen concentration of less than 20 ppb and a boron concentration of 2.0 ppb or more but less than 20 ppb, the plane orientation of the surface of the second diamond single crystal has an absolute value of an inclination angle from the (001) plane orientation of 3.0° or less, the surface roughness Ra of the surface of the second diamond single crystal is 30 nm or less, the thickness of the second diamond single crystal layer is 50 nm or more but 400 nm or less, the surface of the second diamond single crystal layer is hydrogen-terminated by being covered with hydrogen and has p-type conductivity, and further, the hydrogen-terminated surface of the second diamond single crystal layer contains NO ２ is adsorbed, and NO ２ It is characterized by having an adsorption surface formed thereon.

[0018] According to the third aspect, a very thin second diamond single crystal layer having a thickness of 50 nm or more and 400 nm or less is formed on a first diamond single crystal layer having a high concentration of nitrogen and boron, and this second diamond single crystal layer has a nitrogen concentration of less than 20 ppb, a boron concentration of 2.0 ppb or more and less than 20 ppb, a plane orientation of mainly (001) plane orientation, and a surface roughness Ra of 30 nm or less, so that when a field effect transistor is manufactured using the electronic device substrate, for example, a channel, which is a region through which a current flows between the drain and source, can be formed in the second diamond single crystal layer. By forming a channel in this second diamond single crystal layer having an impurity concentration, surface roughness, and thickness that make it difficult for a gate leakage current to flow, it is possible to suppress the gate leakage current and also suppress the drain leakage current, thereby improving the output characteristics and extending the life of the field effect transistor. Furthermore, by specifying the impurity concentration, plane orientation and surface roughness Ra of the first diamond single crystal layer as described above, it becomes easy to form the second diamond single crystal layer with high purity and precision as described above.

[0019] More preferably, in the third aspect, the first diamond single crystal layer has a nitrogen concentration of 0.2 ppb or more and 20 ppb or less, and a boron concentration of 0.001 ppb or more and less than 0.01 ppb, the surface roughness Ra of the surface of said first diamond single crystal layer is less than 20 nm, and the second diamond single crystal layer has a nitrogen concentration of 0.2 ppb or more and less than 20 ppb, and a boron concentration of 2.0 ppb or more and 10 ppb or less, the surface roughness Ra of the surface of said second diamond single crystal is 20 nm or less, and the thickness of said second diamond single crystal layer is 50 nm or more and 200 nm or less, although it is not limited to these ranges.

[0020] A field effect transistor according to a fourth aspect of the present invention comprises a substrate for electronic devices according to any one of the first to third aspects, and the NOx of the second diamond single crystal layer. ２ a source electrode formed on the first region of the adsorption surface; and ２a gate insulating film formed on the second region of the adsorption surface; a gate electrode formed on the gate insulating film; and the NOx of the second diamond single crystal layer. ２ and a drain electrode formed on the third region of the adsorption surface.

[0021] In the field effect transistor according to the fourth aspect of the present invention, by forming a channel in the second diamond single crystal layer which has an impurity concentration, surface roughness and thickness that make it difficult for gate leakage current to flow, as described above, it is possible to suppress gate leakage current and also to suppress drain leakage current, thereby improving output characteristics and extending the life of the field effect transistor.

[0022] An integrated circuit element according to a fifth aspect of the present invention is an integrated circuit element comprising a substrate for an electronic device according to any one of the first to third aspects, and a plurality of field effect transistors formed on the substrate for an electronic device, wherein the field effect transistors are formed by applying a voltage to the NOx of the second diamond single crystal layer. ２ a source electrode formed on the first region of the adsorption surface; and ２ a gate insulating film formed on the second region of the adsorption surface; a gate electrode formed on the gate insulating film; and the NOx of the second diamond single crystal layer. ２ and a drain electrode formed on the third region of the adsorption surface.

[0023] The integrated circuit device according to the fifth aspect of the present invention also forms a channel in the second single-crystal diamond layer, which has an impurity concentration, surface roughness and thickness that make it difficult for gate leakage current to flow, thereby suppressing gate leakage current and also suppressing drain leakage current, thereby improving output characteristics and extending the life of the field-effect transistor. This structure also makes it easy to integrate devices.

[0024] A method for manufacturing a substrate for an electronic device according to a sixth aspect of the present invention comprises preparing a first diamond single crystal layer having a nitrogen concentration of 1.0 ppb or more, a boron concentration of 5.0 ppb or more, a surface orientation having an inclination angle from the (001) orientation of 3.0° or less in absolute value, and a surface roughness Ra of 30 nm or less, and by plasma CVD, introducing onto the first diamond single crystal layer a reactive gas containing hydrocarbon gas, hydrogen gas, and nitrogen gas and boron gas as dopants, while maintaining the temperature of the first diamond single crystal layer at 650°C or more and 950°C or less and the pressure of the reactive gas at 40 Torr or more. and 60 Torr or less, a ratio of the flow rate of the hydrocarbon gas to the flow rate of the hydrogen gas (flow rate of the hydrocarbon gas / flow rate of the hydrogen gas) is 1:200 to 1:50, a nitrogen concentration of less than 0.1 ppb, a boron concentration of less than 5.0 ppb, a surface orientation having an inclination angle from the (001) plane orientation of an absolute value of 3.0° or less, a surface roughness Ra of 30 nm or less, and a thickness of 50 nm or more and 1600 nm or less, and the surface of the second diamond single crystal layer is hydrogen-terminated to impart p-type conductivity, and NO is introduced into the surface of the second diamond single crystal layer. ２ The hydrogen-terminated surface is exposed to NO gas. ２ By adsorbing NO ２ It is characterized by forming an adsorption surface.

[0025] A method for manufacturing a substrate for an electronic device according to a seventh aspect of the present invention comprises preparing a first diamond single crystal layer having a nitrogen concentration of 0.1 ppb or more, a boron concentration of 1.0 ppb or more, a surface orientation having an absolute value of an inclination angle from the (001) orientation of 3.0° or less, and a surface roughness Ra of 30 nm or less, and introducing a reactive gas containing a hydrocarbon gas, a hydrogen gas, and nitrogen gas and boron gas as dopants onto the first diamond single crystal layer by plasma CVD, while setting the temperature of the first diamond single crystal layer to 650°C or more and 950°C or less, the pressure of the reactive gas to 40 Torr or more and 60 Torr or less, and the ratio of the flow rate of the hydrocarbon gas to the flow rate of the hydrogen gas (flow rate of the hydrocarbon gas / flow rate of the hydrogen gas) to 1:200 to 1:50, A second diamond single crystal layer is formed, the second diamond single crystal layer having a nitrogen concentration of less than 0.1 ppb, a boron concentration of less than 1.0 ppb, a surface orientation in which the absolute value of the tilt angle from the (001) surface orientation is 3.0° or less, a surface roughness Ra of 30 nm or less, and a thickness of 50 nm or more and 400 nm or less, and the surface of the second diamond single crystal layer is hydrogen-terminated to impart p-type conductivity, and NO is introduced into the surface of the second diamond single crystal layer. ２ The hydrogen-terminated surface is exposed to NO gas. ２ By adsorbing NO ２ It is characterized by forming an adsorption surface.

[0026] A method for manufacturing an electronic device substrate according to an eighth aspect of the present invention comprises: preparing a first diamond single crystal layer having a nitrogen concentration of less than 20 ppb, a boron concentration of less than 0.01 ppb, a surface orientation having an absolute value of an inclination angle from the (001) orientation of 3.0° or less, and a surface roughness Ra of 30 nm or less; and introducing a reactive gas containing a hydrocarbon gas, a hydrogen gas, and nitrogen gas and boron gas as dopants onto the first diamond single crystal layer by plasma CVD, while setting the temperature of the first diamond single crystal layer to 650°C or more and 950°C or less, the pressure of the reactive gas to 40 Torr or more and 60 Torr or less, and the ratio of the flow rate of the hydrocarbon gas to the flow rate of the hydrogen gas (flow rate of the hydrocarbon gas / flow rate of the hydrogen gas) to 1:200 to 1:50; A second diamond single crystal layer is formed, the second diamond single crystal layer having a nitrogen concentration of less than 20 ppb, a boron concentration of 2.0 ppb or more but less than 20 ppb, a surface orientation in which the absolute value of the tilt angle from the (001) surface orientation is 3.0° or less, a surface roughness Ra of the surface is 30 nm or less, and a thickness of 50 nm or more but 400 nm or less, and the surface of the second diamond single crystal layer is hydrogen-terminated to impart p-type conductivity, and NO is applied to the surface of the second diamond single crystal layer. ２ The hydrogen-terminated surface is exposed to NO gas. ２ By adsorbing NO ２ It is characterized by forming an adsorption surface.

[0027] According to the method for manufacturing a substrate for an electronic device according to any one of the sixth to eighth aspects of the present invention, it is possible to efficiently manufacture a substrate for an electronic device having the above-mentioned excellent properties. In the sixth aspect, the same more preferred ranges as in the first aspect are invoked. In the seventh aspect, the same more preferred ranges as in the second aspect are invoked. In the eighth aspect, the same more preferred ranges as in the third aspect are invoked.

[0028] According to the present invention, by forming a channel in the second diamond single crystal layer, which is formed on the first diamond single crystal layer with high nitrogen and boron concentration, and has impurity concentration, surface roughness and thickness that make leakage current difficult to flow, it is possible to suppress gate leakage current and also suppress drain leakage current, improve output characteristics and extend the life of field effect transistor.In addition, by defining the impurity concentration, plane orientation and surface roughness Ra of the first diamond single crystal layer as above, it is easy to form the second diamond single crystal layer with high purity and high precision as above.

[0029] FIG. 1 is an enlarged cross-sectional view of a substrate for an electronic device according to an embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view of a field effect transistor according to an embodiment of the present invention. FIG. 3 is an enlarged cross-sectional view showing a method for manufacturing a field effect transistor according to an embodiment of the present invention. FIG. 4 is an enlarged cross-sectional view showing a method for manufacturing a field effect transistor according to an embodiment of the present invention. FIG. 5 is an enlarged cross-sectional view showing a method for manufacturing a field effect transistor according to an embodiment of the present invention. FIG. 6 is a graph showing gate leakage characteristics of a field effect transistor according to Example 1 of the present invention. FIG. 7 is a graph showing drain leakage characteristics of a field effect transistor according to Example 1. FIG. 8 is a graph showing the results of a service life test of the field effect transistor according to Example 1. FIG. 9 is a graph showing output characteristics of a field effect transistor according to Comparative Example 1. FIG. 10 is a graph showing output characteristics of a field effect transistor according to Comparative Example 2. FIG. 11 is a graph showing output characteristics of a field effect transistor according to Example 2. FIG. 12 is a graph showing output characteristics of a field effect transistor according to Example 3. FIG. 13 is a graph showing output characteristics of a field effect transistor according to Example 4. FIG. 14 is a graph showing output characteristics of a field effect transistor according to Example 5. FIG. 15 is a graph showing output characteristics of a field effect transistor according to Comparative Example 3. FIG. 16 is a graph showing output characteristics of a field effect transistor according to Comparative Example 4. ＢＲ ) characteristics of the field effect transistors of Examples 2 to 5 and Comparative Examples 1 to 4. Ｄ 1 is a graph showing the thickness d dependency characteristics of R ＯＮ1 is a graph showing the thickness d dependency characteristics of V of the field effect transistors of Examples 2 to 5 and Comparative Examples 1 to 4. ＢＲ 10 is a graph showing the thickness d dependency characteristics of the field effect transistor of Example 6. FIG. 11 is a graph showing the gate leakage characteristics of the field effect transistor of Example 6. FIG. 12 is a graph showing the drain leakage characteristics of the field effect transistor of Example 6. FIG. 13 is an enlarged cross-sectional view of a field effect transistor according to the prior art. FIG. 14 is a graph showing the gate leakage of a field effect transistor according to the prior art. FIG. 15 is a graph showing the drain leakage of a field effect transistor according to the prior art. FIG. 16 is a graph showing the service life of a field effect transistor according to the prior art. FIG. 17 is a graph showing the measurement results by secondary ion mass spectrometry, showing the distribution of nitrogen concentration and boron concentration in the depth direction of the substrate 1 for electronic devices of Example 7. FIG. 18 is a graph showing the output characteristics of the diamond field effect transistor of Example 7. FIG. 19 is a graph showing the high-frequency small signal characteristics of the diamond field effect transistor of Example 7.

[0030] Hereinafter, embodiments of the substrate for an electronic device, the field effect transistor, and the method for manufacturing the substrate for an electronic device of the present invention will be described with reference to the drawings. Note that the dimensions of the components shown in the drawings do not reflect the dimensions of the actual products.

[0031] [First embodiment of electronic device substrate] FIG. 1 is an enlarged cross-sectional view showing one embodiment of an electronic device substrate according to the present invention, and this electronic device substrate 1 has a first diamond single crystal layer 2 and a second diamond single crystal layer 4 formed on the surface of the first diamond single crystal layer 2.

[0032] The first diamond single crystal layer 2 used in the first embodiment has a nitrogen concentration of 1.0 ppb or more and a boron concentration of 5.0 ppb or more. If the nitrogen concentration of the first diamond single crystal layer 2 is less than 1.0 ppb and / or the boron concentration is less than 5.0 ppb, channels will also be formed in the first diamond single crystal layer 2, reducing the effect of forming channels only in the second diamond single crystal layer 4 and increasing the cost of the electronic device substrate 1. The nitrogen concentration of the first diamond single crystal layer 2 may more preferably be 2.0 ppb or more and 1000 ppb or less, and the boron concentration may more preferably be 6.0 ppb or more and 50 ppb or less. Nitrogen concentrations of 20 ppb or less can be measured using secondary ion mass spectroscopy (SIMS), which has a low detection limit, while nitrogen concentrations of 20 ppb or more can be measured using electron spin resonance (ESR, also known as electron paramagnetic resonance (EPR)), which has a relatively high detection limit but good sensitivity.

[0033] The nitrogen concentration and boron concentration in a diamond single crystal can be measured using well-known secondary ion mass spectrometry (SIMS) or electron spin resonance (ESR).

[0034] The plane orientation of the surface 2A of the first diamond single crystal layer 2 has an absolute value of the tilt angle from the (001) plane orientation of 3.0° or less. If the absolute value of the tilt angle exceeds 3.0°, it becomes difficult to align the plane orientation of the second diamond single crystal layer 4 with the (001) plane orientation with high precision. The absolute value of the tilt angle may be 0.3° or more and 3.0° or less. The plane orientation in the diamond single crystal can be measured by electron backscatter diffraction pattern method (EBSP method) using a scanning electron microscope (SEM).

[0035] The surface roughness Ra of the surface 2A of the first diamond single crystal layer 2 is 30 nm or less, and if the surface roughness Ra of the surface 2A exceeds 30 nm, it becomes difficult to sufficiently reduce the roughness and the irregularity of the plane orientation of the surface 4A of the second diamond single crystal layer 4, which may cause problems in the manufacture of the device. The surface roughness Ra of the surface 2A may more preferably be 20 nm or less. There is no particular restriction on the lower limit of the surface roughness Ra of the surface 2A, but making it too small incurs extra costs, so the surface roughness Ra may be 1.0 nm or more. The surface roughness of the diamond single crystal can be measured using a well-known stylus-type surface roughness measuring instrument, a non-contact measuring instrument using white light interferometry, an atomic force microscope, or the like.

[0036] The second diamond single crystal layer 4 has a nitrogen concentration of less than 0.1 ppb and a boron concentration of less than 5.0 ppb. If the nitrogen concentration is 0.1 ppb or more and / or the boron concentration exceeds 5.0 ppb, current will flow via impurities, and the second diamond single crystal layer 4 will not be effective in suppressing gate leakage current and / or drain leakage current. The nitrogen concentration of the second diamond single crystal layer 4 may more preferably be 0.01 ppb or more and less than 0.1 ppb, and the boron concentration may more preferably be 0.01 ppb or more and less than 5.0 ppb.

[0037] The surface orientation of the second diamond single crystal layer 4 has an absolute value of an inclination angle from the (001) orientation of 3.0° or less. If the absolute value of the inclination angle exceeds 3.0°, it becomes difficult to ensure high performance as a field effect transistor. A smaller absolute value of the inclination angle is better, but this increases costs, so the absolute value of the inclination angle may be 0.3° or more.

[0038] The surface roughness Ra of the surface 4A of the second diamond single crystal layer 4 is 30 nm or less. If the surface roughness Ra of the surface 4A exceeds 30 nm, there is a risk of problems occurring in the manufacture of the device. The surface roughness Ra of the surface 4A may more preferably be 20 nm or less. There is no particular lower limit to the surface roughness Ra of the surface 4A, but making it too small incurs extra costs, so the surface roughness Ra may be 1.0 nm or more.

[0039] The thickness d of the second diamond single crystal layer 4 is 50 nm or more and 1600 nm or less. If the thickness d is less than 50 nm, it becomes difficult to confine most of the channel within the second diamond single crystal layer 4, and the gate leakage current suppression effect and / or drain leakage current suppression effect of the present invention becomes insufficient. On the other hand, if the thickness d exceeds 1600 nm, the channel width becomes too large, and the gate leakage current suppression effect and / or drain leakage current suppression effect also becomes insufficient. The thickness d of the second diamond single crystal layer 4 may more preferably be 50 nm or more and 400 nm.

[0040] The surface 4A of the second diamond single crystal layer 4 is covered with hydrogen atoms by, for example, exposing it to hydrogen plasma, so that the ends of the carbon atoms are hydrogen-terminated, and it has p-type conductivity.In diamond, P is the donor impurity and B is the acceptor impurity, but since their ionization energies are 0.58 and 0.37 eV, respectively, which are more than one order of magnitude higher than the thermal energy (26 meV) at room temperature, the ionization rate by the impurity is extremely low, and the carrier concentration required for device operation cannot be obtained.Therefore, by hydrogen-terminating the surface 4A of the second diamond single crystal layer 4, the surface 4A has p-type conductivity, and the conductivity required for the device can be obtained.

[0041] The hydrogen-terminated surface 4A of the second diamond single crystal layer 4 is further treated with NO ２ is adsorbed, and NO ２ The adsorption surface 6 is formed on the hydrogen-terminated surface 4A. ２ By adsorbing hydrogen in a monomolecular state, the hole concentration on the surface 4A can be increased more than in the case of hydrogen termination alone, and the conductivity required for a device can be obtained.

[0042] According to the electronic device substrate 1 of the first embodiment having the above-mentioned configuration, an extremely thin second diamond single crystal layer 4 of 50 nm or more and 1600 nm or less is formed on the first diamond single crystal layer 2 having high concentrations of nitrogen and boron, and this second diamond single crystal layer 4 has a nitrogen concentration of less than 0.1 ppb, a boron concentration of less than 5.0 ppb, a plane orientation mainly of (001), and a surface roughness Ra of 30 nm or less, so that when a field effect transistor is manufactured using the electronic device substrate 1, for example, a channel, which is a region through which current flows between the drain and source, can be formed mainly in the second diamond single crystal layer 4. By forming a channel in the second diamond single crystal layer 4 having an impurity concentration, surface roughness, and thickness that make it difficult for gate leakage current to flow, it is possible to suppress the gate leakage current and also suppress the drain leakage current, thereby improving the output characteristics and extending the life of the field effect transistor. Furthermore, by specifying the impurity concentration, plane orientation and surface roughness Ra of the first diamond single crystal layer 2 as described above, it becomes easy to form the second diamond single crystal layer 4 with high purity and precision as described above.

[0043] [Electronic Device Substrate of Second Embodiment] The electronic device substrate of the second embodiment has the same basic structure as the first embodiment, and will therefore be described again with reference to Fig. 1. In this second embodiment, the parameters of each part are different from those of the first embodiment, and therefore the description will focus on the different points, and the description of the first embodiment will be used for the other points.

[0044] The first diamond single crystal layer 2 used in the second embodiment has a nitrogen concentration of 0.1 ppb or more and a boron concentration of 1.0 ppb or more. If the nitrogen concentration of the first diamond single crystal layer 2 is less than 0.1 ppb and / or the boron concentration is less than 1.0 ppb, the effect of forming channels only in the second diamond single crystal layer 4 will be reduced, and the source gases, methane gas and hydrogen gas, will need to be specially purified (impurities reduced), increasing the cost of the electronic device substrate 1. More preferably, the nitrogen concentration of the first diamond single crystal layer 2 may be 0.2 ppb or more and 1000 ppb or less, and the boron concentration may be 2.0 ppb or more and 50 ppb or less.

[0045] In the second embodiment, the second diamond single crystal layer 4 has a nitrogen concentration of less than 0.1 ppb and a boron concentration of less than 1.0 ppb. If the nitrogen concentration is 0.1 ppb or more and / or the boron concentration is 1.0 ppb or more, current will flow via impurities, and the effect of the second diamond single crystal layer 4 in suppressing gate leakage current and / or drain leakage current will be insufficient. The nitrogen concentration of the second diamond single crystal layer 4 may more preferably be 0.01 ppb or more and less than 0.1 ppb, and the boron concentration may more preferably be 0.01 ppb or more and less than 1.0 ppb.

[0046] In the second embodiment, the plane orientation and surface roughness Ra of the surface 2A of the first diamond single crystal layer 2 may be the same as in the first embodiment, and therefore the same explanation will be used.

[0047] In the second embodiment, the thickness d of the second diamond single crystal layer 4 is set to be 50 nm or more and 400 nm or less. If the thickness d is less than 50 nm, it becomes difficult to confine most of the channel within the second diamond single crystal layer 4, and the gate leakage current suppression effect and / or drain leakage current suppression effect of the present invention becomes insufficient. On the other hand, if the thickness d exceeds 400 nm, the channel thickness becomes too large, and the gate leakage current suppression effect and / or drain leakage current suppression effect also becomes insufficient. The thickness d of the second diamond single crystal layer 4 may more preferably be 50 nm or more and 200 nm or less.

[0048] In the second embodiment, the surface 4A of the second diamond single crystal layer 4 is hydrogen-terminated by being covered with hydrogen, and has p-type conductivity. ２ is adsorbed, and NO ２ The adsorption surface 6 is formed on the second embodiment. These configurations are the same as those in the first embodiment, and therefore the same description will be used.

[0049] According to the second embodiment, an extremely thin second diamond single crystal layer 4 of 50 nm or more and 400 nm or less is formed on a first diamond single crystal layer 2 having high concentrations of nitrogen and boron, and this second diamond single crystal layer 4 has a nitrogen concentration of less than 0.1 ppb, a boron concentration of less than 1.0 ppb, a plane orientation mainly of (001), and a surface roughness Ra of 30 nm or less, so that when a field effect transistor, for example, is manufactured using the electronic device substrate, a channel, which is a region through which current flows between the drain and source, can be formed in the second diamond single crystal layer 4. By forming a channel in the second diamond single crystal layer 4 having an impurity concentration, surface roughness, and thickness that make it difficult for gate leakage current to flow, it is possible to suppress gate leakage current and also suppress drain leakage current, thereby improving output characteristics and extending the life of the field effect transistor. Furthermore, by specifying the impurity concentration, plane orientation and surface roughness Ra of the first diamond single crystal layer 2 as described above, it becomes easy to form the second diamond single crystal layer 4 with high purity and precision as described above.

[0050] [Electronic Device Substrate of Third Embodiment] The electronic device substrate of the third embodiment has the same basic structure as the first and second embodiments, and will therefore be described again with reference to Fig. 1. In this third embodiment, the parameters of each part are different from those of the first and second embodiments, and therefore the description will focus on the different points, and the description of the first and second embodiments will be used for the other points.

[0051] The first diamond single crystal layer 2 used in the third embodiment has a nitrogen concentration of less than 20 ppb and a boron concentration of less than 0.01 ppb. If the nitrogen concentration of the first diamond single crystal layer 2 is 20 ppb or more and / or the boron concentration is 0.01 ppb or more, current will flow via impurities, reducing the effect of forming a channel only in the second diamond single crystal layer 4 and increasing the cost of the electronic device substrate 1. More preferably, the nitrogen concentration of the first diamond single crystal layer 2 may be 0.2 ppb or more and less than 20 ppb, and the boron concentration may be 0.001 ppb or more and less than 0.01 ppb.

[0052] The second diamond single crystal layer 4 in the third embodiment has a nitrogen concentration of less than 20 ppb and a boron concentration of 2.0 ppb or more but less than 20 ppb. If the nitrogen concentration is 20 ppb or more and / or the boron concentration is less than 2.0 ppb or 20 ppb or more, current will flow via impurities, and the second diamond single crystal layer 4 will not be effective in suppressing gate leakage current and / or drain leakage current. The nitrogen concentration of the second diamond single crystal layer 4 may more preferably be 0.2 ppb or more but less than 20 ppb, and the boron concentration may more preferably be 2.0 ppb or more but 10 ppb or less.

[0053] In the third embodiment, the plane orientation and surface roughness Ra of the surface 2A of the first diamond single crystal layer 2 may be the same as those in the first and second embodiments, and therefore the explanations therefor are incorporated herein.

[0054] In the third embodiment, the thickness d of the second diamond single crystal layer 4 is set to 50 nm or more and 400 nm or less. If the thickness d is less than 50 nm, it becomes difficult to confine most of the channel within the second diamond single crystal layer 4, and the effect of suppressing the gate leakage current and / or the drain leakage current of the present invention becomes insufficient. On the other hand, if the thickness d exceeds 400 nm, the channel becomes too thick, and the effect of suppressing the gate leakage current and / or the drain leakage current becomes insufficient. The thickness d of the second diamond single crystal layer 4 may more preferably be 50 nm or more and 200 nm or less.

[0055] In the third embodiment, the surface 4A of the second diamond single crystal layer 4 is hydrogen-terminated by being covered with hydrogen, and has p-type conductivity. ２ is adsorbed, and NO ２ The adsorption surface 6 is formed on the surface 6. These configurations are common to the first and second embodiments, and therefore the same description will be used.

[0056] According to the third embodiment, an extremely thin second diamond single crystal layer 4 of 50 nm or more and 400 nm or less is formed on a first diamond single crystal layer 2 having a nitrogen concentration of less than 20 ppb and a boron concentration of less than 0.01 ppb, and this second diamond single crystal layer 4 has a nitrogen concentration of less than 20 ppb, a boron concentration of 2.0 ppb or more and less than 20 ppb, a plane orientation mainly of (001), and a surface roughness Ra of 30 nm or less, so that when a field effect transistor, for example, is manufactured using the electronic device substrate, a channel, which is a region through which current flows between the drain and source, can be formed in the second diamond single crystal layer 4. By forming a channel in the second diamond single crystal layer 4 having an impurity concentration, surface roughness, and thickness that make it difficult for gate leakage current to flow in this way, it is possible to suppress gate leakage current and also suppress drain leakage current, thereby improving output characteristics and extending the life of the field effect transistor. Furthermore, by specifying the impurity concentration, plane orientation and surface roughness Ra of the first diamond single crystal layer 2 as described above, it becomes easy to form the second diamond single crystal layer 4 with high purity and precision as described above.

[0057] [Field-effect transistor of the fourth embodiment] As shown in FIG. 2, the field-effect transistor of the fourth embodiment is manufactured using the substrate 1 for electronic devices according to any one of the first to third embodiments, and the NOx on the second diamond single crystal layer 4 is ２ The source electrode 8 formed on the first region of the adsorption surface 6 and the NOx of the second diamond single crystal layer 4 ２ A gate insulating film 12B is formed on a second region of the adsorption surface 6 that is different from the first region, a gate electrode 14 is formed on the gate insulating film 12B, and the NOx of the second diamond single crystal layer 4 is formed on the gate insulating film 12B. ２ and a drain electrode 10 formed on a third region different from the first and second regions of the attraction surface 6. A passivation film 12C is formed on the source electrode 8, and a passivation film 12A is formed on the drain electrode 10. In this embodiment, the passivation film 12A, the gate insulating film 12B, and the passivation film 12C are formed as the same insulating layer 12.

[0058] The shapes of the first to third regions formed on the electronic device substrate 1 may be the same as those of conventional field effect transistors, and the shapes of the source electrode 8, gate electrode 14, and drain electrode 10 may also be the same as those of conventional field effect transistors. The materials of the source electrode 8, gate electrode 14, and drain electrode 10 may also be the same as those of conventional field effect transistors, and may be formed of, for example, Au or Al, and their thickness is not limited, but may be about 50 nm or more and 500 nm or less, and more preferably 100 nm or more and 400 nm or less.

[0059] The material and thickness of the insulating layer 12 may be the same as those of a conventional field effect transistor. The material of the insulating layer 12 may be, for example, Al. ２ O ３ , SiO ２ , HfO ２ The thickness of the insulating layer 12 is not limited, but may be about 8 nm or more and 160 nm or less, and more preferably 12 nm or more and 80 nm or less.

[0060] According to the field effect transistor of the fourth embodiment, by forming a channel in the second diamond single crystal layer 4, which has an impurity concentration, surface roughness and thickness that make it difficult for gate leakage current to flow, as described above, it is possible to suppress gate leakage current and drain leakage current, thereby obtaining good output characteristics and extending the life of the field effect transistor.

[0061] [Integrated Circuit of Fifth Embodiment] The integrated circuit element of the fifth embodiment is an integrated circuit element comprising the substrate 1 for electronic devices of any one of the first to third embodiments and a plurality of field effect transistors formed on the substrate 1 for electronic devices, and each field effect transistor is formed by using the NOx of the second diamond single crystal layer 4, as in the third embodiment. ２ The source electrode 8 formed on the first region of the adsorption surface 6 and the NOx of the second diamond single crystal layer 4 ２ A gate insulating film 12B formed on the second region of the adsorption surface 6, a gate electrode 14 formed on the gate insulating film 12B, and the NOx of the second diamond single crystal layer 4. ２and a drain electrode 10 formed on the third region of the absorbing surface 6. The integrated circuit element may include not only a field effect transistor but also other electric circuit elements (resistors, capacitors, inductors, diodes, other semiconductor elements, wiring, etc.).

[0062] The integrated circuit element of the fifth embodiment also forms a channel in the second diamond single crystal layer 4, which has an impurity concentration, surface roughness and thickness that make it difficult for gate leakage current to flow, thereby making it possible to suppress gate leakage current and drain leakage current, thereby obtaining good output characteristics and extending the life of the field effect transistor.

[0063] [Method for Manufacturing a Substrate for an Electronic Device of the Sixth Embodiment] The method for manufacturing a substrate for an electronic device of the sixth embodiment is a method for manufacturing the substrate for an electronic device of the first embodiment, and includes the steps shown in FIGS. 3 to 5.

[0064] [Step of forming second diamond single crystal layer 4] First, a first diamond single crystal layer 2 is prepared. The first diamond single crystal layer 2 may be a commercially available product, or may be fixed on a substrate of some kind. The first diamond single crystal layer 2 used in the fifth embodiment has a nitrogen concentration of 1.0 ppb or more, a boron concentration of 5.0 ppb or more, the plane orientation of the surface 2A has an absolute value of an inclination angle from the (001) plane orientation of 3.0° or less, and the surface roughness Ra of the surface 2A is 30 nm or less. For details and more preferred ranges of the first diamond single crystal layer 2, the explanation of the first embodiment is cited.

[0065] On the first diamond single crystal layer 2A, a CH ４While introducing a reactive gas containing a hydrocarbon gas such as HCl, hydrogen gas, and trace amounts of nitrogen gas and boron gas as dopants, the temperature of the first diamond single crystal layer 2 is set to 650°C or higher and 950°C or lower, the pressure of the reactive gas is set to 40 Torr or higher and 60 Torr or lower, and the ratio of the flow rates of the hydrocarbon gas and hydrogen gas (flow rate of the hydrocarbon gas / flow rate of the hydrogen gas) is set to 1:50 to 1:200, and a second diamond single crystal layer 4 is formed on the surface 2A. By not introducing nitrogen gas or boron gas into the reactive gas, the nitrogen concentration of the second diamond single crystal layer 4 is set to less than 0.1 ppb, and by adjusting the boron gas concentration in the reactive gas, the boron concentration of the second diamond single crystal layer 4 is set to less than 5.0 ppb.

[0066] The plane orientation of the surface 4A of the second diamond single crystal layer 4 is controlled to reflect the plane orientation of the first diamond single crystal layer 2, so that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less. The surface roughness Ra of the surface 4A of the second diamond single crystal layer 4 is controlled to reflect the surface roughness of the surface 2A of the first diamond single crystal layer 2, so that it is 30 nm or less. The thickness of the second diamond single crystal layer 4 is set to be 50 nm or more and 1600 nm or less by controlling the film formation time. The surface 4A of the second diamond single crystal layer 4 is exposed to hydrogen plasma, so that the carbon atoms on the outermost surface are hydrogen-terminated and p-type conductivity is imparted. For details of the second diamond single crystal layer 4, the explanation of the first embodiment is cited.

[0067] [1. NO ２ Doping step / FIG. 3(a)] The surface of the second diamond single crystal layer 4, which has been hydrogen-terminated as described above, is doped with NO. ２ As shown in FIG. 3( a ), NO diluted with nitrogen gas is applied to the hydrogen-terminated surface 4 A of the second diamond single crystal layer 4 . ２ The hydrogen-terminated surface is contacted with NO gas. ２ By adsorbing NO ２ The adsorption surface 6 is formed. ２ The gas used was diluted with nitrogen gas, and NO ２The gas concentration may be 5 ppm to 10% by volume fraction, and more preferably 1% to 10%. The gas used for dilution may be helium or argon in addition to nitrogen. The temperature of the second diamond single crystal layer 4 during the reaction is not limited, but may be 0 to 240°C, or 10 to 120°C.

[0068] [2. Au vapor deposition process / FIG. 3(b)] NO ２ An Au layer 20, which will serve as an electrode, is formed on the second diamond single crystal layer 4 on which the adsorption surface 6 is formed. The thickness of the Au layer 20 is adjusted to match the thickness of the source electrode 8 and drain electrode 10 to be finally formed. For details, the explanation of the third embodiment is cited. Various deposition devices, sputtering devices, etc. can be used to form the Au layer 20.

[0069] 3. Resist spin coating step / Fig. 3(c)] A resist layer 22 is formed using a spin coating device on the second diamond single crystal layer 4 on which the Au layer 20 has been formed. Any commonly used resist may be used for the resist layer 22, and the method of forming the resist layer 22 and the thickness thereof may be the same as in conventional semiconductor device manufacturing methods.

[0070] 3(d)] The resist layer 22 is exposed to light (from g-line to EUV) or electron beams using a photomask having an electrode pattern, and developed, and the solubilized resist-removed portions 24 of the resist layer 22 are etched to form an electrode pattern from the remaining resist layer 22. The methods and conditions for exposure, development, and resist removal may be the same as those used in conventional semiconductor device manufacturing methods.

[0071] 4(a) ] The Au layer 20 is dissolved at the locations corresponding to the resist-removed portions 24 that constitute the electrode pattern, and the Au in the Au-removed portions 26 is removed to form the portions that will become the source electrode 8 and the drain electrode 10. The method and conditions for dissolving the Au layer 20 may be the same as those used in conventional semiconductor device manufacturing methods.

[0072] 6. Resist Removal Step / FIG. 4(b) The resist remaining on the source electrode 8 and the drain electrode 10 is removed to expose the source electrode 8 and the drain electrode 10.

[0073] [7. Re-NO ２ Doping step (FIG. 4(c))] In the area other than the source electrode 8 and the drain electrode 10, NO is doped onto the second diamond single crystal layer 4. ２ The adsorption surface 6 is again filled with NO diluted with nitrogen gas. ２ The gas is brought into contact with the NO ２ NO on adsorption surface 6 ２ This step increases the concentration of the first NO ２ The NO content decreased due to the time allowed after the doping process. ２ This is done to compensate for the ２ The gas contact conditions are the same as those described above in "1. NO ２ The doping process may be the same as the above.

[0074] [8. Al ２ O ３ Layer Deposition Step (FIG. 4( d ))] In order to form an insulating layer 12 on the source electrode 8 , the drain electrode 10 , and the Au removed portion 26 , an Al ２ O ３ The layer is deposited to a constant thickness. ２ O ３ Alternatively, other insulating materials may be used instead of the above. Through this process, a passivation film 12A is formed on the source electrode 8, a passivation film 12C is formed on the drain electrode 10, and a gate insulating film 12B is formed in the Au-removed portion 26. The above description of the insulating layer 12 is applicable.

[0075] 9. Au Vapor Deposition Process (FIG. 5A) An Au layer 28 is formed on the insulating layer 12 to a certain thickness by vapor deposition, sputtering, or the like. The thickness of the Au layer 28 is set to the thickness required for the gate electrode 14. The above description of the gate electrode 14 is applicable.

[0076] 5B] A resist layer 30 is formed on the Au layer 28 using a spin coater or the like. A commonly used resist may be used for the resist layer 30, and the method for forming the resist layer 30 and the thickness thereof may be the same as those used in conventional semiconductor device manufacturing methods.

[0077] 5(c)] The resist layer 30 is exposed to light (g-ray to EUV) or electron beams using a photomask having an electrode pattern, and developed, and the solubilized resist-removed portions of the resist layer 30 are etched to form a pattern of the gate electrode 14 from the remaining resist layer 30. The methods and conditions for exposure, development, and resist removal may be the same as those used in conventional semiconductor device manufacturing methods.

[0078] 12. Au Etching Step (FIG. 5(d))] The Au layer 28 is dissolved at corresponding locations through the removed resist portions that form the pattern of the gate electrode 14, thereby forming portions that will become the gate electrode 14. The method and conditions for dissolving the Au layer 28 may be the same as those used in conventional semiconductor device manufacturing methods.

[0079] According to the manufacturing method of the fifth embodiment configured as described above, it is possible to efficiently manufacture a substrate for an electronic device and a field effect transistor having excellent characteristics as in the first embodiment.

[0080] [Manufacturing Method of Electronic Device Substrate of Seventh Embodiment] The manufacturing method of the seventh embodiment is a method for manufacturing the electronic device substrate of the second embodiment, and since the basic steps are the same as those of the manufacturing method of the sixth embodiment, the description will again refer to Figures 3 to 5. In this seventh embodiment, the parameters of each part are different from those of the sixth embodiment, so the description will focus on the different points, and the description of the sixth embodiment will be used for the other points.

[0081] The first diamond single crystal layer 2 used in the method for manufacturing an electronic device substrate according to the seventh embodiment has a nitrogen concentration of 0.1 ppb or more, a boron concentration of 1.0 ppb or more, a plane orientation of the surface 2A with an absolute value of the tilt angle from the (001) plane orientation of 3.0° or less, and a surface roughness Ra of the surface 2A of 30 nm or less. This is different from the sixth embodiment. For other manufacturing conditions, the explanation for the sixth embodiment is used. For preferred ranges, the explanation for the second embodiment is used.

[0082] According to the manufacturing method of the seventh embodiment, it is possible to efficiently manufacture a substrate for an electronic device and a field effect transistor having the above-mentioned excellent properties.

[0083] [Manufacturing Method of Electronic Device Substrate of Eighth Embodiment] The manufacturing method of the eighth embodiment is a method for manufacturing the electronic device substrate of the third embodiment, and since the basic steps are the same as those of the manufacturing methods of the sixth and seventh embodiments, the method will be described again with reference to Figures 3 to 5. In this eighth embodiment, the parameters of each part are different from those of the sixth and seventh embodiments, so the description will focus on the different points, and the descriptions of the sixth and seventh embodiments will be used for the other points.

[0084] The first diamond single crystal layer 2 used in the method for manufacturing an electronic device substrate according to the eighth embodiment has a nitrogen concentration of less than 20 ppb and a boron concentration of less than 0.01 ppb. This is different from the sixth and seventh embodiments. For other manufacturing conditions, the explanations for the sixth and seventh embodiments are to be cited. For preferred ranges, the explanation for the third embodiment is to be cited.

[0085] According to the manufacturing method of the eighth embodiment, it is possible to efficiently manufacture a substrate for an electronic device and a field effect transistor having the above-mentioned excellent properties.

[0086] Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and it is possible to mutually combine the configurations of the respective embodiments, add other configurations of well-known technologies, or omit some configurations of well-known technologies.

[0087] The present invention will now be described in more detail with reference to examples, but the present invention is not limited to these examples. For ease of understanding, reference will be made to the reference numerals in the drawings.

[0088] [Example 1] A diamond single crystal substrate 1 and field-effect transistor according to Example 1 were manufactured by the following method. An optical-grade first diamond single crystal layer 2 (commercially available) was prepared, having a thickness of 500 μm, a nitrogen concentration of 500 ppb, a boron concentration of 25 ppb, a surface 2A with a (001) plane orientation of ±1.0°, and a surface roughness Ra of 10 nm on the surface 2A. The first diamond single crystal layer 2 did not have a support substrate, and the size of the first diamond single crystal layer 2 was 4.5 mm × 4.5 mm × 0.5 mm thick.

[0089] The first diamond single crystal layer 2 was set in a microwave plasma CVD apparatus (manufactured by Cornes Technology, product name: SDS-5200), and the temperature of the first diamond single crystal layer 2 was set to 750°C, the pressure of the reaction gas was set to 50 Torr, and CH ４ The gas flow rate is 3 ccm (cm ３ / min), H ２ The gas flow rate was 300 ccm, and nitrogen gas and boron gas were intentionally not flowed. A second diamond single crystal layer 4 having a thickness of 100 nm and containing substantially no nitrogen was formed under the condition of a microwave output of 750 W.

[0090] The obtained second diamond single crystal layer 4 had a thickness (d) of 100 nm, a nitrogen concentration less than the detection limit of 1.0 ppb, a boron concentration less than 5.0 ppb, and the surface orientation confirmed by X-ray diffraction was (001) orientation with a slight tilt angle of ±1.0°. The surface roughness measured with an atomic force microscope was 1.0 nm. The surface 4A of the second diamond single crystal layer 4 was covered with hydrogen and had p-type conductivity due to hydrogen termination.

[0091] Next, as shown in FIG. 3(a), at 700° C., NO with a concentration of 2% ２ N ２ The reaction gas diluted with NO was supplied to the microwave plasma CVD apparatus at a pressure of 50 Torr for 2 minutes, and the hydrogen-terminated surface 4A of the second diamond single crystal layer 4 was coated with NO.２ Contact with NO ２ In this state, NO was adsorbed onto the hydrogen-terminated surface 4A. ２ It was thought that the molecules were adsorbed in the form of a monolayer.

[0092] Next, a 50 nm thick Au layer 20 was deposited by vacuum deposition as shown in FIG. 3( b), a resist layer 22 was formed as shown in FIG. 3( c), the resist layer 22 was masked and developed as shown in FIG. 3( d) to form an electrode pattern, the Au layer 20 was etched as shown in FIG. 4( a), and the resist layer 22 was removed as shown in FIG. 4( b), thereby forming the source electrode 8 and the drain electrode 10.

[0093] Next, as shown in FIG. ２ Doping is performed to remove NO from the area where the gate insulating film 12B is to be formed. ２ NO on adsorption surface 6 ２ The amount of adhesion was replenished. ２ The doping conditions are NO ２ Next, as shown in FIG. 4(d), an atomic layer deposition (ALD) apparatus was used to deposit Al ２ O ３ A 16-nm thick layer of Au was deposited on the gate insulating film 12 to form the insulating layer 12. The insulating layer 12 includes a passivation film 12A, a gate insulating film 12B, and a passivation film 12C. Next, using the same ALD apparatus, a 50-nm thick Au layer 28 was deposited as shown in FIG. 5( a), a resist layer 30 was formed as shown in FIG. 5( b), and the resist was masked and developed as shown in FIG. 5( c), forming the gate electrode 14 as shown in FIG. 5( d). This completed the field-effect transistor.

[0094] The field effect transistor of Example 1 was set in a characteristic tester and a performance test was carried out. The results are shown in the graphs of Figures 6 to 8. Figures 6 and 7 show the gate-source voltage (V ＧＳ ) is changed from -7V to 11V, the drain-source voltage (V ＤＳ ) and drain current (I Ｄ) relationship, and FIG. 6 shows the drain current in a linear representation, while FIG. 7 shows the drain current in a logarithmic representation.

[0095] As is clear from a comparison of FIG. 6 with FIG. 24 showing the characteristics of the prior art, in the field effect transistor of Example 1, when the drain-source voltage is near 0 V, a positive drain current (I Ｄ ) was not measured, and no gate leakage current was generated. Therefore, the risk of damage to the gate insulating film 12B was reduced. This indicated that no path for gate leakage current was generated inside the second diamond single crystal layer 4.

[0096] As is clear from a comparison of FIG. 7 with FIG. 25 showing the characteristics of the prior art, in the field effect transistor of Example 1, a negative drain current (I Ｄ ) flowed, and there was almost no drain leakage current. Therefore, it was found that it was possible to obtain the high ON / OFF current ratio required for power semiconductor applications. This indicated that no drain leakage current path was formed inside the second diamond single crystal layer 4.

[0097] FIG. 8 shows the drain current (I Ｄ : upper graph) and gate current (I Ｇ The graph shows the time characteristics of the battery (lower graph). It was operated for 1728 hours, but there was no deterioration (I Ｄ Decrease in I Ｇ The effect was remarkable when compared with Figure 26, which shows the lifespan of the prior art.

[0098] [Examples 2 to 5, Comparative Examples 1 to 4] Field-effect transistors were fabricated using the same structure as in Example 1, but with the film thickness d of the second diamond single crystal layer 4 changed to 0 nm (Fig. 9: Comparative Example 1), 25 nm (Fig. 10: Comparative Example 2), 50 nm (Fig. 11: Example 2), 100 nm (Fig. 12: Example 3), 200 nm (Fig. 13: Example 4), 400 nm (Fig. 14: Example 5), 800 nm (Fig. 15: Comparative Example 3), and 1600 nm (Fig. 16: Comparative Example 4) under the same other conditions, and the output characteristics were measured for each.

[0099] When the film thickness d of the second diamond single crystal layer 4 is increased, the drain current value (I Ｄ ) increases, and the on-resistance (R ＯＮ It was found that the resistance between the drain and source when the FET is ON) decreased. Ｄ is low 、 R ＯＮ Comparative Example 2 has a problem that I Ｄ is low 、 R ＯＮ Comparative Example 3 has a problem that V ＢＲ Comparative Example 4 has a problem that V ＢＲ This resulted in a problem of drain leakage current.

[0100] FIG. 17 shows the off-state breakdown voltage (V ＢＲ As the film thickness d of the second diamond single crystal layer 4 increases, the off-state breakdown voltage (V ＢＲ ) values ​​were found to increase.

[0101] 18 to 20 show the results of I for Examples 2 to 5 and Comparative Examples 1 to 4. Ｄ , R ＯＮ、 V ＢＲ The dependence of I on the thickness d is plotted. Ｄ The optimum thickness was d≧200 nm. ＯＮ The optimum thickness was d≧200 nm. ＢＲ The optimum thickness was d=200 nm.

[0102] [Example 6] An electronic device substrate 1 and a field-effect transistor of Example 6, which corresponds to the second embodiment, were manufactured by the following method. A first diamond single crystal layer 2 (commercially available) was prepared, which was 500 μm thick, had a nitrogen concentration of 0.5 ppb, a boron concentration of 2.5 ppb, a surface 2A with a (001) plane orientation of ±1.0°, and a surface roughness Ra of 5 nm on the surface 2A. The first diamond single crystal layer 2 did not have a support substrate, and the size of the first diamond single crystal layer 2 was 4.5 mm × 4.5 mm × 0.5 mm thick.

[0103] The first diamond single crystal layer 2 was set in a microwave plasma CVD apparatus (manufactured by Cornes Technology, product name: SDS5200S), and the temperature of the first diamond single crystal layer 2 was set to 750°C, the pressure of the reaction gas was set to 50 Torr, and CH ４ The gas flow rate is 3 ccm (cm ３ / min), H ２ The gas flow rate was 300 ccm, and nitrogen gas and boron gas were not flowed. A second diamond single crystal layer containing nitrogen was epitaxially grown to a thickness of 100 nm under the condition of a microwave output of 750 W.

[0104] The obtained second diamond single crystal layer had a thickness (d) of 100 nm, a nitrogen concentration of 0.08 ppb, a boron concentration of 0.5 ppb, a surface orientation of (001) plane orientation ±1.0° measured by electron backscatter diffraction pattern method (EBSP method) using a scanning electron microscope (SEM), and a surface roughness of 1 nm measured by white light interferometry. The surface 4A of the second diamond single crystal layer 4 was covered with hydrogen and had p-type conductivity due to hydrogen termination.

[0105] Next, as shown in FIG. 3(a), at 120° C., NO with a concentration of 2% ２ N ２ The reaction gas diluted to 2% with NO gas was supplied to the microwave plasma CVD apparatus at a pressure of 760 Torr for 2 minutes, and the hydrogen-terminated surface 4A of the second diamond single crystal layer 4 was coated with NO. ２ Contact with NO ２ In this state, NO was adsorbed onto the hydrogen-terminated surface 4A. ２ It was thought that the molecules were adsorbed in the form of a monolayer.

[0106] Next, a 50 nm thick Au layer 20 was deposited by vacuum deposition as shown in FIG. 3( b), a resist layer 22 was formed as shown in FIG. 3( c), the resist layer 22 was masked and developed as shown in FIG. 3( d) to form an electrode pattern, the Au layer 20 was etched as shown in FIG. 4( a), and the resist layer 22 was removed as shown in FIG. 4( b), thereby forming the source electrode 8 and the drain electrode 10.

[0107] Next, as shown in FIG. ２Doping is performed to remove NO from the area where the gate insulating film 12B is to be formed. ２ NO on adsorption surface 6 ２ The amount of adhesion was replenished. ２ The doping conditions are NO ２ Next, as shown in FIG. 4(d), an atomic layer deposition (ALD) apparatus was used to deposit Al ２ O ３ A 16-nm thick layer of Au was deposited on the gate insulating film 12 to form the insulating layer 12. The insulating layer 12 includes a passivation film 12A, a gate insulating film 12B, and a passivation film 12C. Next, using the same ALD apparatus, a 50-nm thick Au layer 28 was deposited as shown in FIG. 5( a), a resist layer 30 was formed as shown in FIG. 5( b), and the resist was masked and developed as shown in FIG. 5( c), forming the gate electrode 14 as shown in FIG. 5( d). This completed the field-effect transistor.

[0108] The field effect transistor of Example 6 was set in a characteristic tester and a performance test was carried out. The results are shown in the graphs of Figures 21 and 22. Figures 21 and 22 show the gate-source voltage (V ＧＳ ) is changed from -7V to 41V, the drain-source voltage (V ＤＳ ) and drain current (I Ｄ 21 shows the drain current in a linear representation, and FIG. 22 shows the drain current in a logarithmic representation.

[0109] As is clear from a comparison of FIG. 21 with FIG. 24 showing the characteristics of the prior art, in the field effect transistor of Example 6, when the drain-source voltage is near 0 V, a negative drain current (I Ｄ ) was not measured, and no gate leakage current was generated. Therefore, the risk of damage to the gate insulating film 12B was reduced. This indicated that no path for gate leakage current was generated inside the second diamond single crystal layer 4.

[0110] As is clear from a comparison of FIG. 22 with FIG. 25 showing the characteristics of the prior art, in the field effect transistor of Example 6, a positive drain current (IＤ ) flowed, and there was almost no drain leakage current. This indicated that it was possible to obtain the high ON / OFF current ratio required for power semiconductor applications. Although a channel was formed inside the second diamond single crystal layer 4, no path for drain leakage current was formed.

[0111] [Example 7] An electronic device substrate 1 and a field-effect transistor of Example 7, which corresponds to the third embodiment, were manufactured by the following method. A first diamond single crystal layer 2 (commercially available) was prepared, which was 500 μm thick, had a nitrogen concentration of 10 ppb, a boron concentration of 0.05 ppb, a surface 2A with a (001) plane orientation of ±1.0°, and a surface roughness Ra of 5 nm on the surface 2A. The first diamond single crystal layer 2 did not have a support substrate, and the size of the first diamond single crystal layer 2 was 4.5 mm × 4.5 mm × 0.5 mm thick.

[0112] The first diamond single crystal layer 2 was set in a microwave plasma CVD apparatus (manufactured by Cornes Technology, product name: SDS5200S), and the temperature of the first diamond single crystal layer 2 was set to 650°C, the pressure of the reaction gas was set to 50 Torr, and CH ４ The gas flow rate is 3 ccm (cm ３ / min), H ２ The gas flow rate was 300 ccm, and nitrogen gas and boron gas were not flowed. A second diamond single crystal layer having a thickness of 500 nm was epitaxially grown under the condition of a microwave output of 750 W.

[0113] The obtained second diamond single crystal layer had a thickness (d) of 500 nm, a nitrogen concentration of 20 ppb, and a boron concentration of 10 ppb.The surface orientation measured by electron backscatter diffraction pattern method (EBSP method) using a scanning electron microscope (SEM) was (001) plane orientation ±1.0°, and the surface roughness measured by white light interferometry was 1 nm.The surface 4A of the second diamond single crystal layer 4 was covered with hydrogen and had p-type conductivity due to hydrogen termination.

[0114] 27 shows the depth distribution of nitrogen and boron concentrations in the electronic device substrate 1 of Example 7, measured by secondary ion mass spectrometry. The surface position of the second diamond single crystal layer 4 is set to 0 nm in the depth direction.

[0115] In the first diamond single crystal layer 2 of Example 7, the nitrogen concentration was below the detection limit (20 ppb) by electron spin resonance (ESR) and the boron concentration was below the detection limit (0.01 ppb). In the second diamond single crystal layer 4, the nitrogen concentration was below the detection limit (20 ppb) by EPR and the boron concentration gradually increased from 2.0 ppb to 20 ppb towards the surface.

[0116] Next, the substrate 1 for an electronic device of Example 7 was used under the same conditions as in Example 6. ２ After forming the adsorption surface, an Au layer 20 was deposited to a thickness of 50 nm by vacuum deposition as shown in FIG. 3( b), a resist layer 22 was formed as shown in FIG. 3( c), the resist layer 22 was masked and developed as shown in FIG. 3( d) to form an electrode pattern, the Au layer 20 was etched as shown in FIG. 4( a), and the resist layer 22 was removed as shown in FIG. 4( b), thereby forming the source electrode 8 and the drain electrode 10.

[0117] Furthermore, as shown in FIG. ２ Doping is performed to remove NO from the area where the gate insulating film 12B is to be formed. ２ NO on adsorption surface 6 ２ The amount of adhesion was replenished. ２ The doping conditions are NO ２ Next, as shown in FIG. 4(d), an atomic layer deposition (ALD) apparatus was used to deposit Al ２ O ３ was deposited to a thickness of 16 nm to form an insulating layer 12. The insulating layer 12 includes a passivation film 12A, a gate insulating film 12B, and a passivation film 12C.

[0118] Next, using the same ALD apparatus, a 50 nm thick Au layer 28 was deposited as shown in Fig. 5(a), a resist layer 30 was formed as shown in Fig. 5(b), and the resist was masked and developed as shown in Fig. 5(c), thereby forming a gate electrode 14 as shown in Fig. 5(d). This completed the field-effect transistor of Example 7.

[0119] The field effect transistor of Example 7 was set in the same characteristic tester as that used in Example 5, and a performance test was carried out. The results are shown in the graphs of Figures 28 and 29. Figure 28 shows the gate-source voltage (V ＧＳ ) is changed from -7V to 15V, the output voltage between the drain and source (V ＤＳ ) and the output current, the drain current (I Ｄ 29 is a graph showing the relationship between the operating frequency (GHz) and the current gain (dB) and the power gain (dB) in the field effect transistor of Example 7, which was tested under the conditions of VGS=5.5 V and VDS=−40 V.

[0120] As shown in FIG. 28, the field effect transistor of Example 7 exhibited excellent characteristics, such as a specific on-resistance (Ron) of 26.73 Ωmm and a maximum drain current (IDMX) of 553 mA / mm.

[0121] 29, the cutoff frequency (fT) of the current gain was 15 GHz, and the cutoff frequency (fMAX) of the power gain was 120 GHz. These performance values ​​were considered to be the world's highest level at the time of measurement.

[0122] According to the present invention, a channel can be formed in the second diamond single crystal layer that has the impurity concentration, surface roughness and thickness that make it difficult for leakage current to flow, so that the gate leakage current can be suppressed and the drain leakage current can be suppressed, improving output characteristics and extending the life of the field effect transistor.In addition, by defining the impurity concentration, plane orientation and surface roughness Ra of the first diamond single crystal layer as above, it is easy to form the second diamond single crystal layer with high purity and high precision as above.

[0123] REFERENCE SIGNS LIST 1 Substrate for electronic device 2 First diamond single crystal layer 2A Surface of first diamond single crystal layer 4 Second diamond single crystal layer 4A Surface of second diamond single crystal layer 6 NO ２ Adsorption surface d Thickness of second diamond single crystal layer 8 Source electrode 10 Drain electrode 12 Insulating layer 12A Passivation film 12B Gate insulating film 12C Passivation film 14 Gate electrode 20 Au layer 22 Resist layer 24 Resist-removed portion 26 Au-removed portion 28 Au layer 30 Resist layer

Claims

1. A diamond single crystal layer comprising: a first diamond single crystal layer; and a second diamond single crystal layer formed on the surface of the first diamond single crystal layer; wherein the first diamond single crystal layer has a nitrogen concentration of 1.0 ppb or more and a boron concentration of 5.0 ppb or more, the surface of the first diamond single crystal layer has a plane orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, and the surface roughness Ra of the surface of the first diamond single crystal layer is 30 nm or less; the second diamond single crystal layer has a nitrogen concentration of less than 0.1 ppb and a boron concentration of less than 5.0 ppb, the surface of the second diamond single crystal has a plane orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, and the surface roughness Ra of the surface of the second diamond single crystal is 30 nm or less, and the thickness of the second diamond single crystal layer is 50 nm or more and 1600 nm or less; The surface of the second diamond single crystal layer is hydrogen-terminated by being covered with hydrogen and has p-type conductivity, and the hydrogen-terminated surface of the second diamond single crystal layer is provided with NO ２ is adsorbed, and NO ２ A substrate for an electronic device, characterized in that an adsorption surface is formed.

2. A diamond single crystal layer comprising: a first diamond single crystal layer; and a second diamond single crystal layer formed on the surface of the first diamond single crystal layer, wherein the first diamond single crystal layer has a nitrogen concentration of 0.1 ppb or more and a boron concentration of 1.0 ppb or more, the surface of the first diamond single crystal layer has a plane orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, and the surface roughness Ra of the surface of the first diamond single crystal layer is 30 nm or less, the second diamond single crystal layer has a nitrogen concentration of less than 0.1 ppb and a boron concentration of less than 1.0 ppb, the surface of the second diamond single crystal has a plane orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, the surface roughness Ra of the surface of the second diamond single crystal is 30 nm or less, and the thickness of the second diamond single crystal layer is 50 nm or more and 400 nm or less, The surface of the second diamond single crystal layer is hydrogen-terminated by being covered with hydrogen, and has p-type conductivity. Furthermore, the hydrogen-terminated surface of the second diamond single crystal layer is provided with NO ２ is adsorbed, and NO ２ A substrate for an electronic device, characterized in that an adsorption surface is formed.

3. A diamond single crystal layer comprising: a first diamond single crystal layer; and a second diamond single crystal layer formed on the surface of the first diamond single crystal layer, wherein the first diamond single crystal layer has a nitrogen concentration of less than 20 ppb and a boron concentration of less than 0.01 ppb, the surface of the first diamond single crystal layer has a plane orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, and the surface roughness Ra of the surface of the first diamond single crystal layer is 30 nm or less, and the second diamond single crystal layer has a nitrogen concentration of less than 20 ppb and a boron concentration of 2.0 ppb or more but less than 20 ppb, the surface of the second diamond single crystal has a plane orientation such that the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, the surface roughness Ra of the surface of the second diamond single crystal is 30 nm or less, and the thickness of the second diamond single crystal layer is 50 nm or more but 400 nm or less, The surface of the second diamond single crystal layer is hydrogen-terminated by being covered with hydrogen, and has p-type conductivity. Furthermore, the hydrogen-terminated surface of the second diamond single crystal layer is provided with NO ２ is adsorbed, and NO ２ A substrate for an electronic device, characterized in that an adsorption surface is formed.

4. A substrate for electronic devices according to any one of claims 1 to 3, and the NO of the second diamond single crystal layer. ２ a source electrode formed on the first region of the adsorption surface; and ２ a gate insulating film formed on the second region of the adsorption surface; a gate electrode formed on the gate insulating film; and a NOx of the second single crystal diamond layer. ２ and a drain electrode formed on the third region of the adsorption surface.

5. An integrated circuit element comprising a substrate for an electronic device according to any one of claims 1 to 3 and a plurality of field effect transistors formed on said substrate for an electronic device, wherein said field effect transistors are ２ a source electrode formed on the first region of the adsorption surface; and ２ a gate insulating film formed on the second region of the adsorption surface; a gate electrode formed on the gate insulating film; and a NOx of the second single crystal diamond layer. ２ a drain electrode formed on the third region of the attraction surface.

6. Preparing a first diamond single crystal layer having a nitrogen concentration of 1.0 ppb or more, a boron concentration of 5.0 ppb or more, a surface orientation with an absolute value of an inclination angle from the (001) surface orientation of 3.0° or less, and a surface roughness Ra of 30 nm or less; a second diamond single crystal layer having a nitrogen concentration of less than 0.1 ppb, a boron concentration of less than 5.0 ppb, a surface orientation of which the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, a surface roughness Ra of 30 nm or less, and a thickness of 50 nm or more and 1600 nm or less, is formed on the first diamond single crystal layer by plasma CVD, while introducing a reactive gas containing hydrocarbon gas, hydrogen gas, and nitrogen gas and boron gas as dopants into the first diamond single crystal layer at a temperature of 650°C or more and 950°C or less, a pressure of the reactive gas of 40 Torr or more and 60 Torr or less, and a ratio of the flow rates of the hydrocarbon gas and the hydrogen gas (flow rate of the hydrocarbon gas / flow rate of the hydrogen gas) of 1:200 to 1:50; and hydrogen-terminating the surface of the second diamond single crystal layer to impart p-type conductivity to the surface of the second diamond single crystal layer. ２ The hydrogen-terminated surface is exposed to NO gas. ２ By adsorbing NO ２ A method for manufacturing a substrate for an electronic device, comprising forming an adsorption surface.

7. Preparing a first diamond single crystal layer having a nitrogen concentration of 0.1 ppb or more, a boron concentration of 1.0 ppb or more, a surface orientation having an inclination angle from the (001) plane orientation of 3.0° or less in absolute value, and a surface roughness Ra of 30 nm or less; a second diamond single crystal layer having a nitrogen concentration of less than 0.1 ppb, a boron concentration of less than 1.0 ppb, a surface orientation of which the absolute value of the tilt angle from the (001) plane orientation is 3.0° or less, a surface roughness Ra of 30 nm or less, and a thickness of 50 nm or more and 400 nm or less, is formed on the first diamond single crystal layer by plasma CVD, while introducing a reactive gas containing hydrocarbon gas and hydrogen gas, and nitrogen gas and boron gas as dopants, at a temperature of 650°C or more and 950°C or less, a pressure of the reactive gas of 40 Torr or more and 60 Torr or less, and a ratio of the flow rates of the hydrocarbon gas and the hydrogen gas (flow rate of the hydrocarbon gas / flow rate of the hydrogen gas) of 1:200 to 1:50; and hydrogen-terminating the surface of the second diamond single crystal layer to impart p-type conductivity to the surface of the second diamond single crystal layer. ２ The hydrogen-terminated surface is exposed to NO gas. ２ By adsorbing NO ２ A method for manufacturing a substrate for an electronic device, comprising forming an adsorption surface.

8. Preparing a first diamond single crystal layer having a nitrogen concentration of less than 20 ppb, a boron concentration of less than 0.01 ppb, a surface orientation with an absolute value of an inclination angle from the (001) surface orientation of 3.0° or less, and a surface roughness Ra of 30 nm or less; a second diamond single crystal layer having a nitrogen concentration of less than 20 ppb, a boron concentration of 2.0 ppb or more and less than 20 ppb, a surface orientation of which the absolute value of the tilt angle from the (001) orientation is 3.0° or less, a surface roughness Ra of 30 nm or less, and a thickness of 50 nm or more and 400 nm or less, is formed on the first diamond single crystal layer by plasma CVD, while introducing a reactive gas containing hydrocarbon gas and hydrogen gas, and nitrogen gas and boron gas as dopants, at a temperature of 650°C or more and 950°C or less, a pressure of the reactive gas of 40 Torr or more and 60 Torr or less, and a ratio of the flow rate of the hydrocarbon gas to the flow rate of the hydrogen gas (flow rate of the hydrocarbon gas / flow rate of the hydrogen gas) of 1:200 to 1:50; and hydrogen-terminating the surface of the second diamond single crystal layer to impart p-type conductivity to the surface of the second diamond single crystal layer. ２ The hydrogen-terminated surface is exposed to NO gas. ２ By adsorbing NO ２ A method for manufacturing a substrate for an electronic device, comprising forming an adsorption surface.

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