Reducing supply voltage range in a power management circuit

Abstract

Reducing a supply voltage range in a power management circuit is provided. The power management circuit includes a transceiver circuit, a power management integrated circuit (PMIC), and a power amplifier circuit that are configured to amplify a radio frequency (RF) signal for transmission in a wireless device. Specifically, the transceiver circuit generates a target voltage, the PMIC generates a supply voltage based on the target voltage, and the power amplifier circuit amplifies the RF signal based on the supply voltage. Herein, the power amplifier circuit can be configured to perform supply modulation and / or load modulation in accordance with an instantaneous power level of the RF signal to raise a minimum level of the supply voltage and thereby reduce a peak-to-peak (a.k.a. maximum-to-minimum) range of the supply voltage. As a result, the power management circuit can operate with improved efficiency and linearity to thereby improve an overall user experience.

Description

REDUCING SUPPL Y VOLTAGE RANGE IN A POWER MANAGEMENT CIRCUITRelated Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63 / 690,934, filed on September 5, 2024, and U.S. provisional patent application serial number 63 / 720,838, filed on November 15, 2024, the disclosures of which are hereby incorporated herein by reference in their entireties.Field of the Disclosure

[0002] The present disclosure is related to operating a power management circuit in a wireless device based on a reduced supply voltage range.

[0003] Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] The redefined user experience requires higher data rates offered by advanced wireless communication technologies such as fifth-generation new- radio (5G-NR). To achieve higher data rates, a mobile communication device is required to amplify a transmission signal to a desired power level to help overcome potential propagation losses and / or interferences. As such, the mobile communication device typically includes a transceiver circuit, a power amplifier circuit, and a power management circuit. Specifically, the transceiver circuit modulates the transmission signal to an intended transmission frequency, the power amplifier circuit amplifies the transmission signal to the desired power level, and the power management circuit supplies an envelope tracking (ET) tothe power amplifier circuit. Understandably, to achieve the best-possible efficiency and performance, the power management circuit must adapt the ET voltage in accordance with a modulation bandwidth of the transmission signal.

[0005] Embodiments of the disclosure relate to reducing a supply voltage range in a power management circuit. The power management circuit includes a transceiver circuit, a power management integrated circuit (PMIC), and a power amplifier circuit that are configured to amplify a radio frequency (RF) signal for transmission in a wireless device. Specifically, the transceiver circuit generates a target voltage, the PMIC generates a supply voltage based on the target voltage, and the power amplifier circuit amplifies the RF signal based on the supply voltage. Herein, the power amplifier circuit can be configured to perform supply modulation and / or load modulation in accordance with an instantaneous power level of the RF signal to raise a minimum level of the supply voltage and thereby reduce a peak-to-peak (a.k.a. maximum-to-minimum) range of the supply voltage. As a result, the power management circuit can operate with improved efficiency and linearity to thereby improve an overall user experience.

[0006] In one aspect, a power management circuit is provided. The power management circuit includes a power amplifier circuit. The power amplifier circuit is configured to amplify an RF signal based on a supply voltage. The power management circuit also includes a PMIC. The PMIC is configured to generate the supply voltage based on a target voltage. The PMIC is also configured to maintain the supply voltage at a minimum voltage level when an instantaneous power level of the RF signal is lower than or equal to a selected power threshold among a first power threshold and a second power threshold higher than the first power threshold. The PMIC is also configured to increase the supply voltage toward a maximum voltage level when the instantaneous power level of the RF signal is higher than the selected power threshold. The power management circuit also includes a transceiver circuit. The transceiver circuit is configured to generate the target voltage with a correction term to thereby offset a ripple in thesupply voltage when the instantaneous power level of the RF signal is lower than or equal to the selected power threshold and the supply voltage is maintained at the minimum voltage level.

[0007] In another aspect, a wireless device is provided. The wireless device includes a power management circuit. The power management circuit includes a power amplifier circuit. The power amplifier circuit is configured to amplify an RF signal based on a supply voltage. The power management circuit also includes a PMIC. The PMIC is configured to generate the supply voltage based on a target voltage. The PMIC is also configured to maintain the supply voltage at a minimum voltage level when an instantaneous power level of the RF signal is lower than or equal to a selected power threshold among a first power threshold and a second power threshold higher than the first power threshold. The PMIC is also configured to increase the supply voltage toward a maximum voltage level when the instantaneous power level of the RF signal is higher than the selected power threshold. The power management circuit also includes a transceiver circuit. The transceiver circuit is configured to generate the target voltage with a correction term to thereby offset a ripple in the supply voltage when the instantaneous power level of the RF signal is lower than or equal to the selected power threshold and the supply voltage is maintained at the minimum voltage level.

[0008] In another aspect, a method for reducing a supply voltage range in a power management circuit is provided. The method includes amplifying an RF signal based on a supply voltage. The method also includes generating the supply voltage based on a target voltage. The method also includes maintaining the supply voltage at a minimum voltage level when an instantaneous power level of the RF signal is lower than or equal to a selected power threshold among a first power threshold and a second power threshold higher than the first power threshold. The method also includes increasing the supply voltage toward a maximum voltage level when the instantaneous power level of the RF signal is higher than the selected power threshold. The method also includes generating the target voltage with a correction term to thereby offset a ripple in the supplyvoltage when the instantaneous power level of the RF signal is lower than or equal to the selected power threshold and the supply voltage is maintained at the minimum voltage level.

[0009] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.Brief Description of the Drawing Figures

[0010] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0011] Figure 1 is a schematic diagram of an exemplary power management circuit configured according to embodiments of the present disclosure to reduce a supply voltage range of a supply voltage;

[0012] Figure 2 is a schematic diagram of an equivalent electrical model of a power amplifier circuit in the power management circuit of Figure 1 that can be configured to operate based on supply modulation and / or load modulation to help reduce the supply voltage range of the supply voltage;

[0013] Figure 3 is a graphic diagram providing an exemplary illustration as to how the power management circuit of Figure 1 can reduce the supply voltage range based on a first embodiment of the present disclosure;

[0014] Figure 4 is a graphic diagram providing an exemplary illustration as to how the power management circuit of Figure 1 can reduce the supply voltage range based on a second embodiment of the present disclosure;

[0015] Figure 5 is a schematic diagram of an exemplary target voltage circuit that can be provided in a transceiver circuit of the power management circuit of Figure 1 to offset a ripple in the supply voltage;

[0016] Figure 6 is a schematic diagram of an exemplary communication device wherein the power management circuit of Figure 1 can be provided; and

[0017] Figure 7 is a flowchart of an exemplary process for reducing the supply voltage range in the power management circuit of Figure 1 .Detailed Description

[0018] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0019] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0020] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or"coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0021] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0024] Embodiments are described herein with reference to reducing a supply voltage range in a power management circuit. The power management circuit includes a transceiver circuit, a power management integrated circuit (PMIC), and a power amplifier circuit that are configured to amplify a radio frequency (RF) signal for transmission in a wireless device. Specifically, the transceiver circuitgenerates a target voltage, the PMIC generates a supply voltage based on the target voltage, and the power amplifier circuit amplifies the RF signal based on the supply voltage. Herein, the power amplifier circuit can be configured to perform supply modulation and / or load modulation in accordance with an instantaneous power level of the RF signal to raise a minimum level of the supply voltage and thereby reduce a peak-to-peak (a.k.a. maximum-to-minimum) range of the supply voltage. As a result, the power management circuit can operate with improved efficiency and linearity to thereby improve an overall user experience.

[0025] Figure 1 is a schematic diagram of an exemplary power management circuit 10 configured according to embodiments of the present disclosure to reduce a supply voltage range VCC-RANGE of a supply voltage Vcc. Herein, the supply voltage range VCC-RANGE is defined by a maximum level VCC-MAX and a minimum level VCC-MIN (VCC-RANGE = VCC-MAX - VCC-MIN) of the supply voltage Vcc. In various embodiments described herein, the power management circuit 10 can be configured to raise the minimum level VCC-MIN of the supply voltage Vcc, while maintaining the maximum level VCC-MAX of the supply voltage Vcc, to thereby reduce the supply voltage range VCC-RANGE. More specifically, the power management circuit 10 can raise the minimum level VCC- IN of the supply voltage Vcc by performing supply modulation and / or load modulation.

[0026] The power management circuit 10 includes a transceiver circuit 12, a PMIC 14, and a power amplifier circuit 16. The transceiver circuit 12 is configured to generate an RF signal 18 having a time-variant input power PIN and a target voltage VTGT that tracks the time-variant input power PIN of the RF signal 18.

[0027] The PMIC 14 is configured to generate the supply voltage Vcc based on the target voltage VTGT. In one embodiment, the PMIC 14 can generate the supply voltage Vcc as an envelope tracking (ET) voltage to track the time-variant input power PIN of the RF signal 18. In another embodiment, the PMIC 14 can generate the supply voltage Vcc as an average power tracking (APT) voltage inaccordance with an average of the time-variant input power PIN of the RF signal 18.

[0028] The power amplifier circuit 16 is configured to amplify the RF signal 18 from the time-variant input power PIN to a time-variant output power POUT based on the supply voltage Vcc. Specifically, the power amplifier circuit 16 includes a first power amplifier 20 and a second power amplifier 22. The first power amplifier 20 is activated all the time to amplify the RF signal 18 based on the supply voltage Vcc, whereas the second power amplifier 22 is activated as needed to further amplify the RF signal 18.

[0029] The power amplifier circuit 16 further includes an impedance modulation circuit 24, which is coupled between a respective output 26 of the first power amplifier 20 and a respective output 28 of the second power amplifier 22. When the second power amplifier 22 is activated, the impedance modulation circuit 24 is configured to modulate a load impedance ZIN at the respective output 26 of the first power amplifier 20.

[0030] In an embodiment, the impedance modulation circuit 24 can be configured to modulate the load impedance ZIN as a function of a load impedance ZL presented by a load circuit 30 (e.g., an RF frontend circuit). Specifically, the load impedance ZIN can be expressed in equation (Eq. 1 ) below.ZIN = K2 / ZL (Eq. 1 )

[0031] In the equation (Eq. 1 ), K represents a configurable modulation term of the impedance modulation circuit 24. For an in-depth description as to how the PMIC 14 can generate the load modulation signal 32 and how the impedance modulation circuit 24 can modulate the load impedance ZIN, please refer to U.S. Patent Application Number 19 / 274,857, filed on July 21 , 2025, and entitled “DYNAMIC IMPEDANCE MODULATION IN A POWER MANAGEMENT CIRCUIT.”

[0032] In an embodiment, the impedance modulation circuit 24 can be configured to receive a load modulation signal 32 from the PMIC 14 and set theconfigurable modulation term K accordingly to thereby modulate the load impedance ZIN to a specific value. When the second power amplifier 22 is deactivated, the impedance modulation circuit 24 will stop modulating the load impedance ZI . Instead, the impedance modulation circuit 24 will present the load impedance ZIN at the respective output 26 with a fixed value (e.g., 4-times the load impedance ZL).

[0033] The operating principles of the power amplifier circuit 16 can be further explained based on an equivalent electrical model of the power amplifier circuit 16. In this regard, Figure 2 is a schematic diagram of an equivalent electrical model 33 of the power amplifier circuit 16 in the power management circuit 10 of Figure 1 that can be configured to operate based on supply modulation and / or load modulation to help reduce the supply voltage range VCC-RANGE of the supply voltage Vcc. Common elements between Figures 1 and 2 are shown therein with common element numbers and will not be re-described herein.

[0034] In the equivalent electrical model 33, each of the first power amplifier 20 and the second power amplifier 22 is modeled as a current source. The first power amplifier 20 is coupled to a first load-line transfer function 34 and the second power amplifier 22 is coupled to a second load-line transfer function 36. In a non-limiting example, each of the first load-line transfer function 34 and the second load-line transfer function 36 can be a transformer. For the sake of simplicity, each of the first load-line transfer function 34 and the second load-line transfer function 36 is assumed to be equal to one (1 ).

[0035] Before the second power amplifier 22 is activated, the first power amplifier 20 will generate a first current IM to thereby amplify the RF signal 18 from the time-variant input power PIN to the time-variant output power POUT. The load circuit 30, which has the load impedance ZL, produces a load current ILOAD based on the supply voltage Vcc. Since the second power amplifier 22 is inactive, the load current ILOAD is thus identical to another load current I’LOAD that flows into the impedance modulation circuit 24. As such, the first power amplifier 20 sees a first voltage VM (VM = K*I’LOAD).

[0036] When the second power amplifier 22 is activated, the second power amplifier 22 will generate a second current j*lp to thereby further amplify the RF signal 18 from the time-variant input power PIN to the time-variant output power POUT. AS such, the load current ILOAD will now equal a sum of the load current I’LOAD and the second current Ip (ILOAD = I’LOAD + j*lp). As such, the second power amplifier 22 sees a second voltage Vp (Vp = -J*K*IM).

[0037] With reference back to Figure 1 , the power amplifier circuit 16 can include a control circuit 38, a peak detector 40, and a phase shifter 42. The peak detector 40 and the phase shifter 42 each receives the RF signal 18 from the transceiver circuit 12. The phase shifter 42 is configured to provide a negative ninety-degree (-90°) phase shift of the RF signal 18 for the second power amplifier 22. For distinction, the RF signal 18 as received from the transceiver circuit 12 can be referred to as an “in-phase input” of the RF signal 18, whereas the phase-shifted RF signal 18 as provided to the second power amplifier 22 can be referred to as a “quadrature input” of the RF signal 18.

[0038] Herein, the peak detector 40 is configured to detect the instantaneous power level of the RF signal 18 based on both the in-phase input and the quadrature input of the RF signal 18. By detecting the instantaneous power level of the RF signal 18 based on both the in-phase input and the quadrature input of the RF signal 18, the peak detector 40 can operate with improved RF filtering and over a wider bandwidth with less group delay. In an embodiment, the peak detector 40 can be an automatic gain control (AGC) configured to operate based on an expected average input power level for different power backoffs.

[0039] The control circuit 38 receives the load modulation signal 32 from the PMIC 14 and the detected instantaneous power level of the RF signal 18. Accordingly, the control circuit 38 can bias the first power amplifier 20 and / or the second power amplifier 22 via a bias signal 44. In an embodiment, the bias signal 44 can be a voltage signal that includes a first bias voltage Vbias -ampi and a second bias voltage Vbias-amP2. The first bias voltage Vbias-ampi is applied to the first power amplifier 20 and the second bias voltage Vbias-amP2 is applied to thesecond power amplifier 22. As an example, the control circuit 38 can use the bias signal 44 to activate or deactivate the second power amplifier 22 as needed.

[0040] In an embodiment, the PMIC 14 includes a current generation circuit 46, a voltage amplifier 48, and an offset capacitor COFF. The current generation circuit 46, which includes a multi-level voltage converter (MCP) 50 coupled in series to a power inductor 52, is configured to generate a low-frequency current IDC as a function of a battery voltage VBAT. The voltage amplifier 48 is biased by a bias voltage VSUP to generate an initial supply voltage VAMP that tracks (increases and decreases) the target voltage VTGT. The offset capacitor COFF is configured to raise the initial supply voltage VA P by an offset voltage VOFF to thereby generate the supply voltage Vcc (Vcc = VAMP + VOFF). Understandably, the PMIC 14 can include additional circuits, such as a feedback loop and a local controller, which are omitted herein for the sake of simplicity.

[0041] The transceiver circuit 12 can include a digital baseband circuit 54, a signal processing circuit 56, a digital amplitude detector 58, and a target voltage circuit 60. The digital baseband circuit 54 is configured to generate a digital signal 62 and the signal processing circuit 56 is configured to modulate the digital signal 62 onto the RF signal 18. Understandably, the signal processing circuit 56 can generate the RF signal 18 from the digital signal 62 by means of many internal circuitries, including but not limited to a data buffer, a delay circuit, a digital predistortion (DPD) circuit, and an RF modulator. These internal circuitries are omitted herein for the sake of simplicity.

[0042] In an embodiment, the digital baseband circuit 54 can generate the digital signal 62 with an in-phase (I) component and a quadrature (Q) component. In this regard, the digital amplitude detector 58 is configured to detect a time-variant digital amplitude l2+Q2of the digital signal 62. The target voltage circuit 60, which will be further discussed in Figure 5, is configured to generate the target voltage VTGT based on the detected time-variant digital amplitude l2+Q2of the digital signal 62 and perform a necessary digital equalization to help suppress unwanted distortion in the supply voltage Vcc.

[0043] Figure 3 is a graphic diagram providing an exemplary illustration as to how the power management circuit 10 of Figure 1 can reduce the supply voltage range VCC-RANGE based on a first embodiment of the present disclosure.Common elements between Figures 1 and 3 are shown therein with common element numbers and will not be re-described herein.

[0044] Herein, the power amplifier circuit 16 is configured to operate based on a first power threshold Po and a second power threshold Pi. Each of the first power threshold Po and the second power threshold Pi is lower than one-half (1 / z) of a peak power level PMAX of the RF signal 18. In an embodiment, the first power threshold Po can be 10 to 16 dB below the peak power level PMAX and the second power threshold Pi is equal to two times the first power threshold Po (Po = 2P1 or Pi = 2xPo).

[0045] When the instantaneous power level of the RF signal 18 is lower than the first power threshold Po, the PMIC 14 maintains the supply voltage Vcc constantly at the minimum voltage level VCC-MIN independent of how the instantaneous power level of the RF signal 18 varies. Herein, the second power amplifier 22 is deactivated, whereas the first power amplifier 20 is activated to amplify the RF signal 18 based on the supply voltage Vcc. As such, the power amplifier circuit 16 is said to operate without modulation.

[0046] When the instantaneous power level of the RF signal 18 is higher than or equal to the first power threshold Po but lower than or equal to the second power threshold Pi, the first power amplifier 20 will operate under full compression, the second power amplifier 22 will be activated, and the impedance modulation circuit 24 will modulate the load impedance ZIN based on equation (Eq. 1 ). As such, the power amplifier circuit 16 is said to operate based on load modulation. The PMIC 14, in the meantime, maintains the supply voltage Vcc at the minimum voltage level VCC-MIN. By clipping the supply voltage Vcc at the second power threshold Pi, it is possible to establish the minimum voltage level VCC-MI above a voltage floor VCC-FLOOR, thus helping to reduce the supply voltage range VCC-RANGE.

[0047] When the instantaneous power level of the RF signal 18 becomes higher than the second power threshold Pi , the second power amplifier 22 will also operate under full compression. As such, the impedance modulation circuit 24 will stop modulating the load impedance ZIN. Instead, the impedance modulation circuit 24 will present the load impedance ZIN at a fixed value (e.g., 4XZL). The PMIC 14 will once again generate the supply voltage Vcc in accordance with the instantaneous power of the RF signal 18. In this regard, the power amplifier circuit 16 will be operating based on supply modulation. In the meantime, the first power amplifier 20 and the second power amplifier 22 will be biased equally by the control circuit 38 to each deliver one-half ( 2) of the timevariant output power POUT and collectively drive the time-variant output power POUT toward the peak power level PMAX.

[0048] Figure 4 is a graphic diagram providing an exemplary illustration as to how the power management circuit 10 of Figure 1 can reduce the supply voltage range VCC-RANGE based on a second embodiment of the present disclosure. Common elements between Figures 1 and 4 are shown therein with common element numbers and will not be re-described herein.

[0049] Herein, the power amplifier circuit 16 is configured to operate based on a first power threshold Po and a second power threshold Pi. Each of the first power threshold Po and the second power threshold Pi is lower than one-half ( 2) of the peak power level PMAX of the RF signal 18. In an embodiment, the first power threshold Po can be 10 to 16 dB below the peak power level PMAX and the second power threshold Pi is less than two times the first power threshold Po (Po < 2P1 or Pi > 2xPo).

[0050] When the instantaneous power level of the RF signal 18 is lower than the first power threshold Po, the PMIC 14 maintains the supply voltage Vcc constant at a minimum voltage level V’CC-MIN independent of how the instantaneous power level of the RF signal 18 varies. Herein, the second power amplifier 22 is deactivated, whereas the first power amplifier 20 is activated to amplify the RF signal 18 based on the supply voltage Vcc. As such, the power amplifier circuit 16 is said to operate without modulation.

[0051] When the instantaneous power level of the RF signal 18 is higher than or equal to the first power threshold Po but lower than or equal to the second power threshold Pi, the first power amplifier 20 will operate under full compression and the second power amplifier 22 will be activated and the impedance modulation circuit 24 will modulate the load impedance ZIN based on equation (Eq. 1 ). However, since the first power threshold Po is less than one- half of the second power threshold Pi, the second power amplifier 22 may not be able to deliver enough current as needed to drive the time-variant output power POUT to where should be. As such, instead of maintaining the supply voltage Vcc at the minimum voltage level VCC-MIN (as shown in Figure 3), the PMIC 14 still needs to increase the supply voltage Vcc from the minimum voltage level V’CC-MIN to help drive up the time-variant output power POUT. Accordingly, the power amplifier circuit 16 is said to operate based on a combination of load modulation and supply modulation.

[0052] In contrast to the embodiment in Figure 3, the supply voltage Vcc is clipped at the first power threshold Po to establish the minimum voltage level V’CC-MIN. Although the minimum voltage level V’CC-MI is somewhat lower than the minimum voltage level VCC-MI in Figure 3 (a.k.a. closer to the voltage floor Vcc- FLOOR than the minimum voltage level VCC- IN), the minimum voltage level V’CC-MIN is nevertheless higher than the voltage floor VCC-FLOO to thereby establish a supply voltage range V’CC-RANGE.

[0053] When the instantaneous power level of the RF signal 18 becomes higher than the second power threshold Pi, the second power amplifier 22 will also operate under full compression. As such, the impedance modulation circuit 24 will stop modulating the load impedance ZIN. Instead, the impedance modulation circuit 24 will present the load impedance ZIN at a fixed value (e.g., 4XZL). The PMIC 14 will once again generate the supply voltage Vcc in accordance with the instantaneous power of the RF signal 18. In this regard, the power amplifier circuit 16 will be operating based on supply modulation. In the meantime, the first power amplifier 20 and the second power amplifier 22 will be biased equally by the control circuit 38 to each deliver one-half (¥2) of the time-variant output power POUT and collectively drive the time-variant output power POUT toward the peak power level PMAX.

[0054] With reference back to Figure 1 , the reduced supply voltage range VCC- RANGE or V’CC-RANGE allows the PMIC 14 to program a larger value of the offset voltage VOFF across the offset capacitor COFF, thus helping to reduce the peak-to- peak range of the initial supply voltage VAMP. Specifically, as shown in equation (Eq. 2) below, the initial supply voltage VAMP is a function of the supply voltage range VCC-RANGE. By reducing the supply voltage range VCC-RANGE, the initial supply voltage VAMP will vary in a smaller range. As such, the voltage amplifier 48 can be less biased to help improve efficiency. Moreover, given that the initial supply voltage VAMP will only vary in the smaller range, it is also possible to reduce the low-frequency current be to help prolong the battery voltage VBAT.VAMP = VCC-RANGE + PHEADROOM + NHEADROOM (Eq. 2)

[0055] As described above, clipping the supply voltage Vcc at the second power threshold Pi (as in Figure 3) or at the first power threshold Po (as in Figure 4) can help reduce the supply voltage range VCC-RANGE or the supply voltage range V’CC-RANGE. However, when the PMIC 14 clips the supply voltage Vcc at the second power threshold Pi to establish the minimum voltage level VCC-MIN or at the first power threshold Po to establish the minimum voltage level V’CC-MIN, the supply voltage Vcc becomes constant. As such, it is necessary to perform additional equalization in the target voltage VTGT to help suppress unwanted distortion (e.g., ripple) in the supply voltage Vcc.

[0056] In this regard, Figure 5 is a schematic diagram providing an exemplary illustration of the target voltage circuit 60 in the power management circuit 10 of Figure 1 . Common elements between Figures 1 and 5 are shown therein with common element numbers and will not be re-described herein.

[0057] Herein, the target voltage circuit 60 includes a voltage processing circuit 64, a voltage equalization circuit 66, a combiner 68, an impedance compensation circuit 70, and a digital-to-analog converter (DAC) 72. The voltageprocessing circuit 64, which may include a digital lookup table and an equalizer (not shown), is configured to generate a digital target voltage VTGT-D based on the detected time-variant digital amplitude Vl2+Q2of the digital signal 62 and perform digital equalization on the digital target voltage VTGT-D to help suppress some unwanted distortion in the supply voltage Vcc.

[0058] However, when the PMIC 14 maintains the supply voltage Vcc constantly at the minimum voltage level VCC-MIN (as in Figure 3) or V’CC-MIN (as in Figure 4), the digital target voltage VTGT-D will not change in accordance with the time-variant input power PIN of the RF signal 18. As a result, the digital target voltage VTGT-D will not be effective in suppressing the unwanted distortion in the supply voltage Vcc, which is introduced when the supply voltage Vcc is clipped and maintained at the minimum voltage level VCC-MIN or V’CC-MIN. In this regard, the voltage equalization circuit 66 is configured to generate a correction term VTERM based on the time-variant digital amplitude Vl2+Q2of the digital signal 62 to thereby help suppress the unwanted distortion in the supply voltage Vcc when the supply voltage Vcc is kept constant at the minimum voltage level VCC-MIN or V’CC-MIN.

[0059] The combiner 68 combines the correction term VTERM with the digital target voltage VTGT-D to thereby generate a modified digital target voltage VTGT-D- MOD. The impedance compensation circuit 70 may perform additional equalization and / or filtering on the modified digital target voltage VTGT-D-MOD before the DAC 72 converts the modified digital target voltage VTGT-D-MOD into the target voltage VTGT.

[0060] With reference back to Figure 1 , the first power threshold Po and the second power threshold Pi, as illustrated in Figures 3 and 4, can be programmable based on a target of average power backoff of the power amplifier circuit 16. Accordingly, the peak detector 40 may be programmable to operate in a (Po - 2 dB) and (Pi + 2 dB) range. In this regard, it is possible to apply an appropriate bias to the second power amplifier 22 such that the second power amplifier 22 can have saturation below (Po - 2 dB) and above (Pi + 2 dB). In an embodiment, the second power amplifier 22 may be biased by the second biasvoltage Vbias-amP2 that is aoxVbias-amPibelow the first power threshold Po and <zi xVbias-ampi above the second power threshold Pi. Herein, Vbias-ampi represents the first bias voltage applied to the first power amplifier 20, and ao and ai are programmable scale factors.

[0061] The power management circuit 10 of Figure 1 can be provided in a communication device to support the embodiments described above. In this regard, Figure 6 is a schematic diagram of an exemplary communication device 100 wherein the power management circuit 10 of Figure 1 can be provided.

[0062] Herein, the communication device 100 can be any type of communication devices, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, base stations (e.g., eNB, gNB, etc.), and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Ultra- wideband (UWB), Bluetooth, and near-field communications. The communication device 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 1 10, multiple antennas 1 12, and user interface circuitry 114. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor, an embedded memory circuit, and a communication bus interface. The receive circuitry 108 receives radio frequency signals via the antennas 1 12 and through the antenna switching circuitry 110 from one or more base stations. A low-noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing.Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converters (ADCs).

[0063] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correctionoperations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

[0064] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 1 12 through the antenna switching circuitry 110. The multiple antennas 1 12 and the replicated transmit 106 and receive circuitry 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0065] In an embodiment, the transmit circuitry 106 and the receive circuitry 108 can function as the transceiver circuit 12 in Figure 1 . Accordingly, the PMIC 14 and the power amplifier circuit 16 can be provided between the transmit circuitry 106 and the antenna switching circuitry 1 10.

[0066] In an embodiment, the power management circuit 10 of Figure 1 can be operated in accordance with a process. In this regard, Figure 7 is a flowchart of an exemplary process 200 for reducing the supply voltage range VCC-RANGE in the power management circuit 10 of Figure 1 .

[0067] Herein, the process 200 includes amplifying the RF signal 18 based on the supply voltage Vcc (step 202). The process 200 also includes generating the supply voltage Vcc based on the target voltage VTGT (step 204). The process 200 also includes maintaining the supply voltage Vcc at a minimum voltage level Vcc MIN or V’CC-MIN when an instantaneous power level of the RF signal 18 is lower than or equal to a selected power threshold among the first power threshold Ro and the second power threshold Pi higher than the first power threshold Po (step 206). The process 200 also includes increasing the supplyvoltage Vcc toward the maximum voltage level VCC-MAX when the instantaneous power level of the RF signal 18 is higher than the selected power threshold (step 208). The process 200 also includes generating the target voltage VTGT with the correction term VTERM to thereby offset a ripple in the supply voltage Vcc when the instantaneous power level of the RF signal 18 is lower than or equal to the selected power threshold and the supply voltage Vcc is maintained at the minimum voltage level VCC-MIN or V’CC-MIN (step 210).

[0068] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:1 . A power management circuit comprising: a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a supply voltage; a power management integrated circuit (PMIC) configured to: generate the supply voltage based on a target voltage; maintain the supply voltage at a minimum voltage level when an instantaneous power level of the RF signal is lower than or equal to a selected power threshold among a first power threshold and a second power threshold higher than the first power threshold; and increase the supply voltage toward a maximum voltage level when the instantaneous power level of the RF signal is higher than the selected power threshold; and a transceiver circuit configured to generate the target voltage with a correction term to thereby offset a ripple in the supply voltage when the instantaneous power level of the RF signal is lower than or equal to the selected power threshold and the supply voltage is maintained at the minimum voltage level.

2. The power management circuit of claim 1 , wherein: the first power threshold is equal to one-half of the second power threshold; the second power threshold is less than one-half of a peak power level of the RF signal; and the selected power threshold is identical to the second power threshold.

3. The power management circuit of claim 2, wherein the power amplifier circuit is further configured to:operate without modulation when the instantaneous power level of the RF signal is lower than or equal to the first power threshold; operate based on supply modulation when the instantaneous power level of the RF signal is higher than the second power threshold; and operate based on load modulation when the instantaneous power level of the RF signal is higher than the first power threshold but lower than or equal to the second power threshold.

4. The power management circuit of claim 2, wherein: the PMIC is further configured to: maintain the supply voltage at the minimum voltage level when the instantaneous power level of the RF signal is lower than or equal to the second power threshold; and increase the supply voltage toward the maximum voltage level when the instantaneous power level of the RF signal is higher than the second power threshold; and the transceiver circuit is further configured to generate the target voltage with the correction term to thereby offset the ripple in the supply voltage when the instantaneous power level of the RF signal is lower than or equal to the second power threshold.

5. The power management circuit of claim 1 , wherein: the first power threshold is less than one-half of the second power threshold; the second power threshold is less than one-half of a peak power level of the RF signal; and the selected power threshold is identical to the first power threshold.

6. The power management circuit of claim 5, wherein the power amplifier circuit is further configured to:operate without modulation when the instantaneous power level of the RF signal is lower than or equal to the first power threshold; operate based on supply modulation when the instantaneous power level of the RF signal is higher than the second power threshold; and operate based on a combination of supply modulation and load modulation when the instantaneous power level of the RF signal is higher than the first power threshold but lower than or equal to the second power threshold.

7. The power management circuit of claim 5, wherein: the PMIC is further configured to: maintain the supply voltage at the minimum voltage level when the instantaneous power level of the RF signal is lower than or equal to the first power threshold; and increase the supply voltage toward the maximum voltage level when the instantaneous power level of the RF signal is higher than the first power threshold; and the transceiver circuit is further configured to generate the target voltage with the correction term to thereby offset the ripple in the supply voltage when the instantaneous power level of the RF signal is lower than or equal to the first power threshold.

8. The power management circuit of claim 1 , wherein the power amplifier circuit comprises: a first power amplifier activated at all times to amplify the RF signal based on the supply voltage; a second power amplifier activated when the instantaneous power level of the RF signal is higher than the first power threshold; and an impedance modulation circuit configured to: modulate a load impedance at an output of the first power amplifier when the second power amplifier is activated; andmaintain the load impedance at a fixed value when the second power amplifier is deactivated.

9. The power management circuit of claim 8, wherein the power amplifier circuit further comprises: a peak detector configured to detect a time-variant input power of the RF signal based on an in-phase input and a quadrature input of the RF signal; and a control circuit configured to bias the first power amplifier and the second power amplifier based on the supply voltage and the detected timevariant input power of the RF signal.

10. A wireless device comprising a power management circuit, the power management circuit comprises: a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a supply voltage; a power management integrated circuit (PMIC) configured to: generate the supply voltage based on a target voltage; maintain the supply voltage at a minimum voltage level when an instantaneous power level of the RF signal is lower than or equal to a selected power threshold among a first power threshold and a second power threshold higher than the first power threshold; and increase the supply voltage toward a maximum voltage level when the instantaneous power level of the RF signal is higher than the selected power threshold; and a transceiver circuit configured to generate the target voltage with a correction term to thereby offset a ripple in the supply voltage when the instantaneous power level of the RF signal is lower than or equal to the selected power threshold and the supply voltage is maintained at the minimum voltage level.1 1 . The wireless device of claim 10, wherein: the first power threshold is equal to one-half of the second power threshold; the second power threshold is less than one-half of a peak power level of the RF signal; and the selected power threshold is identical to the second power threshold.

12. The wireless device of claim 11 , wherein the power amplifier circuit is further configured to: operate without modulation when the instantaneous power level of the RF signal is lower than or equal to the first power threshold; operate based on supply modulation when the instantaneous power level of the RF signal is higher than the second power threshold; and operate based on load modulation when the instantaneous power level of the RF signal is higher than the first power threshold but lower than or equal to the second power threshold.

13. The wireless device of claim 11 , wherein: the PMIC is further configured to: maintain the supply voltage at the minimum voltage level when the instantaneous power level of the RF signal is lower than or equal to the second power threshold; and increase the supply voltage toward the maximum voltage level when the instantaneous power level of the RF signal is higher than the second power threshold; and the transceiver circuit is further configured to generate the target voltage with the correction term to thereby offset the ripple in the supply voltage when the instantaneous power level of the RF signal is lower than or equal to the second power threshold.

14. The wireless device of claim 10, wherein: the first power threshold is less than one-half of the second power threshold; the second power threshold is less than one-half of a peak power level of the RF signal; and the selected power threshold is identical to the first power threshold.

15. The wireless device of claim 14, wherein the power amplifier circuit is further configured to: operate without modulation when the instantaneous power level of the RF signal is lower than or equal to the first power threshold; operate based on supply modulation when the instantaneous power level of the RF signal is higher than the second power threshold; and operate based on a combination of supply modulation and load modulation when the instantaneous power level of the RF signal is higher than the first power threshold but lower than or equal to the second power threshold.

16. The wireless device of claim 14, wherein: the PMIC is further configured to: maintain the supply voltage at the minimum voltage level when the instantaneous power level of the RF signal is lower than or equal to the first power threshold; and increase the supply voltage toward the maximum voltage level when the instantaneous power level of the RF signal is higher than the first power threshold; and the transceiver circuit is further configured to generate the target voltage with the correction term to thereby offset the ripple in the supply voltage when the instantaneous power level of the RF signal is lower than or equal to the first power threshold.

17. The wireless device of claim 10, wherein the power amplifier circuit comprises: a first power amplifier activated at all times to amplify the RF signal based on the supply voltage; a second power amplifier activated when the instantaneous power level of the RF signal is higher than the first power threshold; and an impedance modulation circuit configured to: modulate a load impedance at an output of the first power amplifier when the second power amplifier is activated; and maintain the load impedance at a fixed value when the second power amplifier is deactivated.

18. The wireless device of claim 17, wherein the power amplifier circuit further comprises: a peak detector configured to detect a time-variant input power of the RF signal based on an in-phase input and a quadrature input of the RF signal; and a control circuit configured to bias the first power amplifier and the second power amplifier based on the supply voltage and the detected timevariant input power of the RF signal.

19. A method for reducing a supply voltage range in a power management circuit comprising: amplifying a radio frequency (RF) signal based on a supply voltage; generating the supply voltage based on a target voltage; maintaining the supply voltage at a minimum voltage level when an instantaneous power level of the RF signal is lower than or equal to a selected power threshold among a first power threshold and a second power threshold higher than the first power threshold;increasing the supply voltage toward a maximum voltage level when the instantaneous power level of the RF signal is higher than the selected power threshold; and generating the target voltage with a correction term to thereby offset a ripple in the supply voltage when the instantaneous power level of the RF signal is lower than or equal to the selected power threshold and the supply voltage is maintained at the minimum voltage level.

Images