Semiconductor structure and manufacturing method therefor

Abstract

A manufacturing method for a semiconductor structure, and a semiconductor structure. The manufacturing method comprises: providing a substrate; on the substrate, forming a stacked structure composed of a plurality of semiconductor material layers and a plurality of insulating material layers alternately stacked; forming channel region stacks and an initial gate pillar in the stacked structure, the initial gate pillar at least comprising an initial gate conductive layer and an initial gate dielectric layer, and the initial gate pillar having two opposite first sidewalls that are in contact with two adjacent channel region stacks respectively, and a second sidewall not in contact with the channel region stacks; and at least removing the gate dielectric layer and the gate conductive layer that are located on the second sidewall, to form a target gate pillar, the target gate pillar having two opposite third sidewalls that are in contact with two adjacent channel region stacks respectively. A gate conductive layer located on the third sidewalls has a first length and a gate dielectric layer located on the third sidewalls has a second length, the first length being smaller than the second length. A semiconductor structure having improved performance can be obtained by means of the manufacturing method.

Description

Semiconductor structure and method for manufacturing semiconductor structure

[0001] The present application claims priority from the Chinese patent application No. 202411282682.X filed on September 12, 2024, and entitled "Semiconductor structure and method for manufacturing semiconductor structure", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure. BACKGROUND

[0003] The development of dynamic random access memory (DRAM) pursues high speed, high integration density, low power consumption and other performance indicators. With the miniaturization of semiconductor device structures, the technical barriers encountered by existing structures are becoming more and more obvious. Therefore, developing more novel structures on the basis of existing structures is a favorable means to break through the existing technical barriers.

[0004] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM including multilayer horizontal cells (MHC), generally includes multiple transistors stacked on a substrate, which meets the above-mentioned requirements.

[0005] However, in the process of manufacturing multilayer horizontal storage cells in a small space, especially in the process of manufacturing horizontal storage transistors, the process is difficult, and the performance of the manufactured horizontal storage transistors needs to be improved. SUMMARY

[0006] According to a first aspect of embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate; forming a stack structure on the substrate, the stack structure including a plurality of semiconductor material layers and a plurality of insulating material layers stacked alternately; forming, in the stack structure, channel region stacks extending along a first direction perpendicular to a surface of the substrate and an initial gate pillar, the initial gate pillar including at least an initial gate conductive layer and an initial gate dielectric layer, the initial gate pillar having two opposite first side walls respectively in contact with two adjacent channel region stacks and a second side wall not in contact with any channel region stack; and removing at least the initial gate dielectric layer and the initial gate conductive layer of the initial gate pillar on the second side wall to form a target gate pillar, the target gate pillar including two opposite third side walls respectively in contact with two adjacent channel region stacks, a gate conductive layer having a first length on the third side wall, and a gate dielectric layer having a second length on the third side wall, the gate dielectric layer being between the gate conductive layer and the channel region stacks, the first length being less than the second length, and the first length and the second length being in a second direction parallel to the surface of the substrate and the surface of the third side wall.

[0007] In some embodiments, forming, in the stack structure, channel region stacks extending along a first direction perpendicular to a surface of the substrate includes: forming a plurality of first through holes in the stack structure, the first through holes extending along the first direction and penetrating the stack structure, the first through holes being arranged in a third direction parallel to the surface of the substrate, and the stack structure between adjacent first through holes being the channel region stacks.

[0008] In some embodiments, forming, in the stack structure, an initial gate pillar extending along a first direction perpendicular to a surface of the substrate includes: filling a sacrificial material in the first through holes to form first sacrificial pillars; forming a first mask having a first opening on the stack structure, and etching along the first opening to form second through holes in the first sacrificial pillars, the second through holes penetrating the stack structure and having substantially the same size as the first through holes in the third direction; and sequentially forming the initial gate dielectric layer, the initial gate conductive layer, and a first insulating layer in the second through holes to form the initial gate pillar, the initial gate pillar having two opposite first side walls respectively in contact with two adjacent channel region stacks in the third direction, and the initial gate conductive layer on the first side wall having a third length in the second direction, the third length being greater than the first length and being greater than or equal to the second length.

[0009] In some embodiments, after forming the second through-hole and before forming the initial gate pillar in the second through-hole, the fabrication method further comprises: ion implanting the channel region stack from the second through-hole to form a reverse-type doped channel region.

[0010] In some embodiments, removing at least the initial gate dielectric layer and the initial gate conductive layer of the initial gate pillar on the second sidewall to form the target gate pillar comprises: forming a second mask having a second opening on the stack structure, etching along the second opening to form a third through-hole in the first sacrificial pillar, the third through-hole penetrating the stack structure and exposing the second sidewall of the initial gate pillar; and removing at least the initial gate dielectric layer and the initial gate conductive layer on the second sidewall using the third through-hole to form the target gate pillar, the target gate pillar having two oppositely arranged third sidewalls in contact with two adjacent channel region stacks in the third direction.

[0011] In some embodiments, after forming the third through-hole and before removing at least the initial gate conductive layer on the second sidewall using the third through-hole, the fabrication method further comprises: ion implanting the stack structure adjacent to the channel region stack from the third through-hole to form a lightly doped drain region.

[0012] In some embodiments, after forming the target gate pillar, the fabrication method further comprises: filling a second insulating layer in the third through-hole.

[0013] In some embodiments, after forming the target gate pillar and before filling the second insulating layer in the third through-hole, the fabrication method further comprises: forming an auxiliary gate layer in the third through-hole, the auxiliary gate layer being located at two ends of the gate conductive layer arranged oppositely in the second direction, the work function of the auxiliary gate layer being smaller than the work function of the gate conductive layer.

[0014] In some embodiments, after forming the target gate pillar, the fabrication method further comprises: connecting the gate conductive layers on two third sidewalls located on opposite sides of the same channel region stack in the third direction and in contact with the channel region stack to form a word line structure.

[0015] In some embodiments, after forming the stack structure, the fabrication method further comprises: forming a bit line structure and a capacitor structure, the bit line structure and the capacitor structure being located at two ends of the channel region stack arranged oppositely in the second direction, respectively.

[0016] According to a second aspect of embodiments of the present disclosure, a semiconductor structure is provided, comprising: a substrate; a stack structure formed on the substrate by alternately stacking a plurality of semiconductor layers and a plurality of insulating material layers, the stack structure further comprising at least a channel region stack extending along a first direction perpendicular to a surface of the substrate; and a target gate pillar extending through the stack structure along the first direction, the target gate pillar comprising two oppositely arranged third sidewalls respectively in contact with two adjacent channel region stacks, and a gate conductive layer having a first length and a gate dielectric layer having a second length on the third sidewalls, the gate dielectric layer being between the gate conductive layer and the channel region stacks, the first length being smaller than the second length, and the first length and the second length both being along a second direction parallel to the surface of the substrate and to the surface of the third sidewalls.

[0017] In some embodiments, the channel region stacks and the target gate pillar are alternately arranged along a third direction parallel to the surface of the substrate and perpendicular to the second direction.

[0018] In some embodiments, the target gate pillar further comprises a first insulating layer, and the gate conductive layers on the two oppositely arranged third sidewalls of the same target gate pillar are separated by the first insulating layer.

[0019] In some embodiments, the channel region stack further comprises a reverse-type doped channel region in a region where the channel region stack is in contact with the third sidewall of the target gate pillar, and the stack structure further comprises a lightly doped drain region adjacent to two sides of the channel region stack along the second direction, the ion doping type of the reverse-type doped channel region being opposite to that of the lightly doped drain region.

[0020] In some embodiments, the semiconductor structure further comprises an auxiliary gate layer on two sides of the gate conductive layer on the third sidewall of the target gate pillar along the second direction, the work function of the auxiliary gate layer being smaller than that of the gate conductive layer.

[0021] In some embodiments, the semiconductor structure further comprises a word line structure comprising the gate conductive layers on two oppositely arranged third sidewalls of the same channel region stack along the third direction and in contact with the channel region stack.

[0022] In some embodiments, the semiconductor structure further comprises a bit line structure and a capacitor structure on two oppositely arranged sides of the channel region stack along the second direction, respectively. BRIEF DESCRIPTION OF DRAWINGS

[0023] FIG. 1 is a schematic diagram illustrating providing a substrate according to an exemplary embodiment;

[0024] FIG. 2 is a schematic diagram illustrating forming a stack structure according to an exemplary embodiment;

[0025] FIG. 3 is a schematic diagram illustrating forming a first through-hole and a channel region stack according to an exemplary embodiment;

[0026] FIG. 4 is a schematic diagram illustrating forming a first sacrificial pillar according to an exemplary embodiment;

[0027] FIG. 5 is a schematic diagram illustrating forming a second through-hole according to an exemplary embodiment;

[0028] FIG. 6 is a schematic diagram illustrating forming a reverse-type doped channel region according to an exemplary embodiment;

[0029] FIG. 7 is a schematic diagram illustrating forming an initial gate pillar according to an exemplary embodiment;

[0030] FIG. 8 is a schematic diagram illustrating forming a third through-hole according to an exemplary embodiment;

[0031] FIGS. 9-10 are schematic diagrams illustrating forming a lightly doped drain region stack and removing an initial gate dielectric layer and an initial gate conductive layer of the initial gate pillar on a second sidewall through the third through-hole according to an exemplary embodiment;

[0032] FIG. 11 is a schematic diagram illustrating forming a second insulating layer according to an exemplary embodiment;

[0033] FIG. 12 is a schematic diagram illustrating forming a second insulating layer according to another exemplary embodiment;

[0034] FIG. 13 is a schematic diagram illustrating forming an auxiliary gate and a second insulating layer according to yet another exemplary embodiment;

[0035] FIG. 14 is a schematic diagram illustrating forming a bit line structure and a capacitor structure according to an exemplary embodiment. DETAILED DESCRIPTION

[0036] The technical solutions of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0037] The present disclosure is described more by way of example with reference to the following paragraphs and accompanying drawings. The advantages and features of the disclosure will become more fully apparent in light of the following description and claims, appended hereto. It should be understood that the drawings are not to scale, and are merely intended for use in illustrating the embodiments of the disclosure; and where used, like reference characters designate like elements throughout the several views.

[0038] It is to be understood that the terms "on", "over", and "above" in the present disclosure are to be interpreted in the broadest possible way, such that "on" encompasses not only the meaning of "on" something without intervening intermediate features or layers (i.e., directly on something), but also the meaning of "on" something with intervening intermediate features or layers.

[0039] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0040] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of an underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A layer can include multiple sub-layers.

[0041] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0042] In the related art, the process flow of a 3D memory structure usually needs to form a stack of semiconductor material and insulating material, and then form a memory cell structure based on the semiconductor material, such as a memory transistor, a memory capacitor, a bit line, a word line, and the like. Regarding the formation of the word line structure in the 3D memory structure, there are usually two mainstream formation structures, one of which is that the word line structure controls the transistor structure in the same vertical column along the direction perpendicular to the substrate, and the other of which is that the word line structure controls the transistor structure in the same horizontal row along the direction parallel to the substrate, and the two word line structures have advantages and disadvantages, and the present disclosure mainly introduces the first kind of word line structure and the manufacturing method thereof. The present inventors have found that in the process of forming a vertical word line structure in the stack in the 3D memory structure, due to the limited space size, the gate oxide layer is thinned, and the word line structure is connected at the overlap with the drain as the gate of the transistor and the channel region of the transistor structure, which is easy to cause the gate-induced drain leakage (GIDL) effect, and seriously, it will affect the working performance of the memory transistor, the memory cell structure and even the whole memory device.

[0043] To solve the above technical problems, the present disclosure provides a semiconductor structure and a preparation method thereof. In the following, an example of a semiconductor structure and a preparation method thereof will be specifically introduced with reference to FIGS. 1-14. FIGS. 1-11 are schematic diagrams of a semiconductor structure and a preparation method thereof according to an example of the present disclosure, and FIGS. 11-14 are schematic diagrams of a semiconductor structure according to multiple examples of the present disclosure.

[0044] In an example of the present disclosure, a substrate 101 is provided, as shown in FIG. 1, wherein FIG. 1(c) is a top view toward the substrate 101 and along the direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction), and FIG. 1(a) and FIG. 1(b) are schematic diagrams of the A-A' cross section and the B-B' cross section in FIG. 1(c), respectively, the A-A' cross section is parallel to the X direction and perpendicular to the Y direction, and the B-B' cross section is parallel to the Y direction and perpendicular to the X direction.

[0045] The material of the substrate 101 can be at least one of the following materials: semiconductor materials such as silicon, germanium, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked germanium-silicon-on-insulator (S-SiGeOI), germanium-silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or III-V materials. In an example of the present disclosure, the material of the substrate 101 is monocrystalline silicon.

[0046] In an example embodiment of the present disclosure, a stack structure 102 is formed on a substrate 101, as shown in FIG. 2, where FIG. 2(c) is a top view toward the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction), and FIG. 2(a) and FIG. 2(b) are schematic views along the A-A' cross section and along the B-B' cross section in FIG. 2(c), respectively, where the A-A' cross section is parallel to the X direction and perpendicular to the Y direction, and the B-B' cross section is parallel to the Y direction and perpendicular to the X direction. In some embodiments, the plurality of semiconductor material layers 1022 and the plurality of insulating material layers 1021 are interleaved, i.e., as shown in FIG. 2(a) or FIG. 2(b), one single-layer insulating material layer 1021 is interleaved between any two adjacent single-layer semiconductor material layers 1022, and one single-layer semiconductor material layer 102 is interleaved between any two adjacent single-layer insulating material layers 1021. In the semiconductor material layers, the insulating material layers 1021 or the semiconductor material layers 1022 are closer to the substrate, which is not specifically limited in the present disclosure.

[0047] In some embodiments, the material of the semiconductor material layers 1022 can be at least one or any combination of the following materials: silicon, germanium, silicon-germanium (SiGe), III-V group material, indium gallium zinc oxide (IGZO), two-dimensional material. In an example embodiment of the present disclosure, the material of the semiconductor material layers 1022 is silicon. In some embodiments, the material of the insulating material layers 1021 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride. In an example embodiment of the present disclosure, the material of the insulating material layers 1021 is silicon oxide.

[0048] In an example embodiment of the present disclosure, the method of forming the stack structure 102 includes: using a single-crystal silicon (Si) surface of the substrate 101 as an initial base layer, and growing an initial stack structure of silicon-germanium-silicon (Si-SiGe) alternately stacked on the substrate 101 by an epitaxial growth method. Wherein, the germanium-silicon layer can be formed as a sacrificial layer by adding a germanium source gas in the process of epitaxially growing a silicon layer, and then the sacrificial layer of germanium-silicon is removed by selective lateral etching, and an insulating material is deposited or grown between the silicon layers to replace the germanium-silicon layer, thereby forming the insulating material layers 1021.

[0049] In some embodiments, the number of layers of the insulating material 1021 in the stack structure 102 is one more than the number of layers of the semiconductor material 1022, and both are greater than or equal to 4. In other embodiments, the number of layers of the insulating material 1021 in the stack structure 102 is the same as the number of layers of the semiconductor material 1022, and both are greater than or equal to 4. In some embodiments, the bottom layer of the stack structure 102, i.e., the layer in direct contact with the substrate 101, is an insulating material 1021, to ensure isolation of the bottom memory cell structure from the substrate 101 in subsequent processes. In some embodiments, the top layer of the stack structure 102, i.e., the layer farthest from the substrate 101, is an insulating material 1021, to protect the underlying memory cell structure from damage in subsequent processes.

[0050] In some embodiments, before or after forming the stack structure 102 on the substrate 101, an isolation layer (not shown) is formed on other regions of the substrate 101, where the isolation layer is at the same level as the stack structure 102.

[0051] In an exemplary embodiment of the present disclosure, a plurality of first through-holes 1030 are formed in the stack structure 102, the first through-holes 1030 extending along the Z direction and penetrating the stack structure 102, and the first through-holes 1030 are arranged in the Y direction with a spacing between adjacent first through-holes 1030, and the stack structure 102 between adjacent first through-holes 1030 serves as a channel region stack 1023, as shown in FIG. 3(c), which is a top view toward the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction), and FIG. 3(a) and FIG. 3(b) are schematic views of the cross-sections along A-A’ and B-B’ in FIG. 3(c), respectively, where A-A’ is parallel to the X direction and perpendicular to the Y direction, and B-B’ is parallel to the Y direction and perpendicular to the X direction.

[0052] In some embodiments, the spacing between adjacent first through-holes 1030 is equal. In some embodiments, the cross-sectional shape of the first through-holes 1030 along a direction parallel to the surface of the substrate 101 is rectangular, rounded rectangular, or quasi-rectangular with arc-shaped edges on both ends in the X direction and straight edges on both ends in the Y direction, to ensure that the channel region stack 1023 between adjacent first through-holes 1030 has relatively flat sidewall surfaces.

[0053] In some embodiments, the stack structure 102 can be etched by a lithography process to form the first through-hole 1030. Specifically, a photoresist mask layer can be formed on the stack structure 102, a pattern of the first through-hole 1030 can be formed in the photoresist mask layer by exposure and development, and then dry etching can be performed to etch the stack structure 102 along the pattern to form the first through-hole 1030. In some embodiments, before the photoresist mask layer is coated, an anti-reflective layer and a hard mask layer (not shown) are also formed on the top surface of the stack structure 102, and are removed after the first through-hole 1030 is formed.

[0054] In an exemplary embodiment of the present disclosure, after the first through-hole 1030 is formed, the first through-hole is filled with a sacrificial material to form a first sacrificial column 103, as shown in FIG. 4, where FIG. 4(c) is a top view toward the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction), and FIG. 4(a) and FIG. 4(b) are schematic views along the A-A' cross section and the B-B' cross section in FIG. 4(c) respectively, the A-A' cross section is parallel to the X direction and perpendicular to the Y direction, and the B-B' cross section is parallel to the Y direction and perpendicular to the X direction. Specifically, in some embodiments, a first sacrificial material layer 1031 is deposited in the first through-hole 1030 to cover the inner wall (including the sidewall and the bottom wall) of the first through-hole 1030, and then a second sacrificial material layer 1032 is deposited on the surface of the first sacrificial material layer 1031 to fill the first through-hole 1030, and the first sacrificial material layer 1031 and the second sacrificial material layer 1032 together constitute the first sacrificial column 103. Since the first sacrificial material layer 1031 covers the sidewall of the first through-hole 1030 and the bottom wall, i.e., also covers the sidewall of the channel region stack 1023 and the surface of the substrate 101 which are spaced apart by the first through-hole 1030, the sidewall of the channel region stack 1023 and the surface of the substrate 101 are protected to a certain extent in the subsequent etching process. In other embodiments, the first sacrificial column 103 further includes a third sacrificial material layer (not shown) between the first sacrificial material layer 1031 and the second sacrificial material layer 1032.

[0055] In some embodiments, the materials of the first sacrificial material layer 1031 and the second sacrificial material layer 1032 can be at least one or any combination of the following materials: silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, and polysilicon. In an exemplary embodiment of the present disclosure, the material of the first sacrificial material layer 1031 is silicon oxide, and the material of the second sacrificial material layer 1032 is polysilicon.

[0056] In some embodiments, the deposition method of the first and second sacrificial material layers 1031 and 1032 can employ at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma-assisted chemical vapor deposition (MPCVD), metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD).

[0057] In an exemplary embodiment of the present disclosure, after forming the first sacrificial pillars 103, a first mask 1041 with first openings 1040' is formed on the stack structure 102, and the second through holes 1040 are etched along the first openings 1040' to form in the first sacrificial pillars 103, the second through holes 1040 penetrating the stack structure 102, and at least in the Y direction, the size of the second through holes 1040 is substantially the same as the size of the first through holes 1030. Referring to FIG. 5, where FIG. 5(c) is a top view toward the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction), FIG. 5(a) and FIG. 5(b) are schematic views along the A-A' cross section and the B-B' cross section in FIG. 5(c) respectively, the A-A' cross section is parallel to the X direction and perpendicular to the Y direction, and the B-B' cross section is parallel to the Y direction and perpendicular to the X direction.

[0058] In some embodiments, as viewed from a cross section parallel to the surface of the substrate 101, the second through holes 1040 are located at a position close to the middle of the first sacrificial pillars 103, equivalent or approximately equivalent to a common central axis, it is noted that the direction of the "central axis" here is the direction perpendicular to the surface of the substrate 101. In some embodiments, the second through holes 1040 expose the sidewalls of the channel region stack 1023 on two sidewalls oppositely arranged in the Y direction. In some embodiments, the size of the second through holes 1040 in the X direction is smaller than the size of the first through holes 1030 in the X direction, and greater than or equal to the size of the channel region stack 1023 in the X direction.

[0059] In some embodiments, the first opening 1040’ is in a single long strip shape, with the long side extending along the Y direction, exposing the top surface of part of the first sacrificial columns 103 and the top surface of the entire channel region stack 1023. In some embodiments, the forming method of the first opening 1040’ can etch the first mask 1041 using a photolithography process to form the first opening 1040’. Specifically, a photoresist mask layer can be formed on the first mask 1041, the pattern of the first opening 1040’ is formed in the photoresist mask layer by exposure and development, and then dry etching is performed to etch the first mask 1041 along the pattern to form the first opening 1040’. In some embodiments, before coating the photoresist mask layer, an anti-reflective layer (not shown) is also formed on the top surface of the first mask 1041, and is removed after the first opening 1040’ is formed.

[0060] In some embodiments, the material of the first mask 1041 can be any one or a combination of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In some embodiments, the deposition method of the first mask 1041 can use at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0061] In some embodiments, the etching process of forming the second through hole 1040 is basically the same as the description of the etching process of forming the first through hole 1030 in the foregoing embodiments, which will not be repeated here, but different from the forming of the first through hole 1030 in the foregoing embodiments is that the first mask 1041 will not be removed temporarily after the second through hole 1040 is formed.

[0062] In an example embodiment of the present disclosure, after forming the second through holes 1040, ion implantation LI is performed on the channel region stacks 1023 by the second through holes 1040 to form the inversion doped channel regions 1022a, as shown in FIG. 6(c), which is a top view toward the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction), and FIG. 6(a) and FIG. 6(b) are schematic views along the A-A' cross section and along the B-B' cross section in FIG. 6(c), respectively, the A-A' cross section is parallel to the X direction and perpendicular to the Y direction, and the B-B' cross section is parallel to the Y direction and perpendicular to the X direction. Specifically, the ion implantation LI with an oblique angle is performed on the exposed sidewalls of the channel region stacks 1023 by the second through holes 1040, with the first mask 1041 and the top insulating material layer 1021 exposed by the first openings 1040' as the mask, to form the inversion doped channel regions 1022a on the two sidewalls of each channel region stack 1023 located opposite to each other in the Y direction. It should be noted that the "oblique angle" herein is inclined along the Y direction or the reverse direction of the Y direction with the Z direction (or the reverse direction thereof) as the axis.

[0063] In some embodiments, the ions of the ion implantation LI can be boron ions.

[0064] In an example embodiment of the present disclosure, after forming the inversion doped channel regions 1022a, the initial gate dielectric layer 1051, the initial gate conductive layer 1052 and the first insulating layer are sequentially formed in the second through holes 1040 to constitute the initial gate pillars 105, which have two opposite first sidewalls in the Y direction, respectively in contact with the adjacent two channel region stacks 1023, and the initial gate conductive layer 1052 on the first sidewall of the initial gate pillars 105 has a third length D3 in the X direction, as shown in FIG. 7(c), which is a top view toward the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction), and FIG. 7(a) and FIG. 7(b) are schematic views along the A-A' cross section and along the B-B' cross section in FIG. 7(c), respectively, the A-A' cross section is parallel to the X direction and perpendicular to the Y direction, and the B-B' cross section is parallel to the Y direction and perpendicular to the X direction. In some embodiments, the first insulating layer includes a plurality of insulating sub-layers. In an example embodiment of the present disclosure, the first insulating layer includes a first insulating sub-layer 1053 and a second insulating sub-layer 1054, wherein the first insulating sub-layer 1053 is located at the outer periphery of the second insulating sub-layer 1054. In some embodiments, in the X direction, the sidewall of the initial gate dielectric layer 1051 in contact with the channel region stack 1023 covers at least the surface of the inversion doped channel region 1022a.

[0065] In some embodiments, the material of the first and second insulating sub-layers 1053 and 1054 can be at least one or any combination of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride. In an exemplary embodiment of the present disclosure, the material of the first insulating sub-layer 1053 is silicon nitride, and the material of the second insulating sub-layer 1054 is silicon oxide. In some embodiments, the deposition method of the first insulating layer can be at least one of the following: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD).

[0066] In some embodiments, the material of the initial gate dielectric layer 1051 can be silicon oxide, and the material of the initial gate conductive layer 1052 can be titanium nitride or tungsten. In an exemplary embodiment of the present disclosure, the formation method of the initial gate dielectric layer 1051 employs in-situ steam generation (ISSG) process, and the formation method of the initial gate conductive layer 1052 employs atomic layer deposition (ALD) process.

[0067] In an exemplary embodiment of the present disclosure, after the initial gate pillar 105 is formed, a second mask 1061 with a second opening 1060’ is formed on the stack structure 102, and a third through-hole 1060 is etched along the second opening 1060’ to form in the first sacrificial pillar 103, the third through-hole 1060 penetrates the stack structure 102 and exposes the second sidewall of the initial gate pillar 105, wherein the second sidewall of the initial gate pillar 105 is not in contact with the channel region stack 1023. Referring to FIG. 8, FIG. 8(c) is a top view toward the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e. opposite to the Z direction), FIG. 8(a) and FIG. 8(b) are schematic views along the A-A’ cross section and the B-B’ cross section in FIG. 8(c) respectively, the A-A’ cross section is parallel to the X direction and perpendicular to the Y direction, and the B-B’ cross section is parallel to the Y direction and perpendicular to the X direction. In some embodiments, in the plane direction parallel to the surface of the substrate 101, the position of the second opening 1060’ is adjacent to the two ends of the position of the first opening 1040’ in the X direction in the foregoing embodiments. In some embodiments, the third through-hole 1060 removes all the first sacrificial pillars 103 remaining after the formation of the second through-hole 1040 in the foregoing embodiments. In some embodiments, the third through-hole 1060 is formed while also removing the initial gate dielectric layer 1051 of the initial gate pillar 105 on the second sidewall, as shown in FIG. 8(a).

[0068] In some embodiments, the third through holes 1060 are located near the two ends of the first sacrificial pillars 103 in the X direction, i.e., the third through holes 1060 are adjacent to the two ends of the initial gate pillars 105 in the X direction, as viewed along a cross section parallel to the surface of the substrate 101. In some embodiments, the third through holes 1060 are symmetrically arranged with respect to a plane in which the central axes of the plurality of initial gate pillars 105 arranged in the Y direction are collectively located. In some embodiments, the third through holes 1060 expose at least the sidewalls of the stack structure 102 adjacent to the channel region stack 1023.

[0069] In some embodiments, the second openings 1060’ are in the shape of two long strips, with the long sides extending in the Y direction, exposing the top surfaces of the remaining first sacrificial pillars 103 and the top surfaces of the stack structure 102 adjacent to the channel region stack 1023. In some embodiments, the forming method of the second openings 1060’ can be substantially the same as the forming method of the first openings 1040’ described in the foregoing embodiments, and thus no repeated description is provided herein.

[0070] In some embodiments, the material and forming method of the second mask 1061 can be substantially the same as the material and forming method of the first mask 1041 described in the foregoing embodiments, and thus no repeated description is provided herein.

[0071] In some embodiments, the etching process for forming the third through holes 1060 can be substantially the same as the etching process for forming the first through holes 1030 described in the foregoing embodiments, and thus no repeated description is provided herein. However, unlike the forming of the first through holes 1030 in the foregoing embodiments, the second mask 1061 is not removed temporarily after the forming of the third through holes 1060.

[0072] In an example embodiment of the present disclosure, after the third through-hole 1060 is formed, ion implantation L2 is performed on the stack structure 102 adjacent to the channel region stack 1023 by the third through-hole 1060 to form a lightly doped drain region 1022b (LDD), as shown in FIG. 9, where FIG. 9(c) is a top view toward the substrate 101 and along a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction), and FIG. 9(a) and FIG. 9(b) are schematic views along the A-A' cross section and along the C-C' cross section in FIG. 9(c) respectively, the A-A' cross section is parallel to the X direction and perpendicular to the Y direction, and the C-C' cross section is parallel to the Y direction and perpendicular to the X direction. Specifically, ion implantation L2 at a tilt angle is performed on the sidewalls of the stack structure 102 exposed by the third through-hole 1060, with the second mask 1061 and the top insulating material layer 1021 exposed by the second opening 1060' as a mask, to form the lightly doped drain region 1022b on the two sidewalls of the stack structure 102 exposed by the third through-hole 1060 and oppositely arranged at least in the Y direction, i.e., to form the lightly doped drain region 1022b on the two sidewall surfaces of each semiconductor material layer 1022 of the stack structure 102 exposed by the third through-hole 1060 and oppositely arranged at least in the Y direction, to form a lightly doped drain region stack. It should be noted that the "tilt angle" here is tilted along the Y direction or the reverse direction of the Y direction with the Z direction (or its reverse direction) as the axis. In some embodiments, the lightly doped drain region 1022b is formed on a partial region of the sidewall of the stack structure 102 exposed by the third through-hole 1060; while in other embodiments, the lightly doped drain region 1022b is formed on the entire region of the sidewall of the stack structure 102 exposed by the third through-hole 1060. It should be noted that the "partial region" and "entire region" here both refer to the surface region of each semiconductor material layer 1022, and the insulating material layer 1021 in the stack structure 102 exposed by the third through-hole 1060 will not form the lightly doped drain region 1022b.

[0073] In some embodiments, the ion implantation L2 is opposite to the doping ion type of the ion implantation L1 in the foregoing embodiments, and the ions of the ion implantation L2 can be phosphorus ions or arsenic ions.

[0074] In some embodiments, after the lightly doped drain region 1022b is formed, source and drain doping is further performed on the stack structure 102 adjacent to the two ends of the channel region stack 102 oppositely arranged in the X direction to form source and drain regions, and the doping ion type of the source and drain regions is the same as that of the lightly doped drain region 1022b.

[0075] In an example embodiment of the present disclosure, after the lightly doped drain region 1022b is formed, the initial gate conductive layer 1052 on the second sidewall of the initial gate pillar 105 is removed at least by the third through-hole 1060 to form a target gate pillar 105', which has two oppositely arranged third sidewalls in the Y direction, each of which is in contact with an adjacent two channel region stacks 1023, and a gate conductive layer 1052' with a first length and a gate dielectric layer 1051' with a second length on the third sidewall, the first length being smaller than the second length, as shown in FIG. 10(c), which is a top view of the substrate 101 and in a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction), and FIG. 10(a) and FIG. 10(b) are schematic views of FIG. 10(c) along the A-A' cross section and the B-B' cross section, respectively, the A-A' cross section being parallel to the X direction and perpendicular to the Y direction, and the B-B' cross section being parallel to the Y direction and perpendicular to the X direction. Specifically, a wet chemical etching or a lateral dry etching is used to side etch the initial gate conductive layer 1052 on the second sidewall of the initial gate pillar 105 exposed by the third through-hole 1060 to remove at least the initial gate conductive layer 1052 on the second sidewall.

[0076] In some embodiments, since the initial gate dielectric layer 1051 on the second sidewall of the initial gate pillar 105 has been removed in the process of forming the third through-hole 1060 in the foregoing embodiments, the present side etching only removes the initial gate conductive layer 1052 on the second sidewall. In other embodiments, after the third through-hole 1060 is formed in the foregoing embodiments, the initial gate dielectric layer 1051 on the second sidewall of the initial gate pillar 105 is not removed or not completely removed, and the present side etching first removes the initial gate dielectric layer 1051 on the second sidewall, and then removes the initial gate conductive layer 1052 on the second sidewall.

[0077] In some embodiments, after the initial gate conductive layer 1052 on the second sidewall of the initial gate pillar 105 is removed by the side etching, a small amount of over etching is performed on the initial gate conductive layer 1052 on the first sidewall of the initial gate pillar 105 in contact with the channel region stack 1023 to obtain the target gate pillar 105'.

[0078] In some embodiments, the initial gate pillar 105 in the foregoing embodiments has a third length in the X direction for the initial gate conductive layer 1052 on the first sidewall, which is greater than the first length and greater than or equal to the second length. That is, due to the etching of the initial gate dielectric layer 1051 and the initial gate conductive layer 1052 of the initial gate pillar 105 on the second sidewall, the initial gate dielectric layer 1051 and the initial gate conductive layer 1052 of the initial gate pillar 105 on the first sidewall are also lost to some extent, and the length of the gate conductive layer 1052' on the third sidewall of the target gate pillar 105' formed finally is shorter than that of the original initial gate conductive layer 1052 in the X direction. The projection overlap area of the gate conductive layer 1052' and the lightly doped drain region in the Y direction is reduced, thereby reducing the probability of occurrence of the gate-induced drain leakage (GIDL) effect, reducing the impact of GIDL, and thus improving the working performance of the memory device.

[0079] In an exemplary embodiment of the present disclosure, after the target gate pillar 105' is formed, the second insulating layer 107 is filled in the third through hole 1060, as shown in FIG. 11, FIG. 11(c) is a top view toward the substrate 101 and in a direction perpendicular to the surface of the substrate 101 (i.e., opposite to the Z direction), and FIG. 11(a) and FIG. 10(b) are schematic views along the A-A' cross section and the B-B' cross section in FIG. 10(c), respectively, the A-A' cross section is parallel to the X direction and perpendicular to the Y direction, and the B-B' cross section is parallel to the Y direction and perpendicular to the X direction. In some embodiments, the second insulating layer 107 fills the third through hole 1060 and is in seamless contact with the target gate pillar 105' at opposite ends of the target gate pillar 105' in the X direction.

[0080] In some embodiments, the material and forming method of the second insulating layer 107 can be the same as the description of the material and forming method of the first insulating layer in the foregoing embodiments, which will not be repeated here. In an exemplary embodiment of the present disclosure, the material of the second insulating layer 107 is silicon oxide. The silicon oxide of the second insulating layer 107 has a lower dielectric constant, and when covering the two ends of the gate conductive layer 1052' arranged opposite in the X direction, it can further reduce the impact of the GIDL effect caused by band-to-band tunneling (BTBT).

[0081] In another exemplary embodiment of the present disclosure, referring to FIG. 12, FIG. 12(c) is a top view toward the substrate 101 and along a direction perpendicular to the surface of the substrate 201 (i.e. opposite to the Z direction), and FIG. 12(a) and FIG. 12(b) are schematic views along the A-A' cross section and along the B-B' cross section in FIG. 12(c) respectively, the A-A' cross section is parallel to the X direction and perpendicular to the Y direction, and the B-B' cross section is parallel to the Y direction and perpendicular to the X direction, providing a structure substantially the same as that shown in FIG. 10 in the foregoing embodiments, and different from the structure shown in FIG. 11 and the forming steps, in FIG. 12, before the second insulating layer 2072 is filled in the third through hole, an additional step of forming a third insulating layer 2071 covering the inner wall of the third through hole (including the side wall and the bottom wall) is included, and the third insulating layer 2071 is located between the subsequently filled second insulating layer 2072 and the substrate 201, the stack structure 202 and the target gate pillar 205'.

[0082] In some embodiments, the materials and forming methods of the second insulating layer 2072 and the third insulating layer 2071 are the same as the description of the materials and forming methods of the first insulating layer in the foregoing embodiments, and are not repeated here. In an exemplary embodiment of the present disclosure, the material of the second insulating layer 2072 is silicon oxide, and the material of the third insulating layer 2071 is silicon nitride. The silicon nitride of the third insulating layer 2071 has good oxygen and water vapor barrier function, and when covering the two ends of the gate conductive layer 2052' and the gate dielectric layer 2051' arranged opposite in the X direction, it can protect the gate conductive layer 2052' and the gate dielectric layer 2051' from the influence of oxygen and water vapor in the environment, thereby to a certain extent, guarantee the working performance of the memory device.

[0083] In yet another exemplary embodiment of the present disclosure, referring to FIG. 13, FIG. 13(c) is a top view toward the substrate 101 and along a direction perpendicular to the surface of the substrate 301 (i.e. opposite to the Z direction), and FIG. 13(a) and FIG. 13(b) are schematic views along the A-A' cross section and along the B-B' cross section in FIG. 13(c) respectively, the A-A' cross section is parallel to the X direction and perpendicular to the Y direction, and the B-B' cross section is parallel to the Y direction and perpendicular to the X direction, providing a structure substantially the same as that shown in FIG. 10 in the foregoing embodiments, and different from the structure shown in FIG. 11 and the forming steps, in FIG. 13, before the second insulating layer 307 is filled in the third through hole, an additional step of forming an auxiliary gate layer 308 is included, the auxiliary gate layer 308 is located at the two ends of the gate conductive layer 3052' on the third side wall of the target gate pillar 305, and the work function of the auxiliary gate layer 308 is smaller than that of the gate conductive layer 3052'. Specifically, an auxiliary gate material layer is first formed in the third through hole to cover the inner wall of the third through hole, and then the auxiliary gate material layer in other regions is etched except the positions at the two ends of the gate conductive layer 3052' arranged opposite in the X direction, so as to leave the remaining auxiliary gate material layer as the auxiliary gate layer.

[0084] In some embodiments, the material of the auxiliary gate layer 308 adopts doped polysilicon, and the material of the gate conductive layer 3052’ adopts titanium nitride. Compared with the material of titanium nitride, the doped polysilicon has a lower work function, and the auxiliary gate layer 308 is located at both ends of the gate conductive layer 3052’ on the third sidewall of the target gate pillar 305, which makes up for the problem that the short length of the gate conductive layer in the foregoing embodiments is easy to cause a large gate resistance and poor transmission of electrical signals, and the like. At the same time, since the auxiliary gate layer 308 is located in the overlapping area with the projection of the lightly doped drain region in the Y direction, the auxiliary gate layer with a lower work function can also reduce the influence of the GIDL effect to a certain extent, thereby improving the working performance of the memory device.

[0085] In some embodiments, the deposition method of the auxiliary gate layer 308 can adopt at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD).

[0086] In an exemplary embodiment of the present disclosure, after the target gate pillar 105’ is formed, the gate conductive layer 1052’ on the third sidewall of the two target gate pillars 105’ located on the opposite sides of the same channel region stack 1023 in the Y direction and in contact with the channel region stack 1023 are connected to form a word line structure. Specifically, each word line structure corresponds to each channel region stack 1023 one by one, and each word line structure connects two gate conductive layers 1052’ most adjacent to each corresponding channel region stack 1023 two by two. The main body of the word line structure is the two gate conductive layers 1052’ adjacent to the same channel region stack 1023, which jointly controls the opening or closing of the inversion doped channel region 1022a located in the same channel region stack 1023.

[0087] In an example embodiment of the present disclosure, after the formation of the stack structure 102, a bit line structure and a capacitor structure are further formed, which are respectively located at two ends of the channel region stack 1023 oppositely arranged in the X direction. Specifically, at one end of the stack structure 102 in the X direction, a portion of the semiconductor material layer 1022 is selectively laterally etched and removed, and then a bit line material is filled to form a bit line structure; at the other end of the stack structure 102 in the X direction, a portion of the semiconductor material layer 1022 is selectively laterally etched and removed, and then a capacitor material including a first electrode material, a capacitor dielectric material, and a second electrode material is filled to form a capacitor structure. It should be noted that, before the formation of the capacitor structure, an insulating isolation layer extending in the X direction and the Z direction and penetrating through the stack structure 102 is formed in the stack structure 102 to separate the channel region stacks 1023 and the semiconductor material layer in the Y direction. For reference, the structure and positional relationship of the bit line structure 409 and the capacitor structure 410 in the stack structure 402 can be seen in FIG. 14(e), where FIG. 14(c) is a top view of the substrate 101 and in a direction perpendicular to the surface of the substrate 401 (i.e., opposite to the Z direction), FIG. 14(a), FIG. 14(b), and FIG. 14(d) are schematic views of FIG. 14(c) along the A-A' cross section, the B-B' cross section, and the D-D' cross section, respectively, FIG. 14(e) is a schematic view of FIG. 14(d) along the E-E' cross section, and FIG. 14(f) is a partial enlarged schematic view of the F region (dashed box) in FIG. 14(e), the A-A' cross section and the D-D' cross section are parallel to the X direction and perpendicular to the Y direction, the B-B' cross section is parallel to the Y direction and perpendicular to the X direction, and the E-E' cross section is perpendicular to the Z direction. Each bit line structure 409 is used to provide or sense the induced charge stored or released in each capacitor structure 410 in the same horizontal layer through the semiconductor material layer 4022.

[0088] In some embodiments, the formation sequence of the bit line structure 409, the capacitor structure 410, and the channel region stack 4023 can be various arrangements, for example, the bit line structure 409 can be formed first, then the capacitor structure 410, and finally the channel region stack 4023, or the channel region stack 4023 can be formed first, then the bit line structure 409, and finally the capacitor structure 410, which is not specifically limited in the present disclosure.

[0089] In some embodiments, after selectively laterally etching a portion of the semiconductor material layer, before filling the bit line material and / or the capacitor material, a metal silicide treatment is performed on the end surface of the remaining and exposed semiconductor material layer, to form a bit line contact layer (not shown) and / or a capacitor contact layer (not shown), so as to reduce the contact resistance between the bit line structure and / or the capacitor structure and the semiconductor material layer.

[0090] In some embodiments, the method of selectively etching away part of the semiconductor material layer 1022 can employ wet chemical etching, specifically, ammonia deionized water mixture (ADM), potassium hydroxide solution (KOH) or tetramethylammonium hydroxide (TMAH) as a silicon etching solution to selectively etch the semiconductor material layer 1022.

[0091] In some embodiments, the material of the bit line structure can employ one or more of a combination of titanium nitride, titanium, tungsten, tungsten nitride. In other embodiments, the material of the bit line structure can also employ one or more of molybdenum, ruthenium, copper, platinum, tantalum or their nitrides. In some embodiments, the electrode material in the capacitor structure can employ one or more of a combination of titanium nitride, tantalum nitride, silicon-doped titanium nitride; the capacitor dielectric material of the capacitor structure can employ at least one or more of a combination of zirconium oxide (ZrO2), aluminum oxide (Al2O3), and in other embodiments, the capacitor dielectric material can also be at least one or more of a combination of silicon oxide (SiO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), lead titanate (PZT).

[0092] In some embodiments, the method of forming the material of the bit line structure and the capacitor structure can employ at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating sputtering.

[0093] In the method of preparing the semiconductor structure provided by the present disclosure, in a first aspect, by forming a stack structure on a substrate first, then forming a first sacrificial column in the stack structure, then forming an initial gate column in the first sacrificial column, and then removing the remaining first sacrificial column and side etching the initial gate column to form a target gate column, a gate conductive layer with the target gate column on the third side wall in contact with the channel region stack can be obtained, which can reduce the overlapping area of the lightly doped drain region adjacent to both sides of the channel region stack, thereby reducing the influence of GIDL effect; in a second aspect, the process step of forming the gate conductive layer is relatively low in difficulty and high in feasibility, and without increasing much cost, a structure with high device performance can be obtained.

[0094] Based on the above semiconductor structure preparation method, the present disclosure also provides a semiconductor structure as shown in any of FIGS. 10-14, comprising at least: a substrate 101 (201 / 301 / 401); a stack structure 102 (202 / 302 / 402) of a plurality of semiconductor layers 1022 (2022 / 3022 / 4022) and a plurality of insulating material layers 1021 (2021 / 3021 / 4021) alternately stacked on the substrate 101 (201 / 301 / 401), the stack structure 102 (202 / 302 / 402) comprising at least a channel region stack 1023 (2023 / 3023 / 4023) extending along a Z direction perpendicular to a surface of the substrate 101 (201 / 301 / 401); a target gate pillar 105' (205' / 305' / 405') penetrating the stack structure 102 (202 / 302 / 402) along the Z direction, the target gate pillar 105' (205' / 305' / 405') having a third sidewall in contact with the channel region stack 1023 (2023 / 3023 / 4023), the target gate pillar 105' (205' / 305' / 405') comprising a gate conductive layer 1052' (2052' / 3052' / 4052') on the third sidewall and a gate dielectric layer 1051' (2051' / 3051' / 4051') on an outer surface of the gate conductive layer 1052' (2052' / 3052' / 4052'), the gate conductive layer 1052' (2052' / 3052' / 4052') having a first length, and the gate dielectric layer 1051' (2051' / 3051' / 4051') having a second length, the first length being smaller than the second length; wherein the length directions of the first length and the second length are both X directions, and the X directions are parallel to the surface of the substrate 101 (201 / 301 / 401) and the surface of the third sidewall.

[0095] In some embodiments, in the Y direction, the channel region stacks 1023 (2023 / 3023 / 4023) and the target gate pillars 105' (205' / 305' / 405') are arranged alternately, and the Y direction is parallel to the surface of the substrate 101 (201 / 301 / 401) and perpendicular to the X direction.

[0096] In some embodiments, the same target gate pillar 105' (205' / 305' / 405') has two oppositely arranged third sidewalls in contact with two adjacent channel region stacks 1023 (2023 / 3023 / 4023) respectively, and the gate conductive layers on the two oppositely arranged third sidewalls are isolated by a first insulating layer. In some embodiments, the first insulating layer comprises a first insulating sublayer 1053 (2053 / 3053 / 4053) and a second insulating sublayer 1054 (2054 / 3054 / 4054).

[0097] In some embodiments, the channel region stack 1023 (2023 / 3023 / 4023) further comprises a counter-doped channel region 1022a (2022a / 3022a / 4022a) in the region where the channel region stack 1023 (2023 / 3023 / 4023) is in contact with the third sidewall of the target gate pillar 105' (205' / 305' / 405'), the stack structure 102 (202 / 302 / 402) further comprises a lightly-doped drain region stack, the lightly-doped drain region stack is adjacent to both sides of the channel region stack 1023 (2023 / 3023 / 4023) in the X direction, the lightly-doped drain region stack further comprises a lightly-doped drain region 1022b (2022b / 3022b / 4022b), the ion doping type of the lightly-doped drain region 1022b (2022b / 3022b / 4022b) is opposite to that of the counter-doped channel region 1022a (2022a / 3022a / 4022a). In some embodiments, the doping ion of the counter-doped channel region 1022a can be boron ion, and the doping ion of the lightly-doped drain region 1022b (2022b / 3022b / 4022b) can be phosphorus ion or arsenic ion.

[0098] In some embodiments, as shown in FIG. 11, a second insulating layer 107 is further included, which is located on both sides of the target gate pillar 105' in the X direction. In some embodiments, the material of the second insulating layer 107 is silicon oxide.

[0099] In some embodiments, as shown in FIG. 12, a second insulating layer 2072 and a third insulating layer 2071 are further included, the third insulating layer 2071 is located between the second insulating layer 2072 and the substrate 201, the stack structure 202 and the target gate pillar 205'. In some embodiments, the material of the second insulating layer 2072 is silicon oxide, and the material of the third insulating layer 2071 is silicon nitride.

[0100] In some embodiments, as shown in FIG. 13, an auxiliary gate layer 308 is further included, which is located on both sides of the gate conductive layer 3052' on the third sidewall of the target gate pillar 305', and the work function of the auxiliary gate layer 308 is smaller than that of the gate conductive layer 3052'. In some embodiments, the material of the auxiliary gate layer 308 is doped polysilicon, and the material of the gate conductive layer 3052' is titanium nitride.

[0101] In some embodiments, further comprising word line structures (not shown) including gate conductive layers 1052'(2052' / 3052' / 4052') on third side walls connecting two target gate pillars 105'(205' / 305' / 405') located on opposite sides of and in contact with the same channel region stack 1023(2023 / 3023 / 4023) in the Y direction. Specifically, each word line structure corresponds to each channel region stack 1023(2023 / 3023 / 4023) one-to-one, connecting two gate conductive layers 1052'(2052' / 3052' / 4052') most proximate to each corresponding channel region stack 1023(2023 / 3023 / 4023) two-by-two, respectively, and the main body of the word line structure is the two gate conductive layers 1052'(2052' / 3052' / 4052') adjacent to the same channel region stack 1023(2023 / 3023 / 4023), collectively controlling the turn-on or turn-off of the inversion doped channel region 1022a(2022a / 3022a / 4022a) in the same channel region stack 1023(2023 / 3023 / 4023).

[0102] In some embodiments, referring to FIG. 14, where FIG. 14(c) is a top view toward substrate 101 and along a direction perpendicular to the surface of substrate 401 (i.e. opposite to the Z direction), FIG. 14(a), FIG. 14(b) and FIG. 14(d) are schematic views along A-A’ cross section, along B-B’ cross section and along D-D’ cross section respectively in FIG. 14(c), FIG. 14(e) is a schematic view along E-E’ cross section in FIG. 14(d), FIG. 14(f) is a partial enlarged schematic view in region F (dashed box) in FIG. 14(e), A-A’ cross section and D-D’ cross section are parallel to X direction and perpendicular to Y direction, B-B’ cross section is parallel to Y direction and perpendicular to X direction, E-E’ cross section is perpendicular to Z direction. In an example embodiment of the present disclosure, bit line structure 409 and capacitor structure 410 are further included, and insulating isolation layer 4024 is located in stack structure 402, extending along Z direction and X direction and penetrating through stack structure 402, for spacing each channel region stack 4023 and semiconductor material layer 4022 in Y direction. In some embodiments, semiconductor material layer 4022 has a source / drain region (not shown) at each of the two ends arranged oppositely along X direction, and the source / drain region has the same doping ion type as that of lightly doped drain region 4022b. In some embodiments, bit line structure 409 is connected to the source / drain region at one end of semiconductor material layer 4022 arranged oppositely along X direction in the same horizontal layer, and each capacitor structure 410 is connected to the source / drain region at the other end of semiconductor material layer 4022 arranged oppositely along X direction, and each bit line structure 409 is used to provide or sense the induced charge stored or released in each capacitor structure 410 in the same horizontal layer through semiconductor material layer 4022. In some embodiments, each capacitor structure 410 further includes first electrode layer 4101, capacitor dielectric layer 4102 and second electrode layer 4103 stacked in sequence, as shown in FIG. 14(d) / (e) / (f), first electrode layer 4101 is in contact with semiconductor material layer 4022, capacitor dielectric layer 4102 is located on the surface of first electrode layer 4101, and second electrode layer 4103 is located on the surface of capacitor dielectric layer 4102. In some embodiments, the material of first electrode layer 4101 and second electrode layer 4103 can be any one or a combination of titanium nitride (TiN), titanium (Ti) and silicon-doped titanium nitride (TiSiN), and the material of capacitor dielectric layer 4102 can be at least one or a combination of zirconium oxide (ZrO2) and aluminum oxide (Al2O3).

[0103] In some embodiments, the region where the semiconductor material layer 4022 contacts the bit line structure 409 or the capacitor structure 410 also corresponds to a bit line contact layer (not shown) or a capacitor contact layer (not shown) for reducing the contact resistance at the contact interface. In some embodiments, the material of the bit line contact layer and / or the capacitor contact layer includes a metal silicide material, such as cobalt silicide (CoSi), nickel silicide (NiSi), tungsten silicide (WSi), molybdenum silicide (MoSi), titanium silicide (TiSi), tantalum silicide (TaSi), ruthenium silicide (RuSi), platinum silicide (PtSi).

[0104] In some embodiments, as shown in FIG. 14(f), which is a partial enlarged view of the region F (dashed box) in FIG. 14(e), it can be understood as a partial enlarged view of a basic memory cell structure in the semiconductor structure provided in an example embodiment of the present disclosure, which at least includes: a transistor structure, i.e., the semiconductor material layer 4022 separated by the insulating isolation layer 4024; a word line structure (not shown) connecting the gate conductive layers 4052'-1 and 4052'-2 on the third side wall adjacent to the channel region stack 4023 of the two target gate pillars located on the opposite sides of the channel region stack 4023 in the Y direction, wherein the gate conductive layers 4052'-1 and 4052'-2 respectively have a small or substantially no overlap with the projection of the lightly doped drain regions 4022b-1 and 4022b-2 on the X direction of the channel region stack 4023 on the Y direction; a bit line structure 409 and a capacitor structure 410 respectively located at the opposite ends of the semiconductor material layer 4022 in the X direction, wherein the capacitor structure 410 includes a first electrode layer 4101, a capacitor dielectric layer 4102 and a second electrode layer 4103 stacked in sequence.

[0105] The semiconductor structure provided in the present disclosure has a small overlap between the gate conductive layer on the third side wall of the target gate pillar and the lightly doped drain regions adjacent to the channel region stack, thereby reducing the influence of GIDL effect to a certain extent, and further improving the working performance of the memory device.

[0106] It should be noted that the semiconductor structure in the embodiments of the present disclosure can be used to manufacture 3D DRAM devices, and can also be used to manufacture other 3D devices that need to form metal semiconductor contacts in the stack structure, which is not limited here.

[0107] The various semiconductor structures shown in the embodiments can be used in electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be implemented by a memory, such as a dynamic random access memory (DRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a magnetic random access memory (MRAM), or a resistive random access memory (RRAM).

[0108] The above merely provides the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: Comprising: providing a substrate (101, 201, 301, 401); forming a stack structure (102, 202, 302, 402) comprising a plurality of semiconductor material layers (1022, 2022, 3022, 4022) and a plurality of insulating material layers (1021, 2021, 3021, 4021) alternately stacked on the substrate (101, 201, 301, 401); forming channel region stacks (1023, 2023, 3023, 4023) extending along a first direction perpendicular to a surface of the substrate (101, 201, 301, 401) and an initial gate pillar (105) in the stack structure (102, 202, 302, 402), the initial gate pillar (105) comprising at least an initial gate conductive layer (1052) and an initial gate dielectric layer (1051), the initial gate pillar (105) having two oppositely disposed first sidewalls respectively in contact with two adjacent channel region stacks (1023) and a second sidewall not in contact with any channel region stack (1023); removing at least the initial gate dielectric layer (1051) and the initial gate conductive layer (1052) of the initial gate pillar (105) on the second sidewall to form a target gate pillar (105', 205', 305', 405'), the target gate pillar (105', 205', 305', 405') comprising two oppositely disposed third sidewalls respectively in contact with two adjacent channel region stacks (1023, 2023, 3023, 4023) and a gate conductive layer (1052', 2052', 3052', 4052') having a first length and a gate dielectric layer (1051', 2051', 3051', 4051') having a second length on the third sidewall, the gate dielectric layer (1051', 2051', 3051', 4051') being between the gate conductive layer (1052', 2052', 3052', 4052') and the channel region stacks (1023, 2023, 3023, 4023), the first length being smaller than the second length, the first length and the second length both being in a second direction, the second direction being parallel to the surface of the substrate (101, 201, 301, 401) and the surface of the third sidewall.

2. The method of fabricating a semiconductor structure of claim 1, wherein, forming channel region stacks (1023, 2023, 3023, 4023) extending along a first direction perpendicular to a surface of the substrate (101, 201, 301, 401) in a stack structure (102, 202, 302, 402), comprising: forming a plurality of first through holes (1030) in the stack structure (102, 202, 302, 402), the first through holes (1030) extending along the first direction and penetrating the stack structure (102, 202, 302, 402), the first through holes (1030) being arranged in a third direction parallel to the surface of the substrate (101, 201, 301, 401), the stack structure (102, 202, 302, 402) between adjacent first through holes (1030) serving as the channel region stack (1023, 2023, 3023, 4023), the third direction being perpendicular to the second direction.

3. The method of fabricating a semiconductor structure of claim 2, wherein, forming an initial gate pillar (105) extending along the first direction perpendicular to the surface of the substrate (101, 201, 301, 401) in the stack structure (102, 202, 302, 402), comprising: filling the first through holes (1030) with a sacrificial material to form first sacrificial pillars (103); forming a first mask (1041) with a first opening (1040') on the stack structure (102, 202, 302, 402), etching along the first opening (1040') to form second through holes (1040) in the first sacrificial pillars (103), the second through holes (1040) penetrating the stack structure (102, 202, 302, 402), and in at least the third direction, the size of the second through holes (1040) is substantially the same as the size of the first through holes (1030); forming the initial gate dielectric layer (1051), the initial gate conductive layer (1052) and the first insulating layer (1053, 1054) in the second through holes (1040) in sequence to form the initial gate pillar (105), in the third direction, the initial gate pillar (105) has two opposite first side walls respectively in contact with two adjacent channel region stacks (1023, 2023, 3023, 4023), and in the second direction, the initial gate conductive layer (1052) on the first side wall of the initial gate pillar (105) has a third length, the third length being greater than the first length, and the third length being greater than or equal to the second length.

4. The method of fabricating a semiconductor structure of claim 3, wherein, After forming the second through holes (1040) and before forming the initial gate pillar (105) in the second through holes (1040), the manufacturing method further comprises: performing ion implantation on the channel region stack (1023, 2023, 3023, 4023) from the second through holes (1040) to form an inverted doped channel region (1022a, 2022a, 3022a, 4022a). performing ion implantation on the channel region stack (1023, 2023, 3023, 4023) from the second through holes (1040) to form an inverted doped channel region (1022a, 2022a, 3022a, 4022a).

5. The method of fabricating a semiconductor structure of claim 3, wherein, removing at least the initial gate dielectric layer (1051) and the initial gate conductive layer (1052) on the second sidewall of the initial gate pillar (105) to form a target gate pillar (105', 205', 305', 405'), comprising: forming a second mask (1061) with a second opening (1060') on the stack structure (102, 202, 302, 402), etching along the second opening (1060') to form a third through-hole (1060) in the first sacrificial pillar (103), the third through-hole (1060) penetrating the stack structure (102, 202, 302, 402) and exposing the second sidewall of the initial gate pillar (105); removing at least the initial gate dielectric layer (1051) and the initial gate conductive layer (1052) on the second sidewall of the initial gate pillar (105) by using the third through-hole (1060) to form the target gate pillar (105', 205', 305', 405'), the target gate pillar (105', 205', 305', 405') having two opposite third sidewalls in contact with two adjacent channel region stacks (1023, 2023, 3023, 4023) in the third direction.

6. The method of fabricating a semiconductor structure of claim 5, wherein, After forming the third through-hole (1060) and before removing at least the initial gate conductive layer (1052) on the second sidewall of the initial gate pillar (105) by using the third through-hole (1060), the manufacturing method further comprises: performing ion implantation on the stack structure (102, 202, 302, 402) adjacent to the channel region stack (1023, 2023, 3023, 4023) by the third through-hole (1060) to form a lightly doped drain region (1022b).

7. The method of fabricating a semiconductor structure of claim 5, wherein, After forming the target gate pillar (105', 205', 305', 405'), the manufacturing method further comprises: filling a second insulating layer (107, 2072, 307, 407) in the third through-hole (1060).

8. The method of fabricating a semiconductor structure of claim 7, wherein, After forming the target gate pillar (105', 205', 305', 405') and before filling the second insulating layer (107, 2072, 307, 407) in the third through-hole (1060), the manufacturing method further comprises: forming an auxiliary gate layer (308) in the third through-hole (1060), the auxiliary gate layer (308) being located at two opposite ends of the gate conductive layer (3052') in the second direction, the work function of the auxiliary gate layer (308) being less than the work function of the gate conductive layer (3052').

9. The method of fabricating a semiconductor structure of claim 2, wherein, After forming the target gate pillar (105', 205', 305', 405'), the manufacturing method further comprises: connecting the gate conductive layers (1052', 2052', 3052', 4052') on the two third sidewalls of the channel region stack (1023, 2023, 3023, 4023) located on two opposite sides of the channel region stack (1023, 2023, 3023, 4023) in the third direction and in contact with the channel region stack (1023, 2023, 3023, 4023) to form a word line structure.

10. The method of fabricating a semiconductor structure according to any one of claims 1-9, wherein, After forming the stack structure (102, 202, 302, 402), the manufacturing method further comprises: forming a bit line structure (409) and a capacitor structure (410), the bit line structure (409) and the capacitor structure (410) are respectively located at two opposite ends of the channel region stack (1023, 2023, 3023, 4023) in the second direction.

11. A semiconductor structure, characterized by Comprise: a substrate (101, 201, 301, 401); a stack structure (102, 202, 302, 402) formed by alternately stacking a plurality of semiconductor layers (1022, 2022, 3022, 4022) and a plurality of insulating material layers (1021, 2021, 3021, 4021) on the substrate (101, 201, 301, 401), the stack structure (102, 202, 302, 402) further comprises at least a channel region stack (1023, 2023, 3023, 4023) extending along a first direction perpendicular to the surface of the substrate (101, 201, 301, 401); a target gate pillar (105', 205', 305', 405') penetrating the stack structure (102, 202, 302, 402) along the first direction, the target gate pillar (105', 205', 305', 405') comprises two oppositely arranged third sidewalls in contact with two adjacent channel region stacks (1023, 2023, 3023, 4023), respectively, and a gate conductive layer (1052', 2052', 3052', 4052') with a first length and a gate dielectric layer (1051', 2051', 3051', 4051') with a second length on the third sidewall, the gate dielectric layer (1051', 2051', 3051', 4051') is located between the gate conductive layer (1052', 2052', 3052', 4052') and the channel region stack (1023, 2023, 3023, 4023), the first length is less than the second length, the length directions of the first length and the second length are both the second direction, and the second direction is parallel to the surface of the substrate (101, 201, 301, 401) and the surface of the third sidewall.

12. The semiconductor structure of claim 11, wherein, The channel region stack (1023, 2023, 3023, 4023) and the target gate pillar (105', 205', 305', 405') are alternately arranged along a third direction, and the third direction is parallel to the surface of the substrate (101, 201, 301, 401) and perpendicular to the second direction.

13. The semiconductor structure of claim 12, wherein, The target gate pillar (105', 205', 305', 405') further comprises a first insulating layer (1053, 1054, 2053, 2054, 3053, 3054, 4053, 4054), and the gate conductive layer (1052', 2052', 3052', 4052') on the two third sidewalls of the same target gate pillar (105', 205', 305', 405') arranged opposite along the third direction is isolated by the first insulating layer (1053, 1054, 2053, 2054, 3053, 3054, 4053, 4054).

14. The semiconductor structure of claim 11, wherein, The channel region stack (1023, 2023, 3023, 4023) further comprises a reverse type doped channel region (1022a, 2022a, 3022a, 4022a) located at a region where the channel region stack (1023, 2023, 3023, 4023) contacts the third sidewall of the target gate pillar (105', 205', 305', 405'); the stack structure (102, 202, 302, 402) further comprises a lightly doped drain region (1022b, 2022b, 3022b, 4022b) adjacent to both sides of the channel region stack (1023, 2023, 3023, 4023) arranged opposite along the second direction, and the ion doping type of the lightly doped drain region (1022b, 2022b, 3022b, 4022b) is opposite to that of the reverse type doped channel region (1022a, 2022a, 3022a, 4022a).

15. The semiconductor structure of claim 11, wherein, The semiconductor structure further comprises an auxiliary gate layer (308) located on both sides of the gate conductive layer (3052') on the third sidewall of the target gate pillar (305'), the work function of the auxiliary gate layer (308) being less than that of the gate conductive layer (3052').

16. The semiconductor structure of claim 12, wherein, The semiconductor structure further comprises: A word line structure comprising the gate conductive layer (1052', 2052', 3052', 4052') on both third sidewalls of the same channel region stack (1023, 2023, 3023, 4023) arranged opposite along the third direction and in contact with the channel region stack (1023, 2023, 3023, 4023).

17. The semiconductor structure of any of claims 11-16, wherein, The semiconductor structure further comprises: A bit line structure (409) and a capacitor structure (410), the bit line structure (409) and the capacitor structure (410) being located on both sides of the channel region stack (1023, 2023, 3023, 4023) arranged opposite along the second direction, respectively.

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