Method for manufacturing back contact cell

Abstract

The present application relates to the technical field of photovoltaics, and discloses a method for manufacturing a back contact cell, so as to improve working performance of the back contact cell. The method comprises: providing a semiconductor substrate; in the thickness direction of the semiconductor substrate, sequentially forming a first interface passivation layer and a first doped silicon layer which are stacked on a first surface of the semiconductor substrate; forming an insulating mask pattern on part of a region on the side of the first doped silicon layer facing away from the semiconductor substrate; removing parts of the stacked first interface passivation layer and first doped silicon layer exposed outside the insulating mask pattern; texturing the surface of the region of the first surface exposed outside the insulating mask pattern, and a second surface; forming a first passivation layer on the second surface of the semiconductor substrate; sequentially forming, on the first interface passivation layer and the first doped silicon layer which are stacked and on the first surface, a second interface passivation layer and a second doped silicon layer which are stacked; and selectively etching the second interface passivation layer and second doped silicon layer which are stacked.

Description

Method for manufacturing back contact cell TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaic, in particular to a method for manufacturing back contact cell. BACKGROUND

[0002] A solar cell is a device capable of converting light energy of the sun into electric energy. Specifically, when the solar cell is in working condition, sunlight is shone on the semiconductor p-n junction of the solar cell to form new hole-electron pairs. Under the action of the built-in electric field of the p-n junction, the photo-generated holes flow to the p region, and the photo-generated electrons flow to the n region. After the circuit is connected, an electric current can be generated. The solar cell in which the positive electrode and the negative electrode are both located on the back surface of the cell is a back contact cell. Compared with a double-sided contact solar cell, the front surface of the back contact cell is not blocked by the metal electrode, so that the light receiving surface side of the back contact cell has a higher light utilization rate. Therefore, the back contact cell has a higher short-circuit current and a higher photoelectric conversion efficiency, and is one of the technical directions for realizing high-efficiency crystalline silicon cells.

[0003] However, the manufacturing process of the existing back contact cell is relatively complex, which is not conducive to improving the manufacturing efficiency of the back contact cell and reducing the manufacturing cost. SUMMARY

[0004] The purpose of the present application is to provide a method for manufacturing a back contact cell, which can improve the manufacturing efficiency of the back contact cell, reduce the manufacturing cost, and improve the conversion efficiency of the back contact cell.

[0005] In order to achieve the above-mentioned purpose, the present application provides a method for manufacturing a back contact cell, which comprises the following steps: first, providing a semiconductor substrate. The semiconductor substrate has opposite first and second surfaces. Next, a first interfacial passivation layer and a first doped silicon layer are formed in sequence on the first surface of the semiconductor substrate along the thickness direction of the semiconductor substrate. Next, an insulating mask pattern is formed on a part of the region on the side of the first doped silicon layer away from the semiconductor substrate. Next, the first interfacial passivation layer and the first doped silicon layer which are not covered by the insulating mask pattern are removed. Next, the region of the first surface exposed outside the insulating mask pattern and the second surface are subjected to a texturing treatment. Next, a first passivation layer is formed on the second surface of the semiconductor substrate after the texturing treatment. Next, a second interfacial passivation layer and a second doped silicon layer are formed in sequence on the first surface along the thickness direction of the semiconductor substrate. The conductive type of the second doped silicon layer is opposite to that of the first doped silicon layer. Next, part of the second interfacial passivation layer and the second doped silicon layer located on the first interfacial passivation layer and the first doped silicon layer are removed to expose part of the first interfacial passivation layer and the first doped silicon layer.

[0006] In the technical solution, the first interface passivation layer and the first doped silicon layer are laminated, and the second interface passivation layer and the second doped silicon layer are laminated, which can form passivation contact structures, respectively. The passivation contact structures have excellent interface passivation effect, can selectively collect carriers, reduce the carrier recombination rate of the first surface of the semiconductor substrate, and improve the conversion efficiency of the back contact cell. In addition, after removing the first interface passivation layer and the first doped silicon layer which are not covered by the insulating mask pattern, the area of the first surface which is not formed with the first interface passivation layer and the first doped silicon layer is also exposed. At this time, the area of the first surface exposed outside the insulating mask pattern and the second surface can be textured at the same time, which improves the light trapping effect of the second surface. The part of the second doped silicon layer formed on the area of the first surface exposed outside the insulating mask pattern is also affected by the textured surface and has approximately the same relief topography. Therefore, the specific surface area of the second doped silicon layer away from the semiconductor substrate is increased, which is beneficial to increase the contact area between the second doped silicon layer and the conductive material (such as a transparent conductive layer or an electrode), reduce the transmission loss, and further improve the conversion efficiency of the back contact cell. At the same time, since the area of the first surface exposed outside the insulating mask pattern and the second surface can be textured at the same time, the manufacturing efficiency of the back contact cell can also be improved. In addition, the second interface passivation layer and the second doped silicon layer cover part of the first interface passivation layer and the first doped silicon layer along the thickness direction of the semiconductor substrate, which can reduce the etching amount of the second interface passivation layer and the second doped silicon layer and improve the etching efficiency. At the same time, the edges of the first interface passivation layer and the first doped silicon layer are covered with the second interface passivation layer and the second doped silicon layer, which can prevent the etchant from affecting the edge part of the first interface passivation layer and the first doped silicon layer and improve the collection efficiency of the carriers of the edge part of the first interface passivation layer and the first doped silicon layer. In addition, no isolation groove is arranged between the first interface passivation layer, the first doped silicon layer, the second interface passivation layer, and the second doped silicon layer, and the contact area of the first interface passivation layer, the first doped silicon layer, and the semiconductor substrate and the contact area of the second interface passivation layer, the second doped silicon layer, and the semiconductor substrate can be maximized, which can improve the utilization rate of the semiconductor substrate and further improve the photoelectric conversion efficiency.

[0007] As a possible implementation scheme, the texturing of the area of the first surface exposed outside the insulating mask pattern and the second surface includes: texturing the area of the first surface exposed outside the insulating mask pattern and the second surface, and removing the insulating mask pattern at the same time. Alternatively, the texturing of the area of the first surface exposed outside the insulating mask pattern and the second surface includes: texturing the area of the first surface exposed outside the insulating mask pattern and the second surface; and retaining the insulating mask pattern after the texturing.

[0008] In the technical solution, after the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern are removed, the insulating mask pattern, the area of the first surface of the semiconductor substrate exposed outside the insulating mask pattern and the second surface are all exposed. Based on this, when the texturing treatment is performed, the texturing liquid will not only contact the area of the first surface of the semiconductor substrate exposed outside the insulating mask pattern and the second surface, but also contact the insulating mask pattern. At this time, in the manufacturing method provided by the application, the insulating mask pattern can be removed at the same time when the texturing treatment is performed, or can be removed after the texturing, or can be retained after the texturing treatment. It can be seen that whether the insulating mask pattern is retained after the texturing treatment has two optional examples, which is helpful to reduce the material limitation of the insulating mask pattern, and is also helpful to improve the applicability of the manufacturing method provided by the application in different application scenarios. When the insulating mask pattern is retained, it is helpful to separate the first doped silicon layer and the second doped silicon layer with the opposite conduction type, prevent electric leakage and reduce the forward electric leakage loss of the back contact cell. When the insulating mask pattern is removed, a diode structure with a high reverse breakdown voltage can be formed between the first doped silicon layer and the second doped silicon layer with the opposite conduction type, thereby reducing the hot spot risk of the back contact cell in an installation environment with more shielding objects such as dust.

[0009] As a possible implementation scheme, the sequentially forming the first interface passivation layer and the first doped silicon layer on the first surface of the semiconductor substrate comprises: simultaneously forming the first interface passivation layer and the first doped silicon layer on the first surface of the semiconductor substrate, and forming a first doped silicon glass layer on the side of the first doped silicon layer away from the semiconductor substrate; and the forming the insulating mask pattern on the partial area of the side of the first doped silicon layer away from the semiconductor substrate comprises: patterning the first doped silicon glass layer to form the insulating mask pattern. In this case, the first doped silicon glass layer can be formed at the same time as the first doped silicon layer, without the need to additionally use a deposition process to form a corresponding insulating mask pattern for forming the insulating mask pattern, which is helpful to simplify the manufacturing process of the back contact cell and improve the manufacturing efficiency of the back contact cell.

[0010] As a possible implementation scheme, the sequentially forming the first interface passivation layer and the first doped silicon layer on the first surface of the semiconductor substrate comprises: simultaneously forming the first interface passivation layer and the first doped silicon layer on the first surface of the semiconductor substrate, and forming a first doped silicon glass layer on the side of the first doped silicon layer away from the semiconductor substrate; and the forming the insulating mask pattern on the partial area of the side of the first doped silicon layer away from the semiconductor substrate comprises: forming an insulating layer on the side of the first doped silicon glass layer away from the semiconductor substrate; and patterning the first doped silicon glass layer and the insulating layer to form the insulating mask pattern.

[0011] In the case of adopting the technical scheme, compared with the insulating mask pattern of the single-layer structure, the insulating mask pattern in this case not only includes the first doped silicon glass layer after the patterning treatment, but also includes the insulating layer after the patterning treatment, which is conducive to improving the protection effect of the insulating mask pattern. Secondly, if the insulating mask pattern including the first doped silicon glass layer and the insulating layer is retained after the texturing treatment, the insulating mask pattern has a high insulating isolation effect, which can further reduce the risk of electric leakage of the overlapping part of the second doped silicon layer and the first doped silicon layer along the thickness direction of the semiconductor substrate, and further improve the conversion efficiency of the back contact cell.

[0012] As a possible implementation scheme, the first interface passivation layer and the first doped silicon layer are formed on the first surface of the semiconductor substrate in sequence, including: forming the first interface passivation layer and the first doped silicon layer on the first surface of the semiconductor substrate in sequence, and forming the first doped silicon glass layer on the side of the first doped silicon layer away from the semiconductor substrate; and forming the insulating mask pattern on the partial area of the side of the first doped silicon layer away from the semiconductor substrate includes: removing the first doped silicon glass layer; forming the insulating layer on the side of the first doped silicon layer away from the semiconductor substrate; and patterning the insulating layer to form the insulating mask pattern.

[0013] In the case of adopting the technical scheme, the insulating mask pattern can be directly formed on the side of the first doped silicon glass layer away from the semiconductor substrate. Since the insulating material (such as silicon oxide, aluminum oxide or silicon nitride) for manufacturing the insulating mask pattern may have a passivation effect, it not only has a mask protection and insulating effect, but also can directly perform passivation treatment on the side of the first doped silicon layer away from the semiconductor substrate, which is conducive to reducing the surface defects of the side of the first doped silicon layer away from the semiconductor substrate, and further improving the conversion efficiency of the back contact cell.

[0014] As a possible implementation scheme, the first passivation layer is formed on the second surface of the semiconductor substrate after the texturing treatment, including: forming the first passivation layer on the second surface of the semiconductor substrate at the same time as forming the first passivation layer on the first surface of the semiconductor substrate. Next, the first passivation layer on the first surface of the semiconductor substrate is removed.

[0015] In the case of adopting the technical scheme, the first passivation layer is formed on the second surface of the semiconductor substrate at the same time as forming the first passivation layer on the first surface. The presence of the first passivation layer on the first surface can perform passivation treatment on the side of the first doped silicon layer away from the semiconductor substrate during subsequent annealing treatment, reduce the surface defects of the side of the first doped silicon layer away from the semiconductor substrate, and also prevent the occurrence of problems such as hydrogen escaping affecting the passivation effect of itself due to the exposure of the side of the first doped silicon layer away from the semiconductor substrate after the insulating mask pattern is removed during subsequent annealing treatment, thereby ensuring that the back contact cell has a high conversion efficiency.

[0016] As a possible implementation, the first passivation layer comprises an intrinsic silicon passivation layer. In this case, the intrinsic silicon passivation layer has a higher hydrogen content, which can make the first passivation layer have a higher passivation effect on the second surface of the semiconductor substrate, further improving the conversion efficiency of the back contact cell manufactured.

[0017] As a possible implementation, after sequentially forming the laminated second interface passivation layer and the second doped silicon layer on the first surface, before removing the part of the second interface passivation layer and the second doped silicon layer on the first interface passivation layer and the first doped silicon layer, the method for manufacturing the back contact cell further comprises: forming an anti-reflection layer on the side of the first passivation layer away from the semiconductor substrate. In this case, the reflectivity of the manufactured back contact cell on the second surface side is reduced, further improving the conversion efficiency of the back contact cell.

[0018] As a possible implementation, after the area of the first surface exposed outside the insulating mask pattern and the second surface are subjected to texturing treatment, and before the first passivation layer is formed on the second surface of the semiconductor substrate after the texturing treatment, the laminated second interface passivation layer and the second doped silicon layer are sequentially formed on the first surface.

[0019] In the case of using the above technical solutions, the formation sequence of the laminated second interface passivation layer and the second doped silicon layer can not only be set after the first passivation layer is formed, but also be set after the texturing treatment and before the first passivation layer is formed, which provides another optional example for the manufacturing method provided by the present application, and is conducive to improving the applicability of the manufacturing method provided by the present application in different application scenarios. At the same time, when the first passivation layer is formed on the second surface of the semiconductor substrate, the first passivation layer can be plated around the side surface of the semiconductor substrate and at least part of the area of the first surface. Based on this, when the formation sequence of the laminated second interface passivation layer and the second doped silicon layer is set after the texturing treatment and before the first passivation layer is formed, it is no longer necessary to remove at least the part of the first passivation layer plated on the side of the first surface before forming the laminated second interface passivation layer and the second doped silicon layer, thereby reducing the process steps. Whether to remove the first passivation layer plated on the side of the first surface after the first passivation layer is formed can be determined according to actual needs, reducing the manufacturing requirements. Moreover, in this case, the corresponding structure on the side of the first surface can be made first, and then the corresponding film layers (the first passivation layer and the anti-reflection layer) on the side of the second surface are made, reducing the number of turning over and reducing the risk of damage.

[0020] As a possible implementation, the first passivation layer includes a second doped silicon glass layer, and the dopant in the second doped silicon glass layer is of the same conductivity type as the first doped silicon layer.

[0021] In the above technical solution, compared with the intrinsic silicon passivation layer, the second doped silicon glass layer has higher light transmission characteristics, so compared with the first passivation layer including the intrinsic silicon passivation layer, when the first passivation layer includes the second doped silicon glass layer, the parasitic absorption of the first passivation layer can be reduced, which is conducive to improving the utilization rate of light by the back contact cell. In addition, the second doped silicon glass layer is also doped with a dopant of the same conductivity type as the first doped silicon layer, so that the first passivation layer can not only chemically passivate the second side of the semiconductor substrate, but also field passivate the second side of the semiconductor substrate, which reduces the carrier recombination rate of the second side, and also helps to improve the carrier collection efficiency of the first doped silicon layer and the second doped silicon layer. Compared with the need for separate deposition, the second doped silicon glass layer can be formed by a diffusion process, which simplifies the manufacturing difficulty of the first passivation layer.

[0022] As a possible implementation, forming the first passivation layer on the second surface of the semiconductor substrate after the texturing process includes: forming the first passivation layer and the anti-reflective layer which are sequentially stacked in the thickness direction of the semiconductor substrate on the second surface of the semiconductor substrate. In this case, the reflectivity of the back contact cell on the second side is reduced, and the conversion efficiency of the back contact cell is further improved.

[0023] As a possible implementation, after removing the part of the second interface passivation layer and the second doped silicon layer on the first interface passivation layer and the first doped silicon layer, the manufacturing method of the back contact cell further includes: forming a transparent conductive layer covering the first doped silicon layer and the second doped silicon layer away from the semiconductor substrate. The transparent conductive layer has a through isolation groove formed therein to disconnect the part of the transparent conductive layer corresponding to the first doped silicon layer from the part of the transparent conductive layer corresponding to the second doped silicon layer. Next, a first electrode is formed on the part of the transparent conductive layer corresponding to the first doped silicon layer, and a second electrode is formed on the part of the transparent conductive layer corresponding to the second doped silicon layer. In this case, the transparent conductive layer has high carrier transport characteristics, which is conducive to improving the carrier collection efficiency. In addition, the transparent conductive layer is arranged between the metal electrode and the semiconductor layer, which is conducive to reducing the contact barrier and reducing the contact resistance.

[0024] As a possible implementation, the thickness of the edge portion of the transparent conductive layer adjacent to the isolation groove gradually decreases in the direction close to the isolation groove. In this case, the thickness of the transparent conductive layer close to both sides of the isolation groove is small, and the thickness of the two parts of the transparent conductive layer for transmitting carriers of opposite types is small (the facing area is also small), which is beneficial to reduce the risk of electric leakage and improve the electrical reliability of the back contact cell. Moreover, such arrangement is beneficial to the stress release between other structures in the back contact cell and the transparent conductive layer, avoiding the edge of the transparent conductive layer from being prone to edge collapse or falling off due to excessive stress during the forming process, and improving the structural reliability of the manufactured back contact cell.

[0025] As a possible implementation, the second interface passivation layer and the second doped silicon layer stacked in sequence, and the transparent conductive layer arranged on the second doped silicon layer, all cover the part of the first interface passivation layer and the first doped silicon layer away from the semiconductor substrate. And / or, the part of the first interface passivation layer, the first doped silicon layer, the second interface passivation layer and the second doped silicon layer stacked along the thickness direction of the semiconductor substrate is an overlapping area; at least part of the overlapping area is a reverse leakage area, and in the reverse leakage area, the second doped silicon layer is electrically connected to the first doped silicon layer through the second interface passivation layer.

[0026] In the case of adopting the above technical solution, in the reverse leakage area, the second doped silicon layer can be electrically connected to the first doped silicon layer with opposite conductivity type through the second interface passivation layer to form a built-in diode structure with lower reverse breakdown voltage, thereby reducing the hot spot risk of the back contact cell.

[0027] As a possible implementation, the thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 300 nm.

[0028] In the case of adopting the above technical solution, the presence of the transparent conductive layer can improve the collection efficiency of carriers, and also leaves a margin for thinning the first doped silicon layer. In other words, without reducing the carrier collection efficiency, the thickness of the first doped silicon layer can be appropriately reduced due to the presence of the transparent conductive layer. Based on this, when the thickness of the first doped silicon layer is within the above range, the thickness of the first doped silicon layer is small, which is beneficial to reduce the parasitic absorption of itself, and further improve the working efficiency of the back contact cell. In addition, since the thickness of the first doped silicon layer is small, the forming time of the first doped silicon layer can be reduced, and the production efficiency is improved.

[0029] As a possible implementation, the width of the opening area of the second interface passivation layer and the second doped silicon layer is greater than or equal to 40 μm and less than or equal to 400 μm.

[0030] In the technical scheme, the first doped silicon layer is electrically connected with the corresponding conductive material through the opening region arranged in the second interface passivation layer and the second doped silicon layer, so as to guide the carriers collected by the first doped silicon layer out. The carriers transmitted by the conductive material electrically connected with the first doped silicon layer are opposite to the conductive type of the second doped silicon layer. Compared with the prior art, the width of the opening region for exposing the first doped silicon layer is larger in the back contact cell manufactured by the method, which is beneficial to the corresponding conductive material electrically connected with the first doped silicon layer having a larger forming range under the premise of preventing short circuit, thereby increasing the contact area between the first doped silicon layer and the corresponding conductive material, reducing transmission loss, and improving the electrical reliability of the manufactured back contact cell. In addition, when the width of the opening region is less than or equal to 400 μm, the second interface passivation layer and the second doped silicon layer have more remaining parts after the opening operation, which reduces the etching amount and ensures that the second interface passivation layer and the second doped silicon layer have a certain area ratio on the first side, thereby ensuring that the second doped silicon layer has a higher carrier collection efficiency.

[0031] As a possible implementation, in the first side, the region surface where the first interface passivation layer and the first doped silicon layer are arranged has a tower base-shaped texture structure, and the tower base-shaped texture structure has a bottom surface and a side wall. The thickness of the first interface passivation layer on the bottom surface of the tower base-shaped texture structure is less than the thickness of the first interface passivation layer on the side wall of the tower base-shaped texture structure.

[0032] In the technical scheme, the bottom surface of the tower base-shaped texture structure and the side surface of the tower base-shaped texture structure have different crystal orientations. Specifically, the bottom surface of the tower base-shaped texture structure is

[0110] crystal orientation, and the number of dangling bonds on the surface of the

[0110] crystal orientation is relatively small. The side surface of the tower base-shaped texture structure is

[0111] crystal orientation, and the number of dangling bonds on the

[0111] crystal orientation is relatively large. When the thickness of the first interface passivation layer on the bottom surface of the tower base-shaped texture structure is less than the thickness of the first interface passivation layer on the side wall of the tower base-shaped texture structure, the part of the first interface passivation layer on the side wall of the tower base-shaped texture structure has a relatively high passivation effect, which meets the requirement of the side surface of the tower base-shaped texture structure for high passivation effect, reduces the carrier recombination rate of the side surface of the tower base-shaped texture structure, and further improves the working efficiency of the back contact cell.

[0033] As a possible implementation, the thickness of the first interface passivation layer on the bottom surface of the tower-base-shaped texture structure is greater than or equal to 0.5 nm and less than or equal to 1.5 nm. In this case, the thickness of the first interface passivation layer on the bottom surface of the tower-base-shaped texture structure within the above range is conducive to preventing the passivation effect of this part on the semiconductor substrate from being low due to the small thickness of the first interface passivation layer on the bottom surface of the tower-base-shaped texture structure, and is also conducive to preventing the tunneling resistance of this part from being high due to the large thickness of the first interface passivation layer on the bottom surface of the tower-base-shaped texture structure, so as to balance the passivation effect and the tunneling resistance of the part of the first interface passivation layer on the bottom surface of the tower-base-shaped texture structure, thereby reducing the carrier recombination rate of the side surface of the tower-base-shaped texture structure while ensuring that the first doped silicon layer has a high carrier collection efficiency and reduces transmission loss.

[0034] As a possible implementation, the thickness of the first interface passivation layer on the side wall of the tower-base-shaped texture structure is greater than or equal to 0.5 nm and less than or equal to 2 nm. In this case, the thickness of the first interface passivation layer on the side wall of the tower-base-shaped texture structure within the above range is conducive to preventing the passivation effect of this part from being low due to the small thickness, and is also conducive to preventing the tunneling resistance of this part from being high due to the large thickness of the first interface passivation layer on the side wall of the tower-base-shaped texture structure, so as to balance the passivation effect and the tunneling resistance of the part of the first interface passivation layer on the side wall of the tower-base-shaped texture structure, thereby reducing the carrier recombination rate of the side surface of the tower-base-shaped texture structure while ensuring that the first doped silicon layer has a high carrier collection efficiency and reduces transmission loss.

[0035] As a possible implementation, the thickness of the second interface passivation layer is greater than or equal to 3 nm and less than or equal to 16 nm. In this case, the thickness of the second interface passivation layer is large, which is conducive to enhancing the isolation effect of the second interface passivation layer between the first doped silicon layer and the second doped silicon layer and reducing the risk of electric leakage. Moreover, it can also prevent the contact resistance from being large due to the excessively large thickness of the second interface passivation layer and reduce transmission loss.

[0036] As a possible implementation, the first doped silicon layer is a doped polysilicon layer. The back contact cell further comprises an amorphous silicon layer disposed on the side of the first doped silicon layer away from the semiconductor substrate. In this case, the amorphous silicon layer can passivate the side of the first doped silicon layer away from the semiconductor substrate, reduce the number of surface defects on the side of the first doped silicon layer away from the semiconductor substrate, and improve the conversion efficiency of the back contact cell. In addition, since the work function difference between the amorphous silicon layer and the transparent conductive layer is smaller than the work function difference between the doped polysilicon layer and the transparent conductive layer, i.e., the contact potential barrier between the amorphous silicon layer and the transparent conductive layer is smaller than the contact potential barrier between the doped polysilicon layer and the transparent conductive layer, the contact resistance between the amorphous silicon layer and the transparent conductive layer is smaller than the contact resistance between the doped polysilicon layer and the transparent conductive layer. Therefore, compared with the first doped silicon layer directly contacting the transparent conductive layer, disposing the amorphous silicon layer on the side of the first doped silicon layer away from the semiconductor substrate can achieve more reasonable band matching, reduce the contact resistance, so that the back contact cell can effectively convert sunlight into electrical energy, and improve the photoelectric conversion efficiency of the back contact cell.

[0037] As a possible implementation, removing the part of the second interface passivation layer and the second doped silicon layer on the first interface passivation layer and the first doped silicon layer comprises: removing the part of the second interface passivation layer and the second doped silicon layer on the first interface passivation layer and the first doped silicon layer by laser, and processing the edge part of the opening area of the second doped silicon layer by laser to form a hole structure in the edge part of the second doped silicon layer.

[0038] In the case of using the above technical solution, it can be understood that the hole structure is a hollow structure, so when the hole structure is formed in the edge part of the second doped silicon layer, the risk of electric leakage between the edge part of the second doped silicon layer and the first doped silicon layer can be reduced, and the electrical reliability of the back contact cell can be improved. In addition, the existence of the hole structure can also increase the degree of fluctuation of the edge part of the laminated second interface passivation layer and second doped silicon layer, thereby enhancing the light trapping effect of this part, which is beneficial to improve the double-sided rate of the back contact cell.

[0039] As a possible implementation, the first surface comprises a first region and a second region. The second region comprises a groove. The first interface passivation layer and the first doped silicon layer are located in the first region. The second interface passivation layer and the second doped silicon layer are located in the second region, and the second region covers part of the first interface passivation layer and the first doped silicon layer along the extension to the first region. The surface of the first region is a polished surface, and the bottom surface of the groove is a textured surface. The thickness of the second doped silicon layer on the textured surface is smaller than the thickness of the second doped silicon layer on the polished surface.

[0040] In the technical solution, the recess is arranged, so that the surface of the second region is staggered with the surface of the first region along the thickness direction of the semiconductor substrate, thereby facilitating at least partial staggering of the second interface passivation layer and the second doped silicon layer on the second region with the first interface passivation layer and the first doped silicon layer on the first region, and reducing the risk of leakage. In addition, compared with the polished surface, the rough surface has a larger specific surface area. In the same formation range, the contact area between the second doped silicon layer on the rough surface and the semiconductor substrate is larger, and the contact area between the second doped silicon layer on the polished surface and the semiconductor substrate is smaller. Based on this, when the thickness of the second doped silicon layer on the rough surface is small, after ensuring that the second doped silicon layer on the rough surface has sufficient contact area with the semiconductor substrate, the thickness of the second doped silicon layer on the rough surface can be reduced, thereby ensuring a high carrier collection efficiency while reducing the use of materials for manufacturing the second doped silicon layer on the rough surface. In addition, the thickness of the second doped silicon layer on the polished surface is large, so that the second doped silicon layer on the polished surface has a high field passivation effect and reduces carrier recombination. In this case, the thickness difference between different parts of the second doped silicon layer can be set according to the surface roughness of the first region and the second region and actual requirements, which is not limited here.

[0041] As a possible implementation, the first surface includes a first region and a second region. The second region includes a recess. The surface of the first region is a polished surface, and the bottom surface of the recess is a rough surface. The first interface passivation layer and the first doped silicon layer are located on the first region. The second interface passivation layer and the second doped silicon layer are located on the second region and extend from the second region to cover part of the first interface passivation layer and the first doped silicon layer. The distance from the surface of the first region to the bottom surface of the recess of the semiconductor substrate is greater than or equal to 2 μm and less than or equal to 8 μm.

[0042] In the technical solution, the distance between the surface of the semiconductor substrate in the first region and the bottom surface of the groove is small, so that the first doped silicon layer and the second doped silicon layer are also small in the thickness direction of the semiconductor substrate, and the risk of leakage between the two is low. In the process of texturing the bottom surface of the groove, the semiconductor substrate needs to be etched, so the distance between the surface of the semiconductor substrate in the first region and the bottom surface of the groove also affects the size of the textured structure on the bottom surface. Therefore, the distance between the surface of the semiconductor substrate in the first region and the bottom surface of the groove is within the range, so that the size of the bottom surface of the groove and the textured structure formed on the second surface is small, the second surface has a high light trapping effect, and the specific surface area of the second doped silicon layer away from the semiconductor substrate is increased, further reducing the contact loss between the second doped silicon layer and the corresponding conductive material. In addition, the etching depth of the semiconductor substrate at the groove is large when the distance between the surface of the semiconductor substrate in the first region and the bottom surface of the groove is large, so that the semiconductor substrate has a large light absorption depth, and the back contact cell has a high conversion efficiency.

[0043] As a possible implementation, the first surface includes a first region and a second region; the second region includes a groove. The first interface passivation layer and the first doped silicon layer are located in the first region; the second interface passivation layer and the second doped silicon layer are located in the second region and extend from the second region to the first region to cover part of the first interface passivation layer and the first doped silicon layer. The second doped silicon layer is a doped amorphous silicon layer. After the second interface passivation layer and the second doped silicon layer are sequentially formed on the first surface in the thickness direction of the semiconductor substrate, the manufacturing method of the back contact cell further includes: performing laser irradiation on the second doped silicon layer on the bottom surface of the groove to perform crystallization treatment on the second doped silicon layer.

[0044] In the technical solution, the second doped silicon layer is a doped amorphous silicon layer, which is located in the second region including the groove. The bottom surface of the groove is textured, and the textured structure has a reflection effect on laser. When the second doped silicon layer on the bottom surface of the groove is irradiated by laser, the textured structure reflects the laser, so that the second doped silicon layer is crystallized by heat, the crystallization degree of the second doped silicon layer is improved, the conductive performance of the second doped silicon layer is improved, the contact resistance between the second doped silicon layer and the corresponding conductive material is reduced, and the transmission loss is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0045] The drawings described herein are used to provide further understanding of the present application, and form a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation on the present application. In the drawings:

[0046] Fig. 1 is a flow chart of a manufacturing method of a back contact cell according to an embodiment of the present application;

[0047] Fig. 2 is a schematic diagram of a result of a back contact cell in a manufacturing process according to an embodiment of the present application;

[0048] Fig. 3 is a schematic diagram of a result of a back contact cell in a manufacturing process according to an embodiment of the present application;

[0049] Fig. 4 is a schematic diagram of a result of a back contact cell in a manufacturing process according to an embodiment of the present application;

[0050] Fig. 5 is a schematic diagram of a result of a back contact cell in a manufacturing process according to an embodiment of the present application;

[0051] Fig. 6 is a schematic diagram of a result of a back contact cell in a manufacturing process according to an embodiment of the present application;

[0052] Fig. 7 is a schematic diagram of a result of a back contact cell in a manufacturing process according to an embodiment of the present application;

[0053] Fig. 8 is a schematic diagram of a result of a back contact cell in a manufacturing process according to an embodiment of the present application;

[0054] Fig. 9 is a schematic diagram of a result of a back contact cell in a manufacturing process according to an embodiment of the present application;

[0055] Fig. 10 is a schematic diagram of a result of a back contact cell in a manufacturing process according to an embodiment of the present application;

[0056] Fig. 11 is a schematic diagram of a result of a back contact cell in a manufacturing process according to an embodiment of the present application;

[0057] Fig. 12 is a schematic diagram of a result of a back contact cell in a manufacturing process according to an embodiment of the present application;

[0058] Fig. 13 is a schematic diagram of a result of a back contact cell in a manufacturing process according to an embodiment of the present application;

[0059] Fig. 14 is a schematic diagram of a result of a back contact cell in a manufacturing process according to an embodiment of the present application;

[0060] Fig. 15 is a schematic diagram of a result of a back contact cell in a manufacturing process according to an embodiment of the present application;

[0061] FIG. 16 is a schematic diagram of a result of a back contact cell formed by a manufacturing method provided by an embodiment of the present application in a manufacturing process;

[0062] FIG. 17 is a schematic diagram of a result of a back contact cell formed by a manufacturing method provided by an embodiment of the present application in a manufacturing process;

[0063] FIG. 18 is a schematic diagram of a result of a back contact cell formed by a manufacturing method provided by an embodiment of the present application in a manufacturing process;

[0064] FIG. 19 is a schematic diagram of a result of a back contact cell formed by a manufacturing method provided by an embodiment of the present application in a manufacturing process;

[0065] FIG. 20 is a schematic diagram of a result of a back contact cell formed by a manufacturing method provided by an embodiment of the present application in a manufacturing process;

[0066] FIG. 21 is a schematic diagram of a result of a back contact cell formed by a manufacturing method provided by an embodiment of the present application in a manufacturing process;

[0067] FIG. 22 is a schematic diagram of a result of a back contact cell formed by a manufacturing method provided by an embodiment of the present application in a manufacturing process;

[0068] FIG. 23 is a schematic diagram of a result of a back contact cell formed by a manufacturing method provided by an embodiment of the present application in a manufacturing process;

[0069] FIG. 24 is a schematic diagram of a result of a back contact cell formed by a manufacturing method provided by an embodiment of the present application in a manufacturing process;

[0070] FIG. 25 is a schematic diagram of a result of a back contact cell formed by a manufacturing method provided by an embodiment of the present application in a manufacturing process;

[0071] FIG. 26 is a schematic diagram of a result of a back contact cell formed by a manufacturing method provided by an embodiment of the present application in a manufacturing process;

[0072] FIG. 27 is a schematic diagram of a result of a back contact cell formed by a manufacturing method provided by an embodiment of the present application in a manufacturing process;

[0073] FIG. 28 is a schematic diagram of a result of a back contact cell formed by a manufacturing method provided by an embodiment of the present application in a manufacturing process;

[0074] FIG. 29 is a schematic diagram of a result of a back contact cell formed by a manufacturing method provided by an embodiment of the present application in a manufacturing process;

[0075] Figure 30 is a schematic diagram of the results of a back contact cell formed using the manufacturing method provided by embodiments of the application during the manufacturing process;

[0076] Figure 31 is a schematic diagram of the results of a back contact cell formed using the manufacturing method provided by embodiments of the application during the manufacturing process;

[0077] Figure 32 is a schematic diagram of the results of a back contact cell formed using the manufacturing method provided by embodiments of the application during the manufacturing process;

[0078] Figure 33 is a schematic diagram of the results of a back contact cell formed using the manufacturing method provided by embodiments of the application during the manufacturing process;

[0079] Figure 34 is a schematic diagram of the results of a back contact cell formed using the manufacturing method provided by embodiments of the application during the manufacturing process;

[0080] Figure 35 is a schematic diagram of the results of a back contact cell formed using the manufacturing method provided by embodiments of the application during the manufacturing process;

[0081] Figure 36 is a schematic diagram of the results of a back contact cell formed using the manufacturing method provided by embodiments of the application during the manufacturing process;

[0082] Figure 37 is a schematic diagram of the results of a back contact cell formed using the manufacturing method provided by embodiments of the application during the manufacturing process;

[0083] Figure 38 is a schematic diagram of the results of a back contact cell formed using the manufacturing method provided by embodiments of the application during the manufacturing process;

[0084] Figure 39 is a schematic diagram of the results of a back contact cell formed using the manufacturing method provided by embodiments of the application during the manufacturing process;

[0085] Figure 40 is a schematic diagram of the results of a back contact cell formed using the manufacturing method provided by embodiments of the application during the manufacturing process;

[0086] Figure 41 is a schematic diagram of the results of a back contact cell formed using the manufacturing method provided by embodiments of the application during the manufacturing process;

[0087] Figure 42 is a schematic diagram of the results of a back contact cell formed using the manufacturing method provided by embodiments of the application during the manufacturing process;

[0088] Figure 43 is a schematic diagram of the results of a back contact cell formed using the manufacturing method provided by embodiments of the application during the manufacturing process;

[0089] Figure 44 is a schematic diagram of the result of a back contact cell formed by the manufacturing method provided by the embodiments of the present application in the manufacturing process;

[0090] Figure 45 is a schematic diagram of the result of a back contact cell formed by the manufacturing method provided by the embodiments of the present application in the manufacturing process;

[0091] Figure 46 is a schematic diagram of the result of a back contact cell formed by the manufacturing method provided by the embodiments of the present application in the manufacturing process.

[0092] Reference signs: 11 is a semiconductor substrate, 12 is a first interface passivation layer, 13 is a first doped silicon layer, 14 is a first doped silicon glass layer, 15 is an insulating mask pattern, 16 is an insulating layer, 17 is a first passivation layer, 18 is an anti-reflection layer, 19 is a second interface passivation layer, 20 is a second doped silicon layer, 21 is a transparent conductive layer, 22 is an isolation groove, 23 is a first region, and 24 is a second region. DETAILED DESCRIPTION

[0093] Hereinafter, the embodiments of the present application will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present application. Also, in the following description, the description of well-known structures and techniques is omitted to avoid obscuring the concept of the present application.

[0094] In the drawings, various structural schematic diagrams according to the embodiments of the present application are shown. These diagrams are not drawn to scale, in which some details are exaggerated and some are omitted for the sake of clarity. The shapes of various regions, layers, and the relative sizes and positional relationships between them shown in the diagrams are merely exemplary, and in actuality, they can deviate due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0095] In the context of the present application, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it can be "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved, technical solutions and beneficial effects of the present application more clear, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application and not to limit the present application.

[0096] In addition, the terms "first", "second", "third", "fourth" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or a specific number of the technical features indicated. Therefore, the features defined as "first", "second", "third", "fourth" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0097] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0098] A solar cell is a device capable of converting solar light energy into electrical energy. Specifically, when the solar cell is in working condition, sunlight shines on the semiconductor p-n junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field in the p-n junction, the photo-generated holes flow to the p region, and the photo-generated electrons flow to the n region. After the circuit is connected, current can be generated. Among them, the solar cell with positive electrode and negative electrode on the back of the cell is a back contact cell. Compared with the double-sided contact solar cell, the front side of the back contact cell has no metal electrode shielding, so that the light side of the back contact cell has higher light utilization, and therefore the back contact cell has higher short-circuit current and photoelectric conversion efficiency. It is one of the technical directions to realize high-efficiency crystalline silicon cells at present.

[0099] However, the manufacturing process of the existing back contact cell is relatively complex, which is not conducive to improving the manufacturing efficiency of the back contact cell and reducing the manufacturing cost.

[0100] To solve the above technical problems, the embodiment of the present application provides a manufacturing method of a back contact battery. As shown in FIG. 1, the manufacturing method of the back contact battery provided by the embodiment of the present application comprises the following steps: first, a semiconductor substrate is provided. The semiconductor substrate has opposite first and second surfaces. Next, a first interface passivation layer and a first doped silicon layer are formed in sequence on the first surface of the semiconductor substrate along the thickness direction of the semiconductor substrate. Next, an insulating mask pattern is formed on a partial region of the first doped silicon layer away from the semiconductor substrate. Next, the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern are removed. Next, the region of the first surface not covered by the insulating mask pattern and the second surface are subjected to texturing treatment. Next, a first passivation layer is formed on the second surface of the semiconductor substrate after the texturing treatment. Next, a second interface passivation layer and a second doped silicon layer are formed in sequence on the first surface along the thickness direction of the semiconductor substrate. The conductive type of the second doped silicon layer is opposite to that of the first doped silicon layer. Next, a part of the second interface passivation layer and the second doped silicon layer on the first interface passivation layer and the first doped silicon layer are removed to expose a part of the first interface passivation layer and the first doped silicon layer.

[0101] It should be noted that the embodiment of the present application provides a manufacturing method, and the execution sequence of the operation steps of forming the first passivation layer on the second surface of the semiconductor substrate after the texturing treatment and the operation steps of forming the second interface passivation layer and the second doped silicon layer in sequence on the first surface along the thickness direction of the semiconductor substrate is not specifically limited. The first passivation layer can be formed on the second surface of the semiconductor substrate after the texturing treatment, and then the second interface passivation layer and the second doped silicon layer are formed in sequence on the first surface. Alternatively, the second interface passivation layer and the second doped silicon layer can be formed in sequence on the first surface, and then the first passivation layer is formed on the second surface of the semiconductor substrate after the texturing treatment.

[0102] In the technical solution, the first interface passivation layer and the first doped silicon layer, and the second interface passivation layer and the second doped silicon layer are laminated to form a passivation contact structure, which has excellent interface passivation effect and can selectively collect carriers, reduce the carrier recombination rate of the first surface of the semiconductor substrate, and improve the conversion efficiency of the back contact cell. In addition, after removing the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern, the area of the first surface not covered by the first interface passivation layer and the first doped silicon layer is also exposed. At this time, the area of the first surface exposed outside the insulating mask pattern and the second surface can be subjected to the texturing treatment at the same time, which improves the light trapping effect of the second surface, and the part of the second doped silicon layer formed on the area of the first surface exposed outside the insulating mask pattern also has a rough morphology affected by the textured surface, which increases the specific surface area of the second doped silicon layer away from the semiconductor substrate, and thus is beneficial to increasing the contact area between the second doped silicon layer and the conductive material (such as a transparent conductive layer or an electrode), reducing the transmission loss, and further improving the conversion efficiency of the back contact cell. At the same time, since the area of the first surface exposed outside the insulating mask pattern and the second surface can be subjected to the texturing treatment at the same time, the manufacturing efficiency of the back contact cell can also be improved. Moreover, the second interface passivation layer and the second doped silicon layer cover part of the first interface passivation layer and the first doped silicon layer along the thickness direction of the semiconductor substrate, which can reduce the etching amount of the second interface passivation layer and the second doped silicon layer, and improve the etching capacity. At the same time, the edges of the first interface passivation layer and the first doped silicon layer are covered by the second interface passivation layer and the second doped silicon layer, which can prevent the etchant from affecting the edge part of the first interface passivation layer and the first doped silicon layer, and improve the collection efficiency of the carriers by the edge part of the first interface passivation layer and the first doped silicon layer. In addition, no isolation groove is arranged between the first interface passivation layer, the first doped silicon layer, the second interface passivation layer, and the second doped silicon layer, so that the contact area of the first interface passivation layer, the first doped silicon layer, and the semiconductor substrate, and the contact area of the second interface passivation layer, the second doped silicon layer, and the semiconductor substrate can be maximized, thereby improving the utilization rate of the semiconductor substrate and further improving the photoelectric conversion efficiency.

[0103] Hereinafter, the manufacturing process of the back contact cell provided in the present application will be described according to the cross-sectional views of the operations shown in FIGS. 2 to 38, and divided into various embodiments:

[0104] Embodiment One

[0105] Step 1: Provide a semiconductor substrate. The semiconductor substrate has opposite first and second surfaces.

[0106] Specifically, the material of the semiconductor substrate is not limited in the embodiments of the present application. The semiconductor substrate can be a substrate of any semiconductor material, such as a silicon substrate, a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate. In addition, the semiconductor substrate can be of N-type or P-type.

[0107] In the actual manufacturing process, after the semiconductor substrate is provided, the semiconductor substrate can be pre-cleaned in some examples to remove the cutting damage on the surface of the semiconductor substrate, and the organic matter and other contaminants generated during transportation, thereby improving the yield of the back contact cell to be manufactured.

[0108] Second step: as shown in FIG. 2, a first interface passivation layer 12 and a first doped silicon layer 13 are sequentially formed on the first surface of the semiconductor substrate 11 in the thickness direction of the semiconductor substrate 11.

[0109] Specifically, the material of the first interface passivation layer and the first doped silicon layer is not limited in the embodiments of the present application, and can be set according to actual needs.

[0110] For example, the first interface passivation layer can be an intrinsic silicon layer. The first interface passivation layer and the first doped silicon layer can form a heterojunction structure. In this case, the first interface passivation layer and the first doped silicon layer have a high passivation effect on the surface of the corresponding region in the semiconductor substrate, further reduce the carrier recombination rate of the surface of the region, and improve the conversion efficiency of the back contact cell to be manufactured. The material of the first interface passivation layer and / or the first doped silicon layer can include at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0111] Exemplarily, the first interface passivation layer can be a tunneling passivation layer, and a material of the tunneling passivation layer can include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbon nitride, aluminum nitride, titanium nitride, titanium carbon nitride. Secondly, in the case where the first interface passivation layer is a tunneling passivation layer, the first doped silicon layer includes a doped crystalline silicon layer. Specifically, the first doped silicon layer can include a doped polycrystalline silicon layer and / or a doped monocrystalline silicon layer. In this case, since amorphous silicon, nanocrystalline silicon and microcrystalline silicon are easy to form polycrystalline silicon or monocrystalline silicon at high temperature, and the chemical properties of the tunneling passivation layer and the doped crystalline silicon layer are relatively stable at high temperature, when the first interface passivation layer and the first doped silicon layer with higher thermal stability are formed on the first side of the semiconductor substrate first, the influence of laser radiation heat on the first interface passivation layer and the first doped silicon layer when the second interface passivation layer and the second doped silicon layer are selectively etched by using a laser processing process can be reduced or even avoided, and the yield of the back contact cell is improved. At the same time, the first interface passivation layer and the first doped silicon layer are less sensitive to high-temperature laser thermal damage, and the influence of the laser processing process on the passivation effect of the first interface passivation layer and the first doped silicon layer can be reduced, further increasing the process window and reducing the process difficulty.

[0112] In the case where the first interface passivation layer is a tunneling passivation layer and the first doped silicon layer includes a doped crystalline silicon layer, in the actual manufacturing process, a low-pressure chemical vapor deposition or thermal oxidation process can be used to form the first interface passivation layer on the first side of the semiconductor substrate. Next, in some examples, a chemical vapor deposition process can be used to form an intrinsic silicon layer on the first interface passivation layer, and then a diffusion, ion implantation or doping source coating process can be used to dope the intrinsic silicon layer, so that the intrinsic silicon layer forms a first doped polycrystalline silicon layer.

[0113] In other examples, a chemical vapor deposition process can be used to form a doped amorphous silicon layer on the first interface passivation layer; and then the doped amorphous silicon layer is annealed to form a doped polycrystalline silicon layer. In yet other examples, a chemical vapor deposition process can be used to directly form a first doped silicon layer including at least one of amorphous silicon, microcrystalline silicon and nanocrystalline silicon on the first interface passivation layer.

[0114] It should be noted that, as shown in FIG. 2, when the first interface passivation layer 12 and the first doped silicon layer 13 are formed, the first interface passivation layer 12 and the first doped silicon layer 13 will also be formed on the side surface and at least part of the second surface of the semiconductor substrate 11. In the process of forming the first doped silicon layer 13, if the semiconductor substrate 11 is double-inserted, the first doped silicon layer 13 will be formed on the edge region of the second surface of the semiconductor substrate 11; if the semiconductor substrate 11 is single-inserted, the first doped silicon layer 13 will be formed on the entire second surface of the semiconductor substrate 11 as shown in FIG. 2.

[0115] In addition, as shown in FIG. 2, in the case of using a diffusion process to dope the intrinsic silicon layer, the first doped silicon glass layer 14 will also be formed on the side of the first doped silicon layer 13 away from the semiconductor substrate 11 when the first doped silicon layer 13 is formed.

[0116] Specifically, the thickness of the first interface passivation layer and the first doped silicon layer is not limited in the embodiment of the present application, and can be set according to actual needs.

[0117] For example, the thickness of the first doped silicon layer can be greater than or equal to 30 nm and less than or equal to 300 nm. For example, the thickness of the first doped silicon layer can be 30 nm, 40 nm, 50 nm, 60 nm, 80 nm, 100 nm, 120 nm, 130 nm, 140 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, 300 nm, etc.

[0118] For example, in the case of the first interface passivation layer being a tunneling passivation layer, the thickness of the first interface passivation layer can be greater than or equal to 0.5 nm and less than or equal to 2.5 nm; or, in the case of the first interface passivation layer being an intrinsic silicon layer, the thickness of the first interface passivation layer can be greater than or equal to 4 nm and less than or equal to 18 nm.

[0119] In actual application, the thickness of each part of the first interface passivation layer can be the same or different. In the case that the thickness of each part of the first interface passivation layer is different, in some examples, in the first surface, in the case that the region where the first interface passivation layer and the first doped silicon layer are arranged has a tower base-like texture structure, the thickness of the first interface passivation layer on the bottom surface of the tower base-like texture structure can be less than the thickness of the first interface passivation layer on the sidewall of the tower base-like texture structure. In this case, it can be understood that the bottom surface of the tower base-like texture structure and the sidewall of the tower base-like texture structure have different crystal orientations. Specifically, the bottom surface of the tower base-like texture structure is

[0110] crystal orientation, and the number of dangling bonds on the surface of the

[0110] crystal orientation is relatively small; while the sidewall of the tower base-like texture structure is

[0111] crystal orientation, and the number of dangling bonds on the

[0111] crystal orientation is relatively large. Based on this, when the thickness of the first interface passivation layer on one side of the bottom surface of the tower base-like texture structure is less than the thickness of the first interface passivation layer on the sidewall of the tower base-like texture structure, it is beneficial to make the part of the first interface passivation layer on the sidewall of the tower base-like texture structure have a relatively high passivation effect, meet the requirement of the sidewall of the tower base-like texture structure for high passivation effect, reduce the carrier recombination rate of the sidewall of the tower base-like texture structure, and further improve the working efficiency of the back contact cell manufactured.

[0120] As for the thickness of the first interface passivation layer on the bottom surface of the tower base-like texture structure and the thickness of the first interface passivation layer on the sidewall of the tower base-like texture structure, they can be determined according to the passivation effect requirement of different regions of the tower base-like texture structure and the actual manufacturing process, which is not specifically limited here.

[0121] For example, the thickness of the first interface passivation layer on the bottom surface of the tower base-like texture structure can be 0.5 nm, 0.6 nm, 0.8 nm, 1 nm, 1.2 nm, 1.3 nm or 1.5 nm, etc. In this case, the thickness of the first interface passivation layer on the bottom surface of the tower base-like texture structure within the above range is beneficial to prevent the part from having a low passivation effect on the semiconductor substrate due to the small thickness of the first interface passivation layer on the bottom surface of the tower base-like texture structure; in addition, it is also beneficial to prevent the part from having a high tunneling resistance due to the large thickness of the first interface passivation layer on the bottom surface of the tower base-like texture structure, which is beneficial to achieve a balance between the passivation effect and the tunneling resistance of the part of the first interface passivation layer on the bottom surface of the tower base-like texture structure, so as to reduce the carrier recombination rate of the sidewall of the tower base-like texture structure while ensuring that the first doped silicon layer has a high carrier collection efficiency and reduces transmission loss.

[0122] For example, the thickness of the first interface passivation layer on the sidewall of the tower base-like texture structure can be greater than or equal to 0.5 nm and less than or equal to 2 nm. For example, the thickness of the first interface passivation layer on the sidewall of the tower base-like texture structure can be 0.5 nm, 0.8 nm, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm or 2 nm, etc. In this case, the thickness of the first interface passivation layer on the sidewall of the tower base-like texture structure within the above range is beneficial to prevent the passivation effect of this part from being low due to the small thickness, and is also beneficial to prevent the tunneling resistance of this part from being high due to the large thickness of the first interface passivation layer on the sidewall of the tower base-like texture structure, so as to balance the passivation effect and the tunneling resistance of the part of the first interface passivation layer on the sidewall of the tower base-like texture structure, thereby reducing the carrier recombination rate of the side of the tower base-like texture structure while ensuring that the first doped silicon layer has a high carrier collection efficiency and reduces transmission loss.

[0123] Step 3: As shown in FIG. 3, the first doped silicon glass layer is removed. Specifically, in actual application, a wet etching process (such as using a hydrofluoric acid solution) can be used to remove the first doped silicon glass layer.

[0124] It should be noted that in the case where the first interface passivation layer formed in the second step is an intrinsic silicon layer and the first interface passivation layer and the first doped silicon layer form a heterojunction structure, the third step can also be omitted in some examples.

[0125] Step 4: As shown in FIG. 4, an insulating layer 16 is formed on the side of the first doped silicon layer 13 away from the semiconductor substrate 11. Specifically, a chemical vapor deposition process can be used to form the insulating layer 16 on the side of the first doped silicon layer away from the semiconductor substrate 11. The material of the insulating layer 16 can include any insulating material having a mask protection function, such as aluminum oxide and / or silicon nitride, as long as it can be applied to the manufacturing method provided in the present application. The thickness of the insulating layer 16 can be set according to actual needs.

[0126] It should be noted that the insulating layer can be directly formed on the side of the first doped silicon layer away from the semiconductor substrate. Since the insulating material (such as aluminum oxide or silicon nitride) used to manufacture the insulating layer can have a passivation effect, it not only has a mask protection and insulation effect, but also can directly passivate the side of the first doped silicon layer away from the semiconductor substrate, which is beneficial to reduce the surface defects of the side of the first doped silicon layer away from the semiconductor substrate and further improve the conversion efficiency of the back contact cell. The insulating layer can also select at least one of materials having a hydrogen supplement function, such as aluminum oxide and silicon nitride, to perform hydrogen implantation on the first doped silicon layer, especially in the case where the material of the first doped silicon layer is doped polysilicon, so as to improve the passivation effect of the first doped silicon layer.

[0127] In addition, as shown in FIG. 4 and FIG. 5, the insulating layer 16 is formed on the first side of the semiconductor substrate 11, and also formed on at least part of the side surface and the second side of the semiconductor substrate 11. In this case, in some examples, the insulating layer 16 formed on the second side of the semiconductor substrate 11 can be removed after the formation of the insulating layer 16 and before the subsequent texturing process. The insulating layer 16 formed on the side surface of the semiconductor substrate 11 can be completely removed, partially removed, or completely retained.

[0128] Step 5: As shown in FIG. 6, the insulating layer is patterned to form the insulating mask pattern 15. The patterning of the insulating layer can be achieved by photolithography combined with etching, laser irradiation, or chemical slurry etching, etc. After the patterning, the remaining part of the insulating layer forms the insulating mask pattern 15.

[0129] Step 6: As shown in FIG. 7, the first interface passivation layer 12 and the first doped silicon layer 13 not covered by the insulating mask pattern 15 are removed.

[0130] In actual manufacturing process, the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern can be removed by laser or wet etching, etc. After the removal, at least the part of the first side of the semiconductor substrate exposed outside the insulating mask pattern, and the second side of the semiconductor substrate are exposed (it can be understood that when the insulating layer formed on the second side of the semiconductor substrate is removed, the insulating layer formed on at least part of the side surface of the semiconductor substrate is also removed, and the part of the side surface not corresponding to the insulating layer is also exposed). The etchant and etching conditions used in the wet etching process can be determined according to the actual application scenario, which is not limited here.

[0131] It should be noted that the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern can be removed by the corresponding etching process after the formation of the insulating mask pattern. Alternatively, the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern can be removed at the same time when the insulating layer is patterned to form the insulating mask pattern, which can simplify the process and improve the manufacturing efficiency of the back contact solar cell. For example, part of the insulating layer and part of the first interface passivation layer and the first doped silicon layer can be removed by laser at the same time to finally form the insulating mask pattern and the first interface passivation layer and the first doped silicon layer covered by the insulating mask pattern.

[0132] In addition, the first surface can include a first region and a second region. The first region is defined as a region of the first surface where the first interface passivation layer and the first doped silicon layer are present, and the second region is defined as a region of the first surface where the first interface passivation layer and the first doped silicon layer are not present. After removing the first interface passivation layer and the first doped silicon layer that are not covered by the insulating mask pattern, the surface of the first region can be flush with the surface of the second region. In this case, the portion of the semiconductor substrate corresponding to the second region also has a large light absorption depth in the thickness direction of the semiconductor substrate, which is beneficial to improving the conversion efficiency of the semiconductor substrate. Alternatively, as shown in FIG. 7, the second region 24 can also include a groove. In this case, it indicates that when the first interface passivation layer 12 and the first doped silicon layer 13 that are not covered by the insulating mask pattern 15 are removed, the portions of the first interface passivation layer 12 and the first doped silicon layer 13 present on the second region 24 are all removed, thereby preventing short circuit. At the same time, the presence of the groove causes the surface of the second region 24 to be staggered with the surface of the first region 23 in the thickness direction of the semiconductor substrate 11, which is beneficial to at least partially staggering the second interface passivation layer and the second doped silicon layer present on the second region 24 with the first interface passivation layer 12 and the first doped silicon layer 13 present on the first region 23, thereby reducing the risk of electric leakage. Specifically, the depth of the groove is not limited in the embodiments of the present application and can be determined according to the actual manufacturing process.

[0133] Step 7: As shown in FIGS. 8 and 9, the surface of the region of the first surface exposed outside the insulating mask pattern 15 and the second surface are subjected to texturing treatment.

[0134] Specifically, the texturing treatment can be performed by using a wet etching process, and the treatment solution and the treatment conditions of the texturing treatment can be determined according to the actual application scenario, which are not limited herein. As shown in FIG. 8, after the texturing treatment, the surface of the region of the first surface exposed outside the insulating mask pattern 15 and the second surface are textured. Specifically, as shown in FIG. 8, if the insulating mask pattern 15 covers all regions of the side surface of the semiconductor substrate 11 in the thickness direction of the semiconductor substrate 11, the surface of the region of the first surface exposed outside the insulating mask pattern 15 and the second surface are textured after the texturing treatment. As shown in FIG. 9, if the insulating mask pattern 15 does not cover the side surface of the semiconductor substrate 11 or covers only a part of the side surface of the semiconductor substrate 11 in the thickness direction of the semiconductor substrate 11, the surface of the region of the first surface exposed outside the insulating mask pattern 15 and the second surface are textured after the texturing treatment, and the surface of the region of the side surface of the semiconductor substrate 11 that is not covered by the insulating mask pattern 15 is also textured.

[0135] In actual manufacturing process, in some examples, the surface of the semiconductor substrate exposed to the outside can be polished and cleaned by an alkaline solution. The alkaline solution can be sodium hydroxide or potassium hydroxide, etc. The concentration of the alkaline solution can be 0.1% to 3%. Next, cleaning is performed in a mixed solution including KOH, H2O2 and H2O. Among them, the ratio of KOH, H2O2 and H2O in the mixed solution is (1:2:5), the cleaning temperature is 65°C, and the cleaning time is 360s. Then, the first surface of the semiconductor substrate exposed to the area outside the insulating mask pattern and the second surface are subjected to texturing treatment, for example, using a solution system of TS53V01: KOH: DIW. Among them, the mass percentage concentration of TS53V01 is 0.2% to 1.5%, the mass percentage concentration of KOH is 1% to 3%, and the temperature of the texturing treatment is 75°C to 85°C. Optionally, the mass percentage concentration of TS53V01 is 0.5% to 1%, and the mass percentage concentration of KOH is 1.5% to 2%. Then, cleaning is performed again in a mixed solution including KOH, H2O2 and H2O. The cleaning temperature is 65°C, and the cleaning time is 300s.

[0136] It should be noted that the depth of the groove included in the second region in the first surface is also affected by the above texturing process. Optionally, in the case where the surface of the first region is a polished surface and the groove bottom surface is a textured surface, the distance from the surface of the first region of the semiconductor substrate to the groove bottom surface can be greater than or equal to 2 pm and less than or equal to 8 pm. Specifically, the distance refers to the distance from the surface of the first region of the semiconductor substrate to the bottom of the pyramid structure of the groove bottom surface. For example, the distance from the surface of the first region of the semiconductor substrate to the groove bottom surface can be 2 pm, 2.5 pm, 3 pm, 3.5 pm, 4 pm, 5 pm, 6 pm, 7 pm or 8 pm, etc. In this case, it is beneficial to prevent the distance between the first doped silicon layer and the second doped silicon layer along the thickness direction of the semiconductor substrate from being too small when the distance from the surface of the first region of the semiconductor substrate to the groove bottom surface is small, thereby ensuring a lower risk of leakage between the two; secondly, during the texturing process on the groove bottom surface, the semiconductor substrate needs to be etched, so the distance from the surface of the first region of the semiconductor substrate to the groove bottom surface also affects the size of the textured structure on the groove bottom surface. Based on this, the distance from the surface of the first region of the semiconductor substrate to the groove bottom surface within the above range can also prevent the size of the groove bottom surface and the textured structure formed on the second surface at the same time from being too small when the distance is too small, thereby ensuring that the second surface has a higher light trapping effect, while also being beneficial to increasing the specific surface area of the second doped silicon layer away from the semiconductor substrate, thereby further reducing the contact loss between the second doped silicon layer and the corresponding conductive material. In addition, it can also prevent the etching depth of the semiconductor substrate at the groove from being too large when the distance from the surface of the first region of the semiconductor substrate to the groove bottom surface is too large, thereby ensuring that the semiconductor substrate has a larger light absorption depth, and thereby making the back contact cell have a higher conversion efficiency.

[0137] Step 8: As shown in FIG. 10 and FIG. 11, the insulating mask pattern is removed. Specifically, a wet etching process can be used to remove the insulating mask pattern. The etchant used to remove the insulating mask pattern can be determined according to the material of the insulating mask pattern and actual needs, which is not limited here.

[0138] For example, when the material of the insulating mask pattern is silicon nitride, a hydrofluoric acid with a concentration of 5%wt to 10%wt can be used to remove the insulating mask pattern. The removal time can be, for example, 600s.

[0139] It should be noted that in some examples, the seventh step can be performed first, and then the eighth step is performed; in another example, the seventh step and the eighth step can be performed at the same time, that is, the insulating mask pattern is removed at the same time as the texturing process.

[0140] Step 9: As shown in FIG. 12, the first passivation layer 17 is formed on the second surface of the semiconductor substrate 11, and at the same time, the first passivation layer 17 is also formed on the first surface of the semiconductor substrate 11.

[0141] In actual manufacturing process, the first passivation layer can be formed by chemical vapor deposition (such as low pressure chemical vapor deposition LPCVD or plasma enhanced chemical vapor deposition PECVD, etc.) or atomic layer deposition (ALD) process. The material of the first passivation layer can be set according to actual needs, which is not specifically limited here. For example, the first passivation layer can include an aluminum oxide (AlOx) layer. In addition, as shown in FIG. 12, the first passivation layer 17 is formed on the second surface and the first surface of the semiconductor substrate 11, and at the same time, the first passivation layer 17 can also be formed on the side surface of the semiconductor substrate 11.

[0142] Step 10: As shown in FIG. 13, a reflection reduction layer is formed on the second surface of the semiconductor substrate 11 to reduce the reflectivity of the back contact cell on the second surface side, and further improve the conversion efficiency of the back contact cell. The material of the reflection reduction layer 18 can be determined according to the actual application scenario, which is not specifically limited here. For example, the reflection reduction layer 18 can include a silicon nitride layer. In addition, when the reflection reduction layer 18 is formed on the second surface of the semiconductor substrate 11, the reflection reduction layer 18 can also be formed on the side surface of the semiconductor substrate 11 and at least part of the area on the first surface of the semiconductor substrate 11 due to the wrap plating.

[0143] Step 11: Annealing treatment is performed on the first passivation layer to activate the passivation effect of the first passivation layer. In this process, the presence of the first passivation layer is beneficial to prevent the hydrogen in the first doped silicon layer from escaping, and at the same time, the hydrogen in the first passivation layer can also be injected into the first doped silicon layer, reducing the number of surface defects on the side of the first doped silicon layer away from the semiconductor substrate, and ensuring that the side of the first doped silicon layer away from the semiconductor substrate has a higher passivation effect. It should be noted that in some examples, this step can also not be performed. In other examples, the passivation effect of the first passivation layer can be activated at the same time when the reflection reduction layer is formed on the second surface of the semiconductor substrate 11 in step 10, and the presence of the reflection reduction layer and the first passivation layer is beneficial to prevent the hydrogen in the first doped silicon layer from escaping, and at the same time, the hydrogen in the first passivation layer can also be injected into the first doped silicon layer.

[0144] Twelfth step: after the annealing process and before the formation of the second interface passivation layer and the second doped silicon layer, the anti-reflective layer 18 and the first passivation layer 17 formed on the first side of the semiconductor substrate 11 need to be removed in sequence, as shown in FIG. 13 and FIG. 14. At this time, the first passivation layer 17 and the anti-reflective layer 18 can be completely or partially retained on the side of the semiconductor substrate 11. The removal operation can be performed in a chain cleaning device, and then the semiconductor substrate 11 can be subjected to a metal ion cleaning (i.e., RCA cleaning) after the removal operation and before the subsequent operation, so as to remove the contamination and slight scratches caused by the semiconductor substrate 11 in the chain cleaning device. In some embodiments, the cleaning operation can also not be performed.

[0145] In some embodiments, the twelfth step can also not be performed.

[0146] Thirteenth step: as shown in FIG. 15, the second interface passivation layer 19 and the second doped silicon layer 20 are formed in sequence on the first side of the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11. The second doped silicon layer 20 and the first doped silicon layer 13 have opposite conductivity types.

[0147] In actual manufacturing processes, the second interface passivation layer and the second doped silicon layer can be formed on the first side by using a plasma-enhanced chemical vapor deposition or a low-pressure chemical vapor deposition process. The materials of the second interface passivation layer and the second doped silicon layer can be set according to actual needs.

[0148] For example, the second interface passivation layer can be a tunneling passivation layer, and the material of the tunneling passivation layer can include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbon nitride, aluminum nitride, titanium nitride, and titanium carbon nitride. In addition, in the case where the second interface passivation layer is a tunneling passivation layer, the second doped silicon layer includes a doped crystalline silicon layer. Specifically, the second doped silicon layer can include a doped polycrystalline silicon layer and / or a doped monocrystalline silicon layer.

[0149] For example, the second interface passivation layer can be an intrinsic silicon layer, and the second interface passivation layer and the second doped silicon layer can form a heterojunction structure. At this time, the second interface passivation layer and the second doped silicon layer have a high passivation effect on the corresponding region of the surface of the semiconductor substrate, further reducing the carrier recombination rate of the region of the surface, and improving the conversion efficiency of the back contact cell manufactured. The material of the second interface passivation layer and / or the second doped silicon layer can include at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon.

[0150] It should be noted that, as shown in FIG. 15 and FIG. 16, when the second interface passivation layer 19 and the second doped silicon layer 20 are formed, the second interface passivation layer 19 and the second doped silicon layer 20 will also be formed around the side surface of the semiconductor substrate 11 and at least part of the second surface. In some examples, as shown in FIG. 19, a wet etching process or the like can be used to remove at least part of the second interface passivation layer 19 and the second doped silicon layer 20 around the second surface of the semiconductor substrate 11. The part of the second interface passivation layer 19 and the second doped silicon layer 20 around the side surface of the semiconductor substrate 11 can be completely retained, partially retained, or completely removed.

[0151] As for the conductivity type of the second doped silicon layer, it can be set according to actual needs, as long as the conductivity types of the first doped silicon layer and the second doped silicon layer are opposite.

[0152] Optionally, in the case where the first interface passivation layer is a tunneling passivation layer, the first doped silicon layer is a doped polysilicon, the second interface passivation layer is an intrinsic silicon layer, and the second interface passivation layer and the second doped silicon layer form a heterojunction structure, the conductivity type of the first doped silicon layer can be N-type, and the conductivity type of the second doped silicon layer can be P-type. In this case, compared with P-type doped amorphous silicon, P-type doped microcrystalline silicon, or P-type nanocrystalline silicon material, the contact resistance of P-type doped polysilicon material with the electrode is higher, and the field passivation effect is poorer. Therefore, by setting the conductivity type of the first doped silicon layer as N-type and setting the conductivity type of the second doped silicon layer as P-type, the field passivation effect of the first doped silicon layer can be further improved, and the contact resistance between the first doped silicon layer and the electrode can be reduced, which is beneficial to improving the electrical performance of the back contact cell manufactured.

[0153] As for the thickness of the second interface passivation layer and the second doped silicon layer, it can be set according to actual needs, which is not specifically limited here.

[0154] For example, the thickness of the second interface passivation layer can be 3 nm, 5 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm or 16 nm, etc. In this case, it can be understood that the insulating mask pattern is removed after the texturing process or at the same time as the texturing process, and at this time, the second interface passivation layer and the second doped silicon layer formed on the first surface are directly formed on the semiconductor substrate and the first doped silicon layer. At this time, the overlapping part between the second doped silicon layer and the first doped silicon layer is only separated by the second interface passivation layer. Based on this, when the thickness of the second interface passivation layer is within the above range, the thickness of the second interface passivation layer is large, which is beneficial to enhance the isolation effect of the second interface passivation layer between the first doped silicon layer and the second doped silicon layer overlapping in the thickness direction of the semiconductor substrate, reduce the risk of forward leakage, and improve the conversion efficiency of the back contact cell manufactured. Moreover, it can also prevent the contact resistance from being too large due to the too large thickness of the second interface passivation layer, and reduce the transmission loss.

[0155] In addition, the thickness of each part of the second interface passivation layer can be the same. At this time, each part of the second interface passivation layer has a high passivation effect.

[0156] Alternatively, as shown in FIG. 17, the first surface can include a first region 23 and a second region 24. The second region 24 includes a groove. The first interface passivation layer 12 and the first doped silicon layer 13 are located in the first region 23. The second interface passivation layer 19 and the second doped silicon layer 20 are located in the second region 24, and cover part of the first interface passivation layer 12 and the first doped silicon layer 13 from the second region 24 to the first region 23. The surface of the first region 23 is a polished surface, and the bottom surface of the groove is a textured surface. Moreover, the thickness of the second interface passivation layer 19 on the textured surface can be less than the thickness of the second interface passivation layer 19 on the polished surface. In this case, the presence of the groove makes the surface of the second region 24 staggered with the surface of the first region 23 in the thickness direction of the semiconductor substrate 11, which is beneficial to at least partially stagger the second interface passivation layer 19 and the second doped silicon layer 20 located on the second region 24 with the first interface passivation layer 12 and the first doped silicon layer 13 located on the first region 23, and reduce the risk of leakage. In addition, when the thickness of the second interface passivation layer 19 on the textured surface is small, this part has a low transmission resistance, which is beneficial to reduce the transmission loss. While the thickness of the second interface passivation layer 19 on the polished surface is large, which is beneficial to improve the passivation and insulation effect of the part on the polished surface, reduce the risk of forward leakage, and improve the conversion efficiency of the back contact cell manufactured. In this case, the thickness difference between different parts of the second interface passivation layer 19 can be set according to the surface roughness of the first region 23 and the second region 24 and actual needs, which is not limited here.

[0157] As for the second doped silicon layer, optionally, the thickness of the second doped silicon layer can be greater than or equal to 3 nm and less than or equal to 50 nm. For example, the thickness of the second doped silicon layer can be 3 nm, 5 nm, 8 nm, 10 nm, 20 nm, 30 nm, 40 nm or 50 nm, etc.

[0158] In this case, each part of the second doped silicon layer has a high field passivation effect.

[0159] Alternatively, as shown in FIG. 16, in the case where the first surface includes the first region 23 and the second region 24, the thickness of the second doped silicon layer 20 on the textured surface can also be less than the thickness of the second doped silicon layer 20 on the polished surface. In this case, compared with the polished surface, the specific surface area of the textured surface is larger, and in the same formation range, the contact area between the part of the second doped silicon layer 20 on the textured surface and the semiconductor substrate 11 is larger, while the contact area between the part of the second doped silicon layer 20 on the polished surface and the semiconductor substrate 11 is smaller. Based on this, when the thickness of the second doped silicon layer 20 on the textured surface is small, after ensuring that the part of the second doped silicon layer 20 on the textured surface has sufficient contact area with the semiconductor substrate 11, the thickness of the part can be reserved for a reduction space, which can reduce the use of materials for manufacturing the part of the second doped silicon layer 20 on the textured surface while ensuring a high carrier collection efficiency. In addition, the thickness of the second doped silicon layer 20 on the polished surface is large, so that this part has a high field passivation effect and reduces carrier recombination. In this case, the thickness difference between different parts of the second doped silicon layer 20 can be set according to the surface roughness of the first region 23 and the second region 24 and actual needs, which is not specifically limited here.

[0160] In addition, in some examples, in the actual application process, in the case where the first surface includes the first region and the second region, the second region includes a groove, and the second doped silicon layer is a doped amorphous silicon layer, after sequentially forming the second interface passivation layer and the second doped silicon layer on the first surface in the thickness direction of the semiconductor substrate, the manufacturing method of the back contact cell can further include a fourteenth step of: performing laser irradiation on the second doped silicon layer on the groove bottom surface to perform crystallization treatment on the second doped silicon layer.

[0161] In the technical solution, the second doped silicon layer on the groove bottom surface is irradiated by laser. Under the irradiation of high-temperature laser, the crystallization degree of at least part of the second doped silicon layer on the groove bottom surface is increased. It can be understood that the smaller the crystallization degree of the semiconductor layer is, the smaller the crystal grains in the semiconductor layer are, and even the disorder of amorphous silicon material. The smaller the crystal grains in the semiconductor layer are, the fewer the interfaces between the crystal grains in the semiconductor layer are, so the resistance of the crystal grain interface is larger. Therefore, by increasing the crystallization degree of at least part of the second doped silicon layer on the groove bottom surface, the conductive property of at least part of the second doped silicon layer on the groove bottom surface is improved, the transmission loss between the second doped silicon layer and the corresponding conductive material (such as a transparent conductive layer or a conductive electrode) is reduced, and the conversion efficiency of the back contact cell manufactured is improved.

[0162] It should be noted that the greater the crystallization degree of the embodiment of the present application can refer to the greater the crystallization rate, the greater the crystal grain size, and / or the greater the number of crystal grains. For example, in the case of the second doped silicon layer being a doped amorphous silicon layer (which may contain a small amount of nanocrystalline silicon part inside, but the content of the nanocrystalline silicon part is very small, for example, less than 5%, which is known in the art), at least part of the second doped silicon layer on the groove bottom surface will generate crystal lattice ordered crystal grains, so that the crystallization degree is increased. The crystallization degree of the part of the second doped silicon layer corresponding to the first region is smaller, and at this time, the part with smaller crystallization degree is still amorphous silicon material without crystal grains generated after laser treatment. In this case, the electrical conductivity of at least part of the second doped silicon layer on the groove bottom surface is greater, which is beneficial to reduce the transmission loss of at least part of the second doped silicon layer on the groove bottom surface, and reduce the contact resistance between at least part of the second doped silicon layer on the groove bottom surface and the transparent conductive layer. The crystallization degree of the part of the second doped silicon layer corresponding to the first region is smaller, and at this time, the electrical conductivity of the part of the second doped silicon layer corresponding to the first region is relatively low, which is beneficial to reduce the size of the forward leakage current between the part of the second doped silicon layer corresponding to the first region and the first doped silicon layer, and further improve the conversion efficiency of the back contact cell. Specifically, after the crystallization treatment of the second doped silicon layer, the crystal type of the second doped silicon layer can remain unchanged, and the crystallization degree is increased. For example, before and after the above crystallization treatment, the crystal type of the second doped silicon layer can be microcrystalline silicon, and the crystallization degree is increased from 20% before the crystallization treatment to 80% after the crystallization treatment. Alternatively, after the crystallization treatment of the second doped silicon layer, the crystal type of the second doped silicon layer can also change. For example, before the above crystallization treatment, the crystal type of the second doped silicon layer can be amorphous silicon, and after the crystallization treatment, the crystal type of the second doped silicon layer changes to nanocrystalline silicon or microcrystalline silicon.

[0163] In addition, in the actual manufacturing process, the above-mentioned fourteenth step operation can also not be performed.

[0164] Fifteenth step: as shown in FIG. 17, part of the second interface passivation layer 19 and the second doped silicon layer 20 located on the first interface passivation layer 12 and the first doped silicon layer 13 are removed to expose part of the first interface passivation layer 12 and the first doped silicon layer 13.

[0165] In the actual manufacturing process, laser etching, etching slurry etching, or a combination of photolithography and wet etching process can be used for selective etching of the stacked second interface passivation layer and the second doped silicon layer. It can be understood that after selective etching, the remaining part of the second interface passivation layer and the second doped silicon layer will affect the carrier collection efficiency of the second doped silicon layer. In addition, the first doped silicon layer needs to be electrically connected to the corresponding conductive material through the opening area provided in the second interface passivation layer and the second doped silicon layer, so as to guide the collected carriers out. The carriers transported by the conductive material electrically connected to the first doped silicon layer are opposite to the conductive type of the second doped silicon layer. Therefore, the width of the opening area of the second interface passivation layer and the second doped silicon layer will also affect the formation of the conductive material electrically connected to the first doped silicon layer, and therefore the size of the opening area can be determined according to the requirements of the carrier collection efficiency of the second doped silicon layer and the manufacturing precision and range of the conductive material electrically connected to the first doped silicon layer in the actual application scenario, which is not limited here.

[0166] For example, the width of the opening area can be 40 μm, 80 μm, 100 μm, 150 μm, 200 μm, 250 μm, 260 μm, 280 μm, 300 μm, 320 μm, 340 μm, 360 μm, 380 μm, or 400 μm, etc. In this case, compared with the width of the opening area of the second interface passivation layer and the second doped silicon layer in the prior art back contact cell being less than 40 μm, the width of the opening area for exposing the first doped silicon layer in the back contact cell formed by the manufacturing method provided by the present application is larger, which is beneficial to making the corresponding conductive material electrically connected to the first doped silicon layer have a larger formable range while preventing short circuit, thereby facilitating the increase of the contact area between the first doped silicon layer and the corresponding conductive material, reducing the transmission loss, and improving the electrical reliability of the manufactured back contact cell. Secondly, when the width of the opening area is less than or equal to 400 μm, the remaining part of the second interface passivation layer and the second doped silicon layer after the opening operation is more, which reduces the etching amount, and ensures that the second interface passivation layer and the second doped silicon layer have a certain area ratio on the first side, and ensures that the second doped silicon layer has a higher carrier collection efficiency.

[0167] In addition, in some examples, in the actual manufacturing process, after the laser is used to remove the part of the second interface passivation layer and the second doped silicon layer on the first interface passivation layer and the first doped silicon layer, the edge part of the opening region of the second doped silicon layer can be processed by the laser to form a hole structure in the edge part of the second doped silicon layer. Specifically, the laser etching parameters can be adjusted so that the edge part of the second doped silicon layer near the opening region is heated under the action of high-temperature laser, so that after selective etching, a hole structure is formed in the edge part of the second doped silicon layer. In this case, it can be understood that the hole structure is a hollow structure, so when the hole structure is formed in the edge part of the second doped silicon layer, the edge structure of the second doped silicon layer is loose, which can reduce the risk of electric leakage between the edge part of the second doped silicon layer and the first doped silicon layer, and improve the electrical reliability of the back contact cell. In addition, the existence of the hole structure can also increase the relief degree of the edge part of the laminated second interface passivation layer and second doped silicon layer, thereby enhancing the light trapping effect of this part, which is beneficial to improve the bifaciality of the back contact cell. Specifically, the distribution and size of the holes in the above hole structure can be determined according to the actual manufacturing process, which is not limited here.

[0168] For example, the width of the part of the second doped silicon layer with a hole structure can be greater than or equal to 0.1 μm and less than or equal to 20 μm. For example, the width of the part of the second doped silicon layer with a hole structure can be 0.1 μm, 0.3 μm, 0.5 μm, 0.8 μm, 1 μm, 2 μm, 5 μm, 10 μm, 15 μm or 20 μm, etc. In this case, when the width of the part of the second doped silicon layer with a hole structure is in the above range, the carrier flow between the first doped silicon layer and the second doped silicon layer can be effectively reduced, and the electric leakage can be reduced.

[0169] For example, in the top view of the back contact cell, the shape of the hole structure can be at least one of a circle, an ellipse, and an irregular pattern. In addition, when the shape of the hole structure is at least one of a circle, an ellipse, and an irregular pattern, the hole structure can enhance insulation and reduce electric leakage.

[0170] Sixteenth step: as shown in FIG. 18, a transparent conductive layer 21 is formed covering the first doped silicon layer 13 and the second doped silicon layer 20 away from the semiconductor substrate 11. The transparent conductive layer 21 is formed with a through isolation groove 22 to separate the part of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 from the part of the transparent conductive layer 21 corresponding to the second doped silicon layer 20. Specifically, the material and thickness of the transparent conductive layer 21 and the width of the isolation groove 22 are not limited in the present application, as long as they can be applied to the manufacturing method provided by the present application. In addition, the second doped silicon layer and the second interface passivation layer corresponding to the isolation groove can be removed or not. In the case of removing the second doped silicon layer and the second interface passivation layer corresponding to the isolation groove, the part of the second doped silicon layer close to the opening region can also be provided with the above-mentioned hole structure, and the beneficial effects can be referred to the foregoing, which will not be described here.

[0171] The transparent conductive layer can be formed by physical vapor deposition or other processes, and then a laser etching or etching slurry etching process can be used to open the isolation groove in the transparent conductive layer. Specifically, when etching with etching slurry, the etching slurry can be printed first, and then the etching slurry can be solidified and etched. Next, the etching slurry needs to be cleaned. In addition, the setting of the above-mentioned isolation groove can be determined according to actual needs and manufacturing precision. Alternatively, the isolation groove can be provided at the region where the first doped silicon layer and the second doped silicon layer overlap along the thickness direction of the semiconductor substrate.

[0172] In addition, as shown in FIG. 18, the thickness of each part of the transparent conductive layer 21 can be substantially the same. Alternatively, the thickness of the edge part of the transparent conductive layer adjacent to the isolation groove 22 can also gradually decrease along the direction close to the isolation groove 22. In this case, the thickness of the transparent conductive layer on both sides close to the isolation groove 22 is small, and at this time the thickness of the two parts of the transparent conductive layer for transmitting the opposite carriers is small (the opposite area is also small), which is beneficial to reduce the risk of electric leakage and improve the electrical reliability of the back contact cell. The width of the region where the thickness of the transparent conductive layer gradually decreases and the amplitude of the gradually decreasing thickness can be determined according to the etching parameters when the isolation groove 22 is opened in the transparent conductive layer during actual manufacturing process, which will not be limited here. In addition, such setting is beneficial to the stress release between other structures in the back contact cell and the transparent conductive layer, avoiding the edge of the transparent conductive layer from being prone to edge collapse or falling off due to excessive stress during the forming process, and improving the structural reliability of the manufactured back contact cell.

[0173] Furthermore, in the case that the back contact cell further comprises a transparent conductive layer and the first doped silicon layer comprises a doped silicon layer, the thickness of the first doped silicon layer can be adjusted to reduce the consumption of the first doped silicon layer.

[0174] Optionally, in the case that the back contact cell further comprises a transparent conductive layer, and the first doped silicon layer comprises a doped crystalline silicon layer, the thickness of the first doped silicon layer can be greater than or equal to 30 nm and less than or equal to 300 nm. For example, the thickness of the first doped silicon layer can be 30 nm, 40 nm, 50 nm, 60 nm, 80 nm, 100 nm, 120 nm, 130 nm, 140 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, 300 nm, etc. In this way, in the case that the back contact cell comprises a transparent conductive layer and the first doped silicon layer comprises a doped crystalline silicon layer, since the transparent conductive layer can be responsible for collecting and exporting carriers, the thickness requirement of the first doped silicon layer can be appropriately reduced due to the presence of the transparent conductive layer without reducing the carrier collection efficiency. Based on this, when the thickness of the first doped silicon layer is within the above range, the thickness of the first doped silicon layer is small, which is beneficial to reducing the parasitic absorption of the first doped silicon layer and further improving the working efficiency of the manufactured back contact cell. In addition, since the thickness of the first doped silicon layer is small, the formation time of the first doped silicon layer can be reduced, and the manufacturing efficiency is improved.

[0175] Of course, in the case that the manufactured back contact cell does not comprise the above transparent conductive layer, or in the case that the back contact cell comprises a transparent conductive layer, the thickness of the first doped silicon layer can also be set to other appropriate values according to different application scenarios.

[0176] In addition, in some examples, as shown in FIG. 18, the second interface passivation layer 19 and the second doped silicon layer 20 which are sequentially stacked, and the transparent conductive layer 21 provided on the second doped silicon layer 20 all cover part of the region on the side of the first interface passivation layer 12 and the first doped silicon layer 13 away from the semiconductor substrate 11. And / or, the part of the above first interface passivation layer 12, the first doped silicon layer 13, the second interface passivation layer 19 and the second doped silicon layer 20 which are stacked along the thickness direction of the semiconductor substrate 11 is an overlapping region. The second interface passivation layer 19 is in direct contact with the first doped silicon layer 13 in the overlapping region. Among them, in the overlapping region, the second doped silicon layer 20 can be electrically isolated from the first doped silicon layer 13 through the second interface passivation layer 19. Alternatively, at least part of the overlapping region can also be a reverse leakage region, and in the reverse leakage region, the second doped silicon layer 20 is electrically connected to the first doped silicon layer 13 through the second interface passivation layer 19. In this case, in the reverse leakage region, the second doped silicon layer 20 can be electrically connected to the first doped silicon layer 13 through the second interface passivation layer 19 and the first doped silicon layer 13 which has a conductive type opposite to that of the second doped silicon layer 20, to form a built-in diode structure with a lower reverse breakdown voltage, thereby reducing the hot spot risk of the back contact cell.

[0177] Specifically, the reverse leakage region can be continuously distributed or discontinuously distributed along the length direction of the overlapping region. It can be understood that the width of the reverse leakage region along the width direction of the overlapping region and the length of the continuous distribution of the reverse leakage region along the length direction of the overlapping region will affect the size of the leakage current. Specifically, the greater the width of the reverse leakage region and / or the longer the length of the continuous distribution of the reverse leakage region, the greater the leakage current and the lower the hot spot risk, but the forward leakage current will also be larger. Based on this, the width of the reverse leakage region and the length of the continuous distribution of the reverse leakage region can be determined according to the hot spot risk and conversion efficiency requirements of the back contact battery in the actual application scenario, which is not limited here.

[0178] Seventeenth step: as shown in FIG. 19, a first electrode is formed on the part of the transparent conductive layer 21 corresponding to the first doped silicon layer 13, and a second electrode is formed on the part of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0179] Exemplarily, the first electrode and the second electrode can be formed by screen printing, electroplating and the like. Specifically, the material of the first electrode and the second electrode can include any one of silver, aluminum, copper, nickel or titanium and the like, as long as it can be applied to the manufacturing method provided by the embodiments of the present application.

[0180] It should be noted that in addition to the above-mentioned method of forming the insulating mask pattern, the forming method of the insulating mask pattern in Embodiment 1 of the present application can also include at least the following two methods:

[0181] The first method is to form a first doped silicon glass layer on the part of the first doped silicon layer away from the semiconductor substrate at the same time as forming the first doped silicon layer. Based on this, forming an insulating mask pattern on the part of the first doped silicon layer away from the semiconductor substrate can include: as shown in FIGS. 20 and 21, patterning the first doped silicon glass layer 14 to form an insulating mask pattern 15. At this time, compared with the above-mentioned forming process of the insulating mask pattern, this first method can omit the third step and the fourth step. Replace the above-mentioned fifth step with patterning the first doped silicon glass layer.

[0182] Specifically, as shown in FIG. 20 and FIG. 21, the first doped silicon glass layer 14 can be patterned by means of laser irradiation. The compactness of the area of the first doped silicon glass layer 14 irradiated by the laser is deteriorated, and the area is easy to be etched and removed. The compactness of the area of the first doped silicon glass layer 14 not irradiated by the laser is higher, and the area has a mask protection effect. Of course, other methods can also be used to pattern the first doped silicon glass layer 14. In this case, the first doped silicon glass layer 14 described above can be formed at the same time as the first doped silicon layer 13 is formed, without the need to form a corresponding insulating layer by using a deposition process in order to form the insulating mask pattern 15, which is conducive to simplifying the manufacturing process of the back contact cell and improving the manufacturing efficiency of the back contact cell.

[0183] The second method is to form a first doped silicon glass layer on part of the area of the first doped silicon layer away from the semiconductor substrate at the same time as the first doped silicon layer is formed. Based on this, forming the insulating mask pattern on part of the area of the first doped silicon layer away from the semiconductor substrate can also include: forming an insulating layer 16 on the side of the first doped silicon glass layer 14 away from the semiconductor substrate 11, as shown in FIG. 22 to FIG. 24; and patterning the first doped silicon glass layer 14 and the insulating layer 16 to form the insulating mask pattern 15. At this time, compared with the formation process of the insulating mask pattern described above, the second method can omit the third step. Moreover, the fifth step described above needs to be replaced by patterning the first doped silicon glass layer and the insulating layer.

[0184] Specifically, as shown in FIG. 22 to FIG. 24, the insulating layer can be formed on the side of the first doped silicon glass layer 14 away from the semiconductor substrate 11 by using a chemical vapor deposition process or the like. The material of the insulating layer can include aluminum oxide and / or silicon nitride and other insulating materials having a mask protection effect. The thickness of the insulating layer can be set according to actual needs. Next, the patterning of the first doped silicon glass layer 14 and the insulating layer can be realized by using a photolithography combined with etching, laser irradiation or chemical slurry corrosion process or the like. In this case, compared with the insulating mask pattern 15 of the single-layer structure, the insulating mask pattern 15 in this case not only includes the first doped silicon glass layer 14 after patterning, but also includes the insulating layer after patterning, which is conducive to improving the protection effect of the insulating mask pattern 15.

[0185] In addition, in some embodiments, the eighth step can not be performed in the actual manufacturing process. In other words, as shown in FIG. 25, after the first interface passivation layer 12 and the first doped silicon layer 13 not covered by the insulating mask pattern 15 are removed, and before the second interface passivation layer 19 and the second doped silicon layer 20 are formed, the insulating mask pattern 15 is not removed. At this time, the presence of the insulating mask pattern 15 can separate the first doped silicon layer 13 and the second doped silicon layer 20 along the thickness direction of the semiconductor substrate 11, thereby inhibiting the forward leakage current, reducing the thickness requirement of the second interface passivation layer 19, reducing the transmission resistance of the second interface passivation layer 19, reducing the transmission loss, improving the carrier collection efficiency of the second doped silicon layer 20, and improving the conversion efficiency of the back contact cell.

[0186] In the case where the eighth step is not performed, in the ninth step, the first passivation layer can be formed only on the second surface of the semiconductor substrate after the texturing process. Alternatively, the first passivation layer can be formed on both the first surface and the second surface of the semiconductor substrate.

[0187] In addition, in some examples, in the case where the first doped silicon layer is a doped polysilicon layer, the back contact cell can further include an amorphous silicon layer disposed on the side of the first doped silicon layer away from the semiconductor substrate. In this case, the amorphous silicon layer can passivate the side of the first doped silicon layer away from the semiconductor substrate, reduce the number of surface defects on the side of the first doped silicon layer away from the semiconductor substrate, and improve the conversion efficiency of the back contact cell. In addition, the presence of the amorphous silicon layer can prevent the etchant used to etch the second interface passivation layer and the second doped silicon layer from affecting the first doped silicon layer, further improving the formation quality of the first doped silicon layer. In addition, since the work function difference between the amorphous silicon layer and the transparent conductive layer is smaller than the work function difference between the doped polysilicon layer and the transparent conductive layer, i.e., the contact potential barrier between the amorphous silicon layer and the transparent conductive layer is smaller than the contact potential barrier between the doped polysilicon layer and the transparent conductive layer, the contact resistance between the amorphous silicon layer and the transparent conductive layer is smaller than the contact resistance between the doped polysilicon layer and the transparent conductive layer. Therefore, compared with the case where the first doped silicon layer directly contacts the transparent conductive layer, disposing the amorphous silicon layer on the side of the first doped silicon layer away from the semiconductor substrate can achieve more reasonable band matching, reduce the contact resistance, and enable the back contact cell to effectively convert sunlight into electrical energy, thereby improving the photoelectric conversion efficiency of the back contact cell.

[0188] Specifically, the amorphous silicon layer is formed by high-temperature laser modification of the surface of the first doped silicon layer when the second interface passivation layer and the second doped silicon layer are removed by laser. In addition, the amorphous silicon layer can be located on part of the area at the bottom of the opening region of the second interface passivation layer and the second doped silicon layer, or can cover each area at the bottom of the opening region.

[0189] In addition, the amorphous silicon layer can be continuously distributed in the opening region of the second interface passivation layer and the second doped silicon layer, and disposed on the side of the first doped silicon layer away from the semiconductor substrate; or discontinuously distributed, for example, in the form of scattered point distribution.

[0190] Embodiment 2

[0191] The embodiment 2 only details the steps different from the embodiment 1, and the same steps can refer to the above description of the embodiment 1, which will not be repeated in the embodiment 2. The embodiment 2 is different from the embodiment 1 in that the first passivation layer formed in the eighth step of the embodiment 2 includes an intrinsic silicon passivation layer, and a reflection reduction layer is formed after the formation of the laminated second interface passivation layer and the second doped silicon layer. The embodiment 2 is described in detail as follows:

[0192] First step: providing a semiconductor substrate. The semiconductor substrate has opposite first and second surfaces.

[0193] Second step: as shown in FIG. 2, along the thickness direction of the semiconductor substrate 11, a laminated first interface passivation layer 12 and a first doped silicon layer 13 are sequentially formed on the first surface of the semiconductor substrate 11.

[0194] Third step: as shown in FIG. 3, the first doped silicon glass layer is removed.

[0195] Fourth step: as shown in FIG. 4 and FIG. 5, an insulating layer 16 is formed on the side of the first doped silicon layer 13 away from the semiconductor substrate 11.

[0196] Fifth step: as shown in FIG. 6, the insulating layer is patterned to form an insulating mask pattern 15.

[0197] Sixth step: as shown in FIG. 7, the first interface passivation layer 12 and the first doped silicon layer 13 not covered by the insulating mask pattern 15 are removed.

[0198] Seventh step: as shown in FIG. 8 and FIG. 9, the surface of the region exposed outside the insulating mask pattern 15 on the first surface and the second surface are subjected to texturing treatment.

[0199] Among them, the operations in the first step to the seventh step of the manufacturing method provided by the embodiment 2 are the same as the operations in the first step to the seventh step of the manufacturing method provided by the embodiment 1, and can refer to the description in the embodiment 1, which will not be repeated here. After the texturing treatment, the insulating mask pattern 15 in the manufacturing method provided by the embodiment 2 is retained and not removed.

[0200] The eighth step is shown in FIG. 26, forming a first passivation layer 17 on the second surface of the semiconductor substrate 11. The first passivation layer 17 includes an intrinsic silicon passivation layer. In this case, the intrinsic silicon passivation layer has a high hydrogen content, which can make the first passivation layer 17 have a high passivation effect on the second surface of the semiconductor substrate 11, further improving the conversion efficiency of the back contact cell manufactured. The first passivation layer can be hydrogen implanted, i.e. hydrogen supplemented, to the first doped silicon layer, which can improve the passivation effect of the first doped silicon layer. Moreover, the manufacturing temperature of the intrinsic silicon passivation layer is relatively low, and does not need to be activated by high-temperature annealing, which is conducive to reducing the manufacturing cost of the back contact cell.

[0201] In addition, the eighth step of the manufacturing method provided in Embodiment 2 can only form the first passivation layer on the second surface. Alternatively, the first passivation layer can be formed on the second surface side, and the semiconductor substrate side and at least part of the first surface side can also be coated with the first passivation layer.

[0202] The ninth step is shown in FIG. 27, forming a second interface passivation layer 19 and a second doped silicon layer 20 in sequence on the first surface of the semiconductor substrate 11 in the thickness direction of the semiconductor substrate 11. The second doped silicon layer 20 and the first doped silicon layer 13 have opposite conductivity types.

[0203] The operation of the ninth step of the manufacturing method provided in Embodiment 2 is the same as that of the ninth step of the manufacturing method provided in Embodiment 1, and can refer to the description in Embodiment 1 above, which will not be repeated here. In addition, in the case where the first passivation layer is an intrinsic silicon passivation layer and the second interface passivation layer is an intrinsic silicon layer, the manufacturing method provided in the embodiments of the present application does not specifically limit the formation sequence of the first passivation layer and the second interface passivation layer. The first passivation layer can be formed first, and then the second interface passivation layer can be formed. Alternatively, the second interface passivation layer can be formed first, and then the first passivation layer can be formed.

[0204] The tenth step is shown in FIG. 28, forming an anti-reflection layer on the second surface of the semiconductor substrate 11 to reduce the reflectivity of the back contact cell on the second surface side, further improving the conversion efficiency of the back contact cell. The material of the anti-reflection layer 18 can be determined according to the actual application scenario, which will not be specifically limited here. For example, the anti-reflection layer 18 can include a silicon nitride layer. Secondly, when the anti-reflection layer 18 is formed on the second surface of the semiconductor substrate 11, the anti-reflection layer 18 can also be formed on the side surface of the semiconductor substrate 11 and at least part of the first surface of the semiconductor substrate 11. Therefore, before the operation step, a wet etching process or the like can be used to remove the anti-reflection layer 18 coated on at least part of the first surface of the semiconductor substrate 11. After the removal, the anti-reflection layer 18 on the side surface of the semiconductor substrate 11 can be completely retained or partially retained.

[0205] In addition, in actual application, in some examples, the manufacturing method provided in Embodiment 2 can also include the first surface including the first region and the second region, and the second region including the groove. In this case, when the second doped silicon layer is a doped amorphous silicon layer, after the second interface passivation layer and the second doped silicon layer are sequentially formed on the first surface along the thickness direction of the semiconductor substrate, the manufacturing method of the back contact cell can further include a tenth step of performing laser irradiation on the second doped silicon layer on the groove bottom surface to perform crystallization treatment on the second doped silicon layer. The crystallization treatment mode, treatment degree and treatment effect can be referred to the foregoing, and will not be described here again. In addition, the tenth step can also not be performed.

[0206] A twelfth step: as shown in FIG. 29, the second interface passivation layer 19 and the second doped silicon layer 20 on the first interface passivation layer 12 and the first doped silicon layer 13 are removed to expose part of the first interface passivation layer 12 and the first doped silicon layer 13.

[0207] A thirteenth step: as shown in FIG. 30 and FIG. 31, a transparent conductive layer 21 is formed to cover the first doped silicon layer 13 and the second doped silicon layer 20 away from the semiconductor substrate 11. The transparent conductive layer 21 is formed with a penetrating isolation groove 22 to separate the part of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 from the part of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0208] A fourteenth step: as shown in FIG. 32, a first electrode is formed on the part of the transparent conductive layer 21 corresponding to the first doped silicon layer 13, and a second electrode is formed on the part of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0209] It should be noted that, in addition to the above-mentioned method of forming the insulating mask pattern, the method of forming the insulating mask pattern in Embodiment 2 can also include at least the following two methods:

[0210] It should be noted that, in addition to the above-mentioned method of forming the insulating mask pattern, the method of forming the insulating mask pattern in Embodiment 2 can also include at least the following two methods:

[0211] The first, while forming the first doped silicon layer, a first doped silicon glass layer is formed on a partial region of the first doped silicon layer away from the semiconductor substrate. Based on this, forming the insulating mask pattern on the partial region of the first doped silicon layer away from the semiconductor substrate can include: as shown in FIGS. 20 and 21, performing a patterning process on the first doped silicon glass layer 14 to form the insulating mask pattern 15. At this time, relative to the formation process of the insulating mask pattern described above, the first mode can omit the third step and the fourth step. The fifth step described above is replaced by performing a patterning process on the first doped silicon glass layer.

[0212] The second, while forming the first doped silicon layer, a first doped silicon glass layer is formed on a partial region of the first doped silicon layer away from the semiconductor substrate. Based on this, forming the insulating mask pattern on the partial region of the first doped silicon layer away from the semiconductor substrate can also include: as shown in FIGS. 22 to 24, forming an insulating layer 16 on the side of the first doped silicon glass layer 14 away from the semiconductor substrate 11; and performing a patterning process on the first doped silicon glass layer 14 and the insulating layer 16 to form the insulating mask pattern 15. At this time, relative to the formation process of the insulating mask pattern described above, the second mode can omit the third step. And, the fifth step described above needs to be replaced by performing a patterning process on the first doped silicon glass layer and the insulating layer.

[0213] The specific formation process of the above-mentioned first and second insulating mask patterns can refer to the specific formation process of the first and second insulating mask patterns in Embodiment 1, which will not be described here.

[0214] In addition, in the actual manufacturing process, the insulating mask pattern can also be removed at the same time as performing the seventh step operation, or after performing the seventh step operation, and before performing the eighth step operation described above.

[0215] In addition, in some embodiments, when the first doped silicon layer is a doped polysilicon layer, the back contact cell can further include an amorphous silicon layer disposed on the side of the first doped silicon layer facing away from the semiconductor substrate. In this case, the amorphous silicon layer can passivate the side of the first doped silicon layer facing away from the semiconductor substrate, reduce the number of surface defects on the side of the first doped silicon layer facing away from the semiconductor substrate, and improve the conversion efficiency of the back contact cell. In addition, the presence of the amorphous silicon layer can prevent the etchant used to etch the second interface passivation layer and the second doped silicon layer from affecting the first doped silicon layer, further improving the formation quality of the first doped silicon layer. Furthermore, since the difference in work function between the amorphous silicon layer and the transparent conductive layer is smaller than the difference in work function between the doped polysilicon layer and the transparent conductive layer, i.e., the contact potential barrier between the amorphous silicon layer and the transparent conductive layer is smaller than the contact potential barrier between the doped polysilicon layer and the transparent conductive layer, the contact resistance between the amorphous silicon layer and the transparent conductive layer is smaller than the contact resistance between the doped polysilicon layer and the transparent conductive layer. Therefore, compared to the case where the first doped silicon layer directly contacts the transparent conductive layer, disposing the amorphous silicon layer on the side of the first doped silicon layer facing away from the semiconductor substrate can achieve a more reasonable band matching, reduce the contact resistance, and enable the back contact cell to effectively convert sunlight into electrical energy, thereby improving the photoelectric conversion efficiency of the back contact cell.

[0216] Specifically, the amorphous silicon layer is formed by high-temperature laser modification of the surface of the first doped silicon layer when the second interface passivation layer and the second doped silicon layer are removed by laser. In addition, the amorphous silicon layer can be located on part of the bottom of the opening region of the second interface passivation layer and the second doped silicon layer, or can cover each region of the bottom of the opening region.

[0217] In addition, the amorphous silicon layer can be continuously distributed in the opening region of the second interface passivation layer and the second doped silicon layer and disposed on the side of the first doped silicon layer facing away from the semiconductor substrate, or can be discontinuously distributed, e.g., in the form of scattered dots.

[0218] Embodiment 3

[0219] This embodiment 3 only describes the steps different from those of embodiment 1 in detail. The same steps can refer to the description of embodiment 1, which will not be repeated here. The difference between embodiment 3 and embodiment 1 is that in embodiment 3, the second interface passivation layer and the second doped silicon layer are formed first, and then the first passivation layer and the anti-reflection layer are formed. The following describes embodiment 3 in detail.

[0220] Step 1: Provide a semiconductor substrate. The semiconductor substrate has opposite first and second surfaces.

[0221] Second step: As shown in FIG. 2, a first interface passivation layer 12 and a first doped silicon layer 13 are formed in sequence on the first surface of the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11.

[0222] Third step: As shown in FIG. 3, the first doped silicon glass layer is removed.

[0223] Fourth step: As shown in FIG. 4 and FIG. 5, an insulating layer 16 is formed on the side of the first doped silicon layer 13 away from the semiconductor substrate 11.

[0224] Fifth step: As shown in FIG. 6, the insulating layer 16 is subjected to a patterning process to form an insulating mask pattern 15.

[0225] Sixth step: As shown in FIG. 7, the first interface passivation layer 12 and the first doped silicon layer 13 that are not covered by the insulating mask pattern 15 are removed.

[0226] Seventh step: As shown in FIG. 11 and FIG. 12, a texturing process is performed on the surface of the region exposed outside the insulating mask pattern 15 on the first surface and the second surface.

[0227] Eighth step: As shown in FIG. 8 and FIG. 9, the insulating mask pattern is removed.

[0228] In the manufacturing method provided in Embodiment 3, the operations of the first step to the eighth step are the same as those of the first step to the eighth step in the manufacturing method provided in Embodiment 1, and will not be described here.

[0229] Ninth step: As shown in FIG. 33, a second interface passivation layer 19 and a second doped silicon layer 20 are formed in sequence on the first surface along the thickness direction of the semiconductor substrate 11. The second doped silicon layer 20 and the first doped silicon layer 13 are of opposite conductivity types.

[0230] Tenth step: As shown in FIG. 34, the first passivation layer 17 is formed on the second surface of the semiconductor substrate 11, and the first passivation layer 17 is formed on the first surface of the semiconductor substrate 11.

[0231] Eleventh step: As shown in FIG. 35, an anti-reflection layer is formed on the second surface of the semiconductor substrate 11.

[0232] In the manufacturing method provided in Embodiment 3, the manner of forming the corresponding structures in the ninth step to the eleventh step is the same as that of forming the corresponding structures in the ninth step, the tenth step, and the twelfth step in the manufacturing method provided in Embodiment 1, and will not be described here.

[0233] Twelfth step: The first passivation layer provided on the second surface of the semiconductor substrate is processed by laser annealing to activate the passivation performance of the first passivation layer.

[0234] It should be noted that the manufacturing method provided in Embodiment 1 needs to perform annealing treatment after forming the first passivation layer (or forming the first passivation layer and the antireflection layer) to activate the passivation performance. The manufacturing method provided in Embodiment 3 activates the passivation performance of the first passivation layer by laser treatment after forming the first passivation layer (or forming the first passivation layer and the antireflection layer), and the processing temperature of the laser annealing is relatively low, which can reduce the influence of high temperature on the formed structure and is conducive to reducing the manufacturing cost. In some examples, the twelfth step can also be omitted. In other examples, the passivation performance of the first passivation layer can be activated at the same time when the antireflection layer is formed on the second side of the semiconductor substrate 11 in the eleventh step, without separate annealing.

[0235] Thirteenth step: As shown in FIG. 36, the antireflection layer 18 plated around the first side and the first passivation layer 17 formed on the first side need to be removed in sequence. At this time, the portions of the first passivation layer 17 and the antireflection layer 18 plated around the side of the semiconductor substrate 11 can be all retained or partially retained. The above removal operation can be performed in a chain cleaning device, and then the semiconductor substrate 11 can be subjected to metal ion cleaning (i.e., RCA cleaning) after the above removal operation and before the subsequent operation, so as to remove the pollution and slight scratches caused by the semiconductor substrate 11 in the chain cleaning device. In some embodiments, the cleaning operation can also not be performed.

[0236] In some examples, the thirteenth step can also not be performed.

[0237] Fourteenth step: As shown in FIG. 37, part of the second interface passivation layer 19 and the second doped silicon layer 20 located on the first interface passivation layer 12 and the first doped silicon layer 13 are removed to expose part of the first interface passivation layer 12 and the first doped silicon layer 13.

[0238] Fifteenth step: As shown in FIG. 38, a transparent conductive layer 21 covering the first doped silicon layer 13 and the second doped silicon layer 20 away from the semiconductor substrate 11 is formed. The transparent conductive layer 21 is formed with a through isolation groove 22 to disconnect the part of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 from the part of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0239] Sixteenth step: As shown in FIG. 39, a first electrode is formed on the part of the transparent conductive layer 21 corresponding to the first doped silicon layer 13, and a second electrode is formed on the part of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0240] In the manufacturing method provided in Embodiment 3, the operations of the fourteenth to sixteenth steps are the same as those of the fifteenth to seventeenth steps in the manufacturing method provided in Embodiment 1, and will not be repeated here.

[0241] It is worth noting that, unlike the manufacturing method provided in Embodiment 1, the manufacturing method provided in Embodiment 3 is to form the laminated second interface passivation layer and the second doped silicon layer on the first surface after the texturing treatment is performed on the surface of the region exposed outside the insulating mask pattern and the second surface, and before the first passivation layer is formed on the second surface after the texturing treatment is performed on the semiconductor substrate. In this case, the manufacturing method provided in the embodiments of the present application can be added as another optional example, which is conducive to improving the applicability of the manufacturing method provided in the embodiments of the present application in different application scenarios. At the same time, when the first passivation layer is formed on the second surface after the texturing treatment is performed on the semiconductor substrate, the first passivation layer can be plated around the side surface of the semiconductor substrate and at least part of the region of the first surface. Based on this, when the formation sequence of the laminated second interface passivation layer and the second doped silicon layer is set after the texturing treatment and before the formation of at least the first passivation layer, it is no longer necessary to remove at least the part of the first passivation layer plated on the side of the first surface before the laminated second interface passivation layer and the second doped silicon layer are formed, thereby reducing the process steps. The decision whether to remove the first passivation layer plated on the side of the first surface after at least the first passivation layer is formed can be determined according to actual needs, reducing manufacturing requirements. Moreover, in this case, the corresponding structure on the side of the first surface can be made first, and then the corresponding film layers (the first passivation layer and the anti-reflection layer) on the side of the second surface can be made, reducing the number of turning over and reducing the risk of damage. In addition, in the case where the material of the second doped silicon layer includes at least one of amorphous silicon, microcrystalline silicon and nanocrystalline silicon, the structure located on the side of the first surface is made first, and then the structure located on the side of the second surface is made. Moreover, the thermal stability of amorphous silicon, microcrystalline silicon and nanocrystalline silicon is poorer than that of polycrystalline silicon and single crystal silicon, so only laser annealing that can be locally processed can be used, and rapid annealing cannot be used.

[0242] It should be noted that, in addition to forming the insulating mask pattern in the manner described above, the formation of the insulating mask pattern in Embodiment 3 of the present application can also include at least the following two ways:

[0243] The first way is to form a first doped silicon glass layer on part of the region on the side of the first doped silicon layer away from the semiconductor substrate while forming the first doped silicon layer. Based on this, forming the insulating mask pattern on part of the region on the side of the first doped silicon layer away from the semiconductor substrate can include: as shown in FIGS. 20 and 21, patterning the first doped silicon glass layer 14 to form the insulating mask pattern 15. At this time, compared with the formation process of the insulating mask pattern described above, this first way can omit the third step and the fourth step. The fifth step described above is replaced by patterning the first doped silicon glass layer.

[0244] The second way is to form the first doped silicon glass layer on the partial region of the first doped silicon layer on the side of the first doped silicon layer away from the semiconductor substrate. Based on this, the forming of the insulating mask pattern on the partial region of the first doped silicon layer on the side of the first doped silicon layer away from the semiconductor substrate can also include: as shown in FIGS. 22-24, forming the insulating layer 16 on the side of the first doped silicon glass layer 14 away from the semiconductor substrate 11; and performing a patterning process on the first doped silicon glass layer 14 and the insulating layer 16 to form the insulating mask pattern 15. At this time, compared with the forming process of the insulating mask pattern described above, the third step can be omitted in the second way. Moreover, the fifth step described above needs to be replaced by performing a patterning process on the first doped silicon glass layer and the insulating layer.

[0245] The specific forming process of the first and second insulating mask patterns described above can refer to the specific forming process of the first and second insulating mask patterns in Embodiment 1, which will not be described here again.

[0246] In addition, in the actual manufacturing process, the operation of the eighth step described above can also not be performed. In other words, as shown in FIG. 39, after removing the first interface passivation layer 12 and the first doped silicon layer 13 not covered by the insulating mask pattern 15, and before forming the laminated second interface passivation layer 19 and the second doped silicon layer 20, the insulating mask pattern 15 is not removed. At this time, the existence of the insulating mask pattern 15 can separate the first doped silicon layer 13 and the second doped silicon layer 20 along the thickness direction of the semiconductor substrate 11, inhibit the forward leakage, and at the same time, reduce the thickness requirement of the second interface passivation layer 19, reduce the transmission resistance of the second interface passivation layer 19, reduce the transmission loss, and be beneficial to improve the carrier collection efficiency of the second doped silicon layer 20 and improve the conversion efficiency of the back contact cell.

[0247] In the case where the eighth step is not performed, in the tenth step, the first passivation layer can be formed only on the second surface of the semiconductor substrate after the texturing process is performed. Alternatively, the first passivation layer can also be formed on both the first surface and the second surface of the semiconductor substrate.

[0248] In addition, in some embodiments, when the first doped silicon layer is a doped polysilicon layer, the back contact cell can further include an amorphous silicon layer disposed on the side of the first doped silicon layer facing away from the semiconductor substrate. In this case, the amorphous silicon layer can passivate the side of the first doped silicon layer facing away from the semiconductor substrate, reduce the number of surface defects on the side of the first doped silicon layer facing away from the semiconductor substrate, and improve the conversion efficiency of the back contact cell. In addition, the presence of the amorphous silicon layer can prevent the etchant used to etch the second interface passivation layer and the second doped silicon layer from affecting the first doped silicon layer, further improving the formation quality of the first doped silicon layer. In addition, since the difference in work function between the amorphous silicon layer and the transparent conductive layer is smaller than the difference in work function between the doped polysilicon layer and the transparent conductive layer, i.e., the contact potential barrier between the amorphous silicon layer and the transparent conductive layer is smaller than the contact potential barrier between the doped polysilicon layer and the transparent conductive layer, the contact resistance between the amorphous silicon layer and the transparent conductive layer is smaller than the contact resistance between the doped polysilicon layer and the transparent conductive layer. Therefore, compared to the case where the first doped silicon layer directly contacts the transparent conductive layer, disposing the amorphous silicon layer on the side of the first doped silicon layer facing away from the semiconductor substrate can achieve a more reasonable band matching, reduce the contact resistance, and enable the back contact cell to effectively convert sunlight into electrical energy, thereby improving the photoelectric conversion efficiency of the back contact cell.

[0249] Specifically, the amorphous silicon layer is formed by high-temperature laser modification of the surface of the first doped silicon layer when the second interface passivation layer and the second doped silicon layer are removed by laser. In addition, the amorphous silicon layer can be located on part of the bottom of the opening region of the second interface passivation layer and the second doped silicon layer, or can cover each region of the bottom of the opening region.

[0250] In addition, the amorphous silicon layer can be continuously distributed in the opening region of the second interface passivation layer and the second doped silicon layer and disposed on the side of the first doped silicon layer facing away from the semiconductor substrate, or can be discontinuously distributed, e.g., in the form of discrete dots.

[0251] Embodiment 4

[0252] This embodiment 4 only describes the steps different from those of embodiment 1 in detail, and the same steps can refer to the description of embodiment 1. Embodiment 4 is different from embodiment 1 in that the first passivation layer formed in the eighth step of embodiment 4 includes a second doped silicon glass layer and / or an aluminum oxide layer. The following describes embodiment 4 in detail.

[0253] Step 1: Provide a semiconductor substrate. The semiconductor substrate has opposite first and second surfaces.

[0254] Second step: as shown in FIG. 2, along the thickness direction of the semiconductor substrate 11, a first interface passivation layer 12 and a first doped silicon layer 13 are formed on the first surface of the semiconductor substrate 11 in sequence.

[0255] Third step: as shown in FIG. 3, the first doped silicon glass layer is removed.

[0256] Fourth step: as shown in FIG. 4 and FIG. 5, an insulating layer 16 is formed on the side of the first doped silicon layer 13 away from the semiconductor substrate 11.

[0257] Fifth step: as shown in FIG. 6, the insulating layer 16 is subjected to a patterning process to form an insulating mask pattern 15.

[0258] Sixth step: as shown in FIG. 7, the first interface passivation layer 12 and the first doped silicon layer 13 that are not covered by the insulating mask pattern 15 are removed.

[0259] Seventh step: as shown in FIG. 8 and FIG. 9, a texturing process is performed on the surface of the region of the first surface exposed outside the insulating mask pattern 15 and the second surface.

[0260] Eighth step: as shown in FIG. 26, a first passivation layer 17 is formed on the second surface of the semiconductor substrate 11.

[0261] The first passivation layer can include any film layer having a passivation effect, such as a second doped silicon glass layer and / or an aluminum oxide layer, as long as it can be applied to the manufacturing method provided in the embodiments. The conductive type of the dopant in the second doped silicon glass layer is the same as that of the first doped silicon layer. In this case, compared with the intrinsic silicon passivation layer, the second doped silicon glass layer and the aluminum oxide layer have higher light transmission characteristics, so compared with the first passivation layer including the intrinsic silicon passivation layer, the parasitic absorption of the first passivation layer can be reduced when the first passivation layer includes the second doped silicon glass layer and / or the aluminum oxide layer, which is conducive to improving the utilization rate of light by the back contact cell. In addition, the second doped silicon glass layer is also doped with a dopant of the same conductive type as the first doped silicon layer, so that the first passivation layer can not only perform chemical passivation on the side of the second surface of the semiconductor substrate, but also perform field passivation on the side of the second surface of the semiconductor substrate, which reduces the carrier recombination rate on the side of the second surface and is conducive to improving the carrier collection efficiency of the first doped silicon layer and the second doped silicon layer. Compared with the need for separate deposition, the second doped silicon glass layer can be formed by a diffusion process, which simplifies the manufacturing difficulty of the first passivation layer.

[0262] In addition, in the case where the first passivation layer is the second doped silicon glass layer, the first passivation layer can be formed on the second surface of the semiconductor substrate after the texturing process is performed, and the first passivation layer can also be formed on the first surface side. In the case where the first passivation layer is the aluminum oxide layer, the first passivation layer can be formed only on the second surface, and the first passivation layer can not be formed on the first surface side.

[0263] Ninth step: As shown in FIG. 40, a reflection-reducing layer is formed on the second surface of the semiconductor substrate 11.

[0264] Tenth step: The first passivation layer disposed on the second surface of the semiconductor substrate is processed by laser annealing to activate the passivation performance. In some examples, the tenth step can also be omitted. In other examples, the passivation performance of the first passivation layer can be activated at the same time when the reflection-reducing layer is formed on the second surface of the semiconductor substrate 11 in the ninth step, without a separate annealing.

[0265] Eleventh step: As shown in FIG. 41, the reflection-reducing layer 18 plated around the first surface side and the first passivation layer 17 formed on the first surface side are sequentially removed.

[0266] Twelfth step: As shown in FIGS. 42 and 43, a laminated second interface passivation layer 19 and a second doped silicon layer 20 are sequentially formed on the first surface in the thickness direction of the semiconductor substrate 11. The second doped silicon layer 20 and the first doped silicon layer 13 are opposite in conductive type.

[0267] Thirteenth step: As shown in FIG. 44, part of the second interface passivation layer 19 and the second doped silicon layer 20 located on the first interface passivation layer 12 and the first doped silicon layer 13 are removed to expose part of the first interface passivation layer 12 and the first doped silicon layer 13.

[0268] Fourteenth step: As shown in FIG. 45, a transparent conductive layer 21 is formed covering the first doped silicon layer 13 and the second doped silicon layer 20 away from the semiconductor substrate 11 side. An isolation groove 22 is formed through the transparent conductive layer 21 to disconnect the part of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 from the part of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0269] Fifteenth step: As shown in FIG. 46, a first electrode is formed on the part of the transparent conductive layer 21 corresponding to the first doped silicon layer 13, and a second electrode is formed on the part of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0270] The first step to the fifteenth step in the manufacturing method provided by the embodiment 4 are the same as the first step to the seventh step and the ninth step to the seventeenth step in the manufacturing method provided by the embodiment 1 except that the first step to the seventh step in the manufacturing method provided by the embodiment 4 retain the insulating mask pattern and the first passivation layer can further include the second doped silicon glass layer after the seventh step operation, which will not be repeated here.

[0271] It should be noted that in addition to the formation of the insulating mask pattern in the manner described above, the formation of the insulating mask pattern in the embodiment 4 of the present application can also include at least the following two ways:

[0272] The first way is that the first doped silicon glass layer is formed on the partial region of the first doped silicon layer away from the semiconductor substrate at the same time when the first doped silicon layer is formed. Based on this, the formation of the insulating mask pattern on the partial region of the first doped silicon layer away from the semiconductor substrate can include: as shown in FIGS. 20 and 21, the first doped silicon glass layer 14 is patterned to form the insulating mask pattern 15. At this time, the first way can omit the third step and the fourth step with respect to the formation process of the insulating mask pattern described above. The fifth step described above is replaced by patterning the first doped silicon glass layer.

[0273] The second way is that the first doped silicon glass layer is formed on the partial region of the first doped silicon layer away from the semiconductor substrate at the same time when the first doped silicon layer is formed. Based on this, the formation of the insulating mask pattern on the partial region of the first doped silicon layer away from the semiconductor substrate can also include: as shown in FIGS. 22 to 24, the insulating layer 16 is formed on the side of the first doped silicon glass layer 14 away from the semiconductor substrate 11, and the first doped silicon glass layer 14 and the insulating layer 16 are patterned to form the insulating mask pattern 15. At this time, the second way can omit the third step with respect to the formation process of the insulating mask pattern described above. And the fifth step described above is replaced by patterning the first doped silicon glass layer and the insulating layer.

[0274] The specific formation process of the first and second insulating mask patterns described above can refer to the specific formation process of the first and second insulating mask patterns in the embodiment 1, which will not be repeated here.

[0275] In addition, in the actual manufacturing process, the insulating mask pattern can also be removed at the same time as the seventh step operation is performed, or after the seventh step operation is performed and before the eighth step operation described above is performed. At this time, in the eighth step, the first passivation layer is formed on the second surface of the semiconductor substrate after the texturing process is performed, and the first passivation layer is also formed on the first surface to perform hydrogen implantation on the first doped silicon layer through the first passivation layer to reduce the number of defects on the side of the first doped silicon layer away from the semiconductor substrate.

[0276] In addition, in some embodiments, when the first doped silicon layer is a doped polysilicon layer, the back contact cell can further include an amorphous silicon layer disposed on the side of the first doped silicon layer facing away from the semiconductor substrate. In this case, the amorphous silicon layer can passivate the side of the first doped silicon layer facing away from the semiconductor substrate, reduce the number of surface defects on the side of the first doped silicon layer facing away from the semiconductor substrate, and improve the conversion efficiency of the back contact cell. In addition, the presence of the amorphous silicon layer can prevent the etchant used to etch the second interface passivation layer and the second doped silicon layer from affecting the first doped silicon layer, further improving the formation quality of the first doped silicon layer. In addition, since the difference in work function between the amorphous silicon layer and the transparent conductive layer is smaller than the difference in work function between the doped polysilicon layer and the transparent conductive layer, i.e., the contact potential barrier between the amorphous silicon layer and the transparent conductive layer is smaller than the contact potential barrier between the doped polysilicon layer and the transparent conductive layer, the contact resistance between the amorphous silicon layer and the transparent conductive layer is smaller than the contact resistance between the doped polysilicon layer and the transparent conductive layer. Therefore, compared to the case where the first doped silicon layer directly contacts the transparent conductive layer, disposing the amorphous silicon layer on the side of the first doped silicon layer facing away from the semiconductor substrate can achieve a more reasonable band matching, reduce the contact resistance, and enable the back contact cell to effectively convert sunlight into electrical energy, thereby improving the photoelectric conversion efficiency of the back contact cell.

[0277] Specifically, the amorphous silicon layer is formed by high-temperature laser modification of the surface of the first doped silicon layer when the second interface passivation layer and the second doped silicon layer are removed by laser. In addition, the amorphous silicon layer can be located on part of the bottom of the opening region of the second interface passivation layer and the second doped silicon layer, or can cover each region of the bottom of the opening region.

[0278] In addition, the amorphous silicon layer can be continuously distributed in the opening region of the second interface passivation layer and the second doped silicon layer, and disposed on the side of the first doped silicon layer facing away from the semiconductor substrate; or it can be discontinuously distributed, for example, in the form of scattered dots.

[0279] In the above description, the patterning, etching, and other technical details of each layer are not described in detail. However, those skilled in the art will understand that various technical means can be used to form layers, regions, and the like with the desired shape. In addition, those skilled in the art can design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0280] The above described embodiments of the application have been described. However, these embodiments are merely meant to be illustrative of the application and not limiting thereof. The scope of the application is defined by the appended claims and their equivalents. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the application.

Claims

1. A method of manufacturing a back contact cell, wherein, Comprising: providing a semiconductor substrate; the semiconductor substrate has opposite first and second faces; forming a first interface passivation layer and a first doped silicon layer in this order on the first face of the semiconductor substrate along the thickness direction of the semiconductor substrate; forming an insulating mask pattern on a partial region of the first doped silicon layer on the side facing away from the semiconductor substrate; removing the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern; performing a texturizing treatment on the region of the first face exposed outside the insulating mask pattern and the second face; forming a first passivation layer on the second face of the semiconductor substrate after the texturizing treatment; forming a second interface passivation layer and a second doped silicon layer in this order on the first face along the thickness direction of the semiconductor substrate; the second doped silicon layer and the first doped silicon layer are of opposite conductivity types; removing a portion of the second interface passivation layer and the second doped silicon layer on the first interface passivation layer and the first doped silicon layer to expose a portion of the first interface passivation layer and the first doped silicon layer.

2. The method of manufacturing a back contact cell according to claim 1, wherein, The method further comprises: removing the insulating mask pattern at the same time as or after the texturizing treatment on the region of the first face exposed outside the insulating mask pattern and the second face; or retaining the insulating mask pattern after the texturizing treatment on the region of the first face exposed outside the insulating mask pattern and the second face.

3. The method of manufacturing a back contact cell according to claim 1 or 2, wherein, the forming a first interface passivation layer and a first doped silicon layer in this order on the first face of the semiconductor substrate comprises: forming a first doped silicon glass layer on the side of the first doped silicon layer facing away from the semiconductor substrate at the same time as forming the first interface passivation layer and the first doped silicon layer in this order on the first face of the semiconductor substrate; the forming an insulating mask pattern on a partial region of the first doped silicon layer on the side facing away from the semiconductor substrate comprises: patterning the first doped silicon glass layer to form the insulating mask pattern; or, the forming a first interface passivation layer and a first doped silicon layer in this order on the first face of the semiconductor substrate comprises: forming a first doped silicon glass layer on the side of the first doped silicon layer facing away from the semiconductor substrate at the same time as forming the first interface passivation layer and the first doped silicon layer in this order on the first face of the semiconductor substrate; the forming an insulating mask pattern on a partial region of the first doped silicon layer on the side facing away from the semiconductor substrate comprises: forming an insulating layer on the side of the first doped silicon glass layer facing away from the semiconductor substrate; and patterning the first doped silicon glass layer and the insulating layer to form the insulating mask pattern; Or, the forming the first interface passivation layer and the first doped silicon layer on the first surface of the semiconductor substrate in sequence comprises: simultaneously with the forming the first interface passivation layer and the first doped silicon layer on the first surface of the semiconductor substrate in sequence, forming a first doped silicon glass layer on a side of the first doped silicon layer away from the semiconductor substrate. The forming the insulating mask pattern on the partial region of the side of the first doped silicon layer away from the semiconductor substrate comprises: removing the first doped silicon glass layer; forming an insulating layer on the side of the first doped silicon layer away from the semiconductor substrate; and performing a patterning process on the insulating layer to form the insulating mask pattern.

4. The method of manufacturing back contact cells of claim 1, wherein, The forming the first passivation layer on the second surface of the semiconductor substrate comprises: Simultaneously with the forming the first passivation layer on the second surface of the semiconductor substrate, forming the first passivation layer on the first surface of the semiconductor substrate; Removing the first passivation layer on the first surface of the semiconductor substrate.

5. The method of fabricating back contact cells of claim 1, wherein, The first passivation layer comprises an intrinsic amorphous silicon layer; And / or, after the forming the second interface passivation layer and the second doped silicon layer on the first surface in sequence, and before the removing the partial second interface passivation layer and the partial second doped silicon layer on the first interface passivation layer and the first doped silicon layer, the method further comprises: forming an anti-reflection layer on a side of the first passivation layer away from the semiconductor substrate.

6. The method of fabricating back contact cells of claim 1, wherein, The method comprises: after the performing the texturing process on the region of the first surface exposed outside the insulating mask pattern and the second surface, and before the forming the first passivation layer on the second surface of the semiconductor substrate after the performing the texturing process on the semiconductor substrate, performing the forming the second interface passivation layer and the second doped silicon layer on the first surface in sequence.

7. The method of fabricating back contact cells of claim 1, wherein, The first passivation layer comprises a second doped silicon glass layer, and a conductive type of a dopant in the second doped silicon glass layer is the same as a conductive type of the first doped silicon layer; And / or, the forming the first passivation layer on the second surface of the semiconductor substrate comprises: forming the first passivation layer and an anti-reflection layer on the second surface of the semiconductor substrate in sequence along a thickness direction of the semiconductor substrate.

8. The method of fabricating back contact cells of claim 1, wherein, After the removing the partial second interface passivation layer and the partial second doped silicon layer on the first interface passivation layer and the first doped silicon layer, the method for manufacturing the back contact cell further comprises: forming a transparent conductive layer covering the first doped silicon layer and the second doped silicon layer away from the semiconductor substrate; the transparent conductive layer is formed with an isolation groove penetrating through the transparent conductive layer, and the isolation groove is used to disconnect a portion of the transparent conductive layer corresponding to the first doped silicon layer from a portion of the transparent conductive layer corresponding to the second doped silicon layer; forming a first electrode on the portion of the transparent conductive layer corresponding to the first doped silicon layer, and forming a second electrode on the portion of the transparent conductive layer corresponding to the second doped silicon layer.

9. The method of manufacturing a back contact cell of claim 8, wherein, An edge portion of the transparent conductive layer adjacent to the isolation groove gradually decreases in thickness along a direction close to the isolation groove.

10. The method of manufacturing a back contact cell according to claim 8 or 9, wherein, The second interface passivation layer and the second doped silicon layer which are stacked in sequence, and the transparent conductive layer disposed on the second doped silicon layer, all cover a partial area of the first interface passivation layer and the first doped silicon layer away from the semiconductor substrate.

11. The method of fabricating back contact cells of claim 1, wherein, The thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 300 nm; And / or, the width of the opening area of the second interface passivation layer and the second doped silicon layer is greater than or equal to 40 μm and less than or equal to 400 μm.

12. The method of fabricating back contact cells of claim 1, wherein, The area of the first surface for forming the first interface passivation layer and the first doped silicon layer has a tower base-like textured structure with a bottom surface and a sidewall; The thickness of the first interface passivation layer on the bottom surface of the tower base-like textured structure is less than the thickness of the first interface passivation layer on the sidewall of the tower base-like textured structure.

13. The method of fabricating back contact cells of claim 1, wherein, The thickness of the second interface passivation layer is greater than or equal to 3 nm and less than or equal to 16 nm.

14. The method of fabricating back contact cells of claim 1, wherein, The first doped silicon layer is a doped polysilicon layer; The back contact cell further comprises an amorphous silicon layer which is located in the opening area of the second interface passivation layer and the second doped silicon layer and disposed on the side of the first doped silicon layer away from the semiconductor substrate.

15. The method of fabricating back contact cells of claim 1, wherein, The removing of the partial second interface passivation layer and the partial second doped silicon layer on the first interface passivation layer and the first doped silicon layer comprises: The removing of the partial second interface passivation layer and the partial second doped silicon layer on the first interface passivation layer and the first doped silicon layer by laser, and the edge portion of the opening area of the second doped silicon layer is treated by laser to form a hole structure in the edge portion of the opening area of the second doped silicon layer.

16. The method of fabricating back contact cells of claim 1, wherein, The first surface comprises a first area and a second area; the second area comprises a groove; The first interface passivation layer and the first doped silicon layer are located in the first area; the second interface passivation layer and the second doped silicon layer are located in the second area and extend from the second area to the first area to cover part of the first interface passivation layer and the first doped silicon layer; The surface of the first area is a polished surface, and the bottom surface of the groove is a textured surface; the thickness of the second doped silicon layer on the textured surface is less than the thickness of the second doped silicon layer on the polished surface.

17. The method of fabricating back contact cells of claim 1, wherein, The first surface comprises a first area and a second area; the second area comprises a groove; the surface of the first area is a polished surface, and the bottom surface of the groove is a textured surface; The first interface passivation layer and the first doped silicon layer are located in the first area; the second interface passivation layer and the second doped silicon layer are located in the second area and extend from the second area to the first area to cover part of the first interface passivation layer and the first doped silicon layer; The distance from the surface of the first area to the bottom surface of the groove of the semiconductor substrate is greater than or equal to 2 μm and less than or equal to 8 μm.

18. The manufacturing method of the back contact cell according to claim 1, the first surface comprises a first area and a second area; the second area comprises a groove; The first interface passivation layer and the first doped silicon layer are located in the first region; the second interface passivation layer and the second doped silicon layer are located in the second region and extend from the second region to the first region to cover part of the first interface passivation layer and the first doped silicon layer; The second doped silicon layer is a doped amorphous silicon layer; The manufacturing method of the back contact cell further includes, after sequentially forming a laminated second interface passivation layer and a second doped silicon layer on the first surface in the thickness direction of the semiconductor substrate: The second doped silicon layer located on the groove bottom surface of the groove is subjected to laser irradiation to perform crystallization treatment on the second doped silicon layer.

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