Instruction classification processing method and apparatus, terminal device, and storage medium

Abstract

The present disclosure relates to the technical field of instruction processing. Disclosed are an instruction classification processing method and apparatus, a terminal device, and a storage medium. The method comprises: when an instruction packet issued by a host computer is received, classifying instructions in the instruction packet; on the basis of the types of the instructions, assigning the instruction packet to parallel threads of the corresponding categories, and caching the instruction packet into cache spaces corresponding to the parallel threads; and when the instruction packet is retrieved, sequentially retrieving the instruction packet from the cache spaces in a storage order, parsing the instruction packet to obtain corresponding function execution signals, and outputting the function execution signals. The method for performing parallel processing and caching on the instructions improves processing efficiency and avoids instruction loss.

Description

Instruction classification processing method and device, terminal equipment and storage medium

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to the Chinese patent application No. 2024112698164, filed on September 11, 2024, and entitled "Instruction classification processing method and device, terminal equipment and storage medium", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of instruction processing, and in particular to an instruction classification processing method, device, terminal equipment and storage medium. BACKGROUND

[0004] In the electronic device development system, communication between devices or chips is necessary, and communication enables interaction between devices or chips. In general, in the communication process, a common bus such as UART, PCIE, etc. is used, and a communication protocol is formulated according to the application scenario to carry interaction instructions. Generally, when a device receives communication, it will parse and execute the corresponding operation according to the formulated protocol. For slow and intermittent control instruction scenarios, this is feasible. However, when a device continuously receives various control instructions from a host computer, if it still parses and executes serially, it will lead to two problems: one is that continuous similar instructions are not completed and subsequent instructions are lost, and the other is that different types of instructions are blocked. Obviously, such a device has limitations and is prone to errors. SUMMARY

[0005] Therefore, the embodiments of the present disclosure provide an instruction classification processing method, which can effectively solve the problems of instruction loss and blocking.

[0006] In a first aspect, the embodiments of the present disclosure provide an instruction classification processing method, comprising:

[0007] When an instruction package issued by a host computer is received, the instructions in the instruction package are classified;

[0008] According to the type of the instructions, the instruction package is allocated to a parallel thread of a corresponding category, and the instruction package is cached in a cache space corresponding to the parallel thread;

[0009] When the instruction package is called, the instruction package is sequentially called from the cache space in the order of storage, and a corresponding function execution signal is obtained by parsing the instruction package, and the function execution signal is output.

[0010] In an embodiment, when the instruction package issued by the host computer is received, the instructions in the instruction package are classified, comprising:

[0011] receive an instruction package from a host computer, determine a communication protocol address of a stored instruction in the instruction package according to a communication protocol;

[0012] determine a kind of the instruction according to an address segment where the communication protocol address is located.

[0013] In an embodiment, the instruction packages in the cache space are sequentially called in a storage order, comprising:

[0014] if there is an instruction package being parsed at present, suspend calling the instruction package from the cache space;

[0015] if there is no instruction package being parsed at present, call the instruction package stored first from the cache space.

[0016] In an embodiment, the parsing the instruction package to obtain a corresponding function execution signal, comprising:

[0017] determine an instruction position of the instruction stored in the instruction package according to a communication protocol, extract the instruction and determine a corresponding communication protocol address;

[0018] parse the instruction, determine a function kind corresponding to the instruction, and generate a corresponding execution signal according to the function kind.

[0019] In an embodiment, after determining the function kind corresponding to the instruction, further comprising:

[0020] determine a matching kind corresponding to the communication protocol address according to the communication protocol address and a preset function matching table;

[0021] if the matching kind and the function kind are different, perform a packet loss operation on the current instruction package.

[0022] In an embodiment, after the instruction package is cached into the cache space corresponding to the parallel thread, further comprising:

[0023] output a storage state of the cache space to provide debugging information.

[0024] In an embodiment, the communication protocol sets a frame bit width and an instruction field, and the determination of the instruction position of the instruction stored in the instruction package, the extraction of the instruction and the determination of the corresponding communication protocol address according to the communication protocol, comprising:

[0025] count and traverse from a package header of the instruction package in the frame bit width, to obtain an instruction under the instruction field and a communication protocol address where the instruction is located.

[0026] In a second aspect, the disclosure further provides an instruction classification processing device, comprising:

[0027] a classification module, configured to classify instructions in the instruction package when the instruction package is received;

[0028] a cache module, configured to distribute the instruction package to a parallel thread of a corresponding category according to the category of the instructions, and cache the instruction package in a cache space corresponding to the parallel thread;

[0029] a parsing module, configured to sequentially call and parse the instruction package from the cache space in a storage order to obtain a corresponding function execution signal when the instruction package is called, and output the function execution signal.

[0030] In a third aspect, the present disclosure provides a terminal device, which comprises a processor and a memory, the memory stores a computer program, and the processor is configured to execute the computer program to implement the instruction classification processing method.

[0031] In a fourth aspect, the present disclosure provides a computer readable storage medium, which stores a computer program, and the computer program implements the instruction classification processing method when executed on a processor.

[0032] The embodiments of the present disclosure have the following beneficial effects:

[0033] The instruction classification processing method of the present disclosure adopts a design of classifying and buffering instructions and then parsing, has the ability to immediately process multiple communication instructions in parallel without causing blocking, thereby speeding up the response speed. In addition, the number of classifications can be configured to increase or decrease the number of parallel threads, and the cache space can be defined by the user, which has the characteristics of compatibility, high fault tolerance, and fast communication rate in electronic device systems. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present disclosure, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0035] FIG. 1 shows a flowchart of an instruction classification processing method according to an embodiment of the present disclosure;

[0036] FIG. 2 shows a data flow diagram of the instruction classification processing according to an embodiment of the present disclosure;

[0037] FIG. 3 shows a structural diagram of an instruction classification processing device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present disclosure will be described clearly and completely in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments.

[0039] The components of the embodiments of the present disclosure generally described and illustrated in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed present disclosure, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present disclosure.

[0040] Hereinafter, the terms "include", "have", and their conjugates used in the various embodiments of the present disclosure merely mean to indicate that there is a certain feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. In addition, the terms "first", "second", "third", and the like are used only to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0041] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present disclosure belong. The terms (such as those defined in a generally used dictionary) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of the present disclosure.

[0042] The technical solutions of the present disclosure can determine the instruction category according to the protocol address stored in the instruction in the instruction package when the device receives the instruction package by pre-setting the classification rule. Different categories of instructions are processed and cached through different threads, realizing parallel and cache processing between different instructions, avoiding instruction loss and blocking.

[0043] The method will be described below in conjunction with some specific embodiments.

[0044] The embodiments of the present disclosure provide an instruction classification processing method, and FIG. 1 shows a flowchart of the instruction classification processing method according to an embodiment of the present disclosure. Illustratively, the instruction classification processing method includes the following steps:

[0045] Step S100, when receiving the instruction package issued by the upper computer, the instructions in the instruction package are classified.

[0046] The embodiment is applied to the scene of inter-device communication or inter-device and chip communication. The method of the embodiment is mainly applied to the processing device on the receiving instruction side. The processing device can be various engineering devices or control devices, and the like.

[0047] The upper computer sends control instructions to the processing device or chip. The control instructions are encapsulated into an instruction package through a communication protocol and then sent to the corresponding processing device. The processing device classifies the instructions carried in the instruction package when receiving the instruction package.

[0048] It should be noted that various instructions in the embodiment have various functions. For each instruction, a communication protocol address is allocated. The protocol address is the address reserved in the instruction package for storing the instruction. The control instruction is encapsulated into the instruction package in the communication protocol address. The communication protocol addresses corresponding to the instructions classified into the same category are also classified into the same interval. For example, instruction A and instruction B are instructions of the same category. The addresses of the two instructions are different, but the addresses allocated to the two instructions are in an interval.

[0049] Thus, when identifying the instruction package, the address section where the communication protocol address of the instruction stored in the instruction package is located can be determined to determine the category of the instruction.

[0050] The category division of the above instructions is based on whether the instructions are mutually exclusive or can be executed synchronously. For instructions that cannot be executed synchronously, they are classified into the same category. For example, instruction A is to open a switch, and instruction B is to close the switch. Obviously, a switch cannot be opened and closed at the same time and cannot be parallel. Therefore, instruction A and instruction B are instructions of the same category. Instruction C is configured to control the voltage size. Instruction C can be executed synchronously with instruction A and instruction B. Therefore, instruction C is not of the same category as instruction A and instruction B. When allocating addresses, instruction C will not be in the same address interval as instruction A and instruction B.

[0051] It can be understood that the category here can be completely customized by the user according to the actual working environment. Instructions that do not repel each other are classified into different categories, and instructions that repel each other are classified into the same category. At the same time, considering that there are a large number of instructions, too many categories may have the opposite effect. Therefore, instructions that do not repel each other can also be classified into the same category to some extent. That is, as long as the instructions of different categories can be executed in parallel, how to classify can be flexibly set according to the actual situation. This setting can be completed through a self-defined communication protocol.

[0052] The correspondence between the instruction and the protocol address can be preset through the communication protocol to ensure that the host computer can store the instruction in the specified protocol address according to the correspondence when packaging.

[0053] After the device receives the instruction package, the address interval where the control instruction is stored can be determined through the information carried by the package (at this time, the package does not need to be parsed), and it can be determined what kind of instruction the received instruction package is.

[0054] It should be noted that this step only performs a classification operation and does not perform parsing, so it can be considered that the received instruction package is classified based on the carried instruction, thereby facilitating subsequent parsing.

[0055] In step S200, the instruction package is allocated to a corresponding parallel thread according to the type of the instruction, and the instruction package is cached in a cache space corresponding to the parallel thread.

[0056] Based on the foregoing classification operation, the instruction package will be allocated to the corresponding parallel thread according to the respective category, wherein the parallel thread is a plurality of threads divided for parallel computation, and each thread corresponds to each instruction category.

[0057] The correspondence between the parallel thread and the category can also be designed in advance through the communication protocol, for example, category 1 corresponds to thread 1, and so on, so that several categories generate several threads, thereby realizing parallel processing of multiple instruction packages.

[0058] Each parallel thread caches the instruction package after receiving it, wherein each parallel thread has a corresponding cache space, so that instruction packages of different categories are respectively stored in the cache space corresponding to the parallel thread, and instruction packages of different categories are not stored in the same cache space.

[0059] It should be noted that the host computer issues instructions in series, one after another, and the embodiment classifies the instruction package according to the category and caches it through each thread, which can ensure that the instruction package will not be discarded even if it cannot be parsed at the first time, and the parallel processing of multiple threads can increase the processing efficiency of the instruction package.

[0060] After the instruction package is cached, the storage amount in the current cache space can also be output, because the storage resource is not infinite, and the output storage amount can be used as a monitoring and debugging means to effectively locate the problem when the problem occurs, and can provide a basis for selecting and optimizing the storage space size used by each parallel cache logic.

[0061] For example, in the preset communication protocol, the base frame width of the communication instruction package, the instruction storage location, and the storage space allocated to the instruction can be set as the related parameters configured to store the instruction package, and the number of instruction categories can be set, so that the corresponding number of communication address segments is divided according to the number of categories, to realize flexible setting of the storage and classification of the instruction package. Moreover, for different application scenarios, there are some instructions that are not needed, which can be excluded from the protocol and not classified, so that the communication address does not need to be allocated for these unused instructions, thereby saving the use space.

[0062] In step S300, when the instruction package is called, it is sequentially called from the cache space in the storage order, and the corresponding function execution signal is obtained by analyzing the instruction package, and the function execution signal is output.

[0063] Among them, the instruction package can be stored in the cache space in the form of a queue, so that the cached instruction package can be sequentially called in the first-in, first-out order.

[0064] The instruction package is called for analysis, to obtain the instruction and perform the corresponding operation, and each thread can only analyze one instruction package at a time, so if the current is being analyzed, the instruction package will not be called from the cache space, and when the analysis task is idle after the analysis of an instruction package is completed, the earliest stored instruction package will be called from the cache space for analysis. The instruction package can obtain the instruction in the instruction package, and then the corresponding execution signal can be generated, and the execution signal is output to the corresponding execution device, which completes the task of the instruction package.

[0065] It can be understood that each thread works in parallel, so each instruction package cached in different cache spaces will be analyzed and executed in parallel. As can be known from the operations of steps S100 and S200, these instruction packages are classified, and the instruction packages of different categories do not exclude each other and can be executed in parallel, which ensures the execution efficiency of the instructions. Moreover, when too many instructions are issued too quickly, these instructions can be pre-cached, so that the issued instructions will not be lost and can be executed in the original order.

[0066] When analyzing the instruction package, the communication protocol address where the instruction is stored in the instruction package is determined according to the communication protocol.

[0067] The frame bit width of the communication protocol base frame and the instruction field are set in the communication protocol, the frame bit width is the byte width of the base frame, for example, 1 bit or 2 bits, and the instruction field is the field name indicating the storage instruction position, for example, it can be "name" or "order".

[0068] When parsing, starting from the packet header of the instruction packet, traverse in frame bit width units, one field after another, find the corresponding instruction field, find the instruction storage location, and then get the instruction from the instruction field, and at this time the instruction location is located, and the specific communication protocol address of the instruction storage can be obtained.

[0069] In the classification of the foregoing step S100, only the address segment to which the communication protocol address belongs is determined, and the communication protocol address of the instruction is determined in this step. Since one communication protocol address corresponds to one instruction, the communication protocol address can be matched and verified to determine whether the type of the instruction and the thread classified at present are a correct corresponding relationship.

[0070] The corresponding relationship between the type of the instruction and the thread classified at present can be recorded by presetting a function matching table. The function matching table is set synchronously when the communication protocol is set. When the communication protocol address is obtained, the function matching table and the communication protocol address can be used to determine whether the instruction is correctly allocated to the current thread. If so, the corresponding execution signal can be generated according to the instruction.

[0071] In some embodiments, the matching type corresponding to the communication protocol address is determined according to the communication protocol address and the preset function matching table. If the matching type and the function type are different, the current instruction packet is discarded.

[0072] The function matching table records the types corresponding to different address intervals. The matching type corresponding to the communication protocol address is determined according to the address interval in which the communication protocol address is located. If the matching type and the function type of the instruction are consistent, it is determined that the instruction is correctly allocated to the current thread. If the matching type and the function type of the instruction are inconsistent, it is determined that the instruction is not correctly allocated to the current thread.

[0073] Specifically, the communication protocol address of the instruction is compared with the address interval of the instruction type corresponding to the current thread in the function matching table. If it falls within the interval recorded in the function matching table, it means that the matching is successful, otherwise the matching fails.

[0074] The execution signal is a signal for controlling the corresponding execution device to execute the instruction based on the above instruction. The execution device is a downstream device that specifically executes the instruction, for example, a switch signal, and the selected switch device specifically executes the switch action.

[0075] The execution signal needs to be generated by the processing device receiving the instruction and then issued to the specific execution device. For example, the above-mentioned instruction is often a directly executable code instruction such as "FF" and the like, and there is a one-to-one correspondence between the code instruction and the specific execution information. As long as the aforementioned matching operation is successful, the instruction can be directly issued, the instruction can be automatically matched to the corresponding execution signal for output, and then the corresponding operation is performed.

[0076] In addition, when parsing the instruction, if it is found that the instruction type and the current thread do not match, a packet loss operation is directly performed, and the instruction is not executed. For example, sometimes when testing, the upper computer intentionally sends meaningless error instructions, at this time the instruction will have an error address, at this time the packet loss operation needs to be performed. There is also a case where the upper computer packet is wrong, at this time the packet loss is also needed, so as to avoid the synchronization execution of mutually exclusive instructions and bring confusion.

[0077] As shown in FIG. 2, it is a processing flow diagram of the instruction issued by the upper computer in the embodiment.

[0078] The upper computer sends an instruction to the processing device 100, and the instruction is a serially issued instruction packet. After the processing device 100 receives the instruction packet, a classification operation is performed according to the communication protocol, and each instruction packet is distributed to different threads for parallel processing. Each thread first buffers the instructions, and then takes out the instruction packet in the order of the buffered instructions to perform a parsing operation, and then issues the instruction to the corresponding execution device.

[0079] The instruction classification processing method of the embodiment adopts the operation of classifying and buffering the instructions before parsing, so that multiple instructions can be processed in parallel when processing the instructions, and blocking and instruction loss are avoided, the response speed is accelerated, and the classification number can be configured to increase or decrease the parallel thread capacity and the cache space can be user-defined. The characteristics of the electronic device system have compatibility, high fault tolerance, and fast communication rate.

[0080] The embodiment of the present disclosure also provides an instruction classification processing method, as shown in FIG. 3, and the embodiment also provides an instruction classification processing device, which comprises:

[0081] The classification module 10 is configured to classify the instructions in the instruction packet issued by the upper computer when receiving the instruction packet.

[0082] The cache module 20 is configured to distribute the instruction packet to the corresponding parallel thread according to the type of the instruction, and buffer the instruction packet in the cache space corresponding to the parallel thread.

[0083] The parsing module 30 is configured to sequentially call the instruction packages from the cache space in the storage order when the instruction packages are called, and parse the instruction packages to obtain corresponding function execution signals, and output the function execution signals.

[0084] Optionally, the classification module 10 is specifically configured to receive an instruction package issued by a host computer, determine a communication protocol address of a storage instruction in the instruction package according to a communication protocol, and determine the type of the instruction according to an address segment where the communication protocol address is located.

[0085] Optionally, the classification module 10 is further configured to classify the instructions according to whether the instructions can be executed synchronously, and determine that the instructions that cannot be executed synchronously are of the same type.

[0086] Optionally, the cache module 20 is specifically configured to suspend calling the instruction packages from the cache space if there is an instruction package being parsed at present, and call the instruction package stored first from the cache space if there is no instruction package being parsed at present.

[0087] Optionally, the parsing module 30 is specifically configured to determine an instruction position where the instruction is stored in the instruction package according to a communication protocol, extract the instruction and determine a corresponding communication protocol address, parse the instruction to determine a function type corresponding to the instruction, and generate a corresponding execution signal according to the function type.

[0088] Optionally, the parsing module 30 is further configured to determine whether the instruction package is correctly allocated to a current thread according to the communication protocol address and a preset function matching table, and generate a corresponding execution signal according to the instruction if the instruction package is correctly allocated to the current thread.

[0089] Optionally, the parsing module 30 is further configured to determine a matching type corresponding to the communication protocol address according to the communication protocol address and the preset function matching table, and perform a packet loss operation on a current instruction package if the matching type and the function type are different.

[0090] Optionally, the parsing module 30 is further configured to compare the communication protocol address of the instruction with an address interval of an instruction type corresponding to the current thread in the function matching table, and determine that matching is successful if the communication protocol address falls into an interval recorded in the function matching table.

[0091] Optionally, the cache module 20 is further configured to output a storage amount state of the cache space to provide debugging information.

[0092] Optionally, the communication protocol sets a frame bit width and an instruction field; the parsing module 30 is further configured to count and traverse from a packet header of the instruction packet in units of the frame bit width to determine a position of the instruction field, to obtain an instruction under the instruction field, and a communication protocol address where the instruction is located.

[0093] It can be understood that the device of the embodiment corresponds to the method of the above-mentioned embodiment, and the optional items in the above-mentioned embodiment are also applicable to the embodiment, and thus will not be described again here.

[0094] The disclosure also provides a terminal device, which comprises a processor and a memory, the memory stores a computer program, and the processor is configured to execute the computer program to implement the instruction classification processing method.

[0095] The terminal device can be a device carrying a control chip or other device with computing power, which can receive instructions from a host computer and parse them, and then transmit them to an execution device. For example, a memory with a chip, a solid state disk, a single chip microcomputer, etc.

[0096] The disclosure also provides a computer readable storage medium, which stores a computer program, and the computer program implements the instruction classification processing method when executed on a processor.

[0097] The processor can be an integrated circuit chip with signal processing capability. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU), and a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or at least one of the above. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor or the like, which can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the disclosure.

[0098] The memory can be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM) and the like. Among them, the memory is configured to store a computer program, and the processor can execute the computer program accordingly after receiving an execution instruction.

[0099] For example, the computer readable storage medium can include, but is not limited to, a variety of media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0100] In several embodiments provided by the present disclosure, it should be understood that the disclosed apparatus and method can also be implemented by other means. The apparatus embodiments described above are only illustrative, for example, the flowcharts and structural diagrams in the drawings show the possible implementation architecture, functions and operations of the apparatus, method and computer program product according to the embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code, which contains one or more executable instructions for realizing the specified logical function. It should also be noted that in alternative implementation ways, the functions annotated in the blocks can also occur in different order from that annotated in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and sometimes they can be executed in reverse order, depending on the functions involved. It should also be noted that each block in the structural diagram and / or flowchart, and the combination of blocks in the structural diagram and / or flowchart, can be realized by a dedicated hardware-based system that executes the specified functions or actions, or can be realized by a combination of special hardware and computer instructions.

[0101] In addition, each functional module or unit in the various embodiments of the present disclosure can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0102] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present disclosure.

[0103] The above merely describes specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Industrial applicability

[0104] With the above scheme, a classification instruction buffer post-analysis design is adopted, which has immediate parallel processing of multiple communication instructions and does not cause blocking, thereby speeding up the response speed. In addition, the classification number is configurable to increase or decrease the parallel line capacity and the cache space can be user-defined. In the electronic device system, it has the characteristics of compatibility, high fault tolerance, fast communication rate, etc.

Claims

1. A method of instruction classification processing, the method comprising: The method comprises the following steps: when receiving the instruction package issued by the upper computer, classifying the instructions in the instruction package; according to the category of the instructions, distributing the instruction package to the corresponding parallel thread of the category, and at the same time, caching the instruction package in the cache space corresponding to the parallel thread; when the instruction package is called, sequentially calling the instruction package from the cache space in the order of storage, and analyzing the instruction package to obtain the corresponding function execution signal, and outputting the function execution signal.

2. The instruction classification processing method according to claim 1, characterized by, The step of classifying the instructions in the instruction package when receiving the instruction package issued by the upper computer comprises the following steps: receiving the instruction package issued by the upper computer, and determining the communication protocol address of the instructions stored in the instruction package according to the communication protocol; determining the category of the instructions according to the address segment where the communication protocol address is located.

3. The instruction classification processing method according to claim 1, characterized by, The step of classifying the instructions in the instruction package comprises the following steps: classifying the instructions according to whether the instructions can be executed synchronously, and determining that the instructions that cannot be executed synchronously belong to the same category.

4. The instruction classification processing method according to claim 1, characterized by, The step of sequentially calling the instruction package from the cache space in the order of storage comprises the following steps: if the current instruction package is being analyzed, pause calling the instruction package from the cache space; if the current instruction package is not being analyzed, call the instruction package stored first from the cache space.

5. The instruction classification processing method according to claim 1, characterized by, The step of analyzing the instruction package to obtain the corresponding function execution signal comprises the following steps: determining the instruction position of the instructions stored in the instruction package according to the communication protocol, extracting the instructions and determining the corresponding communication protocol address; analyzing the instructions to determine the function category corresponding to the instructions, and generating the corresponding execution signal according to the function category.

6. The instruction classification processing method according to claim 5, characterized by, The step of analyzing the instruction package to obtain the corresponding function execution signal further comprises the following steps: determining whether the instruction package is correctly distributed to the current thread according to the communication protocol address and the preset function matching table; if the instruction package is correctly distributed to the current thread, generating the corresponding execution signal according to the instructions.

7. The instruction classification processing method according to claim 5 or 6, characterized by, After determining the function category corresponding to the instructions, the method further comprises the following steps: determining the matching category corresponding to the communication protocol address according to the communication protocol address and the preset function matching table; if the matching category and the function category are different, performing a packet loss operation on the current instruction package.

8. The instruction classification processing method according to claim 7, characterized by, After determining the matching category corresponding to the communication protocol address, the method further comprises the following steps: comparing the communication protocol address of the instructions with the address interval of the instruction category corresponding to the current thread in the function matching table, and if the address interval falls within the interval recorded in the function matching table, determining that the matching is successful.

9. The instruction classification processing method according to claim 1, characterized by, After caching the instruction package in the cache space corresponding to the parallel thread, the method further comprises the following steps: outputting the storage state of the cache space to provide debugging information.

10. The method of claim 5-9, wherein, The communication protocol sets the frame bit width and the instruction field. The step of determining the instruction position of the instructions stored in the instruction package according to the communication protocol, extracting the instructions and determining the corresponding communication protocol address comprises the following steps: counting and traversing from the header of the instruction package in units of the frame bit width to determine the position of the instruction field, so as to obtain the instructions under the instruction field and the communication protocol address where the instructions are located.

11. An instruction classifying processing apparatus characterized by comprising: The method comprises the following steps: The classification module is configured to classify the instructions in the instruction package when the instruction package is received. The cache module is configured to distribute the instruction package to a parallel thread of a corresponding category according to the category of the instructions, and cache the instruction package in a cache space corresponding to the parallel thread. The analysis module is configured to sequentially call and analyze the instruction package in the cache space in a storage order to obtain a corresponding function execution signal when the instruction package is called, and output the function execution signal.

12. A terminal device, comprising: The terminal device comprises a processor and a memory, the memory stores a computer program, and the processor is configured to execute the computer program to implement the instruction classification processing method in any one of claims 1-10.

13. A computer-readable storage medium, characterized in that, The computer program is stored in the memory and executed on the processor to implement the instruction classification processing method in any one of claims 1-10.

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