Decoding device and decoding method

Abstract

One embodiment of the present invention is a decoding device used for coherent digital signal processing, the decoding device comprising a likelihood calculation unit and a decoding unit. The likelihood calculation unit is provided from the first lane to the (d-1)-th (d is an integer of 2 or more) lane, and calculates a likelihood for each of the first lane to the (d-1)-th lane using a distributed decoding metric obtained by demodulating reception data obtained by adding communication path noise to transmission data transmitted from a transmission device. When the likelihood calculated by the likelihood calculation unit is input and the decoding process is represented by a factor graph, the decoding unit performs decoding using a soft decision decoder corresponding to one element code among the plurality of element codes in each iterative process.

Description

Decoder and decoding method

[0001] The present invention relates to the technology of decoders and decoding methods.

[0002] In optical transmission, FEC (Forward Error Correction) is important in both power and decoding characteristics. Note that FEC is a function that enables a communication system to achieve transmission with extremely few errors even under the influence of noise and other obstacles. For example, in an optical transmission network for data centers, low-complexity soft-decision decoding methods represented by short code length linear codes and Chase2 decoding are used. Note that since the decoding calculation amount increases exponentially as the code length increases, the low-complexity decoding method is limited to application to short code length linear codes. Therefore, the decoding performance is limited by the code length. To solve the problem of the decoding performance being limited, in recent years, the CP-MLC (Channel-polarized multilevel coding) method has been proposed (see, for example, Non-Patent Document 1). Also, as an improved version of CP-MLC, the CP-MLC-ID (Channel-Polarized MultiLevel Coding with Iterative Decoding) method has been proposed.

[0003] T. Kakizaki et al., “Improved Performance-complexity Trade-offs for Soft-decision Decoding by Channel-polarized Multilevel Coding”, 49th European Conference on Optical Communications, ECOC2023, 2023

[0004] However, in the prior art, since the decoding calculation amount is large, there is a problem that the power consumption of the decoding process may also increase, especially in areas where low-power optical transceivers such as short-distance optical transmission are required. In view of the above circumstances, the present invention aims to provide a technology capable of reducing the decoding calculation amount.

[0005] One aspect of the present invention is a decoding device used in coherent digital signal processing, which is provided on the first lane to the (d - 1)-th lane (d is an integer of 2 or more), and uses the decoded metric obtained by demodulating the received data to which communication channel noise is added to the transmitted data transmitted from the transmitting device to calculate the likelihood for each of the first lane to the (d - 1)-th lane. A likelihood calculation unit, and a decoding unit that inputs the likelihood calculated by the likelihood calculation unit and decodes using a soft decision decoder corresponding to one element code among a plurality of element codes in each iterative process when the decoding process is represented by a factor graph. A decoding device comprising:

[0006] One aspect of the present invention is a decoding method performed by a decoding device used in coherent digital signal processing. The likelihood calculation unit is provided on the first lane to the (d - 1)-th lane (d is an integer of 2 or more), and uses the decoded metric obtained by demodulating the received data to which communication channel noise is added to the transmitted data transmitted from the transmitting device to calculate the likelihood for each of the first lane to the (d - 1)-th lane. The decoding unit inputs the calculated likelihood and decodes using a soft decision decoder corresponding to one element code among a plurality of element codes in each iterative process when the decoding process is represented by a factor graph.

[0007] According to the present invention, it is possible to reduce the decoding calculation amount.

[0008] It is a diagram showing a system configuration example of a communication system according to an embodiment. It is a diagram showing a configuration example of a transmitting device according to an embodiment. It is a diagram showing a configuration example of a decoding device according to an embodiment. It is a diagram showing an outline of a hardware configuration example of a decoding device applied to an embodiment. It is a diagram showing an example of a factor graph representation of a decoding device in an embodiment. It is a flowchart of a processing procedure of a decoding device according to an embodiment. It is a diagram showing an example of an evaluation result of decoding performance.

[0009] Embodiments of the present invention will be described in detail with reference to the drawings. Figure 1 is a diagram showing an example of the system configuration of the communication system of this embodiment. As shown in Figure 1, the communication system 1 includes, for example, a transmitting device 2, a transmission line 3, and a receiving device 4. The receiving device 4 includes, for example, a receiving unit 41, a symbol demapping unit 42, and a decoding device 43. The communication system 1 is used, for example, for coherent digital signal processing.

[0010] The transmitting device 2 generates a transmission signal and sends the generated transmission signal to the receiving device 4 via the transmission line 3. An example of the configuration of the transmitting device 2 will be described later.

[0011] Transmission path 3 is, for example, an optical transmission path using an optical fiber cable.

[0012] The receiving device 4 receives the transmission signal transmitted by the transmitting device 2.

[0013] The receiving unit 41 receives the transmission signal transmitted from the transmitting device 2.

[0014] The symbol demapping unit 42 uses the estimated noise value of the communication channel to demap (demodulate) the equalized signal (received symbol). The symbol demapping unit 42 uses, for example, the coordinates of an ideal signal point (signal symbol) defined in the IQ plane to demap the received symbol mapped to the IQ plane to the likelihood ratio corresponding to each bit of the bit sequence represented by the received symbol. "Demapping processing" is equivalent to, for example, the operation of calculating the LLR (log-likelihood ratio) used for error correction decoding. The symbol demapping unit 42 also uses the LLR (log-likelihood ratio) corresponding to the demapped bit sequence to perform error correction decoding of the error correction block.

[0015] The decoding device 43 performs decoding on the received transmitted signal. An example of the configuration of the decoding device 43 will be described later.

[0016] Next, an example of the configuration of the transmitting device 2 will be described. Figure 2 is a diagram showing an example of the configuration of the transmitting device of this embodiment. As shown in Figure 2, the transmitting device 2 includes, for example, an encoding device 21, a symbol mapping unit 22, and a transmitting unit 23. The encoding device 21 includes, for example, an output encoder 211, a 1:d conversion unit 212, an encoder 213 (213-1, 213-2, ..., 213-(d-1)), and a bit interleaver 214 (S (cursive) １～ｄ It comprises (214-1, 214-2, ..., 214-d), a logical OR unit 215 (215-1, 215-2, ..., 215-(d-1)), and a d:1 conversion unit 216.

[0017] The output encoder 211 encodes the information to be transmitted using, for example, HD-FEC (Hard-Decision FEC) technology. HD-FEC technology is a hard-decision (HD) decoding technique within the FEC system. Here, hard-decision is a method in which, for example, when dealing with binary values ​​0 and 1, the shifted values ​​are determined to be either 0 or 1 before decoding.

[0018] The 1:d conversion unit 212 performs a serial-parallel conversion 1:d on the encoded data.

[0019] Encoder 213 encodes bits corresponding to 1 to d using SD-FEC technology. SD-FEC technology is a soft-decision (SD) decoding technique within the FEC method. Soft-decision is a method of decoding that, for example, when dealing with binary values ​​0 and 1, uses an intermediate value between 0 and 1 as confidence information for the shifted values. Encoder 213 also performs serial-parallel conversion 1:d and divides the data z' ｉ For (where i is an integer from 1 to d-1), error-corrected encoding is performed on the data z ｉ I'll do that.

[0020] The bit interleaver 214 has the role of dispersing reliability information with low reliability among a plurality of codewords when such reliability information occurs burstily in some of the codewords on the decoder side. Also, the bit interleaver 214 performs a process of shuffling a frame composed of a plurality of codewords on a bit-by-bit basis. Note that, for simplicity, FIG. 2 shows an example in which one codeword is input, but actually, this is parallelized and shuffled with other codewords. The bit interleaver 214 converts each of z ｉ , z ｄ into s ｊ (j is an integer from 1 to d). For example, the bit interleaver 214 performs a process of collecting one bit each from n different positions of n z ｉ to form n bits for s ｉ . For example, when n = 3, the bit interleaver 214 performs the conversion as follows. z (the first) 011 z (the second) 100 z (the third) 110... s (the first) 011 (collecting the first bit of each z) s (the first) 101 (collecting the second bit of each z) s (the first) 100 (collecting the third bit of each z) Note that the above example is just an example and is not limited to this.

[0021] The exclusive OR unit 215 takes the exclusive OR of each codeword s ｉ of each lane with the codeword of the bottom lane (the d-th lane) and s ｄ on a vector-by-vector basis. Note that the exclusive OR is a process of outputting a vector (a １ (with “+” in the white circle) b １ as an element, where the exclusive OR of each element a １ and b<​​​​​​​​​​​​​​​​​​​​​​​and s ｄ A parallel-to-serial conversion d:1 is performed on it.

[0023] The symbol mapping unit 22 performs symbol mapping processing on the data that has been converted in parallel to serial d:1.

[0024] The transmitting unit 23 transmits the symbol-mapped transmission signal to the receiving device 4 via the transmission line 3.

[0025] Next, an example of the configuration of the decoding device 43 of the receiving device 4 will be described. Figure 3 is a diagram showing an example of the configuration of the decoding device of this embodiment. As shown in Figure 3, the decoding device 43 includes, for example, a distributor 431, a likelihood calculation unit 432 (432-1, 432-2, ..., 432-(d-1)), a decoding unit 434, an HD likelihood calculation unit 435 (decoding unit), and a bit deinterleaver 436 (S (cursive) －１ ｄ The decoding unit 434 includes a bit deinterleaver 433 (S (cursive) －１ １～ｄ－１ It is equipped with (433-1, 433-2, ..., 433-(d-1)) and an SD decoder 434 (434-1, 434-2, ..., 434-(d-1)).

[0026] The distributor 431 receives the value demapped by the symbol demapping unit 42. The value demapped by the symbol demapping unit 42 is the received signal L Ｆ = (L(1), L(2), ..., L(f)) (where F is an integer from 1 to f). Here, L(f) is LLR corresponding to the bits of lane f. The distributor 220 shares the received signal L from the first lane to the dth lane. Specifically, the distributor 431 copies and shares the same symbol to all lanes from the first lane to the dth lane.

[0027] The likelihood calculation unit 432 is located on the first lane to the (d-1)th lane. The likelihood calculation unit 432 calculates the log-likelihood ratio for each of the first to (d-1)th lanes based on a value shared by each of the first to (d-1)th lanes by the distributor 431 (for example, the received signal L). The likelihood calculation unit 432 also receives the decoding result from the SD decoder 434 as feedback.

[0028] The decoding unit 434 decodes the received signal using the information output by the likelihood calculation unit 432.

[0029] The bit deinterleaver 433 performs the inverse transformation of the process performed by the bit interleaver, thereby transforming the likelihood calculated by the likelihood calculation unit 432 and outputting it to the SD decoder 434.

[0030] The SD decoder 434 performs error correction decoding using the log-likelihood ratio obtained by the bit deinterleaver 433 from the log-likelihood ratio for each lane from the first to the (d-1)th lane calculated by the likelihood calculation unit 432. Here, the SD decoder 434 performs soft-input soft-output decoding, such as each iteration of Pyndiah-Chase decoding, and outputs the result of the soft determination to the d:1 converter 438. The SD decoder 434 also feeds back the decoding results for each lane from the first to the (d-1)th lane to the likelihood calculation unit 432.

[0031] The HD likelihood calculation unit 435 is located on the d-th lane. The HD likelihood calculation unit 435 calculates the likelihood γ based on the value shared by each of the 1st lane to the (d-1) lanes by the distributor 431 (for example, the received signal L) and the decoding result fed back from the SD decoder 434. ｄ Calculate.

[0032] The bit deinterleaver 436 performs the inverse transformation of the process performed by the bit interleaver, thereby converting the likelihood γ calculated by the HD likelihood calculation unit 435. ｄ The result is converted in reverse and output to the HD decoder 437.

[0033] The HD decoder 437 uses the information output by the bit deinterleaver 436 to perform a hard determination and outputs the result of the hard determination to the d:1 converter 438.

[0034] Furthermore, a portion of the receiving device 4 is composed of, for example, a processor such as a CPU (Central Processing Unit) and memory. The receiving device 4 functions as a symbol demapping unit 42 and a decoding device 43 when the processor executes a program. Some of the functions of the receiving device 4 may be implemented using hardware such as an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), or an FPGA (Field Programmable Gate Array). The above program may be recorded on a computer-readable recording medium. Computer-readable recording media include, for example, portable media such as flexible disks, magneto-optical disks, ROMs, CD-ROMs, semiconductor memory devices (e.g., SSDs: Solid State Drives), and memory devices such as hard disks and semiconductor memory devices built into computer systems. The above program may be transmitted via a telecommunications line.

[0035] Next, an example of the hardware configuration of the decoding device 43 will be described. Figure 4 is a schematic diagram of an example of the hardware configuration of a decoding device applied to this embodiment. The decoding device 43 includes, for example, a processor 401, a main memory 402, a communication interface 403, an auxiliary storage device 404, an input / output interface 405, and an internal bus 406. The processor 401, the main memory 402, the communication interface 403, the auxiliary storage device 404, and the input / output interface 405 are connected to each other so as to be able to communicate via the internal bus 406. The configuration of the decoding device 43 may also be applied to, for example, a receiving device 4. In this case, for example, the transmitting unit 23 may be configured using the communication interface 403 or the input / output interface 405. Also, for example, the storage unit 14 of the decoding device 43 may be configured using the main memory 402 and the auxiliary storage device 94. Furthermore, the decoding device 43 may be configured using the processor 401, the main memory 402, and the auxiliary storage device 94.

[0036] Next, an example of processing by the decoding device 43 will be described. Figure 5 shows an example of a factor graph representation of the decoding device in this embodiment.

[0037] A factor graph is a bipartite graph representation used to represent a multivariable global function as the product of local functions, each having a smaller subset of variables. It consists of a set of variable nodes (VNs) and a set of check nodes (CNs). As shown in Figure 5, in a factor graph, the set of variable nodes corresponding to random variables is represented by circles (white circles), and the check nodes corresponding to functions are represented by squares (white squares). Edges connect the variable nodes corresponding to random variables in the function corresponding to the check node to the check node.

[0038] In Figure 5, the white rectangle 451 is the check node p(y) in the first lane. １ |b １ ), the white square 452 is the check node p(y) in the d lane. ｄ |b ｄ ), the white square 453 is the check node p(y) in the second lane. ２ |b ２ ) The white square 457 is check node δ in the first lane. １ (•) and the white square 458 is the check node δ in the second lane. ２ (•) is the case. Note that δ(•) is an indicator function that returns "1" if the logical expression inside (•) is true, and "0" if it is false. Also, the white circle 459 is s １ , White circle 460 is s ２ That is the case.

[0039] Also, the white circle 454 is variable b １ The white circle 455 is variable b ｄ The white circle 456 is variable b ２ This is the case. In addition to factor 452 of the d-th lane, the white circle 455 also contains other check nodes (CN) (δ ｊ (s ｊ (A white circle with a "+" inside; the exclusive OR symbol) bｊ (A white circle with a "+" inside; the exclusive OR symbol) b ｄ It connects to (= 0).

[0040] Furthermore, the processing units 461 and 462 correspond to the decoding unit 434 and perform encoding and soft determination. Also, the processing unit 461 has s １ A bit variable node for other codewords is connected. Processing unit 462 is connected to s ２ A bit variable node is connected to the other codewords.

[0041] Furthermore, as shown in g1 of Figure 5, the decoding device 43 performs the following process in the first lane: Equation (1). As shown in g21 of Figure 5, the decoding device 43 performs the following process in the second lane: Equation (1) and Equation (2), each process is performed by the check node p(y １ |b １ Message (ψ) from ) to function node b1, check node p(y ２ |b ２ This is a message (ψ) from ) to function node b2.

[0042]

[0043]

[0044] As shown in g2 of Figure 5, the decoding device 43 performs the following process in the first lane: Equation (3). As shown in g22 of Figure 5, the decoding device 43 performs the following process in the second lane: Equation (4). In equations (1) and (2), φ is the variable node from b1 to check node δ. １ This is a message to [someone / something].

[0045]

[0046]

[0047] As shown in g3 of Figure 5, the decoding device 43 performs the following process (5) in the first lane. As shown in g23 of Figure 5, the decoding device 43 performs the following process (6) in the second lane.

[0048]

[0049]

[0050] Furthermore, as shown in g5 of Figure 5, the decoding device 43 performs the following process in the d-th lane: (7)

[0051]

[0052] Next, an example of the message processing procedure performed by the decoding device 43 will be explained using Figures 5 and 6. Figure 6 is a flowchart of the processing procedure of the decoding device in this embodiment. The decoding device 43 performs message processing in the following procedure.

[0053] (Step S1) The decoding device 43 performs the following process (8) with i=1 (Figure 5 g11).

[0054]

[0055] (Step S2) The decoding device 43 performs the following process (9) with i=1 (Figure 5 g12). In equation (9), D is, for example, a soft-decision input soft-decision output decoder using a Pyndiah-Chase decoder or a soft-decision input hard-decision output decoder using a Chase decoder. The operators in the open circles are composite mappings.

[0056]

[0057] (Step S3) The decoding device 43 performs the following process (10) with i=1 (Figure 5 g13).

[0058]

[0059] (Step S4) The decoding device 43 performs the following process (11) with i=1 (Figure 5 g14).

[0060]

[0061] (Step S5) The decoding device 43 performs the following process (12) with i=1 (Figure 5 g15).

[0062]

[0063] (Step S6) The decoding device 43 performs the following process (13) with i = 2 (Figure 5 g31).

[0064]

[0065] (Step S7) The decoding device 43 performs the following process (14) with i = 2 (Figure 5 g32).

[0066]

[0067] The decoding device 43 then performs the same processing as in steps S2 to S5, with i=2.

[0068] (Step S8) The decoding device 43 performs the following process (15). In equation (15), m is given by equation (16). ｍａｘ This is the maximum value among the values ​​in lanes 1 through d-1.

[0069]

[0070]

[0071] (Step S9) The decoding device 43 performs the following process (17).

[0072]

[0073] (Step S10) The decoding device 43 uses the likelihood γ obtained in step S9. ｄ A hard judgment is performed on the result, and then a hard judgment decoding is performed.

[0074] Here, we will briefly explain an example of the processing procedure in the comparative example. In the comparative example's method, message processing is performed in parallel for j (1 ≤ j ≤ d-1) using the following procedure.

[0075] The decoding device takes i=1 and ψ_(δ ｊ ,s ｊ ) [1] (The "_" indicates that the contents in parentheses below it are subscripts) The first process is performed. Next, the decoder sets i=1 and φ_(s ｊ ,S (cursive) －１ ｊ ○ (operator) D (cursive) ｊ ) Perform the process in [1] (second process). Next, the decoder sets i=1 and ψ_(S (cursive) －１ ｊ ○ (operator) D (cursive) ｊ ,s ｊ) Perform the process in [1] (third process). Next, the decoder sets i=1 and ψ_(s ｊ , δ ｊ ) Perform the process in [1] (fourth process). Next, the decoder sets i=1 and ψ_(δ ｊ , b ｄ ) Perform the process in [1] (fifth process).

[0076] Next, the decoding device sets i = 2 to ψ_(b ｄ , δ ｊ ) Perform the process in [2] (sixth process). Next, the decoder sets i = 2 and ψ_(δ ｊ ,s ｊ ) Perform the process in [2] (seventh process). The decoding device repeats the process thereafter. After that, the decoding device performs ψ_(δ ｊ , b ｄ ) [I ｍａｘ Calculate ] and further φ_(b ｄ , p(y ｄ |b ｄ ) = γ ｄ The decoding device then calculates the likelihood γ. ｄ A hard decision is performed on the result, and then hard decision decoding is performed. Thus, in conventional techniques, it was necessary to perform soft decision decoding for each iteration and each element code.

[0077] In contrast, in this embodiment, the above-described process only requires decoding with the code of one element out of multiple elements in each iteration, thus reducing the computational complexity. As a result, according to this embodiment, the number of iterations can be increased with the same computational complexity.

[0078] Next, we will explain an example of the results of the decoding performance evaluation. Figure 7 is a diagram showing an example of the decoding performance evaluation results. In Figure 7, the horizontal axis is Eb / NO [dB], and the vertical axis is Pre-outer FEC BER (bit error rate). The solid line g101 represents the decoding performance when decoding using the method of this embodiment, the dashed line g102 represents the decoding performance when decoding using a conventional method, and the dashed line g103 represents the Outer FEC-BER threshold level.

[0079] The evaluation conditions are as follows: ・Binary-input additional white Gaussian noise channel ・Element code is (128,106)-extended BCH code. Here, (n,k) represents a code with code length n and information bit length k. ・SD decoder is sequential statistic decoding (number of codeword candidates 832). ・The number of lanes d in this embodiment and the prior art (see Non-Patent Literature 2) was set to 3. The decoding characteristics of the prior art method (number of iterations 3) and this embodiment (number of iterations 6), where the number of executions in the SD decoder is 6 relative to the throughput, were evaluated by numerical simulation.

[0080] As shown by arrow g111 in Figure 7, it was confirmed that the decoding characteristics can be improved by approximately 0.05 dB compared to the conventional method using the method of this embodiment.

[0081] In the decoding device 43 configured in this way, for example, a CP-MLC-ID iterative decoder is represented as a factor graph, and message scheduling is performed on the factor graph representation, making it possible to efficiently reduce the decoding computation time.

[0082] Furthermore, compared to the conventional technology, the decoding device 43 only requires decoding with a single-element code in each iteration, thus reducing the computational complexity. As a result, according to this embodiment, the number of iterations can be increased with the same computational complexity.

[0083] While embodiments of this invention have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments and includes designs and the like that do not depart from the spirit of this invention.

[0084] The present invention is applicable to communication systems, receiving devices, decoding devices, and the like.

[0085] 1...Communication system, 2...Transmitter, 3...Transmission line, 4...Receiver, 41...Receiver unit, 42...Symbol demapping unit, 43...Decoder

Claims

1. A decoding device used in coherent digital signal processing, comprising: a likelihood calculation unit provided on lanes 1 to (d-1) (where d is an integer of 2 or more), which calculates likelihood for each lane from 1 to (d-1) using a decoding metric obtained and distributed by demodulating received data, which has channel noise added to transmitted data transmitted from a transmitting device; and a decoding unit which receives the likelihood calculated by the likelihood calculation unit as input and, when the decoding process is represented as a factor graph, decodes using a soft-decision decoder corresponding to one element code among a plurality of element codes in each iteration.

2. The decoding unit determines the δ at the maximum value of I (where I is the first to d-1 lanes). ｍ (δ ｍ is δ ｍ A function that returns "1" if the logical expression inside the parentheses is true, and "0" if it is false, where m is I ｍａｘ mod(d-1))(I ｍａｘ (is the maximum value among the first to d-1 lanes) and the variable b in the d lane. ｄ The message ψ is calculated, and further, the likelihood γ in the d lane is calculated. ｄ The likelihood γ calculated is calculated. ｄ The decoding device according to claim 1, which performs hard judgment on the input and decodes it by performing hard judgment decoding.

3. The decoding unit comprises: a first inverse transform unit to which the likelihood calculated by the likelihood calculation unit is input; a soft-decision decoder to which the information transformed by the first inverse transform unit is input; an HD likelihood calculation unit to which the information to be input to the likelihood calculation unit is input; a second inverse transform unit to which the likelihood calculated by the HD likelihood calculation unit is input; and a hard-decision decoder to which the information transformed by the second inverse transform unit is input, wherein the HD likelihood calculation unit, the second inverse transform unit, and the hard-decision decoder decode using a soft-decision decoder corresponding to one element code among a plurality of element codes in each iterative process, the decoding device according to claim 1 or claim 2.

4. A decoding method performed by a decoding device used in coherent digital signal processing, wherein a likelihood calculation unit is provided on lanes 1 to 1(d-1) (where d is an integer of 2 or more) and calculates a likelihood for each lane from 1 to 1(d-1) using a decoding metric obtained and distributed by demodulating received data which has channel noise added to transmitted data transmitted from a transmitting device; and a decoding unit receives the calculated likelihood as input and, when the decoding process is represented as a factor graph, decodes in each iteration using a soft-decision decoder corresponding to one element code among a plurality of element codes.

Images