Compare elimination in bypass networks for out of order processing

Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for bypassing in out of order processing. One of the methods includes storing, in a reservation station, a bypass value that indicates a stage of an execution pipeline used to execute a producer instruction; selecting, using the bypass value, output data from the stage of the execution pipeline from data generated by at least two execution pipelines used to execute the producer instruction; and executing a consumer instruction stored in the reservation station associated with the bypass value using the selected output.

Description

Attorney Docket No. 56113-0750W01COMPARE ELIMINATION IN BYPASS NETWORKS FOR OUT OF ORDER PROCESSINGBACKGROUND

[0001] Out-of-order processing allows a computer’s CPU to execute instructions as resources become available, rather than strictly following the original program sequence. This method decouples the execution order from the programmed order to optimize the use of available processing power. Instructions are dynamically scheduled and executed based on operand availability, which can lead to improved performance. The final results are reordered to match the original program order, ensuring that the logic of the program remains correct. Instructions that produce results, referred to as producers, typically write those results into a register file into a destination register. Dependent instructions, referred to as consumers, read results for their source register operands from the register file. To achieve high performance, before results are available in the register file, bypass paths may be implemented such that dependent instructions can be issued and executed quicker than they would otherwise be able to if they had to wait to read the results after they are available in the register file. Existing bypass systems require many comparator (CAM) circuits to obtain intermediate output data, e.g., using bypass paths. Such circuits use significant power and silicon area.SUMMARY

[0002] In general, one innovative aspect of the subject matter described in this specification can be embodied in hardware that includes a reservation station configured to store a bypass value that indicates a stage of an execution pipeline used for a producer instruction; a physical register configured to store results of the producer instruction; a source bypass multiplexor configured to select output data from a set of execution pipelines that includes the execution pipeline based on the bypass value; and execution circuitry’ configured to execute an instruction associated with the bypass value stored in the reservation station using the selected output data from the source bypass multiplexor.

[0003] The foregoing and other embodiments can each optionally include one or more of the following features, alone or in combination. In particular, one embodiment includes all the following features in combination. Feature 1 : The bypass value is configured to change over time. Feature 2: The bypass value is configured to monotonically increase over time. Feature 3: The source bypass multiplexor is configured to obtain the output data from both the physical register and one or more intermediate stages within the set of executionAttorney Docket No. 56113-0750W01 pipelines. Feature 4: The bypass value includes a bit vector. Feature 5: The hardware comprises an issue multiplexor configured to process instructions stored in the reservation station based on instruction selection logic circuitry.

[0004] In general, another innovative aspect of the subject matter described in this specification can be embodied in methods that include the actions of storing, in a reservation station, a bypass value that indicates a stage of an execution pipeline used to execute a producer instruction; selecting, using the bypass value, output data from the stage of the execution pipeline from data generated by at least two execution pipelines used to execute the producer instruction; and executing a consumer instruction stored in the reservation station associated with the bypass value using the selected output. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

[0005] The foregoing and other embodiments can each optionally include one or more of the following features, alone or in combination. In particular, one embodiment includes all the following features in combination. Feature 1: A hardware processor implementing the method comprises: a first register configured to store a mapping between a producer identifier and a physical register identifier for the producer instruction; a second register configured to store the bypass value that indicates the stage of the execution pipeline used to execute the producer instruction; a source bypass multiplexor configured to select, using the bypass value, the output data from the stage of the execution pipeline from data generated by the at least two execution pipelines used to execute the producer instruction; and execution circuitry configured to execute the consumer instruction stored in the reservation station associated with the bypass value. Feature 2: The bypass value is configured to change over time. Feature 3: Actions include storing a mapping between (i) data representing w here the consumer instruction is configured to w rite output data and (ii) data representing where the consumer instruction is configured to obtain data for processing. Feature 4: Storing the bypass value comprises: storing a vector, wherein the vector includes a single value representing the stage of the execution pipeline used to execute the producer instruction. Feature 5: Actions include generating a vector representing the bypass value, w herein selecting the output from the stage of the execution pipeline comprises: selecting, using the generated vector, the output from the data generated by the at least two execution pipelines used to execute the producer instruction.Attorney Docket No. 56113-0750W01Feature 6: Selecting the output data comprises: multiplexing the data generated by the at least two execution pipelines used to execute the producer instruction.

[0006] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 is an example electronic device.

[0008] FIG. 2 is an example processing system.

[0009] FIG. 3 is an example bypass circuit.

[0010] FIG. 4 is an example process for bypassing in out of order processing.

[0011] Like reference numbers and designations in the various drawings indicate like elements.DETAILED DESCRIPTION

[0012] The Physical Register File (PRE) in out-of-order (OOO) processing is written by instructions producing data results and is read by consumers for source data. Processors, such as high performing CPU’s, can have pipelines with multiple processing stages before a final result of a producer is written to the PRF. A consumer can read source data from the PRF or bypass the PRF by reading intermediate processing data from one or more of the processing stages in a pipeline, e.g., prior to the pipeline resulting in data written to the PRF. When a consumer reads source data by bypassing the PRF, the consumer can use circuits referred to as bypass networks. Such bypass networks can be costly with respect to power as they involve using comparator (CAM) circuits to compare a consumer’s source PRF identification (ID) with the producer’s destination PRF ID across all possible bypass stages.

[0013] Techniques described in this document improve operation of a processor by reducing the required power of performing OOO processing, e.g., by reducing a number of CAM circuits required by consumers to obtain intermediate processor output. Techniques include using information of the intermediate stage for which data is to be obtained as control information for selecting intermediate output. The information of the intermediate stage for which data is to be obtained can be present at the time a producer generates such intermediate output for a consumer instruction. For example, the information of theAttorney Docket No. 56113-0750W01 intermediate stage can include two values representing (i) an execution lane and (ii) a stage within the execution lane where the intermediate output is to be generated. The information can be used by a multiplexor to select output from a set of intermediate outputs without having additional CAM circuits to compare data across all intermediate stages. Because each CAM circuit requires power and chip space, the techniques reduce power requirements of a computer chip and allow for additional elements or a smaller footprint.

[0014] FIG. 1 shows an example electronic device 100 that includes a system-on-chip (SoC) 106. The device 100 can be any device of the devices 102, such as a smartphone 102a, a tablet 102b, a laptop 102c, or a wearable device 102d. In general, the device 100 can be any device that processes data. The device 100 includes the SoC 106 and memory devices 104. The SoC 106 can transmit data to and from the memory’ device 104 to perform operations. The SoC 106 includes processing blocks 108, a memory’ unit 110, and a central processing unit (CPU) 112. The processing blocks 108 can be configured to perform operations, such as speech detection, machine learning processing, telecommunication signal processing, or a combination of these, among others. The processing blocks 108 can read or write to the memory devices 104. The memory unit 110 can be used as an interface for reading or writing data to the memory devices 104. The memory unit 110 can store data for processing or processing results generated by processing in the SoC 106. The CPU 112 can execute instructions, perform calculations, or help to control system functionality. The CPU 112 can include a single processor or multiple cores. The CPU 112 can be configured for general-purpose computing. The processing blocks 108 can be used to perform one or more functions not performed by the CPU 112 — e.g., processes that are performed frequently enough, or are process intensive enough, to warrant dedicated circuitry.

[0015] FIG. 2 shows an example processing system 200. The processing system 200 can be embodied in the CPU 112 or other elements of the device 100. In some cases, the processing system 200 can be embodied in an element, such as a GPU or SoC. The element can have multiple execution units. The element can use data bypasses to speed up execution of dependent instructions without waiting for data to be written to a register file. The system 200 can be embodied in circuits of a computer chip to help reduce power consumption of the chip w hen executing instructions. In general, techniques described can be used in bypass circuits for any elements in computer processing, such as instructions which can include micro-operations. A reservation station can track instructions which can include tracking instructions or micro-architected micro-operations. Instructions can beAttorney Docket No. 56113-0750W01 cracked by a decoder into multiple simpler micro-operations (also referred to as operations, ops, uops), e.g., before a rename process. Micro-operations can be processed in the same way as instructions for purposes of the techniques described in this document.

[0016] The system 200 includes a rename table 204, a reservation station (RSV) table 208, a selection circuit 210, an execution circuit 212, a physical register file (PRF) 214, and a bypass circuit 216. In general, the system 200 can improve operation, over existing computer chips, by using a bypass value stored in the RSV 208 to obtain source data from the bypass circuit 21 which results in fewer physical comparison circuits required on the computer chip itself, e.g., CAMs that compare a consumer instruction’s source PRF identifier with a producer instruction’s destination PRF identifier across all possible bypass stages can be replaced with the proposed use of the bypass value stored in the RSV 208 and associated techniques.

[0017] The system 200 is described in stages A through E which include operations performed using one or more circuits on a computer chip. In stage A, the system 200 renames destination logical registers to physical registers (e.g., physical register identifier) and writes those mappings into the rename table 204. Along with those mappings, in some cases, the system 200 writes information about which execution pipeline a given instruction will be scheduled to execute on or port bound to (e.g., a producer identifier). The system 200 can make mappings in the rename table 204 available for the RSV 208, e.g., in same cycle source renames. Data indicating the destination and source can be included in instruction data 202. The instruction data 202 can be generated by another element, such as an element on the SoC 106 or an element of the CPU 112. For any instruction, source and destination register information can be generated in a decode stage of a CPU pipeline that precedes a renaming stage, wherein the generated information can be used as input in the renaming stage. The system 200 can store the mapping between the destination and source in the rename table 204. The destination can indicate where, e.g., in what CPU register location, an instruction is configured to write output data. The source register can indicate a location from which an instruction is configured to obtain data.

[0018] The rename table 204 can include one or more mappings between a logical register identification or logical register number (LRN) and a physical register identification of physical register number (PRN). Each instruction executed, e.g., by the central processing unit 112, can access the rename table 204 to read out one or more source register PRNs and write a mapping for one or more destination registers into the rename table 204. Each instruction can be configured to obtain data for processing from one or more sourceAttorney Docket No. 56113-0750W01 registers and write output data to one or more destination registers. Instructions can be executed serially or in parallel and can use previously executed instruction output as input. In this way, instructions can be chained together to create more complex sets.

[0019] A producer can refer to an instruction that produces an output result. A consumer can refer to an instruction that consumes at least some output data for subsequent processing. When a producer is scheduled for execution (e.g., issued on an execution pipeline), the producer can broadcast its destination PRN. Broadcasting a PRN can include providing a signal value within one or more circuits that indicates the PRN. The destination PRN can represent where an output result generated by the producer will be stored in the PRF after processing.

[0020] In existing systems, a CAM circuit can be used to wake up entries in an RSV. In particular, a source of an instruction can be set to ready when a CAM circuit finds a match between a destination PRN and a PRN of the source. An additional set of CAMs can be used after instructions have been issued between older instruction destination PRNs in the execution pipeline against younger instruction source PRNs in the execution pipeline to compute the bypass controls. Existing systems can have two sets of CAMs. The first set can be used to mark source operand ready status which can wake up entries in an RSV. The second set can be used in execution unit pipelines to compare source destinations of producer instructions currently being executed against sources of subsequently issued consumer instructions to compute bypass controls. The proposed techniques of this specification allow for the removal of the second set of CAMs. The first set of CAMs can be used for both waking up entries and comparing source destinations between producers and consumers. Techniques described can further reduce the number of compares performed by the first set of CAMs, e.g., the system can use bypass values to mux destination PRNs from different execution pipes down before comparing against sources to reduce a number of compares. The number of compares can be reduced from N number of pipes per source to one compare per source, where N can be any number depending on system implementation.

[0021] The techniques described in this document improve processing by eliminating CAMs of existing systems by using producer identifier information to MUX down the destination PRN broadcasts to create a subset of destination PRNs for comparison. A bypass value can be used to further reduce power in a bypass network, e.g., by identifying a particular bypass stage within an execution pipeline of the producer. A reduced set of destination PRN broadcasts can be compared using fewer CAM circuits than existingAttorney Docket No. 56113-0750W01 systems that require CAMing against destination PRN broadcasts across all execution pipes.

[0022] The system 200 improves on existing systems by using a bypass value stored in an RSV, such as the RSV 208, to facilitate obtaining data from the bypass circuit 216, e.g., to select intermediate or final output of prior processing, while using fewer CAM circuits. In some cases, the bypass value includes two or more values. For example, the bypass value can include a producer identifier value that identifies a pipeline of a producer instruction and a bypass stage value that identifies a bypass stage within the pipeline.

[0023] In some cases, the bypass circuit 216 uses a multiplexor circuit to select output from among a set of inputs based on selection criteria. The selection criteria can be included in the RSV table 208 and can include an indication of an execution pipeline and an execution stage representing a circuit that will provide intermediate or final output for use by a consumer instruction. The selection criteria can include a bypass value stored in the RSV 208. The bypass circuit 216 can reduce power of a processor by multiplexing down, or MUXing down, to a subset of processing output that represents a processing output to be used in a subsequent consumer process. The bypass circuit 216 can use a producer identifier (e.g., included in the data 206 from the rename table 204). By reducing the possible pipelines using a bypass value in the RSV 208, the system 200 requires fewer CAM circuits to obtain and process intermediate processing output from a bypass network.

[0024] The following describes aspects of the system 200 in more detail, including the techniques that enable CAM circuits to be eliminated in OOO processing with regard to stages A through E shown in FIG. 2.

[0025] The system 200 can update the rename table 204 with the producer identifier that corresponds to the destination. For example, the system 200 can include, for each instruction to be executed, a producer identifier value and a PRN value. By using a producer identifier, physical register space can be reused for one or more instructions. By mapping a logical destination register to a unique physical register number (PRN) the system 200 allows logical registers to be re-used multiple times in out of order processing by breaking false dependencies in a program sequence. Two instructions may use the same physical register as a destination but may be separated in time such that the two instructions can both use the same physical register destination without conflict. To achieve efficiency and reduce the required size of a physical register destination, a producer identifier can be generated that uniquely refers to each instruction for a given physical register. In this way, physical register space can be reused and conserved.Attorney Docket No. 56113-0750W01

[0026] In stage B, the RSV table 208 obtains data 206 from the rename table 204. The data 206 includes a source producer identifier and a physical register identification (PRN). For example, the producer identifier and the PRN can be based on the destination and source information of the instruction data 202. The producer identifier and the PRN can be stored in the RSV table 208. Each element stored in the RSV table 208 can include an identifier, such as an operation code. The identifier can uniquely identify each instruction and corresponding data stored in the RSV table 208. Each element can include a destination PRN, e.g., where the instruction will write output.

[0027] Each instruction stored in the RSV table 208 can include a bypass value. The bypass value can include data that represents a combination of a producer identifier (e.g., which execution pipeline is used for executing a producer instruction) and a bypass stage corresponding to the producer identifier (e.g., a pipeline stage in a given execution pipeline). For example, a combination of a producer identifier and a bypass stage can represent intermediate output or final output to be used as a source for processing by a given instruction. In some cases, the bypass value includes a value of the producer identification of the data 206. In some cases, the bypass value includes a bit vector whose width is equal to a number of possible bypass stages of a given producer execution pipeline. The bits can represent a latency between a producer and consumer instruction which can be used by the system 200 to determine from which stage in an execution pipeline to obtain data.

[0028] In some cases, a bypass value is generated at the time of a source being set ready. For example, a source for an instruction can be set to ready through a process of wakeup, e.g., when the producer is issued to the execution circuit. A bypass value can be generated at the time of wakeup and can be updated to track a latency between a time of wakeup and a time when a consumer operation is selected by a selection circuit, e.g., using a monotonically increasing or decreasing value that increments or decrements corresponding to each compute cycle of the system 200. Latency information can identify if data can be obtained from the bypass circuit 216.

[0029] Each element in the RSV table 208 can include a source PRN. such as a value indicating a physical register identification. The source PRN can refer to a location in a physical register file, such as the PRF 214, where data for processing by an instruction is to be obtained prior to execution. Each instruction stored in the RSV table 208 that requires input data can refer to a source PRN indicating where the input data can be obtained. Each instruction stored in the RSV table 208 can include a source ready value. The source readyAttorney Docket No. 56113-0750W01 value can indicate when there is a value matching one or more criteria at the source PRN — e.g., the source ready value can indicate when an operation is ready to be performed because, before input data is ready, the operation might not be able to be performed. Each instruction in the RSV table 208 can include one or more sources of data for processing. Each source of data can include a bypass value, source PRN, and source ready value. In some cases, multiple destination PRNs are used by an operation.

[0030] Consumer instructions can get source data either from a PRF or through bypass networks from internal stages. The proposed techniques use a producer identifier to reduce power, e.g., by multiplexing down data paths from various execution pipelines to one or more of interest. The producer identifier can be used with a new field, stored in the RSV table 208 and referred to as the bypass value, to further reduce power. The RSV table 208 can include a producer identifier (e.g., identifying an execution pipeline for a producer instruction execution) and information tracking latency between a consumer wakeup and a consumer select (e.g., representing a producer execution lane, such as a bypass stage that will provide data). The producer identifier and the latency information can be used to reduce data bypass power, e.g., by reducing the number of CAM circuits required in OOO processing.

[0031] The bypass value can include a stage identification. As discussed, the stage identification can be represented as a bit vector, e.g., whose width is equal to the number of possible bypass stages. For example, if the number of possible bypass stages is twenty, a bit vector can include 20 values where the sole 1 , or sole 0 depending on implementation, indicates a bypass stage from which to obtain intermediate data. The stage identification bits can represent a latency between a producer and a consumer issuing. The latency between a producer and a consumer can indicate which processing stage will output data to be used as source data. The producer can refer to a producer that generates output that can be used as a source for a consumer, where the consumer represents one or more instructions represented as elements in the RSV table 208 with a source PRN that matches a destination PRN of the producer.

[0032] In some cases, the stage identification bits are written at the same time source ready bits are set, e.g., on operation wakeup. For example, when operations are scheduled to be performed and included in the RSV table 208, the stage identification bits can be written. In some cases, the bits are monotonically decreasing over time, e.g., from a first time when the stage identification bits are written to a second time when the results of a producer operation are written in PRF. In some cases, the bypass value can include a counter or bitAttorney Docket No. 56113-0750W01 vector. The bypass value can start from a value set at a time of wakeup, for a corresponding source, and increment until a time when a consumer of the RSV table 208, that includes the bypass value, is selected and issued for execution. The bypass value can increment, e.g., by one every compute cycle. The bypass value can keep track of a latency from when a producer is selected, and a corresponding source is woken up, to when a consumer that uses the woken up source is selected for execution. In some cases, the bypass value can increment to a value between 0 and N, where N can represent a number of bypass stages available from which to obtain data.

[0033] In stage C, the selection circuit 210 provides data from the RSV table 208 to the execution circuit 212 and the bypass circuit 216. The selection circuit 210 can broadcast one or more destination PRNs to the RSV table 208, e.g.. to set ready bits and bypass values. The selection circuit 210 can, at issue time, obtain values for an instruction of the RSV table 208, such as a source producer identifier, a bypass value, a source PRN, or a combination of these among others. The selection circuit 210 can include circuits to select one or more instructions of the RSV table 208 that include sources that are ready, as indicated by source ready values for each instruction. The selection circuit 210 can select instructions based on an age of instructions, where an age can indicate an amount of time since a given instruction was added to the RSV table 208. An instruction that has been in the RSV table 208 the longest, and has sources that are ready, can be selected. In some cases, other selection criteria are used.

[0034] In stage D, the execution circuit 212 obtains data from the selection circuit 210. For example, the execution circuit 212 can obtain a producer identifier. The execution circuit 212 can begin processing operations of a producer process. For example, the selection circuit 210 can identify a first instruction element in the RSV table 208. The first instruction relies on a producer instruction to generate data to be used as source data for the first instruction.. The selection circuit 210 can obtain data for the first instruction in the RSV table 208 and start the execution of the producer instruction in the execution circuit 212. The execution of the producer instruction in the execution circuit 212 can generate results to be used by the first instruction. The results of the producer instruction, generated by the execution circuit 212 can be stored in the PRF 214, at a location specified by a destination PRN, or can be stored in intermediate storage for one or more intermediate processing stages prior to storage at the PRF 214. The techniques described include storing a bypass value with the first instruction in the RSV table 208. The bypass circuit 216 can use the stored bypass value to obtain output data from the producer instruction execution,Attorney Docket No. 56113-0750W01 such as intermediate stage processing prior to final results being written to the PRF 214 or data written to the PRF 214. Using the stored bypass value can reduce latency for obtaining output data from the producer instruction.

[0035] Continuing the previous example, in stage E, the bypass circuit 216 can select data from the execution circuit 212, the PRF 214, or a combination of both to be used for the first instruction stored in the RSV table 208. The data from the execution circuit 212 or the PRF 214 can include output data from the producer instruction. Intermediate data obtained by the bypass circuit 216 can be provided to the execution circuit 212 for processing one or more instructions of the RSV table 208. Instructions executed by the execution circuit 212 can wake up corresponding sources corresponding to registers used by the executed instructions as destination registers. Wake up can occur in response to selection for, after, or during execution. This process of waking up can start the cycle of bypass value generation, and subsequent bypass network processing, over again. The bypass circuit 216 can obtain a version of the bypass value for an instruction stored in the RSV table 208. In some cases, a decoder circuit is used to decode a bypass value. The decoder circuit can decode a producer identifier and a bypass stage identification value included in the bypass value of an instruction of the RSV table 208. The decoder circuit can decode to generate a one hot vector representing the one stage of a producer instruction pipeline that is expected to generate intermediate output for processing by a selected instruction from the RSV table 208. The bypass circuit 216 can use the bypass value to select output from the execution circuit 212 or the PRF 214.

[0036] For example, as show n in the example bypass circuit of FIG. 3, the bypass circuit 216 can decode, or obtain previously decoded information, representing a bypass value 302. The bypass value 302 can be a version included in the RSV table 208 or a decoded version, e.g., a vector with values indicating from which stage the bypass circuit 216 is to obtain an output value 310. For example, the bypass value 302 can be decoded into a vector 304. The vector 304 includes zero values and a single value, e.g., a value of “1”, that indicates a stage to obtain output. The single value can correspond to a processing stage of the processing stages 306 for which an instruction of the RSV table 208 requires data. In the example of FIG. 3, the bypass circuit 216 obtains the output value 310 representing output from intermediate processing stage 307. The bypass circuit 216 can obtain output values from the PRF 308, e.g., in a case where a producer has already written a result to the PRF 214. The output value 310 can be used by an instruction stored in the RSV table 208 to generate subsequent output. The output value 310 can be provided, e.g., by the bypassAttorney Docket No. 56113-0750W01 circuit 216 of FIG. 2, to the execution circuit 212, to execute operations using the output value 310. In some cases, the output value 310 includes a destination PRN indicating a source destination that a producer instruction is writing to. The output value 310 can be compared, using one or more CAMs, to a source PRN of the RSV table 208 to determine whether or not to wake up one or more sources.

[0037] The processing system 200 can include a hardware processor (e.g., CPU 112 as depicted and described with reference to FIG. 1). For example, such a hardware processor can include one or more of a renaming register, a reservation station, an issue multiplexor, a physical register, a source bypass multiplexor, or execution circuitry. In some cases, the rename table 204 of FIG. 2 is an example of the renaming register and is configured to store a mapping between a producer identifier (e.g., source) and physical register identifier (e.g., destination). In some cases, the RSV table 208 of FIG. 2 is an example of a reservation station used in a hardware processor and is configured to store (i) source and destination information for operations to be executed (e.g., from the instruction data 202) and (ii) a bypass stage value that indicates a stage of a first execution pipeline used by the identified producer (e.g., the bypass value 302 of FIG. 3). In some cases, the selection circuit 210 of FIG. 2 is an example of the issue multiplexor and is configured to process data obtained from the reservation station based on instruction selection logic circuitry'. In some cases, the PRF 214 of the FIG. 2 is an example of the physical register and is configured to store results of performed operations. In some cases, the bypass circuit 216 is an example of the source bypass multiplexor and is configured to select a portion of execution output generated by a set of execution pipelines, where the execution output is obtained from at least one of (i) the physical register or (ii) an intermediate stage within an execution pipeline, and wherein the set of execution pipelines includes the first execution pipeline (e.g., the output value 310 obtained from the processing stages 306 and the PRF 308. In some cases, the execution circuit 212 of the FIG. 2 is an example of the execution circuitry and is configured to perform one or more operations using the selected portion of execution output from the source bypass multiplexor (e.g., after obtaining the output value 310, the output value 310 can be used by the execution circuit 212 in a subsequent operation that is included in the RSV table 208).

[0038] A hardware processor, such as a hardware processor configured to perform operations described in reference to FIG. 2, can include one or more of a reservation station configured to store a bypass value that indicates a stage of an execution pipeline used for a producer instruction; a physical register configured to store results of the producerAttorney Docket No. 56113-0750W01 instruction; a source bypass multiplexor configured to select output data from a set of execution pipelines that includes the execution pipeline based on the bypass value; and execution circuitry configured to execute an instruction associated with the bypass value stored in the reservation station using the selected output data from the source bypass multiplexor.

[0039] FIG. 4 is a flowchart of an example process 400 for bypassing in out of order processing. For convenience, the process 400 will be described as being performed by a system of one or more computers, located in one or more locations, and programmed appropriately in accordance with this specification. For example, an electronic device, e.g., the electronic device 100 of FIG. 1, appropriately configured, can perform the process 400. A processing system, such as the processing system of FIG. 2, appropriately configured, can perform the process 400.

[0040] The process 400 includes storing, in a reservation station, a bypass value that indicates a stage of an execution pipeline used to execute a producer instruction (402). In some cases, the bypass value is configured to change over time. As shown in FIG. 2, the RSV table 208 can store producer identification and physical register identification information for one or more operations with a bypass value. The RSV table 208 can store a bypass value, such as the bypass value 302 shown in FIG. 3.

[0041] In some cases, the rename table 204 can store a mapping between a source and destination, e.g., provided in instruction data 202. The destination can indicate where, e.g., which particular location in a physical register file, an operation is configured to write output data. The source can indicate where, e.g., which particular location in a physical register file, an operation is configured to obtain data for processing to generate data to be stored at the destination.

[0042] The process 400 includes selecting, using the bypass value, output data from the stage of the execution pipeline from data generated by at least two execution pipelines used to execute the producer instruction (404). For example, the bypass circuit 216 can select the output value 310 using the bypass value 302 as shown in FIG. 3.

[0043] The process 400 includes executing a consumer instruction stored in the reservation station associated with the bypass value using the selected output (406). For example, the bypass circuit 216 can provide the output value 310 for an operation in the RSV table 208. The execution circuit 212 can be used to generate an operation result using the output value 310.Attorney Docket No. 56113-0750W01

[0044] The subject matter and the actions and operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The subject matter and the actions and operations described in this specification can be implemented as or in one or more computer programs, e.g., one or more modules of computer program instructions, encoded on a computer program carrier, for execution by, or to control the operation of, data processing apparatus. The carrier can be a tangible non-transitory computer storage medium. Alternatively or in addition, the carrier can be an artificially- generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storage medium can be or be part of a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. A computer storage medium is not a propagated signal.

[0045] The term '‘data processing apparatus’’ encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. Data processing apparatus can include special-purpose logic circuitry, e.g., an FPGA (field programmable gate array), an ASIC (application-specific integrated circuit) . or a GPU (graphics processing unit). The apparatus can also include, in addition to hardware, code that creates an execution environment for computer programs, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0046] A computer program can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages; and it can be deployed in any form, including as a stand-alone program, e.g., as an app, or as a module, component, engine, subroutine, or other unit suitable for executing in a computing environment, which environment may include one or more computers interconnected by a data communication network in one or more locations.

[0047] A computer program may, but need not, correspond to a file in a file system. A computer program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicatedAttorney Docket No. 56113-0750W01 to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub-programs, or portions of code.

[0048] The processes and logic flows described in this specification can be performed by one or more computers executing one or more computer programs to perform operations by operating on input data and generating output. The processes and logic flows can also be performed by special-purpose logic circuitry, e.g., an FPGA. an ASIC, or a GPU, or by a combination of special-purpose logic circuitry and one or more programmed computers.

[0049] Computers suitable for the execution of a computer program can be based on general or special-purpose microprocessors or both, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a readonly memory or a random access memory or both. The essential elements of a computer are a central processing unit for executing instructions and one or more memory devices for storing instructions and data. The central processing unit and the memory can be supplemented by, or incorporated in, special-purpose logic circuitry .

[0050] Generally, a computer will also include, or be operatively coupled to, one or more mass storage devices, and be configured to receive data from or transfer data to the mass storage devices. The mass storage devices can be, for example, magnetic, magneto-optical, or optical disks, or solid state drives. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device, e.g., a universal serial bus (USB) flash drive, to name just a few.

[0051] To provide for interaction with a user, the subject matter described in this specification can be implemented on one or more computers having, or configured to communicate with, a display device, e.g., a LCD (liquid crystal display) monitor, or a virtual -reality (VR) or augmented-reality (AR) display, for displaying information to the user, and an input device by which the user can provide input to the computer, e.g., a keyboard and a pointing device, e.g., a mouse, a trackball or touchpad. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback and responses provided to the user can be any form of sensory feedback, e.g., visual, auditory, speech, or tactile feedback or responses; and input from the user can be received in any form, including acoustic, speech, tactile, or eye tracking input, including touch motion or gestures, or kinetic motion or gestures or orientation motion or gestures. In addition, a computer can interact with a user by sending documents to and receivingAttorney Docket No. 56113-0750W01 documents from a device that is used by the user; for example, by sending web pages to a web browser on a user's device in response to requests received from the web browser, or by interacting with an app running on a user device, e.g., a smartphone or electronic tablet. Also, a computer can interact with a user by sending text messages or other forms of message to a personal device, e.g., a smartphone that is running a messaging application, and receiving responsive messages from the user in return.

[0052] This specification uses the term “configured to” in connection with systems, apparatus, and computer program components. That a system of one or more computers is configured to perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. That one or more computer programs is configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by data processing apparatus, cause the apparatus to perform the operations or actions. That special-purpose logic circuitry is configured to perform particular operations or actions means that the circuitry has electronic logic that performs the operations or actions.

[0053] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what is being claimed, which is defined by the claims themselves, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially be claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claim may be directed to a subcombination or variation of a subcombination.

[0054] Similarly, while operations are depicted in the drawings and recited in the claims in a particular order, this by itself should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should notAttorney Docket No. 56113-0750W01 be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0055] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

[0056] What is claimed is:

Claims

Attorney Docket No. 56113-0750W01CLAIMS1. A hardware processor comprising: a reservation station configured to store a bypass value that indicates a stage of an execution pipeline used for a producer instruction; a physical register configured to store results of the producer instruction; a source bypass multiplexor configured to select output data from a set of execution pipelines that includes the execution pipeline based on the bypass value; and execution circuitry configured to execute an instruction associated with the bypass value stored in the reservation station using the selected output data from the source bypass multiplexor.

2. The hardware processor of claim 1, wherein the bypass value is configured to change over time.

3. The hardware processor of claim 2, wherein the bypass value is configured to monotonically increase over time.

4. The hardware processor of claim 1, wherein the source bypass multiplexor is configured to obtain the output data from both the physical register and one or more intermediate stages within the set of execution pipelines.

5. The hardware processor of claim 1, wherein the bypass value includes a bit vector.

6. The hardware processor of claim 1 , comprising: an issue multiplexor configured to process instructions stored in the reservation station based on instruction selection logic circuitry.

7. A method implemented by a hardware processor, comprising: storing, in a reservation station, a bypass value that indicates a stage of an execution pipeline used to execute a producer instruction;Attorney Docket No. 56113-0750W01 selecting, using the bypass value, output data from the stage of the execution pipeline from data generated by at least two execution pipelines used to execute the producer instruction; and executing a consumer instruction stored in the reservation station associated with the bypass value using the selected output.

8. The method of claim 7. wherein the hardware processor implementing the method comprises: a first register configured to store a mapping between a producer identifier and a physical register identifier for the producer instruction; a second register configured to store the bypass value that indicates the stage of the execution pipeline used to execute the producer instruction; a source bypass multiplexor configured to select, using the bypass value, the output data from the stage of the execution pipeline from data generated by the at least two execution pipelines used to execute the producer instruction; and execution circuitry configured to execute the consumer instruction stored in the reservation station associated with the bypass value.

9. The method of claim 7, wherein the bypass value is configured to change over time.

10. The method of claim 7, comprising: storing a mapping between (i) data representing where the consumer instruction is configured to write output data and (ii) data representing where the consumer instruction is configured to obtain data for processing.

11. The method of claim 7, wherein storing the bypass value comprises: storing a vector, wherein the vector includes a single value representing the stage of the execution pipeline used to execute the producer instruction.

12. The method of claim 7, comprising: generating a vector representing the bypass value, wherein selecting the output from the stage of the execution pipeline comprises:Attorney Docket No. 56113-0750W01 selecting, using the generated vector, the output from the data generated by the at least two execution pipelines used to execute the producer instruction.

13. The method of claim 7, wherein selecting the output data comprises: multiplexing the data generated by the at least two execution pipelines used to execute the producer instruction.

14. One or more computer storage media encoded with instructions that, when executed by one or more computers, cause the one or more computers to perform the method of any of claims 7 to 13.

15. A system comprising one or more computers and one or more storage devices on which are stored instructions that are operable, when executed by the one or more computers, to cause the one or more computers to perform the method of any of claims 7 to 13.

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