Systems and methods for timing synchronization of a plurality of serializers

Abstract

Systems and methods are provided for timing synchronization of serial data stream outputs of a plurality of serializers. The method involves providing a first serial data stream output of a first serializer of the plurality of serializers to an "AND" gate; selecting each serializer of the plurality of serializers other than the first serializer, to determine a timing offset for the serial data stream output of each selected serializer by providing the serial data stream output of the selected serializer to the "AND" gate, and then adjusting the timing offset for the serial data stream output of the selected serializer until an oversampling of a gate data stream output from the "AND" gate indicates a maximum timing alignment between the serial data stream output of the selected serializer and the first serial data stream output; and controlling the timing synchronization based on the determined timing offsets.

Description

Title: SYSTEMS AND METHODS FOR TIMING SYNCHRONIZATION OF A PLURALITY OF SERIALIZERSCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to United States Provisional Patent Application No. 63 / 696,508, filed September 19, 2024, the entirety of which is incorporated herein by reference.FIELD

[0002] The embodiments described herein generally relate to timing synchronization, and in particular to systems and methods for timing synchronization of serial data stream outputs of a plurality of serializers.BACKGROUND

[0003] The following is not an admission that anything discussed below is part of the prior art or part of the common general knowledge of a person skilled in the art.

[0004] Field programmable gate arrays (FPGAs) are used in many applications, including telecommunication and industrial applications, due to their high configurability and temporal precision. A FPGA chip may include multiple serializers or SerDes (serializer / deserializer). A serializer or SerDes can convert a parallel data stream input to a serial data stream output, or vice versa. The number of parallel bits that can be input at one time, to the serializer, when converting a parallel signal to a serial signal (or the number of parallel bits that can be output when converting a serial signal to a parallel signal) may be referred to as the bus size of the serializer.

[0005] A FPGA may provide an identical parallel data stream input to multiple serializers. In response, the serializers may generate serial data stream outputs that may be communicated over independent communication channels. Many applications (e.g., high- frequency trading) may require that the multiple serial data steam outputs provided over the independent communication channels are synchronized with high temporal precision.SUMMARY

[0006] This summary is intended to introduce the reader to the more detailed description that follows and not to limit or define any claimed or as yet unclaimed invention. One or more inventions may reside in any combination or sub-combination of the elements or process steps disclosed in any part of this document including its claims and figures.

[0007] The various examples described herein generally relate to systems and method for timing synchronization. The examples described herein can involve timing synchronization of serial data stream outputs of a plurality of serializers.

[0008] In accordance with an aspect of this disclosure, there is provided a method of timing synchronization of serial data stream outputs of a plurality of serializers. The method involves providing a first serial data stream output of a first serializer of the plurality of serializers to an “AND” gate. The method further involves selecting each serializer of the plurality of serializers other than the first serializer, to determine a timing offset for the serial data stream output of each selected serializer by providing the serial data stream output of the selected serializer to the “AND” gate; and then adjusting the timing offset for the serial data stream output of the selected serializer until an oversampling of a gate data stream output from the “AND” gate indicates a maximum timing alignment between the serial data stream output of the selected serializer and the first serial data stream output. The method further involves controlling the timing synchronization of the serial data stream outputs of the plurality of serializers based on the determined timing offsets.

[0009] A single field programmable gate array (FPGA) chip can include the plurality of serializers.

[0010] The method can further involve detecting a reset of a subset of the plurality of serializers, and in response to the reset detection: selecting as the first serializer any one of the plurality of serializers that is not associated with the reset detection; selecting each serializer associated with the reset detection to determine the timing offset for each serializer associated with the reset detection; and controlling the timing synchronization of the serial data stream outputs of the plurality of serializers based on the determined timing offsets for each serializer.

[0011] Providing the first serial data stream output of the first serializer, selecting the serial data stream output of each serializer other than the first serializer, and controlling thetiming synchronization of the serial data stream outputs of the plurality of serializers can be automatically performed in response to a synchronization command input.

[0012] An identical synchronization data input can be provided by a FPGA to the first serializer and the selected serializer for determining the timing offset.

[0013] In response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer can include identical data having relative timing misalignment corresponding to the timing offsets.

[0014] In response to the first serializer and the selected serializer supporting more than two voltage levels, the identical synchronization data input can be generated so that the serial data stream outputs of the first serializer and the selected serializer each include only two voltage levels including a low voltage level and a high voltage level.

[0015] In response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer can include a first sequence of “0”s or corresponding low voltage level values, at least one “1” or corresponding high voltage level value and a second sequence of “0”s or corresponding low voltage level values.

[0016] A number of “1”s in the gate data stream output from the “AND” gate can indicate the timing alignment between the serial data stream output of the selected serializer and the first serial data stream output.

[0017] A maximum data rate of the “AND” gate can be lower than a maximum data rate of the plurality of serializers and the synchronization data input can be provided by the FPGA so that the serial data stream outputs from the plurality of serializers to the “AND” gate comprises multiple repeating bits.

[0018] In accordance with an aspect of this disclosure, a system for timing synchronization of serial data stream outputs of a plurality of serializers is provided. The system includes an “AND” gate; and a FPGA circuit board including a FPGA. The FPGA is configured to provide a first serial data stream output of a first serializer of the plurality of serializers to the “AND” gate. The FPGA is further configured to select each serializer of the plurality of serializers other than the first serializer to determine a timing offset for the serial data stream output of each selected serializer by providing the serial data stream output of the selected serializer to the “AND” gate; and then adjusting the timing offset for the serialdata stream output of the selected serializer until an oversampling of a gate data stream output from the “AND” gate indicates a maximum timing alignment between the serial data stream output of the selected serializer and the first serial data stream output. The FPGA is further configured to control the timing synchronization of the serial data stream outputs of the plurality of serializers based on the determined timing offsets.

[0019] The system can further include a combination of multiple logical elements including the “AND” gate. The combination of multiple logical elements can be configured to: receive the serial data stream outputs of the plurality of serializers; provide the serial data stream outputs of the first serializer and each selected serializer to the “AND” gate; and provide the gate data stream output from the “AND” gate to the FPGA for the oversampling.

[0020] A single FPGA chip can include the plurality of serializers.

[0021] The FPGA can be further configured to detect a reset of a subset of the plurality of serializers and in response to the reset detection: select as the first serializer any one of the plurality of serializers that is not associated with the reset detection; select each serializer associated with the reset detection to determine the timing offset for each serializer associated with the reset detection; and control the timing synchronization of the serial data stream outputs of the plurality of serializers based on the determined timing offsets for each serializer.

[0022] The FPGA can be configured to control the timing synchronization of the serial data stream outputs of the plurality of serializers in response to a synchronization command input.

[0023] The FPGA circuit board can further include the “AND” gate.

[0024] The system can further include an external circuit board that includes the “AND” gate.

[0025] The external circuit board can be connected to a quad small form-factor pluggable (QSFP) slot of the FPGA circuit board.

[0026] The external circuit board can include at least two small form-factor pluggable (SFP) modules and each of the at least two SFP modules can be connected to a SFP slot of the FPGA circuit board.

[0027] The FPGA can be configured to provide an identical synchronization data input to the first serializer and the selected serializer for determining the timing offset.

[0028] In response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer can include identical data having relative timing misalignment corresponding to the timing offsets.

[0029] In response to the first serializer and the selected serializer supporting more than two voltage levels, the FPGA can be configured to provide the identical synchronization data input so that the serial data stream outputs of the first serializer and the selected serializer each have only two voltage levels including a low voltage level and a high voltage level.

[0030] In response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer can include a first sequence of “0”s or corresponding low voltage level values, at least one “1” or corresponding high voltage level value and a second sequence of “0”s or corresponding low voltage level values.

[0031] A number of “1”s in the gate data stream output from the “AND” gate can indicate the timing alignment between the serial data stream output of the selected serializer and the first serial data stream output.

[0032] A maximum data rate of the “AND” gate can be lower than a maximum data rate of the plurality of serializers and the FPGA can be configured to provide the synchronization data input so that the serial data stream outputs from the plurality of serializers to the “AND” gate includes multiple repeating bits.

[0033] The FPGA can be configured to control timing of the serial data stream outputs of the plurality of serializers using multiple shift registers.

[0034] In accordance with an aspect of this disclosure, a method of timing synchronization of serial data stream outputs of a plurality of serializers is provided. The method involves operating a switching circuit to provide a first serial data stream output of a first serializer of the plurality of serializers to an “AND” gate; and operating the switching circuit to select each serializer in the plurality of serializers other than the first serializer, to determine a timing offset for the serial data stream output of each selected serializer by providing the serial data stream output of the selected serializer to the “AND” gate. The method further involves adjusting, by a FPGA, the timing offset for the serial data stream output of the selectedserializer until an oversampling of a gate data stream output from the “AND” gate indicates a maximum timing alignment between the serial data stream output of the selected serializer and the first serial data stream output; and controlling, by the FPGA, the timing synchronization of the serial data stream outputs of the plurality of serializers based on the determined timing offsets.

[0035] The switching circuit can include a combination of logical elements, a multiplexer, a crossbar, or a cross-point switch.

[0036] An identical synchronization data input can be provided by the FPGA to the first serializer and the selected serializer for determining the timing offsets.

[0037] In response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer can include identical data having relative timing misalignment corresponding to the timing offsets.

[0038] In response to the first serializer and the selected serializer supporting more than two voltage levels, the identical synchronization data input can be generated so that the serial data stream outputs of the first serializer and the selected serializer each have only two voltage levels including a low voltage level and a high voltage level.

[0039] In response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer can include a first sequence of “0”s or corresponding low voltage level values, at least one “1” or corresponding high voltage level value and a second sequence of “0”s or corresponding low voltage level values.

[0040] A number of “1”s in the gate data stream output from the “AND” gate can indicate the timing alignment between the serial data stream output of the selected serializer and the first serial data stream output.

[0041] A maximum data rate of the “AND” gate can be lower than a maximum data rate of the plurality of serializers and the synchronization data input can be provided by the FPGA so that the serial data stream outputs from the plurality of serializers to the “AND” gate includes multiple repeating bits.

[0042] The method can further involve receiving an input designating the plurality of serializers for timing synchronization, and wherein the timing synchronization of the serialdata stream outputs of the plurality of serializers is controlled in response to the received input.

[0043] In accordance with an aspect of this disclosure, a system for timing synchronization of serial data stream outputs of a plurality of serializers is provided. The system includes a switching circuit, an “AND” gate, a controller, and a FPGA. The switching circuit has multiple input ports and multiple output ports, each serializer of the plurality of serializers being connected to an input port of the multiple input ports of the switching circuit to provide the serial data stream output from that serializer to that input port. The “AND” gate has a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the first gate input terminal is connected to a first output port of the multiple output ports of the switching circuit and the second gate input terminal is connected to a second output port of the switching circuit. The controller is configured to operate the switching circuit to provide a first serial data stream output of a first serializer of the plurality of serializers to the “AND” gate; and operate the switching circuit to select each serializer of the plurality of serializers other than the first serializer to determine a timing offset for the serial data stream output of each selected serializer by providing the serial data stream output of the selected serializer to the “AND” gate. The FPGA is configured to adjust the timing offset for the serial data stream output of the selected serializer until an oversampling of a gate data stream output from the “AND” gate indicates a maximum timing alignment between the serial data stream output of the selected serializer and the first serial data stream output; and control the timing synchronization of the serial data stream outputs of the plurality of serializers based on the determined timing offsets.

[0044] The switching circuit can include a combination of logical elements, a multiplexer, a crossbar, or a cross-point switch.

[0045] A single FPGA chip can include the plurality of serializers.

[0046] A single FPGA circuit board can include the FPGA, the switching circuit, the controller and the “AND” gate.

[0047] A FPGA circuit board can include the FPGA and an external circuit board can include the switching circuit, the controller and the “AND” gate.

[0048] The external circuit board can be connected to the FPGA circuit board using a Samtec Accelerate® connector, a small form-factor pluggable (SFP) slot, a quad small form-factor pluggable (QSFP) slot or a quad small form-factor pluggable double density (QSFPDD) slot.

[0049] A FPGA circuit board can include the FPGA, a first external circuit board can include the switching circuit and the controller, and a second external circuit board can include the “AND” gate.

[0050] The first external circuit board can be connected to the FPGA circuit board using a Samtec Accelerate® connector, a SFP slot, a quad small form-factor pluggable (QSFP) slot or a quad small form-factor pluggable double density (QSFPDD) slot.

[0051] The second external circuit board can be connected to the first external circuit board using a Samtec Accelerate® connector, a SFP slot, a quad small form-factor pluggable (QSFP) slot or a quad small form-factor pluggable double density (QSFPDD) slot.

[0052] The FPGA can be configured to provide an identical synchronization data input to the first serializer and the selected serializer for determining the timing offsets.

[0053] In response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer can include identical data having relative timing misalignment corresponding to the timing offsets.

[0054] In response to the first serializer and the selected serializer supporting more than two voltage levels, the FPGA can be configured to provide the identical synchronization data input so that the serial data stream outputs of the first serializer and the selected serializer each have only two voltage levels including a low voltage level and a high voltage level.

[0055] In response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer can include a first sequence of “0”s or corresponding low voltage level values, at least one “1” or corresponding high voltage level value and a second sequence of “0”s or corresponding low voltage level values.

[0056] A number of “1”s in the gate data stream output from the “AND” gate can indicate the timing alignment between the serial data stream output of the selected serializer and the first serial data stream output.

[0057] A maximum data rate of the “AND” gate can be lower than a maximum data rate of the plurality of serializers and the FPGA can be configured to provide the synchronizationdata input so that the serial data stream outputs from the plurality of serializers to the “AND” gate includes multiple repeating bits.

[0058] The FPGA can be configured to control timing of the serial data stream outputs of the plurality of serializers using multiple shift registers.

[0059] The FPGA can be further configured to receive an input designating the plurality of serializers for timing synchronization, and the FPGA can control the timing synchronization of the serial data stream outputs of the plurality of serializers in response to the received input.

[0060] It will be appreciated that the aspects and examples of systems and methods described herein may be used in any combination or sub-combination. Further aspects and advantages of the examples described herein will appear from the following description taken together with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0061] For a better understanding of the examples described herein and to show more clearly how they may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings which show at least one example, and in which:

[0062] FIG. 1 is a timing diagram showing timing misalignment between two example serial data streams;

[0063] FIG. 2A is a block diagram of an example system for timing synchronization of serial data stream outputs of a plurality of serializers;

[0064] FIG. 2B is a block diagram of another example system for timing synchronization of serial data stream outputs of a plurality of serializers;

[0065] FIG. 2C is a block diagram of another example system for timing synchronization of serial data stream outputs of a plurality of serializers;

[0066] FIG. 2D is a block diagram of another example system for timing synchronization of serial data stream outputs of a plurality of serializers;

[0067] FIG. 2E is a block diagram of another example system for timing synchronization of serial data stream outputs of a plurality of serializers;

[0068] FIG. 2F is a block diagram of another example system for timing synchronization of serial data stream outputs of a plurality of serializers;

[0069] FIG. 3 is a block diagram of an example serializer of the system of FIG. 2A;

[0070] FIG. 4A is a perspective view of an example retrofit device for the system of FIG. 2D;

[0071] FIG. 4B is another perspective view of the retrofit device of FIG. 4A;

[0072] FIG. 5 is a perspective view of another example retrofit device for the system of FIG. 2D;

[0073] FIG. 6 is a flowchart illustrating an example method of timing synchronization of serial data stream outputs of a plurality of serializers; and

[0074] FIGS. 7A-7D are timing diagrams showing example serial data stream outputs generated during the method of FIG. 6.

[0075] The skilled person in the art will understand that the drawings, described below, are for illustration purposes only. The drawings are not intended to limit the scope of the applicants' teachings in any way. Also, it will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.DESCRIPTION OF VARIOUS EMBODIMENTS

[0076] It will be appreciated that numerous specific details are set forth in order to provide a thorough understanding of the examples described herein. However, it will be understood by those of ordinary skill in the art that the examples described herein may be practiced without these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to obscure the examples described herein. Furthermore, this description is not to be considered as limiting the scope of the examples described herein in any way, but rather as merely describing the implementation of the various examples described herein.

[0077] It should be noted that terms of degree such as "substantially", "about" and "approximately" when used herein mean a reasonable amount of deviation of the modified term such that the end result is not significantly changed. These terms of degree should be construed as including a deviation of the modified term if this deviation would not negate the meaning of the term it modifies.

[0078] In addition, as used herein, the wording “and / or” is intended to represent an inclusive-or. That is, “X and / or Y” is intended to mean X or Y or both, for example. As a further example, “X, Y, and / or Z” is intended to mean X or Y or Z or any combination thereof.

[0079] The terms "including," "comprising" and variations thereof mean "including but not limited to," unless expressly specified otherwise. A listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise. The terms "a," "an" and "the" mean "one or more," unless expressly specified otherwise.

[0080] As used herein and in the claims, two or more elements are said to be “coupled”, “connected”, “attached”, or “fastened” where the parts are joined or operate together either directly or indirectly (i.e. , through one or more intermediate parts), so long as a link occurs. As used herein and in the claims, two or more elements are said to be “directly coupled”, “directly connected”, “directly attached”, or “directly fastened” where the element are connected in physical contact with each other. None of the terms “coupled”, “connected”, “attached”, and “fastened” distinguish the manner in which two or more elements are joined together.

[0081] The systems and methods described herein may be implemented in hardware or software, or a combination of both. The described examples may be implemented in computer programs executing on programmable computers, each computer including at least one processor, a data storage system (including volatile memory or non-volatile memory or other data storage elements or a combination thereof), and at least one communication interface. For example and without limitation, the programmable computers may be a server, network appliance, embedded device, computer expansion module, a personal computer, laptop, personal data assistant, cellular telephone, smart-phone device, tablet computer, a wireless device or any other computing device capable of being configured to carry out the methods described herein.

[0082] Optionally, the communication interface may be a network communication interface. Further optionally, when elements are combined, the communication interface may be a software communication interface, such as those for inter-process communication (IPC). Further optionally, there may be a combination of communication interfaces implemented as hardware, software, and combination thereof.

[0083] Program code may be applied to input data to perform the functions described herein and to generate output information. The output information is applied to one or more output devices, in known fashion.

[0084] Each program may be implemented in a high-level procedural or object oriented programming and / or scripting language, or both, to communicate with a computer system. However, the programs may be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language. Each such computer program may be stored on a storage media or a device (e.g. ROM, magnetic disk, optical disc) readable by a general or special purpose programmable computer, for configuring and operating the computer when the storage media or device is read by the computer to perform the procedures described herein. The system may also be implemented as a non-transitory computer-readable storage medium, configured with a computer program, where the storage medium so configured causes a computer to operate in a specific and predefined manner to perform the functions described herein.

[0085] Furthermore, the system, processes and methods described herein are capable of being distributed in a computer program product comprising a computer readable medium that bears computer usable instructions for one or more processors. The medium may be provided in various forms, including one or more diskettes, compact disks, tapes, chips, wireline transmissions, satellite transmissions, internet transmission or downloads, magnetic and electronic storage media, digital and analog signals, and the like. The computer useable instructions may also be in various forms, including compiled and non-compiled code.

[0086] Some elements herein may be identified by a part number, which is composed of a base number followed by an alphabetical or subscript-numerical suffix (e.g., 112a, or 112i ). Multiple elements herein may be identified by part numbers that share a base number in common and that differ by their suffixes (e.g., 112i, 1122, and 112s). All elements with acommon base number may be referred to collectively or generically using the base number without a suffix (e.g., 112).

[0087] The present disclosure generally relates to timing synchronization of serial data stream outputs of a plurality of serializers. Timing synchronization with high temporal precision may be required in many industrial and telecommunication applications. For example, in high-frequency trading applications, high temporal precision may be required for timing synchronization of serial data streams carrying trading-related data. As other examples, high temporal precision may be required in many data center and many high- performance computing, aerospace and data center applications.

[0088] Reference is now made to FIG. 1 , which is a timing diagram showing timing misalignment 112 between example serial data streams 104 and 108. The serial data streams 104 and 108 may be generated in response to an identical parallel data stream input. For example, a FPGA may provide an identical parallel data stream input to a first serializer and a second serializer. In response, the first serializer and the second serializer may generate independent serial data stream outputs 104 and 108 respectively. While the serial data streams 104 and 108 may include identical data, serial data stream 108 may have a timing delay with reference to serial data stream 104. The timing delay can result in a timing misalignment 112 between serial data streams 104 and 108.

[0089] The timing misalignment may be associated with a startup or a reset of the serializers and may be caused by factors including temperature, humidity effects on the serializer circuitry. In some cases, the timing misalignment may be associated with different distances (e.g., corresponding to different lengths of traces) between a FPGA pin and an output port that the FPGA pin is routed to. Data rate requirements imposed on the serializers (e.g., FPGA may not operate with low input parallel data width for high data rate operations) may cause the timing misalignment to increase. The timing misalignment can limit the precision or accuracy of timing synchronization between otherwise identical serial data streams. Many applications (e.g., high-frequency trading) may require independent serial data streams that are synchronized and have high timing alignment.

[0090] As will be described in greater detail below, the disclosed systems and methods can enable timing synchronization of serial data stream outputs of two or more serializers by determining the timing misalignment between the serial data streams and synchronizing theserial data streams to reduce / elim inate the timing misalignment. The timing synchronization may be performed during startup or reset of one or more of the serializers. Optionally, the timing synchronization may be performed in response to a synchronization command input. The synchronization command input may be a user input or may be automatically generated (e.g., in response to a trigger condition being met).

[0091] Reference is now made to FIG. 2A, which is a block diagram of an example system 200a for timing synchronization of serial data stream outputs of a plurality of serializers. System 200a may be used for synchronizing timing of any suitable number of serializers, for example, two or greater number of serializers.

[0092] System 200a may include a FPGA circuit board 204a. The FPGA circuit board 204a can include a variety of electronic components that are connected by a variety of electronic connections. FPGA circuit board 204a may include one or more FPGAs 208, a switching circuit 216, a controller 220, and at least one AND gate 224. In the illustrated example, FPGA circuit board 204a includes a single FPGA 208. Alternatively, FPGA circuit board 204a may include two or more FPGAs.

[0093] FPGA 208 may be implemented as an integrated circuit (IC), chip, and / or microchip. For example, FPGA 208 may be implemented as a set of electronic circuits on a semiconductor material, connected by conductive traces or wires. FPGA 208 may include a variety of electronic components that are reconfigurable (i.e. , field programmable) to perform different functions.

[0094] FPGA 208 may include one or more serializers 212, a processor 228, and a memory 232. FPGA 208 may include any suitable number of serializers. In the illustrated example, FPGA 208 includes serializers 212a-212n.

[0095] Serializers 212 of FPGA 208 can receive a clock signal from clock generator 236 and operate at a frequency corresponding to the clock signal frequency. Optionally, serializers 212 can receive the clock signal from an internal clock generator of FPGA 208. In the illustrated example, serializers 212 receive the clock signal from clock generator 236 that is external to FPGA 208. The external clock generator may enable higher accuracy performance for serializers 212 compared with using an internal clock generator of FPGA 208.

[0096] In the illustrated example, the same FPGA board 204a includes serializers 212 and clock generator 236. In other examples, clock generator 236 may be located on an external board that is connected to FPGA board 204a.

[0097] Concurrent reference is now made to FIGS. 2A and 3. FIG. 3 is a block diagram of an example serializer 212 of FPGA 208. Serializer 212 may include a clock multiplier 304 and an input sampler 308.

[0098] Input sampler 308 can sample signals received at the serializer 212. For example, input sampler 308 can sample a serial data stream input received at serializer 212.

[0099] Clock multiplier 304 can change signal frequencies, such as a clock signal. To convert a single serial data stream into a number of parallel data streams with the same bitrate, some components of the serializer 212 can operate at a higher clock speed than other components of FPGA 208. For example, if the serializer 212 has a bus size of eighty bits (i.e., can convert a single serial data stream into eighty parallel data streams), the serializer 212 can read eighty bits in the serial data stream in the time that one bit is output to each of the parallel data streams. That is, in this example, the serializer 212 can sample the serial data stream at a speed that is eighty times faster than the parallel data streams are output by the serializer 212.

[0100] The clock multiplier 304 of the serializer 212 can be configured to have a faster clock speed than other components of FPGA 208. The clock multiplier 304 can receive the clock signal from clock generator 236 and increase the frequency of the clock signal to provide a faster clock speed. For example, the clock speed of some of the components of FPGA 208 may be less than 1 gigahertz, whereas the clock speed of the clock multiplier 304 may be greater than 4 gigahertz or, in some cases, greater than 15 gigahertz (e.g., the clock speed of clock multiplier 304 may be 30 gigahertz). The clock multiplier 304 can include components such as, but not limited to, a PLL (phase-locked loop) or a CMUPLL (clock multiplier unit phase-locked loop).

[0101] The clock multiplier 304 can be configured to provide its clock speed to various components of the serializer 212 including, for example, input sampler 308. As a result, input sampler 308 can be configured to operate at the clock speed of the clock multiplier 304 to sample a signal received at serializer 212. Input sampler 308 may sample the received signal by measuring the value of the received signal during each clock cycle of the clock signalprovided by the clock multiplier 304. Accordingly, the number of samples measured by input sampler 308 can correspond to the clock speed of input sampler 308. That is, a higher clock speed typically corresponds to a larger number of measurements. The larger number of measurements can enable serializer 212 to oversample an input signal received by FPGA 208. For example, serializer 212 may be used to oversample an output data stream of AND gate 224, as will be described in greater detail herein below.

[0102] Optionally, processor 228 may be located external to FPGA 208 (for example, on FPGA circuit board 204a or an external circuit board connected to FPGA circuit board 204a. In the illustrated example, FPGA 208 includes processor 228. Processor 228 can be any suitable electronic component or logic implemented in the FPGA components for performing data processing and / or control operations. Processor 228 may perform various processing operations on data received by serializer 212. Optionally, processor 228 may control operations of other components of FPGA 208. For example, processor 228 may detect the timing misalignment between serial data stream outputs of serializers 212 based on the oversampled data stream output of AND gate 224. As another example, processor 228 may control the timing synchronization of serializers 212 based on the detected timing misalignments.

[0103] Optionally, memory 232 may be located external to FPGA 208 (for example, on FPGA circuit board 204a or an external circuit board connected to FPGA circuit board 204a. In the illustrated example, FPGA 208 includes memory 232. Memory 232 can be any suitable electronic component or logic implemented in the FPGA for storing processor-executable instructions and / or data for use with FPGA 208. Memory 232 can receive data from various other components of FPGA circuit board 204a and store the received data. For example, memory 232 can store instructions executable by processor 228 to control the timing synchronization of serializers 212. As another example, memory 232 can store timing offset data corresponding to maximum timing alignment for the serial data steam output of each serializer 212, as will be described in greater detail herein below.

[0104] Switching circuit 216 may be any suitable switching circuit having two or more input ports 240 and one or more output ports 244. Optionally, switching circuit 216 may be implemented as a combination of logical elements, a multiplexer, a crossbar or a cross-point switch.

[0105] Switching circuit 216 may have any suitable number of input ports 240. In the illustrated example, switching circuit 216 includes n number of input ports 240a-240n. Each serializer 212 may be connected to an input port 240 to provide the serial data stream output from that serializer 212 to that input port 240. For example, serial data stream output from serializer 212a may be provided to input port 240a and serial data stream output from serializer 212b may be provided to input port 240b.

[0106] Output ports 244 of switching circuit 216 may be connected to gate input terminals 248 of AND gate 224. For example, output ports 244a and 244b of switching circuit 216 may be connected to AND gate input terminals 248a and 248b respectively. A gate output terminal 252 of AND gate 224 may be connected to FPGA 208. A serializer 212 of FPGA 208 may be used to oversample the output provided by AND gate 224.

[0107] Controller 220 may be configured to operate switching circuit 216 to provide the serial data stream output from any two selected serializers 212 to AND gate 224. Controller 220 may operate switching circuit 216 based on command inputs received from FPGA 208. For example, controller 220 may receive a command input to provide the serial data stream output from serializers 212a and 212b to AND gate 224. In response, controller 220 may operate switching circuit 216 to route inputs received at input ports 240a and 240b to output ports 244a and 244b. As another example, controller 220 may receive a command input to provide the serial data stream output from serializers 212a and 212n to AND gate 224. In response, controller 220 may operate switching circuit 216 to route inputs received at input ports 240a and 240n to output ports 244a and 244b.

[0108] Reference is now made to FIG. 2B, which is a block diagram of an example system 200b for timing synchronization of serial data stream outputs of a plurality of serializers. System 200b may be used for synchronizing timing of any suitable number of serializers, for example, two or greater number of serializers.

[0109] System 200b may include at least one FPGA circuit board 204b and an external circuit board 256. The external circuit board 256 may be connected to FPGA circuit board 204b using a connection interface 260.

[0110] FPGA circuit board 204b may include one or more FPGAs 208. In the illustrated example, FPGA circuit board 204b includes a single FPGA 208. Alternatively, FPGA circuit board 204b may include two or more FPGAs. In the illustrated example, FPGA 208 includesprocessor 228 and memory 232. Alternatively, processor 228 and / or memory 232 may be located external to FPGA 208 (for example, on FPGA circuit board 204b or an external circuit board connected to FPGA circuit board 204b).

[0111] External circuit board 256 may include a switching circuit 216, a controller 220, and an AND gate 224.

[0112] Connection interface 260 may be any suitable connection interface that enables bidirectional communication between FPGA circuit board 204b and external circuit board 256. Preferably, connection interface 260 may be any suitable high-speed connection interface. For example, external circuit board 256 may be connected to FPGA circuit board 204b using Samtec’s AcceleRate® family of interconnects, small form-factor pluggable (SFP), quad small form-factor pluggable (QSFP), quad small form-factor pluggable double density (QSFP-DD), peripheral component interconnect express (PCIe) or universal serial bus (USB) connectors.

[0113] Connection interface 260 can enable the serial data stream outputs from serializers 212 to be provided to input ports 240 of switching circuit 216. Further, connection interface 260 can enable the output data stream from AND gate 224 to be provided to FPGA 208 for oversampling.

[0114] Optionally, external circuit board 256 may be implemented using a retrofit device. The retrofit device may be detachably connected to FPGA circuit board 204b.

[0115] In the illustrated example, a single FPGA circuit board 204b includes serializers 212a-212n of one FPGA 208. Alternatively, system 200b may include multiple FPGAs and serializers 212a-212n may be located on different FPGAs. System 200b may include multiple connection interfaces to provide interconnections between external circuit board 256 and the multiple FPGA circuit boards.

[0116] Reference is now made to FIG. 20, which is a block diagram of an example system 200c for timing synchronization of serial data stream outputs of a plurality of serializers. System 200c may be used for synchronizing timing of any suitable number of serializers, for example, two or greater number of serializers.

[0117] System 200c may include at least one FPGA circuit board 204c, a first external circuit board 264, and a second external circuit board 272. The first external circuit board264 may be connected to FPGA circuit board 204c using a first connection interface 268. The second external circuit board 272 may be connected to first external circuit board 264 using a second connection interface 276.

[0118] FPGA circuit board 204c may include one or more FPGAs 208. In the illustrated example, FPGA circuit board 204c includes a single FPGA 208. Alternatively, FPGA circuit board 204c may include two or more FPGAs. In the illustrated example, FPGA 208 includes processor 228 and memory 232. Alternatively, processor 228 and / or memory 232 may be located external to FPGA 208 (for example, on FPGA circuit board 204c or an external circuit board connected to FPGA circuit board 204c).

[0119] First external circuit board 264 may include a switching circuit 216 and a controller 220. Second external circuit board 272 may include an AND gate 224.

[0120] Connection interfaces 268 and 276 may be any suitable connection interface. Preferably, connection interfaces 268 and / or 276 may be any suitable high-speed connection interface. For example, first external circuit board 264 may be connected to FPGA circuit board 204c using Samtec’s AcceleRate® family of interconnects, small form-factor pluggable (SFP), quad small form-factor pluggable (QSFP), quad small form-factor pluggable double density (QSFP-DD), peripheral component interconnect express (PCIe) or universal serial bus (USB) connectors. Second external circuit board 272 may be connected to first external circuit board 264 using Samtec’s AcceleRate® family of interconnects, small form-factor pluggable (SFP), quad small form-factor pluggable (QSFP), quad small form-factor pluggable double density (QSFP-DD), peripheral component interconnect express (PCIe) or universal serial bus (USB) connectors.

[0121] First connection interface 268 can enable the serial data stream outputs from serializers 212 to be provided to input ports 240 of switching circuit 216. Second connection interface 276 can enable the output ports 244 of switching circuit 216 to be connected to AND gate input terminals 248. The combination of first connection interface 268 and second connection interface 276 can enable the output data stream from AND gate 224 to be provided to FPGA 208 for oversampling.

[0122] Optionally, first external circuit board 264 and / or second external circuit board 272 may be implemented using a retrofit device. The retrofit device may be detachably connected to FPGA circuit board 204c.

[0123] In the illustrated example, a single FPGA circuit board 204c includes serializers 212a-212n of one FPGA 208. Alternatively, system 200c may include multiple FPGAs and serializers 212a-212n may be located on different FPGAs. System 200c may include multiple connection interfaces to provide interconnections between first external circuit board 264, second external circuit board 272 and the multiple FPGA circuit boards.

[0124] Reference is now made to FIG. 2D, which is a block diagram of an example system 200d for timing synchronization of serial data stream outputs of a plurality of serializers. System 200d may be used for synchronizing timing of any suitable number of serializers, for example, two or greater number of serializers.

[0125] System 200d may include at least one FPGA circuit board 204d and an external circuit board 280. The external circuit board 280 may be connected to FPGA circuit board 204d using a connection interface 284.

[0126] FPGA circuit board 204d may include one or more FPGAs 208, a switching circuit 216, and a controller 220. In the illustrated example, FPGA circuit board 204d includes a single FPGA 208. Alternatively, FPGA circuit board 204d may include two or more FPGAs. In the illustrated example, FPGA 208 includes processor 228 and memory 232. Alternatively, processor 228 and / or memory 232 may be located external to FPGA 208 (for example, on FPGA circuit board 204d or an external circuit board connected to FPGA circuit board 204d).

[0127] External circuit board 280 may include an AND gate 224. Connection interface 284 may be any suitable connection interface that enables bidirectional communication between FPGA circuit board 204d and external circuit board 280. Preferably, connection interface 284 may be any suitable high-speed connection interface. For example, external circuit board 280 may be connected to FPGA circuit board 204d using Samtec’s AcceleRate® family of interconnects, small form-factor pluggable (SFP), quad small formfactor pluggable (QSFP), quad small form-factor pluggable double density (QSFP-DD), peripheral component interconnect express (PCIe) or universal serial bus (USB) connectors.

[0128] Connection interface 284 can enable the outputs from output ports 244 of switching circuit 216 to be provided to AND gate input terminals 248. Further, connection interface 284 can enable the output data stream from AND gate 224 to be provided to FPGA 208 for oversampling.

[0129] Optionally, external circuit board 280 may be implemented using a retrofit device. The retrofit device may be detachably connected to FPGA circuit board 204d.

[0130] In the illustrated example, a single FPGA circuit board 204d includes serializers 212a-212n of one FPGA 208. Alternatively, system 200d may include multiple FPGAs 212a- 212n may be located on different FPGAs. System 200d may include multiple connection interfaces to provide interconnections between external circuit board 280 and the multiple FPGA circuit boards.

[0131] Reference is now made to FIG. 2E, which is a block diagram of an example system 200e for timing synchronization of serial data stream outputs of two serializers 212a and 212b. System 200e may include a FPGA circuit board 204e having an FPGA 208 and an AND gate 224. System 200e may not include a switching circuit because only two serial data stream outputs need to be synchronized.

[0132] In the illustrated example, FPGA 208 includes processor 228 and memory 232. Alternatively, processor 228 and / or memory 232 may be located external to FPGA 208 (for example, on FPGA circuit board 204e or an external circuit board connected to FPGA circuit board 204e).

[0133] In the illustrated example, FPGA circuit board 204e includes a single FPGA 208. Alternatively, FPGA circuit board 204e may include two or more FPGAs.

[0134] In the illustrated example, a single FPGA circuit board 204e includes serializers 212a and 212b of one FPGA 208. Alternatively, system 200e may include two or more FPGAs circuit boards and serializers 212a and 212b may be located on different FPGAs.

[0135] In the illustrated example, FPGA circuit board 204e includes AND gate 224. Alternatively, an external circuit board may include AND gate 224. The external circuit board may be connected to FPGA circuit board 204e using any suitable connection interface that enables bidirectional communication between FPGA circuit board 204e and AND gate 224. Preferably, the connection interface may be any suitable high-speed connection interface. The connection interface may enable providing the serial data stream outputs from serializers 212a and 212b to gate input terminals 248 and providing the output data stream from AND gate 224 to FPGA 208 for oversampling. Optionally, the external circuit board may be implemented using a retrofit device. The retrofit device may be detachably connected to FPGA circuit board 204e.

[0136] Reference is now made to FIG. 2F, which is a block diagram of an example system 200f for timing synchronization of serial data stream outputs of a plurality of serializers. System 200f may be used for synchronizing timing of any suitable number of serializers, for example, two or greater number of serializers.

[0137] System 200f may include a FPGA circuit board 204f having an FPGA 208 and a timing offset detection circuit 292. Timing offset detection may have any suitable design to provide the combined functionality, described herein above, of switching circuit 216 and AND gate 224. In the illustrated example, timing offset detection circuit 292 may include a multiinput AND gate. The serial data stream outputs of serializers 212a-212n may be connected to the multiple inputs 294a-294n of the AND gate. FPGA 208 may be configured to utilize the multi-input AND gate to compare any two serial data stream outputs by controlling the other serial data stream outputs at logic “1”. The gate output terminal 296 may be connected to FPGA 208 to oversample the output data stream from the AND gate.

[0138] In other examples, timing offset detection circuit 292 may include any suitable combination of logical elements. For example, timing offset detection circuit 292 may include a combination of AND gates and OR gates. As another example, timing offset detection circuit 292 may include a combination of multiple AND gates with fanout buffers.

[0139] In the illustrated example, FPGA 208 includes processor 228 and memory 232. Alternatively, processor 228 and / or memory 232 may be located external to FPGA 208 (for example, on FPGA circuit board 204f or an external circuit board connected to FPGA circuit board 204f).

[0140] In the illustrated example, FPGA circuit board 204f includes a single FPGA 208. Alternatively, FPGA circuit board 204f may include two or more FPGAs.

[0141] In the illustrated example, a single FPGA circuit board 204f includes serializers 212a-212n of one FPGA 208. Alternatively, system 200f may include two or more FPGAs and serializers 212a-212n may be located on different FPGAs.

[0142] In the illustrated example, FPGA circuit board 204f includes timing offset detection circuit 292. Alternatively, an external circuit board may include timing offset detection circuit 292. The external circuit board may be connected to FPGA circuit board 204f using any suitable connection interface that enables bidirectional communication between FPGA circuit board 204f and timing offset detection circuit 292. Preferably, the connection interface maybe any suitable high-speed connection interface. The connection interface may enable providing the serial data stream outputs from serializers 212a-212n to gate input terminals 294a-294n and providing the output data stream from the AND gate to FPGA 208 for oversampling. Optionally, the external circuit board may be implemented using a retrofit device. The retrofit device may be detachably connected to FPGA circuit board 204f.

[0143] Reference is now made to FIGS. 4A and 4B showing perspective views of an example retrofit device 404. Retrofit device 404 may include an AND gate, a switching circuit and / or a timing offset detection circuit. In the illustrated example, retrofit device 404 may include an external circuit board 280 having an AND gate 224.

[0144] Retrofit device 404 may be insertable into a QSFP slot of an FPGA circuit board (e.g., FPGA circuit board 204b, 204c, or 204d) to provide a high-speed connection interface 284 having four bidirectional data lanes available for communication between FPGA circuit board 204d and external circuit board 280. During operation, only two of the four available data lanes may be utilized for providing the outputs from switching circuit 216 to AND gate 224 and for providing the output data stream from AND gate 224 to FPGA 208 for oversampling. In examples where the retrofit device includes a timing offset detection circuit having a combination of multiple logical elements, all four of the available data lanes may be utilized during operation.

[0145] Reference is now made to FIG. 5 showing a perspective view of an example retrofit device 504. Retrofit device 504 may include an AND gate, a switching circuit and / or a timing offset detection circuit. In the illustrated example, retrofit device 504 includes an external circuit board 280 having an AND gate 224. Retrofit device 504 may include a combination of two SFP modules 508a and 508b.

[0146] Retrofit device 504 may be insertable into two SFP slots of an FPGA circuit board (e.g., FPGA circuit board 204b, 204c, or 204d) to provide a high-speed connection interface (e.g., connection interfaces 260, 268, 276 or 284). The high-speed connection interface may include two high-speed transmit data lanes and two high-speed receive data lanes (each SFP module 508 enabling one high-speed transmit data lane and one high-speed receive data lane). During operation, the two high-speed transmit data lanes of connection interface 284 may be utilized to provide the outputs from switching circuit 216 to AND gate 224 andany one of the two high-speed receive data lanes may be utilized to provide the output data stream from AND gate 224 to FPGA 208 for oversampling.

[0147] Reference is now made to FIG. 6, which is a flowchart illustrating an example method 600 of timing synchronization of serial data stream outputs of a plurality of serializers. Method 600 may be performed, for example, using system 200 and concurrent reference is made herein to components illustrated in FIGS. 2A to 2D.

[0148] Memory 232 of FGPA 208 may store process-executable instructions for execution of method 600. Processor 228 may execute the instructions to perform method 600 for timing synchronization of serial data stream outputs of serializers 212a-212n. A single FPGA chip or different FPGA chips on one or more FPGA circuit boards may include the serializers 212a-212n.

[0149] At act 604, a first serial data stream output of a first serializer may be provided to an AND gate. For example, processor 228 may provide the serial data stream output of serializer 212a to AND gate 224. Optionally, processor 228 may provide a command input to controller 220 to operate switching circuit 216 to enable the serial data stream output of serializer 212a to be provided at AND gate input terminal 248a.

[0150] At act 608, method 600 may include selecting serializer other than the first serializer (e.g., serializers 212b-212n) to determine a timing offset for the serial data stream output of each selected serializer. Method 600 may further include performing acts 612 and 616 to determine the timing offset for the selected serializer.

[0151] For example, method 600 may include timing synchronization of serial data stream outputs of two serializers 212a and 212b. Processor 228 may select serializer 212a as the first serializer at act 604. Further, selecting each serializer other than the first serializer may only include selecting serializer 212b and determining a timing offset for the serial data stream output of serializer 212b.

[0152] As another example, method 600 may include timing synchronization of serial data stream outputs of three serializers 212a, 212b and 212c. Processor 228 may select serializer 212a as the first serializer at act 604. Further, selecting each serializer other than the first serializer may include processor 228 first selecting serializer 212b and determining a timing offset for the serial data stream output of serializer 212b. Further, processor 228 may select serializer 212c and determining a timing offset for the serial data stream output of serializer212c. The selection may be further extended in a similar manner based on the total number of serializers to be synchronized.

[0153] For each selected serializer, at act 612, the serial data stream output of the selected serializer is provided to the AND gate. For example, if serializer 212b is the selected serializer, processor 228 may provide the serial data stream output of serializer 212b to AND gate 224. Optionally, processor 228 may provide a command input to controller 220 to operate switching circuit 216 to enable the serial data stream output of serializer 212b to be provided at AND gate input terminal 248b.

[0154] At act 616, the timing offset for the serial data stream output of the selected serializer may be adjusted until an oversampling of a gate data stream output from the AND gate indicates a maximum timing alignment between the serial data stream output of the selected serializer and the first serial data stream output. For example, if serializer 212b is the selected serializer, processor 228 may adjust the timing offset for the serial data stream output of serializer 212b until the oversampled gate data stream output from AND gate 224 indicates maximum timing alignment between the serial data stream outputs of serializer 212a and serializer 212b.

[0155] Reference is now additionally made to FIGS. 7A to 7D showing timing diagrams of example serial data stream outputs 704, 708 and 712 of serializer 212a, serializer 212b and AND gate 224 respectively. As illustrated in FIG. 7A, serial data stream outputs 704 and 708 may include identical data but having timing misalignment 716a. Optionally, processor 228 may provide an identical synchronization data input to the serializers for the purpose of determining the timing offset. In the illustrated example, serial data stream outputs 704 and 708 include a first sequence of “0”s, followed by a “1” (corresponding to time duration 720 for output 708 and time duration 724 for output 704), further followed by a second sequence of “0”s. Because of timing misalignment 716a, there may not be any overlap between time durations 720 and 724 and therefore, serial data stream output 712 of AND gate may include all “0”s (as illustrated in FIG. 7A).

[0156] Processor 228 may adjust the timing offset for the serial data stream output 708 by shifting the output data (either left or right) by one bit. Any suitable technique / component may be used for shifting the output by one bit. Optionally, method 300 may utilize one or more shift registers to shift the output by any suitable number of bits. In the exampleillustrated in FIG. 7B, processor 228 right shifts the serial data stream output 708 by duration 728b corresponding to one bit. As illustrated in FIG. 7B, this can reduce the timing misalignment from 716a (FIG. 7A) to 716b (FIG. 7B). Further, there may be an overlap between time durations 720 and 724 and the serial data stream output 712 of the AND gate may be “1” for duration 732b where both serial data stream outputs 704 and 708 are “1”.

[0157] As illustrated in FIG. 70, processor 228 may further adjust the timing offset for the serial data stream output 708 by shifting the output further right by another bit. The total timing offset (with reference to initial position in FIG. 7A) may be 728c. As illustrated in FIG. 7C, this can further reduce the magnitude of timing misalignment from 716b (FIG. 7B) to 716c (FIG. 7C). The overlap between time durations 720 and 724 may be greater in FIG. 7C compared with FIG. 7B. Therefore, the duration 732c for which serial data stream output 712 of the AND gate is “1” may be greater compared with duration 732b (FIG. 7B).

[0158] As illustrated in FIG. 7D, processor 228 may further adjust the timing offset for the serial data stream output 708 by shifting the output further right by another bit. The total timing offset (with reference to initial position in FIG. 7A) may be 728d. As illustrated in FIG. 7D, this can increase the magnitude of timing misalignment from 716c (FIG. 70) to 716d (FIG. 7D). There may not be any overlap between time durations 720 and 724 and therefore, serial data stream output 712 of AND gate may include all “0”s.

[0159] Processor 228 may stop adjusting the timing offset further in response to an increasing trend of timing misalignment. Optionally, processor 228 may perform a fixed number of timing offsets. The fixed number may be based on performance parameters associated with the serializers.

[0160] An oversampling of the serial data stream output 712 of AND gate 224 can indicate the timing misalignment between serial data stream outputs 704 and 708. For example, serial data stream outputs 704 and 708 may correspond to a clock speed of 1 gigahertz, and the serial data stream output 712 of AND gate 224 may be oversampled at any suitable higher frequency (e.g., 30 gigahertz).

[0161] For the timing diagrams illustrated in FIGS. 7A to 7D, the oversampled serial data stream output 712 of AND gate 224 may include all 0s for the examples illustrated in FIGS. 7A and 7D. For the example illustrated in FIG. 7B, the oversampled serial data stream output 712 of AND gate 224 may include a first sequence of 0s, m number of 1 s corresponding toduration 732b and a second sequence of Os. For the example illustrated in FIG. 7C, the oversampled serial data stream output 712 of AND gate 224 may include a first sequence of Os, n2 number of 1 s corresponding to duration 732c and a second sequence of Os. n2 can be greater than m (corresponding to duration 732c being greater than duration 732b) indicating maximum timing alignment between serial data stream outputs 704 and 708. In response, processor 228 may use the corresponding timing offset 728c as the determined timing offset for selected serializer 212b with reference to serializer 212a. The determined timing offset may be stored in memory 232.

[0162] At act 620, processor 228 may check whether a timing offset has been determined for each of the other serializers 212b-212n. Processor 228 may repeat acts 608, 612 and 616 for any remaining serializers until a timing offset is determined for each of the other serializers 212b-212n. If a timing offset has been determined for each of the other serializers, method 600 may proceed to act 624.

[0163] The granularity of the misalignment detection may be limited by the maximum supported data rate of the AND gate. For example, the data rate of AND gate 224 may be lower than the maximum supported data rate of serializers 212. To address this issue, processor 228 may provide a synchronization data input including multiple repeating bits to serializers 212 for the purpose of determining the timing offset. The repetition factor may be selected based on the difference in the maximum supported data rates.

[0164] For example, the maximum supported data rate by the AND gate may be 10.7 Gbps (corresponding to a time duration of 93ps). The example AND gate may support misalignment detection for the 10Gbps Ethernet Standard, corresponding to a data rate of 10.3125Gbps and a single bit duration of 96.9ps. However, the example AND gate may not support accurate misalignment detection for higher data rates such as 25G Ethernet (corresponding to data rate of 25.78125Gbps and a single bit duration of 38.4ps). In this example, processor 228 may provide a synchronization data input including a repetition factor of 3 or greater. For an example repetition factor of 3, the synchronization data input may include 3 repeated bits for each data bit (e.g., 3 repeated “1”s for each “1”). Processor 228 may provide the synchronization data input including the repeated bits to serializers 212. In response, the serial data stream output of each serializer may include a first sequence of “0”s, followed by 3 repeating “1”s, followed by a second sequence of “0”s. The total durationof the 3 repeated “1”s can be 3 * 38.4ps = 115.2ps and the example AND gate can support accurate misalignment detection because 115.2ps > 93ps.

[0165] While the examples of timing offset determination described herein above are with reference to a simple transmission media between the serializers and the AND gate (e.g., having just two voltage levels - a voltage level corresponding to a logic “0” and a high voltage level corresponding to a logic “1”), method 600 may be suitably adapted for more complex transmission media. For example, the transmission media between the serializers and the AND gate may utilize PAM4 modulation having four voltage levels. Method 600 may utilize a synchronization data input that includes a sequence of “00” (instead of a “0”) and “10” (instead of a “1”) so that the input at the AND gate is limited to the two voltage levels corresponding to “00” and “10”.

[0166] At act 624, the timing synchronization of the serial data stream outputs of the serializers may be controlled based on the determined timing offsets. Any suitable technique and / or components may be used for the timing synchronization. For example, shift registers may be used to left or right shift the serial data stream outputs. The determined timing offsets can indicate the timing relationship between all the serial data stream outputs. Processor 228 may select the most delayed serial data stream output as a reference output and synchronize all the other serial data stream outputs with respect to the most delayed serial data stream output based on the determined timing offsets.

[0167] Method 600 may be executed in response to a synchronization command input. For example, system 200 may execute method 600 in response to a synchronization command input from an external device. Optionally, method 600 may be automatically executed based on a stored schedule (e.g., based on scheduling instructions stored in memory 232).

[0168] Alternatively or in addition, method 600 may be automatically executed based on a trigger condition being met. For example, system 200 may execute method 600 in response to detecting a reset of serializers 212. Method 600 may be performed as described herein above if the reset detection is associated with all serializers 212a-212n. If the reset detection is associated with only a subset of serializers 212a-212n, processor 228 may select any one of the non-reset serializers as the first serializer. The timing offset of the other nonreset serializers with reference to the first serializer may already be determined. Processor228 may perform acts 608, 612 and 616 to determine the timing offset for each of the reset serializers. Further, processor 228 may control the timing synchronization of the serial data stream outputs based on the previously determined timing offsets for the non-reset serializers and the newly determined timing offsets for the reset serializers.

[0169] Optionally, method 600 may be executed each time for timing synchronization of serial data stream outputs of the same set of serializers 212a-212n. For example, the process-executable instructions stored in memory 232 may specify the serializers for timing synchronization. Alternatively, method 600 may not always be executed for the same set of serializers. For example, method 600 may include receiving an input designating the serializers for timing synchronization. For example, FPGA 208 may receive an input designating serializers 212a-212d for timing synchronization. In response, method 600 may proceed through acts 604-624 to synchronize the serial data stream outputs of designated serializers 212a-212d.

[0170] Numerous specific details are set forth herein in order to provide a thorough understanding of the examples described herein. However, it will be understood by those of ordinary skill in the art that these examples may be practiced without these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to obscure the description of the examples. Furthermore, this description is not to be considered as limiting the scope of these examples in any way, but rather as merely describing the implementation of these various examples.

Claims

WE CLAIM:1 . A method of timing synchronization of serial data stream outputs of a plurality of serializers, the method comprising: providing a first serial data stream output of a first serializer of the plurality of serializers to an “AND” gate; selecting each serializer of the plurality of serializers other than the first serializer, to determine a timing offset for the serial data stream output of each selected serializer by: providing the serial data stream output of the selected serializer to the “AND” gate; and then adjusting the timing offset for the serial data stream output of the selected serializer until an oversampling of a gate data stream output from the “AND” gate indicates a maximum timing alignment between the serial data stream output of the selected serializer and the first serial data stream output; and controlling the timing synchronization of the serial data stream outputs of the plurality of serializers based on the determined timing offsets.

2. The method of claim 1 , wherein a single field programmable gate array (FPGA) chip comprises the plurality of serializers.

3. The method of any one of claims 1 and 2, further comprising detecting a reset of a subset of the plurality of serializers, and in response to the reset detection: selecting as the first serializer any one of the plurality of serializers that is not associated with the reset detection; selecting each serializer associated with the reset detection to determine the timing offset for each serializer associated with the reset detection; and controlling the timing synchronization of the serial data stream outputs of the plurality of serializers based on the determined timing offsets for each serializer.

4. The method of any one of claims 1 to 3, wherein providing the first serial data stream output of the first serializer, selecting the serial data stream output of each serializer other than the first serializer, and controlling the timing synchronization of the serial data stream outputs of the plurality of serializers are automatically performed in response to a synchronization command input.

5. The method of any one of claims 1 to 4, wherein an identical synchronization data input is provided by a FPGA to the first serializer and the selected serializer for determining the timing offset.

6. The method of claim 5, wherein, in response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer comprises identical data having relative timing misalignment corresponding to the timing offsets.

7. The method of claim 6, wherein, in response to the first serializer and the selected serializer supporting more than two voltage levels, the identical synchronization data input is generated so that the serial data stream outputs of the first serializer and the selected serializer each comprise only two voltage levels including a low voltage level and a high voltage level.

8. The method of claim 7, wherein, in response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer comprises a first sequence of “0”s or corresponding low voltage level values, at least one “1” or corresponding high voltage level value and a second sequence of “0”s or corresponding low voltage level values.

9. The method of claim 8, wherein a number of “1”s in the gate data stream output from the “AND” gate indicates the timing alignment between the serial data stream output of the selected serializer and the first serial data stream output.

10. The method of any one of claims 5 to 9, wherein a maximum data rate of the “AND” gate is lower than a maximum data rate of the plurality of serializers and the synchronization data input is provided by the FPGA so that the serial data stream outputs from the plurality of serializers to the “AND” gate comprises multiple repeating bits.

11. A system for timing synchronization of serial data stream outputs of a plurality of serializers, the system comprising: an “AND” gate; and a FPGA circuit board including a FPGA configured to: provide a first serial data stream output of a first serializer of the plurality of serializers to the “AND” gate; select each serializer of the plurality of serializers other than the first serializer to determine a timing offset for the serial data stream output of each selected serializer by: providing the serial data stream output of the selected serializer to the “AND” gate; and then adjusting the timing offset for the serial data stream output of the selected serializer until an oversampling of a gate data stream output from the “AND” gate indicates a maximum timing alignment between the serial data stream output of the selected serializer and the first serial data stream output; and control the timing synchronization of the serial data stream outputs of the plurality of serializers based on the determined timing offsets.

12. The system of claim 11 , further comprising a combination of multiple logical elements including the “AND” gate, the combination of multiple logical elements being configured to: receive the serial data stream outputs of the plurality of serializers; provide the serial data stream outputs of the first serializer and each selected serializer to the “AND” gate; and provide the gate data stream output from the “AND” gate to the FPGA for the oversampling.

13. The system of any one of claims 11 and 12, wherein a single FPGA chip comprises the plurality of serializers.

14. The system of any one of claims 11 to 13, wherein the FPGA is further configured to detect a reset of a subset of the plurality of serializers and in response to the reset detection: select as the first serializer any one of the plurality of serializers that is not associated with the reset detection; select each serializer associated with the reset detection to determine the timing offset for each serializer associated with the reset detection; and control the timing synchronization of the serial data stream outputs of the plurality of serializers based on the determined timing offsets for each serializer.

15. The system of any one of claims 11 to 14, wherein the FPGA is configured to control the timing synchronization of the serial data stream outputs of the plurality of serializers in response to a synchronization command input.

16. The system of any one of claims 11 to 15, wherein the FPGA circuit board further includes the “AND” gate.

17. The system of any one of claims 11 to 15 further comprising an external circuit board that includes the “AND” gate.

18. The system of claim 17, wherein the external circuit board is connected to a quad small form-factor pluggable (QSFP) slot of the FPGA circuit board.

19. The system of any one of claims 17 and 18, wherein the external circuit board comprises at least two small form-factor pluggable (SFP) modules and each of the at least two SFP modules is connected to a SFP slot of the FPGA circuit board.

20. The system of any one of claims 11 to 19, wherein the FPGA is configured to provide an identical synchronization data input to the first serializer and the selected serializer for determining the timing offset.21 . The system of claim 20, wherein, in response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer comprises identical data having relative timing misalignment corresponding to the timing offsets.

22. The system of claim 21 , wherein, in response to the first serializer and the selected serializer supporting more than two voltage levels, the FPGA is configured to provide the identical synchronization data input so that the serial data stream outputs of the first serializer and the selected serializer each comprise only two voltage levels including a low voltage level and a high voltage level.

23. The system of claim 22, wherein, in response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer comprises a first sequence of “0”s or corresponding low voltage level values, at least one “1” or corresponding high voltage level value and a second sequence of “0”s or corresponding low voltage level values.

24. The system of claim 23, wherein a number of “1”s in the gate data stream output from the “AND” gate indicates the timing alignment between the serial data stream output of the selected serializer and the first serial data stream output.

25. The system of any one of claims 20 to 24, wherein a maximum data rate of the “AND” gate is lower than a maximum data rate of the plurality of serializers and the FPGA is configured to provide the synchronization data input so that the serial data stream outputs from the plurality of serializers to the “AND” gate comprises multiple repeating bits.

26. The system of any one of claims 11 to 26, wherein the FPGA is configured to control timing of the serial data stream outputs of the plurality of serializers using multiple shift registers.

27. A method of timing synchronization of serial data stream outputs of a plurality of serializers, the method comprising:operating a switching circuit to provide a first serial data stream output of a first serializer of the plurality of serializers to an “AND” gate; operating the switching circuit to select each serializer in the plurality of serializers other than the first serializer, to determine a timing offset for the serial data stream output of each selected serializer by providing the serial data stream output of the selected serializer to the “AND” gate; adjusting, by a FPGA, the timing offset for the serial data stream output of the selected serializer until an oversampling of a gate data stream output from the “AND” gate indicates a maximum timing alignment between the serial data stream output of the selected serializer and the first serial data stream output; and controlling, by the FPGA, the timing synchronization of the serial data stream outputs of the plurality of serializers based on the determined timing offsets.

28. The method of claim 27, wherein the switching circuit comprises a combination of logical elements, a multiplexer, a crossbar, or a cross-point switch.

29. The method of any one of claims 27 and 28, wherein an identical synchronization data input is provided by the FPGA to the first serializer and the selected serializer for determining the timing offsets.

30. The method of claim 29, wherein, in response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer comprises identical data having relative timing misalignment corresponding to the timing offsets.31 . The method of claim 30, wherein, in response to the first serializer and the selected serializer supporting more than two voltage levels, the identical synchronization data input is generated so that the serial data stream outputs of the first serializer and the selected serializer each comprise only two voltage levels including a low voltage level and a high voltage level.

32. The method of claim 31 , wherein, in response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializercomprises a first sequence of “0”s or corresponding low voltage level values, at least one “1” or corresponding high voltage level value and a second sequence of “0”s or corresponding low voltage level values.

33. The method of claim 32, wherein a number of “1”s in the gate data stream output from the “AND” gate indicates the timing alignment between the serial data stream output of the selected serializer and the first serial data stream output.

34. The method of any one of claims 29 to 33, wherein a maximum data rate of the “AND” gate is lower than a maximum data rate of the plurality of serializers and the synchronization data input is provided by the FPGA so that the serial data stream outputs from the plurality of serializers to the “AND” gate comprises multiple repeating bits.

35. The method of any one of claims 29 to 34 further comprising receiving an input designating the plurality of serializers for timing synchronization, and wherein the timing synchronization of the serial data stream outputs of the plurality of serializers is controlled in response to the received input.

36. A system for timing synchronization of serial data stream outputs of a plurality of serializers, the system comprising: a switching circuit having multiple input ports and multiple output ports, each serializer of the plurality of serializers being connected to an input port of the multiple input ports of the switching circuit to provide the serial data stream output from that serializer to that input port; an “AND” gate having a first gate input terminal, a second gate input terminal and a gate output terminal, wherein the first gate input terminal is connected to a first output port of the multiple output ports of the switching circuit and the second gate input terminal is connected to a second output port of the switching circuit; a controller configured to: operate the switching circuit to provide a first serial data stream output of a first serializer of the plurality of serializers to the “AND” gate; andoperate the switching circuit to select each serializer of the plurality of serializers other than the first serializer to determine a timing offset for the serial data stream output of each selected serializer by providing the serial data stream output of the selected serializer to the “AND” gate; and a FPGA configured to: adjust the timing offset for the serial data stream output of the selected serializer until an oversampling of a gate data stream output from the “AND” gate indicates a maximum timing alignment between the serial data stream output of the selected serializer and the first serial data stream output; and control the timing synchronization of the serial data stream outputs of the plurality of serializers based on the determined timing offsets.

37. The system of claim 36, wherein the switching circuit comprises a combination of logical elements, a multiplexer, a crossbar, or a cross-point switch.

38. The system of any one of claims 36 and 37, wherein a single FPGA chip comprises the plurality of serializers.

39. The system of any one of claims 36 to 38, wherein a single FPGA circuit board comprises the FPGA, the switching circuit, the controller and the “AND” gate.

40. The system of any one of claims 36 to 38, wherein a FPGA circuit board includes the FPGA and an external circuit board includes the switching circuit, the controller and the “AND” gate.41 . The system of claim 40, wherein the external circuit board is connected to the FPGA circuit board using a Samtec Accelerate® connector, a small form-factor pluggable (SFP) slot, a quad small form-factor pluggable (QSFP) slot or a quad small form-factor pluggable double density (QSFPDD) slot.

42. The system of any one of claims 36 to 38, wherein a FPGA circuit board includes the FPGA, a first external circuit board includes the switching circuit and the controller, and a second external circuit board includes the “AND” gate.

43. The system of claim 42, wherein the first external circuit board is connected to the FPGA circuit board using a Samtec Accelerate® connector, a SFP slot, a quad small form-factor pluggable (QSFP) slot or a quad small form-factor pluggable double density (QSFPDD) slot.

44. The system of claim 42, wherein the second external circuit board is connected to the first external circuit board using a Samtec Accelerate® connector, a SFP slot, a quad small form-factor pluggable (QSFP) slot or a quad small form-factor pluggable double density (QSFPDD) slot.

45. The system of any one of claims 36 to 44, wherein the FPGA is configured to provide an identical synchronization data input to the first serializer and the selected serializer for determining the timing offsets.

46. The system of claim 45, wherein, in response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer comprises identical data having relative timing misalignment corresponding to the timing offsets.

47. The system of claim 46, wherein, in response to the first serializer and the selected serializer supporting more than two voltage levels, the FPGA is configured to provide the identical synchronization data input so that the serial data stream outputs of the first serializer and the selected serializer each comprise only two voltage levels including a low voltage level and a high voltage level.

48. The system of claim 47, wherein, in response to the identical synchronization data input, the serial data stream outputs of the first serializer and the selected serializer comprises a first sequence of “0”s or corresponding low voltage level values, at least one “1” or corresponding high voltage level value and a second sequence of “0”s or corresponding low voltage level values.

49. The system of claim 48, wherein a number of “1”s in the gate data stream output from the “AND” gate indicates the timing alignment between the serial data stream output of the selected serializer and the first serial data stream output.

50. The system of any one of claims 45 to 49, wherein a maximum data rate of the “AND” gate is lower than a maximum data rate of the plurality of serializers and the FPGA is configured to provide the synchronization data input so that the serial data stream outputs from the plurality of serializers to the “AND” gate comprises multiple repeating bits.51 . The system of any one of claims 36 to 50, wherein the FPGA is configured to control timing of the serial data stream outputs of the plurality of serializers using multiple shift registers.

52. The system of any one of claims 36 to 50, wherein the FPGA is further configured to receive an input designating the plurality of serializers for timing synchronization, and the FPGA controls the timing synchronization of the serial data stream outputs of the plurality of serializers in response to the received input.

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