Power semiconductor device, power supply circuit, and electronic device

Abstract

The present application relates to a power semiconductor device, a power supply circuit, and an electronic device. The power semiconductor device comprises a power semiconductor device body, a signal processing circuit and a gate port, wherein the power semiconductor device body comprises a first gate structure and a second gate structure independent of each other, the first gate structure comprising a first gate electrode, the second gate structure comprising a second gate electrode, the first gate electrode being connected to the gate port, and the second gate electrode being connected to the gate port by means of the signal processing circuit; the gate port is used for connecting to an external circuit and loading for the first gate electrode and the second gate electrode a control signal provided by the external circuit; the signal processing circuit is used for processing the control signal and then loading the processed control signal onto the second gate electrode; and under the control of the control signal, the first gate electrode and the second gate electrode are used for controlling the state of the power semiconductor device body and reducing the switching loss of the power semiconductor device body. The power semiconductor device provided in the present application has fewer ports and exhibits low loss.

Description

Power semiconductor devices, power supply circuits and electronic equipment

[0001] This application claims priority to Chinese Patent Application No. 202411322177.3, filed on September 20, 2024, entitled "Power Semiconductor Device, Power Supply Circuit and Electronic Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to power semiconductor devices, and more specifically to a power semiconductor device, a power supply circuit, and an electronic device. Background Technology

[0003] Among power semiconductor devices, dual-gate power semiconductor devices are widely used in new energy vehicles, rail transit, charging piles, power grids, home appliances, data storage, photovoltaics, industrial control, energy storage, and consumer electronics due to their high efficiency, high reliability, and long lifespan. However, dual-gate power semiconductor devices have a large number of ports, which increases the design difficulty of control circuits, and switching losses need to be reduced. Summary of the Invention

[0004] This application provides a power semiconductor device, a power supply circuit, and an electronic device to further reduce the losses of dual-gate power semiconductor devices.

[0005] In a first aspect, embodiments of this application provide a power semiconductor device. This device may include a Lateral Double-Diffused Metal Oxide Semiconductor (LDMOS), an Insulated Gate Bipolar Transistor (IGBT), a Shielded Gate Trench MOSFET (SGT), or a MOSFET in a Driver and MOSFET (DrMOS) configuration, comprising two independent gate structures. The device may include a power semiconductor device body, a signal processing circuit, and a gate port. The power semiconductor device body includes a first gate structure and a second gate structure, which are independent of each other. The first gate structure includes a first gate electrode, and the second gate structure includes a second gate electrode. The first gate electrode is connected to the gate port, and the second gate electrode is connected to the gate port via the signal processing circuit. The gate port is used to connect to an external circuit to load control signals provided by the external circuit onto the first and second gate electrodes. The signal processing circuit processes the control signals and then loads them onto the second gate electrode. The first and second gate electrodes are used to control the state of the power semiconductor device body under the control of the control signal and reduce the switching losses of the power semiconductor device body. In the power semiconductor device provided in this application embodiment, the second gate electrode is connected to the gate port through a signal processing circuit, so that both gate structures can be connected to the external circuit through a gate port and can be controlled independently without adding additional ports. This not only achieves the same number of ports for a power semiconductor device with multiple gates as for a power semiconductor device with a single gate, but also reduces the design difficulty of the control circuit of the power semiconductor device, and optimizes the dynamic characteristics of the power semiconductor device with multiple gates, reducing its switching losses.

[0006] In one possible implementation, the signal processing circuit includes a first delay circuit. The second gate electrode is connected to the gate port through the first delay circuit. The first delay circuit delays the control signal before applying it to the second gate electrode. The first gate electrode generates a first voltage signal under the control signal, and the second gate electrode generates a second voltage signal under the signal applied by the first delay circuit. During the turn-on phase of the device, the second voltage signal rises to a high level when the first voltage signal reaches the Miller plateau, which reduces the device's turn-on loss.

[0007] In one possible implementation, the signal processing circuit further includes a first chopper circuit. The second gate electrode is connected to the first delay circuit via the first chopper circuit. The first chopper circuit performs chopping processing on the signal loaded in the first delay circuit and then loads it onto the second gate electrode. The second voltage signal is generated by the second gate electrode under the action of the signal loaded by the first chopper circuit. During the turn-off phase of the device, the second voltage signal drops to a low level when the first voltage signal reaches the Miller plateau, which can reduce the turn-on loss of the device while reducing the turn-off loss.

[0008] In one possible implementation, the signal processing circuit further includes a level shifting circuit. The second gate electrode is connected to the first chopper circuit via the level shifting circuit. The level shifting circuit performs level shifting processing on the signal applied by the first chopper circuit and then applies it to the second gate electrode. The second voltage signal is generated by the second gate electrode under the action of the signal applied by the level shifting circuit. Furthermore, the aforementioned low level is a negative voltage, which can reduce the device's turn-on loss while further reducing the device's turn-off loss.

[0009] In one possible implementation, the signal processing circuit further includes a second chopper circuit. The second gate electrode is connected to the level shifting circuit via the second chopper circuit. The second chopper circuit chops the signal applied by the level shifting circuit and then applies it to the second gate electrode. The second voltage signal is generated by the second gate electrode under the action of the signal applied by the second chopper circuit. The second voltage signal rises to 0 volts after the duration of the low level reaches a preset duration. In this implementation, by controlling the duration of the low level of the second voltage signal through the second chopper circuit, the minimum voltage of the second voltage signal during the device turn-on phase can be made 0 volts, thereby further reducing the device's turn-off losses while avoiding increasing the device's turn-on losses.

[0010] In one possible implementation, the signal processing circuit further includes a third chopper circuit. The second gate electrode is connected to the level shifting circuit via the third chopper circuit. The third chopper circuit chops the signal applied by the level shifting circuit and then applies it to the second gate electrode. The second voltage signal is generated by the second gate electrode under the action of the signal applied by the third chopper circuit. The second voltage signal drops to 0 volts after the high-level duration reaches a preset duration. This further reduces the device's turn-off loss while avoiding the use of too many passive components to maintain a high level, thereby reducing the device area and further improving device performance.

[0011] In one possible implementation, the first gate electrode is connected to the gate port via a signal processing circuit. This signal processing circuit further includes a second delay circuit. The first gate electrode is connected to the gate port via the second delay circuit. The second delay circuit delays the control signal before applying it to the first gate electrode. The first voltage signal is generated by the first gate electrode under the influence of the signal applied by the second delay circuit. During the device's turn-off phase, the second voltage signal drops to a low level when the first voltage signal reaches its Miller plateau, thus reducing the device's turn-off losses.

[0012] When the aforementioned power semiconductor device is a discrete device such as an IGBT, MOSFET (e.g., a Vertical Double-Diffused Metal Oxide Semiconductor Field Effect Transistor (VDMOS) and an SGT), it may further include a package housing, with the power semiconductor device body and signal processing circuit located inside the package housing, and the gate port disposed on the package housing.

[0013] The aforementioned power semiconductor devices can also be integrated into DrMOS, and the gate port can be connected to the driver in DrMOS, resulting in lower DrMOS losses and smaller size.

[0014] The aforementioned power semiconductor devices are mainly used in low-voltage, high-current applications, such as servers using Power Supply in a Package (PSiP) packaging technology, information and communication technology (ICT) chips, artificial intelligence (AI) chips, and smartphones, portable Android devices (PADs), smart wearable devices, and automotive devices with low-voltage, high-current fast charging capabilities.

[0015] Secondly, embodiments of this application provide a power supply circuit, including the device described in any of the first aspects above. This power supply circuit can be a power supply circuit in a PSiP packaged power supply, or it can be a power supply circuit for ICT chips, AI chips, and smartphones, tablets (portable Android devices, PADs), smart wearable devices, in-vehicle devices, etc., that have low-voltage, high-current fast charging capabilities.

[0016] Thirdly, embodiments of this application provide an electronic device including the power supply circuit described in any of the second aspects above. This electronic device can be a server with the power supply using a PSiP package, a smartphone, a tablet, a smart wearable device, an in-vehicle device, etc., featuring low-voltage, high-current fast charging capabilities. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 is a schematic diagram of an example of a power semiconductor device provided in an embodiment of this application;

[0019] Figure 2a is another structural schematic diagram of the power semiconductor device provided in the embodiment of this application;

[0020] Figure 2b is another structural schematic diagram of the power semiconductor device provided in the embodiment of this application;

[0021] Figure 3a is a schematic diagram of an example structure of the body in the power semiconductor device provided in the embodiment of this application;

[0022] Figure 3b is a schematic diagram of an LDMOS structure;

[0023] Figure 3c is another example of the structural schematic diagram of the body in the power semiconductor device provided in the embodiment of this application;

[0024] Figure 4a is another structural schematic diagram of the power semiconductor device provided in the embodiment of this application;

[0025] Figure 4b is another example of a power semiconductor device provided in the embodiments of this application;

[0026] Figure 5a is a schematic diagram of an example of a power semiconductor device provided in an embodiment of this application;

[0027] Figure 5b is a schematic diagram of the voltage signal generated by the gate electrode in the device shown in Figure 5a;

[0028] Figure 6a is another schematic diagram of the power semiconductor device provided in the embodiment of this application;

[0029] Figure 6b is a schematic diagram of the voltage signal generated by the gate electrode in the device shown in Figure 6a;

[0030] Figure 7a is a schematic diagram of another example of a power semiconductor device provided in the embodiments of this application;

[0031] Figure 7b is a schematic diagram of the voltage signal generated by the gate electrode in the device shown in Figure 7a;

[0032] Figure 8a is a schematic diagram of another example of the power semiconductor device provided in the embodiments of this application;

[0033] Figure 8b is a schematic diagram of the voltage signal generated by the gate electrode in the device shown in Figure 8a;

[0034] Figure 9a is another schematic diagram of the power semiconductor device provided in the embodiment of this application;

[0035] Figure 9b is a schematic diagram of the voltage signal generated by the gate electrode in the device shown in Figure 9a;

[0036] Figure 10 is a schematic diagram of another example of the power semiconductor device provided in the embodiments of this application;

[0037] Figure 11a is a schematic diagram of another example of a power semiconductor device provided in an embodiment of this application;

[0038] Figure 11b is a schematic diagram of the voltage signal generated by the gate electrode in the device shown in Figure 11a;

[0039] Figure 12 is a schematic diagram of an application of the power semiconductor device provided in an embodiment of this application. Detailed Implementation

[0040] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0041] Figure 1 is a schematic diagram of an example of a power semiconductor device provided in an embodiment of this application. As shown in Figure 1, the power semiconductor device includes a power semiconductor device body, a signal processing circuit, a gate port G, a source port S, and a drain port D. The power semiconductor device body includes a first gate electrode G1, a second gate electrode G2, a source electrode, and a drain electrode. There is one gate port G, one source port S, and one drain port D. The gate port G is connected to the first gate electrode G1 and is connected to the second gate electrode G2 through the signal processing circuit. The source port S is connected to the source electrode, and the drain port D is connected to the drain electrode. The end of the signal processing circuit connected to the gate port G is the input terminal, and the end connected to the second gate electrode G2 is the first output terminal.

[0042] The power semiconductor device body can be an N-type MOS, as shown in Figure 2a.

[0043] The power semiconductor device body can also be a P-type MOS, as shown in Figure 2b.

[0044] When the power semiconductor device provided in this application embodiment is a MOSFET, the power semiconductor device body is a MOSFET body. An example structure of the MOSFET body is shown in Figure 3a, including: a semiconductor substrate, a semiconductor active layer, a semiconductor body region, a source structure, a drain structure, a first gate structure, and a second gate structure 12. The semiconductor active layer is located on the semiconductor substrate, and the source structure, drain structure, first gate structure, and second gate structure 12 are located on the semiconductor active layer.

[0045] The source structure includes a source electrode S, two source contact regions, and a body contact region. The source electrode S is located on the two source contact regions and the body contact region, and its lower surface is connected to the two source contact regions and the body contact region. The two source contact regions and the body contact region are located in the semiconductor body region, with the body contact region located between the two source contact regions.

[0046] The first gate structure has two components: a trench gate structure 111 and a planar gate structure 112. The trench gate structure 111 and the planar gate structure 112 are located on opposite sides of the source structure, with the planar gate structure 112 situated between the source and drain structures. The trench gate structure 111 extends longitudinally into the active semiconductor layer, contacting the semiconductor bulk region. The trench gate structure 111 includes a gate electrode G11, a trench gate dielectric, and a conductive material surrounded by the trench gate dielectric. The planar gate structure 112 includes a gate electrode G12 and a planar gate dielectric. The gate electrodes G11 and G12 are connected by a metal wire, making the trench gate structure 111 and the planar gate structure 112 equipotential. The second gate structure 12 includes a gate electrode G2 and a trench gate dielectric surrounding the gate electrode G2. The first gate structure and the second gate structure 12 are separated by the trench gate dielectric and are independent of each other. Gate electrodes G11 and G12 are the first gate electrodes, and gate electrode G2 is the second gate electrode.

[0047] The drain structure includes a drain electrode D and a drain contact region. A portion of the drain contact region is located in the semiconductor active layer, and another portion is located between the semiconductor substrate and the semiconductor active layer.

[0048] In this design, the semiconductor substrate, the semiconductor body region, and the body contact region constitute the first conductivity type, while the semiconductor active layer, the two source contact regions, and the drain contact region constitute the second conductivity type. When the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type.

[0049] When the power semiconductor device provided in the embodiments of this application is an LDMOS, the power semiconductor device body is an LDMOS body. LDMOS is an integrable lateral power device that can be used in smart power integrated circuits (SPiCs) in fields such as automotive electronics, flat panel displays, switching power supplies, motor drives, industrial control, and power management.

[0050] Another structural example of an LDMOS substrate is shown in Figure 3c, including: a substrate, a first body region, a drift region, a second body region, a source region, a drain region, a field oxide layer, a source electrode S, a first gate electrode G1, a silicide barrier layer, a second gate electrode G2, and a drain electrode D. The first body region and the second body region are of the first conductivity type, while the source region, drift region, and drain region are of the second conductivity type. The first body region and the drift region are located on the substrate. The second body region and the source region are located within the first body region. The right side of the first body region is tangent to the left side of the drift region, and the drain region is located within the drift region. The field oxide layer is located on the first body region and the drift region. Within the field oxide layer, the source electrode S, the first gate electrode G1, the silicide barrier layer, the second gate electrode G2, and the drain electrode D are sequentially disposed. Furthermore, the source electrode S is located on the second body region and the source region. The left side of the first gate electrode G1 and the right side of the source region are on the same vertical line. The silicide barrier layer overlaps with the first gate electrode G1. The second gate electrode G2 is located on the silicide barrier layer, and the drain electrode is located on the drain region. The first gate electrode G1 and the field oxide layer constitute the first gate structure 31, and the second gate electrode G2 and the field oxide layer constitute the second gate structure 32. The first gate structure 31 and the second gate structure 32 are isolated by the silicide barrier layer and are independent of each other.

[0051] The second gate electrode G2 is separated from the source field plate in the LDMOS shown in Figure 3b. The source field plate shown in Figure 3b is used to reduce the surface field, thereby optimizing the static characteristics of the device. By separating the source field plate as the second gate electrode and setting the voltage of the second gate electrode separately when the device is off or on, the dynamic characteristics of the device can be optimized. For example, for NLDMOS, in the off state, by setting the second gate electrode to a negative potential, its auxiliary drift region is depleted, which helps the device achieve the expected breakdown voltage at a higher drift region concentration. This achieves the goal of increasing the on-current and reducing the on-resistance Ron,sp without reducing the device breakdown voltage.

[0052] It is understood that the power semiconductor device body in the embodiments of this application is not limited to the contents shown in the above embodiments, and may include more or fewer structures or parts. For example, there may be more than two first gate structures, and / or more than one second gate structure, etc.

[0053] Figure 4a is another structural schematic diagram of the power semiconductor device provided in the embodiment of this application. As shown in Figure 4a, in this embodiment, the power semiconductor device body is the MOSFET body shown in Figure 3a. The signal processing circuit is integrated in the semiconductor device, and the gate port G is connected to the first gate electrode (gate electrode G11 and gate electrode G12) through a metal wire, and is connected to the second gate electrode (gate electrode G2) through the signal processing circuit.

[0054] Figure 4b is a schematic diagram of another example of the power semiconductor device provided in this application embodiment. As shown in Figure 4a, in this embodiment, the power semiconductor device body is the LDMOS body shown in Figure 3c. The gate port G is connected to the first gate electrode G1 through a metal wire and to the second gate electrode G2 through a signal processing circuit.

[0055] In some embodiments, the power semiconductor device further includes a package housing, such as package housing 41 shown in FIG. 4a, package housing 42 shown in FIG. 4b, etc. The package housing encapsulates the power semiconductor device body and signal processing circuitry internally, and the gate port G, the source port S (the external interface of the source electrode S), and the drain port D (the external interface of the drain electrode D) are pins extending out of the package housing.

[0056] The power semiconductor device provided in the above embodiments, by setting a signal processing circuit connected between the gate port and the second gate electrode within the device, allows the external circuit to control the first gate electrode and the second gate electrode differently by providing only one gate control signal. This achieves the goal of further optimizing the dynamic characteristics of the power semiconductor device and reducing switching losses without adding additional ports.

[0057] Figure 5a is a schematic diagram of an example of a power semiconductor device provided in an embodiment of this application. In this embodiment, the power semiconductor device body is an N-type MOSFET, including a first gate electrode G1 and a second gate electrode G2, and the signal processing circuit is a first delay circuit. The gate port G is connected to the second gate electrode G2 through the first delay circuit and to the first gate electrode G1 through a metal wire.

[0058] When a voltage signal Vin as shown in Figure 5b is applied to the gate port G, the first gate electrode G1 generates a voltage signal V as shown in Figure 5b under the action of Vin. G1 After Vin is processed by the first delay circuit, the second gate electrode G2 generates a voltage signal V as shown in Figure 5b. G2 .

[0059] As shown in Figure 5b, V G2 The delay time compared to Vin is t0. During the device turn-on phase, V G1Enter the Miller platform at time t1, and V at time t2. G1 After the Miller plateau ends, at time t3, the first gate electrode G1 is charged to the operating voltage V. H (that is, V) G1 Upgrade to V H At time t4, the device begins to turn off, and Vin and V G1 It begins to decline, at time t5 V G1 Entering the Miller platform, at time t6 V G1 End of Miller platform, at time t7 V G1 Reduced to 0 volts, V G2 Compared to V G1 The duration for the time to drop to 0 early is t8.

[0060] The power semiconductor device provided in this embodiment delays the voltage signal at the gate port through a first delay circuit, so that the second gate, during the device turn-on phase, delays the voltage signal V at the first gate electrode. G1 A positive voltage is generated upon entering the Miller plateau, which charges the drift region of the auxiliary device, i.e., it charges the internal parasitic capacitance C of the device. GD Charging accelerates the device's turn-on speed and reduces turn-on losses. Specifically, when t0 > 0 and t0 = t1, the turn-on losses are even lower. The power semiconductor device provided in this embodiment reduces switching losses and optimizes device switching characteristics without adding additional ports, making it easier to apply in integrated circuit design.

[0061] Figure 6a is another schematic diagram of the power semiconductor device provided in this application embodiment. Based on the embodiment shown in Figure 5a, the power semiconductor device provided in this embodiment further includes a first chopper circuit. The first delay circuit is connected to the second gate electrode G2 through the first chopper circuit.

[0062] When a voltage signal Vin is applied to the gate port G, under the action of the first delay circuit and the first chopper circuit, the second gate electrode G2 generates a voltage signal V as shown in Figure 6b. G2 .

[0063] As shown in Figure 6b, during the device turn-off phase, V G2 Compared to V shown in Figure 5b G2 The V shown in Figure 6b G2 It drops to 0 before t6, that is, before the first gate electrode voltage signal V. G1 When the Miller plateau is about to end, the second gate electrode is turned off, prematurely discharging the carriers modulated by the second gate electrode, assisting the depletion of the drift region, accelerating the device turn-off speed, and reducing the device turn-off loss. Specifically, when t8 = t7 - t6, or in other words, V... G2 When t6 drops to 0 volts, the device turn-off loss is lower.

[0064] Figure 7a is a schematic diagram of another example of a power semiconductor device provided in this application. Based on the embodiment shown in Figure 6a, the power semiconductor device provided in this embodiment further includes a level shifting circuit. The first chopper circuit is connected to the second gate electrode G2 through the level shifting circuit.

[0065] When a voltage signal Vin is applied to the gate port G, the second gate electrode G2 generates a voltage signal V as shown in Figure 7b under the action of the first delay circuit, the first chopper circuit, and the level shifting circuit. G2 Compared to the V shown in Figure 6b G2 The voltage signal V shown in Figure 7b G2 During the device turn-on phase, from 0 to t0, from the negative pressure V L The voltage rises to 0 volts, and during the device turn-off phase (t7-t8), it begins to decrease from 0 volts, dropping to a negative voltage V before time t7. L Among them, V L The absolute value is determined by the size that the actual circuit can realize.

[0066] The power semiconductor device provided in this embodiment further utilizes a level shifting circuit to reduce the voltage signal generated on the second gate electrode to a negative voltage when the device is turned off, which further assists in the depletion of the drift region, further reduces the turn-off loss of the device, and optimizes the dynamic characteristics of the device.

[0067] Figure 8a is a schematic diagram of another example of the power semiconductor device provided in this application embodiment. Based on the embodiment shown in Figure 7a, the power semiconductor device provided in this embodiment further includes a second chopper circuit. The level shifting circuit is connected to the second gate electrode G2 through the second chopper circuit.

[0068] When a voltage signal Vin is applied to the gate port G, under the action of the first delay circuit, the first chopper circuit, the level shifting circuit, and the second chopper circuit, the second gate electrode G2 generates a voltage signal V as shown in Figure 8b. G2 Compared to the V shown in Figure 7b G2 The voltage signal V shown in Figure 8b G2 During the device turn-on phase, from 0 to t0, the voltage is 0 volts. During the device turn-off phase, at time t7, the voltage increases from the negative voltage V. L Rise to 0 volts.

[0069] The power semiconductor device provided in this embodiment further utilizes the second chopper circuit to raise the second gate electrode to 0 volts when the device is turned off, thereby ensuring that the minimum voltage of the second gate electrode in the next device turn-on phase is 0 volts, thus avoiding increased device turn-on losses caused by the second gate electrode starting to charge from a negative voltage during the device turn-on phase.

[0070] Figure 9a is another schematic diagram of the power semiconductor device provided in this application embodiment. The power semiconductor device provided in this embodiment differs from the embodiment shown in Figure 8a in that the level shifting circuit is connected to the second gate electrode G2 through a third chopper circuit.

[0071] When a voltage signal Vin is applied to the gate port G, the second gate electrode G2 generates a voltage signal V as shown in Figure 9b under the action of the first delay circuit, the first chopper circuit, the level shifting circuit, and the third chopper circuit. G2 Compared to the V shown in Figure 8b G2 The voltage signal V shown in Figure 9b G2 The voltage rises to the operating voltage V during the device's power-on phase. H After a period of time t9, the voltage begins to decrease, reaching 0 volts before time t3. This avoids using too many passive devices to maintain the high level of the second gate electrode, helps reduce the device size, and further assists in the discharge of carriers in the device's drift region, reducing turn-off losses and improving device performance. In particular, the effect is even better when t9 > t2 - t1.

[0072] In some embodiments, the first chopper circuit is the same as the third chopper circuit, so as to reduce the area of ​​the integrated signal processing circuit inside the low-loss lateral power semiconductor device provided by the present invention.

[0073] In the device shown in the above embodiments, the second gate timing signal V can be changed by adjusting the delay circuit and the chopper circuit. G2 The high / low duty cycle minimizes the switching losses of the device, enabling it to achieve optimal dynamic performance.

[0074] Figure 10 is a schematic diagram of another example of a power semiconductor device provided in this application. The power semiconductor device provided in this embodiment differs from the above embodiments in that the gate port G is also connected to the first gate electrode G1 via a signal processing circuit. The end of the signal processing circuit connected to the first gate electrode G1 is the second output terminal.

[0075] Figure 11a is a schematic diagram of another example of a power semiconductor device provided in an embodiment of this application. The power semiconductor device provided in this embodiment differs from the device shown in Figure 5a in that the signal processing circuit further includes a second delay circuit, and the gate port G is connected to the first gate electrode G1 through the second delay circuit.

[0076] When a voltage signal Vin is applied to the gate port G, under the action of the second delay circuit, the first gate electrode G1 generates a voltage signal V as shown in Figure 9b. G1 As shown in Figure 9b, during the device turn-on phase, V G1Relative to Vin, the voltage increases from 0 volts starting at time t11, reaches the Miller plateau at time t12, ends the Miller plateau at time t13, and rises to the operating voltage V at time t14. H During the device turn-off phase, V G1 Compared to Vin, starting from time t15, V H The voltage drops, reaching the Miller plateau at time t16, ending at time t17, and dropping to 0 volts at time t18, compared to V. G2 The moment when the voltage drops to 0 volts is delayed by t8, and t8 > t18 - t17. Therefore, it can be seen that V G2 In V G1 The voltage was reduced to 0 volts before the Miller plateau was terminated, thus reducing the device's turn-off losses.

[0077] It is understood that the power semiconductor devices provided in this application are not limited to the devices provided in the above embodiments. For a specific semiconductor device, the selection of delay circuit, chopper circuit, and level shifting circuit can be determined based on the Miller plateau size and input signal delay size. For example, a chopper circuit can be further added to the device shown in Figure 11a. The chopper circuit can be set between the first delay circuit and / or the second delay circuit and the corresponding first gate electrode and / or second gate electrode according to the actual situation, so as to reduce switching losses.

[0078] In some embodiments, any of the above-mentioned power semiconductor devices can also be used in DrMOS. In this embodiment, any of the above-mentioned power semiconductor devices is integrated with a gate driver, and the gate port is connected to the gate driver of the DrMOS. This allows for higher power efficiency through the integration of the above-mentioned power semiconductor devices into the DrMOS, meeting the demands of processors (including microprocessors) for higher power current and power density in the development of artificial intelligence technology.

[0079] The power semiconductor device provided in this application uses a signal processing circuit to regulate the signal applied to the gate port, allowing the signals acting on the first and second gate electrodes to be flexibly adjusted according to requirements. This alters the dynamic characteristics of the lateral power device, reduces parasitic capacitance, and ultimately lowers switching losses. The device provided in the above embodiments uses a signal processing circuit to flexibly control the independent first and second gate electrodes, reducing the parasitic capacitance of the device (such as LDMOS), thereby accelerating the device's turn-on / turn-off speed and reducing turn-on / turn-off losses. For integrated circuit design, this power semiconductor device structure avoids introducing new ports through the second gate structure, reducing the difficulty of integrated circuit design and meeting the high-frequency and miniaturization requirements of the rapidly developing intelligent integrated power supplies. Furthermore, accelerating the device's turn-on / turn-off speed reduces the adverse effects of the trade-off between on-resistance and parasitic capacitance, meeting the application requirements of LDMOS in low-voltage, high-current fields such as servers, DrMOS, ICT chips, and AI chips.

[0080] The power supply circuit provided in this application embodiment includes the power semiconductor device provided in any of the above embodiments. This power supply circuit can be a power module using a PSiP package, an SPiC, a DC-DC converter module, a rectifier and filter circuit, a power conversion circuit, etc. By using the aforementioned low-power semiconductor device, the power supply circuit can further reduce its own power consumption, and has fewer device ports (three ports), which helps to reduce the design difficulty and size of the power supply circuit. As shown in Figure 12, the non-isolated DC-DC module uses an embedded chip / component package (ECP), which has the advantages of high density and high integration. By using the power semiconductor device provided in the above embodiments, losses can be reduced, circuit design difficulty can be reduced, and the size of the module can be further reduced; for example, its length and width may be less than 11 mm, and its height may be less than 4 mm.

[0081] The electronic device provided in this application embodiment includes any of the aforementioned power supply circuits. The electronic device includes a functional module and any of the aforementioned power supply circuits. The functional module may include electronic processing circuits such as a processor and memory for implementing the functions of the electronic device. The electronic device may be a server, mobile phone, portable computer, smart wearable device, vehicle-mounted device, or other device that requires low-voltage, high-current power. It is understood that in some embodiments, in addition to the aforementioned functional modules and power supply circuits, the electronic device may also include auxiliary parts such as a casing and fixing components; this is not limited here and may vary depending on the actual situation or requirements. The electronic device provided in this application embodiment, by adopting the aforementioned power supply circuits, has lower energy consumption and a smaller size, which is beneficial for saving energy and space.

[0082] It should be understood that the embodiments described in this application are only some embodiments, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0083] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. The term “and / or” used herein is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Additionally, the character “ / ” in this document generally indicates that the preceding and following related objects are in an “or” relationship. The terms “first,” “second,” and “third” used herein are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. For example, “first delay circuit” and “second delay circuit” may be two circuits with the same structure and devices, two circuits with the same structure but different devices, two circuits with different structures but the same devices, or two circuits with different structures and devices.

[0084] For the same or similar parts among the various embodiments in this specification, please refer to each other.

Claims

1. A power semiconductor device, characterized in that, include: A power semiconductor device body, a signal processing circuit, and a gate port; The power semiconductor device body includes a first gate structure and a second gate structure that are independent of each other. The first gate structure includes a first gate electrode, and the second gate structure includes a second gate electrode. The first gate electrode is connected to the gate port, and the second gate electrode is connected to the gate port through the signal processing circuit. The gate port is used to connect to an external circuit and load the control signal provided by the external circuit onto the first gate electrode and the second gate electrode. The signal processing circuit is used to process the control signal and then load it onto the second gate electrode. The first gate electrode and the second gate electrode are used to control the state of the power semiconductor device body under the control of the control signal, and to reduce the switching loss of the power semiconductor device body.

2. The device according to claim 1, characterized in that, The signal processing circuit includes a first delay circuit, and the second gate electrode is connected to the gate port through the first delay circuit. The first delay circuit is used to delay the control signal and then load it onto the second gate electrode. The first gate electrode generates a first voltage signal under the action of the control signal, and the second gate electrode generates a second voltage signal under the action of the signal applied by the first delay circuit. During the turn-on phase of the device, the second voltage signal rises to a high level when the first voltage signal reaches the Miller plateau.

3. The device according to claim 2, characterized in that, The signal processing circuit further includes a first chopper circuit. The second gate electrode is connected to the first delay circuit through the first chopper circuit. The first chopper circuit is used to chop the signal loaded by the first delay circuit and then load it onto the second gate electrode. The second voltage signal is generated by the second gate electrode under the action of the signal loaded by the first chopper circuit. During the device's turn-off phase, the second voltage signal drops to a low level when the first voltage signal reaches the Miller plateau.

4. The device according to claim 3, characterized in that, The signal processing circuit further includes a level shifting circuit. The second gate electrode is connected to the first chopper circuit through the level shifting circuit. The level shifting circuit is used to perform level shifting processing on the signal loaded by the first chopper circuit and then load it onto the second gate electrode. The second voltage signal is generated by the second gate electrode under the action of the signal loaded by the level shifting circuit. The low level is a negative voltage.

5. The device according to claim 4, characterized in that, The signal processing circuit further includes a second chopper circuit. The second gate electrode is connected to the level shifting circuit through the second chopper circuit. The second chopper circuit is used to chop the signal loaded by the level shifting circuit and then load it onto the second gate electrode. The second voltage signal is generated by the second gate electrode under the action of the signal loaded by the second chopper circuit. The second voltage signal rises to 0 volts after the duration of the low level reaches a preset duration.

6. The device according to claim 4, characterized in that, The signal processing circuit further includes a third chopper circuit. The second gate electrode is connected to the level shifting circuit through the third chopper circuit. The third chopper circuit is used to chop the signal loaded by the level shifting circuit and then load it onto the second gate electrode. The second voltage signal is generated by the second gate electrode under the action of the signal loaded by the third chopper circuit. The second voltage signal drops to 0 volts after the high level duration reaches a preset duration.

7. The device according to claim 2, characterized in that, The first gate electrode is connected to the gate port through the signal processing circuit. The signal processing circuit further includes a second delay circuit. The first gate electrode is connected to the gate port through the second delay circuit. The second delay circuit is used to delay the control signal and then apply it to the first gate electrode. The first voltage signal is generated by the first gate electrode under the action of the signal applied by the second delay circuit. During the device's turn-off phase, the second voltage signal drops to a low level when the first voltage signal reaches the Miller plateau.

8. The device according to any one of claims 1 to 7, characterized in that, The gate port is used to connect to external circuitry via a driver.

9. A power supply circuit, characterized in that, Includes the device described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the power supply circuit described in claim 9.

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