Data reading circuit and method, and memory and electronic device

Abstract

Provided in the present disclosure are a data reading circuit and method, and a memory and an electronic device. The circuit comprises: a comparison circuit and a control circuit. The comparison circuit is used for individually comparing a target current with N first currents, in order to generate N first comparison signals, wherein the N first currents define N+1 current intervals, and the N first comparison signals indicate a target current interval among the N+1 current intervals. The control circuit is used for generating M second currents on the basis of the N first comparison signals, wherein the M second currents divide the target current interval into M+1 sub-intervals, and each sub-interval corresponds to a value of read data. The comparison circuit is further used for comparing the target current with the M second currents, in order to generate M second comparison signals, wherein the M second comparison signals indicate a target sub-interval among the M+1 sub-intervals. The control circuit is further used for determining, on the basis of the N first comparison signals and the M second comparison signals, the value of the read data, wherein the value of the read data is a value corresponding to the target sub-interval.

Description

Data reading circuit, method, memory and electronic device

[0001] Cross-reference to related applications

[0002] This application claims priority to the Chinese patent application No. 2024113236463, filed on September 20, 2024, and entitled "A data reading circuit, method, memory and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of memory, and in particular, to a data reading circuit, method, memory and electronic device. BACKGROUND

[0004] With the development of semiconductor technology, the integration of chips manufactured using semiconductor materials is becoming higher and higher, the number of field-effect transistors (FETs) contained in the chip is becoming more and more, and the size of the chip is becoming smaller and smaller to adapt to the trend of miniaturization of electronic devices. However, with the increase of integration, the storage structure continues to shrink, and the charge storage continues to decrease, and the leakage is too fast, which causes the refresh frequency of the memory to reach the limit, so it is necessary to propose a new storage architecture or data reading method to meet the demand of high refresh frequency. SUMMARY

[0005] The present disclosure provides a data reading circuit, method, memory and electronic device.

[0006] In a first aspect, the present disclosure provides a data reading circuit, comprising a comparison circuit and a control circuit.

[0007] The comparison circuit is configured to compare a target current from a storage unit with N first currents respectively, and generate N first comparison signals; the storage unit is configured to store read data; the N first currents divide N+1 current intervals; and the N first comparison signals indicate a target current interval in the N+1 current intervals.

[0008] The control circuit is configured to receive the N first comparison signals, and generate M second currents according to the N first comparison signals; M and N are both integers greater than 0, and M is less than or equal to N; the M second currents divide the target current interval into M+1 sub-intervals, and each sub-interval corresponds to a value of the read data.

[0009] The comparison circuit is further configured to compare the target current with the M second currents to generate M second comparison signals, the M second comparison signals indicating a target subinterval in the M+1 subintervals.

[0010] The control circuit is further configured to determine a value of the read data according to the N first comparison signals and the M second comparison signals, the value of the read data being a value corresponding to the target subinterval.

[0011] In some embodiments, the control circuit includes a logic circuit and a current generation circuit.

[0012] The logic circuit is configured to generate a first control signal and send the first control signal to the current generation circuit, the first control signal indicating values of the N first currents.

[0013] The current generation circuit is configured to receive the first control signal and generate the N first currents according to the first control signal.

[0014] The logic circuit is further configured to receive the N first comparison signals and generate a second control signal according to the N first comparison signals, and send the second control signal to the current generation circuit, the second control signal indicating values of the M second currents.

[0015] The current generation circuit is configured to receive the second control signal and generate the M second currents according to the second control signal.

[0016] In some embodiments, the first control signal includes N first control sub-signals, and the second control signal includes M second control sub-signals, the N first control sub-signals and the N first currents correspond one-to-one, and the M second control sub-signals and the M second currents correspond one-to-one, and the current generation circuit includes N current generation sub-circuits, wherein:

[0017] The current generation sub-circuit is configured to receive a corresponding first control sub-signal and generate a corresponding first current according to the first control sub-signal.

[0018] The current generation sub-circuit is further configured to receive a corresponding second control sub-signal and generate a corresponding second current according to the second control sub-signal.

[0019] In some embodiments, the comparison circuit includes N comparison sub-circuits, wherein:

[0020] The comparison sub-circuit is configured to receive the target current and the corresponding first current, and compare the target current and the corresponding first current to generate a corresponding first comparison signal.

[0021] The comparison sub-circuit is further configured to receive the target current and the corresponding second current, and compare the target current and the corresponding second current to generate a corresponding second comparison signal.

[0022] In some embodiments, the comparison sub-circuit is a sensitive amplifier.

[0023] In some embodiments, the data reading circuit further comprises a current replication circuit; wherein:

[0024] The current replication circuit is configured to replicate the target current from the storage unit into N parts, and send the replicated N parts of the target current to each of the comparison sub-circuits, respectively.

[0025] In some embodiments, the read data is n-bit data, n is a positive integer, and N = n-1.

[0026] In a second aspect, the embodiments of the present disclosure provide a data reading method, which comprises:

[0027] comparing the target current from the storage unit with N first currents respectively to generate N first comparison signals; the storage unit is configured to store read data; the N first currents divide N+1 current intervals; the N first comparison signals indicate a target current interval in the N+1 current intervals;

[0028] generating M second currents according to the N first comparison signals; M and N are both integers greater than 0, and M is less than or equal to N; the M second currents divide the target current interval into M+1 sub-intervals, and each of the sub-intervals corresponds to a value of the read data;

[0029] comparing the target current with the M second currents to generate M second comparison signals; the M second comparison signals indicate a target sub-interval in the M+1 sub-intervals;

[0030] determining the value of the read data according to the N first comparison signals and the M second comparison signals, wherein the value of the read data is the value corresponding to the target sub-interval.

[0031] In a third aspect, the embodiments of the present disclosure provide a memory, comprising a storage array and a data reading circuit according to any one of the first aspect; the storage array comprises a plurality of storage units, and the data reading circuit is connected to the storage units.

[0032] the storage unit, configured to store the read data;

[0033] the data reading circuit, configured to read the read data from the storage unit.

[0034] In a fourth aspect, an electronic device is provided, which includes the memory as described in the third aspect. BRIEF DESCRIPTION OF DRAWINGS

[0035] FIG. 1 is a schematic structural diagram of a storage unit according to an embodiment of the present disclosure;

[0036] FIG. 2 is a schematic diagram of a read process of serial sensing 4-bit data according to an embodiment of the present disclosure;

[0037] FIG. 3 is a schematic diagram of a component structure of a data reading circuit according to an embodiment of the present disclosure;

[0038] FIG. 4 is a schematic diagram of a current interval division corresponding to 3-bit data according to an embodiment of the present disclosure;

[0039] FIG. 5 is a schematic diagram of a component structure of a data reading circuit according to an embodiment of the present disclosure;

[0040] FIG. 6 is a schematic diagram of a component structure of a 3-bit data reading circuit according to an embodiment of the present disclosure;

[0041] FIG. 7 is a schematic diagram of a corresponding relationship between 3-bit data and current and different read conditions according to an embodiment of the present disclosure;

[0042] FIG. 8 is a schematic diagram of a component structure of a 4-bit data reading circuit according to an embodiment of the present disclosure;

[0043] FIG. 9 is a schematic diagram of a current interval division corresponding to 4-bit data and different read conditions according to an embodiment of the present disclosure;

[0044] FIG. 10 is a schematic diagram of a flow of a multi-bit data reading method according to an embodiment of the present disclosure;

[0045] FIG. 11 is a schematic diagram of a component structure of a memory according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related disclosure, and not to limit the disclosure. In addition, it should be noted that, for the convenience of description, only the parts related to the disclosure are shown in the drawings.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the disclosure.

[0048] In the following description, reference is made to the "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or a different subset of all possible embodiments and can be combined with each other, without conflict, unless otherwise indicated.

[0049] It should be noted that the terms "first\second\third" involved in the embodiments of the disclosure are only to distinguish similar objects, and do not represent the specific order of the objects. Understandably, "first\second\third" can be interchanged with specific order or sequence as allowed, so that the embodiments of the disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0050] Before the embodiments of the disclosure are further described in detail, the terms and phrases involved in the embodiments of the disclosure are explained, and the terms and phrases involved in the embodiments of the disclosure are applicable to the following explanations:

[0051] Field-effect transistor (FET);

[0052] Dynamic Random Access Memory (DRAM);

[0053] 2Transistor 0 Capacitor (2T0C);

[0054] Write Word Line (WWL);

[0055] Write Bit Line (WBL);

[0056] Read Word Line (RWL);

[0057] Read Bit Line (RBL);

[0058] Bit Line (BL);

[0059] bit;

[0060] microampere (μA);

[0061] Active command (ACT);

[0062] ACT to internal read or write delay time (TRCD);

[0063] Double Data Rate (DDR);

[0064] Joint Electron Device Engineering Council (JEDEC);

[0065] Standard (SPEC);

[0066] nanoseconds (ns).

[0067] With the increasing integration of semiconductor devices, storing multiple bits of data in one memory cell becomes an important technology, which can achieve multiple storage densities or compatibility in the same occupied space (with economic and efficient advantages). In the exemplary embodiments of the present disclosure, the data reading method in the present disclosure is explained by taking DRAM memory as an example, but the present disclosure is not limited thereto.

[0068] As shown in FIG. 1, an exemplary structure schematic diagram of a memory cell provided by an embodiment of the present disclosure is shown, which includes two transistors, respectively denoted as a write transistor and a read transistor. The gate of the write transistor is connected to a write word line (WWL), and the source of the write transistor is connected to a write bit line (WBL). The source and the drain of the read transistor are connected to a read word line (RWL) and a read bit line (RBL), respectively. The drain of the write transistor and the gate of the read transistor are connected as a storage node, i.e., the memory cell is a 2T0C structure. In the embodiments of the present disclosure, the data reading method is explained by taking a 2T0C memory cell as an example, but this is not limited thereto. The data reading circuit and method are also applicable to other memory cell structures, for example, a memory cell that includes more or fewer transistors, or a memory cell that includes a capacitor.

[0069] The 2T0C memory cell stores charge by using gate capacitance and changes the transistor transconductance to store information, without using the capacitor in the conventional memory cell (compared to the transistor, the capacitor usually occupies a larger area). Therefore, the size of the memory can be significantly reduced and the integration of the chip can be improved. When storing multiple bit data by using the 2T0C memory cell, there are two ways to read the data. One is parallel sensing, i.e., reading out all the data at one time. The other is serial sensing, i.e., reading one bit of data at a time, and reading out the data in multiple stages.

[0070] For parallel sensing multi-bit data of 2T0C memory cell, the process is briefly described as follows: taking 2-bit data as an example, there are four possible values: 00, 01, 10, 11; it is assumed that the current values corresponding to the four values are: 0 μA, 1 μA, 2 μA, 3 μA (allowing a certain error range, the current values involved subsequently all include the error in the allowable range, which will not be described again), and correspondingly, three reference currents are needed to distinguish the four values. For example, the values of the three reference currents are 0.5 μA, 1.5 μA, 2.5 μA. When reading 2-bit data, the current copying circuit copies the current of the 2T0C memory cell three times, three circuits for generating reference currents generate the aforementioned three reference currents, and three circuits for comparing the current size compare the cell current with each reference current to determine in which range the cell current is located according to the comparison result, and the corresponding logic decoding circuit is decoded to obtain the read 2-bit data. For example, the comparison result shows that the cell current is greater than 1.5 μA and less than 2.5 μA, the current value in this range is 2 μA, and the corresponding 2-bit data is 10. For 3-bit data, there are eight possible values, so seven reference currents are needed to distinguish eight different values, and correspondingly, the circuit for parallel sensing 3-bit data needs seven circuits for generating reference currents and seven circuits for comparing the current size, and more bit data needs more circuits, resulting in too large circuit area.

[0071] For serial sensing multi-bit data of 2T0C memory cell, only one circuit for generating reference current and one circuit for comparing the current size are needed, and the process is briefly described as follows: still taking the above 2-bit data as an example, it is divided into two reading stages, in the first stage, the cell current is compared with the reference current of 1.5 μA, if the comparison result is greater, it means that the value of 2-bit data may be 10 or 11, if the comparison result is less, it means that the value of 2-bit data may be 00 or 01; it is assumed that the comparison result is greater, then the reference current of 2.5 μA is generated, and the cell current is compared with the reference current of 2.5 μA, if the comparison result is greater, it means that the value of 2-bit data is 11, otherwise, it is 10. Similarly, for 3-bit data, it is divided into three reading stages; for 4-bit data, four reading stages are needed.

[0072] As another example of reading 4-bit data as serial sensing, FIG. 2 is a schematic diagram of a corresponding reading process, where the horizontal axis is time t and the vertical axis is current I. The 4-bit data has the following 16 possible values (the binary values are outside the brackets and the corresponding decimal values are inside the brackets): 0000 (0), 0001 (1), 0010 (2), 0011 (3), 0100 (4), 0101 (5), 0110 (6), 0111 (7), 1000 (8), 1001 (9), 1010 (10), 1011 (11), 1100 (12), 1101 (13), 1110 (14), 1111 (15); suppose the currents corresponding to the 16 values are (increasing in turn): I 1.0 , I 1.1 , I 1.2 , I 1.3 , I 1.4 , …, I 1.14 , I 1.15 , there are 15 reference currents to distinguish the 16 values: I 2.0 , I 2.1 , I 2.2 , I 2.3 , …, I 2.13 , I 2.14 ; it can be understood that I 1.i < I 2.i < I 1.(i+1) , where i is an integer between 0 and 14 (inclusive).

[0073] For 4-bit data, serial sensing still only needs 1 circuit to generate reference current and 1 circuit to compare current size, as shown in FIG. 2, divided into four reading stages. In the first stage, the cell current (I cell ) is compared with the reference current I 2.7 ; suppose the comparison result is that I cell is greater than I 2.7 , then in the second stage I cell is compared with I 2.11 ; suppose the comparison result is still greater, then in the third stage I cell is compared with I 2.13 ; suppose the comparison result is still greater, then in the fourth stage I cell is compared with I 2.14 ; if the comparison result is still greater, the 4-bit data is I 1.15 corresponding to 1111, otherwise, the 4-bit data is I 1.14 corresponding to 1110.

[0074] It can be seen that for the parallel reading mode, the more possible values (denoted as X) of the multi-bit data, the more (X-1) circuits for generating reference currents and (X-1) circuits for comparing the cell current with the reference current are needed, and the cell current needs to be copied (X-1) times; for the serial reading mode, the more bits (denoted as Y) of the multi-bit data, the more Y reading stages are needed.

[0075] For a 2T0C memory cell with n bits per memory cell (n≥3), parallel sensing will occupy too much circuit space, and serial sensing will increase the delay of data reading (corresponding to the TRCD timing parameter in DRAM). In the DDR5 JEDEC, the minimum TRCD allowed is about 15 ns, and for serial sensing, it is difficult to complete n≥3 reading stages within 15 ns. Therefore, it is challenging to apply a 2T0C memory cell with more than or equal to 3-bit data to DRAM using the existing reading method.

[0076] Based on this, the embodiments of the present disclosure provide a multi-bit data reading circuit, for multi-bit data of 3 bits and above, data reading can be completed in two stages, on the one hand, the circuit area is saved, on the other hand, excessive delay is avoided, and the TRCD meets the standard requirements of JEDEC.

[0077] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0078] In an embodiment of the present disclosure, referring to FIG. 3, a schematic diagram of a constituent structure of a data reading circuit 10 provided by the embodiments of the present disclosure is shown. As shown in FIG. 3, the data reading circuit 10 includes a comparison circuit 11 and a control circuit 12; wherein:

[0079] The comparison circuit 11 is configured to compare a target current from a memory cell 20 with N first currents respectively, and generate N first comparison signals; the memory cell 20 is configured to store data to be read; the N first currents divide N+1 current intervals; and the N first comparison signals indicate a target current interval in the N+1 current intervals;

[0080] The control circuit 12 is configured to receive the N first comparison signals, and generate M second currents according to the N first comparison signals; M and N are both integers greater than 0, and M is less than or equal to N; and the M second currents divide the target current interval into M+1 subintervals, each subinterval corresponding to a value of the data to be read;

[0081] The comparison circuit 11 is further configured to compare the target current with the M second currents, and generate M second comparison signals; and the M second comparison signals indicate a target subinterval in the M+1 subintervals;

[0082] The control circuit 12 is further configured to determine the value of the read data according to the N first comparison signals and the M second comparison signals, the value of the read data being the value corresponding to the target sub-interval.

[0083] It should be noted that in the embodiments of the present disclosure, the storage unit 20 can be a multi-bit storage unit, and the read data stored in the storage unit 20 can be multi-bit data. The multi-bit data is denoted as n-bit data, where n is a positive integer, and more specifically, n can be an integer greater than or equal to 3. That is, the data reading circuit 10 can be used for reading 3-bit and more multi-bit data, and only two stages are required to realize the reading of multi-bit data. The multi-bit storage unit can be a 2T0C storage unit, or can further include more transistors.

[0084] As shown in FIG. 3, for example, when there is a demand to read data from the storage unit 20, the control circuit 12 can receive an instruction related to the reading, thereby generating N first currents, and the target current is the cell current, which can be the current on the RBL connected to the reading tube in the selected 2T0C storage unit. That is, the comparison circuit 11 can be connected (directly or indirectly) to the RBL, so as to be able to obtain the target current. The control circuit 12 is further configured to output the read data.

[0085] It should be further noted that for n-bit data (binary number), there are at most 2 n possible values, and 2 n will be used as an example in the following. For example, for 3-bit data, there are 8 possible values, and the 8 values correspond to eight preset currents respectively. Assuming that the values and the corresponding preset currents from small to large are as follows: 000 corresponds to I1, 001 corresponds to I2, 010 corresponds to I3, 011 corresponds to I4, 100 corresponds to I5, 101 corresponds to I6, 110 corresponds to I7, and 111 corresponds to I8. Seven reference currents can distinguish the 8 values, for example: the seven reference currents are I ref1 , I ref2 , …, I ref7 .

[0086] As shown in FIG. 4, the eight preset currents and the seven reference currents have the following relationship: I1<I ref1 <I2<I ref2 <I3<I ref3 <I4<I ref4 <I5<I ref5 <I6<I ref6 <I7<I ref7 <I8

[0087] corresponding to the read data is 3 bits, two first currents are set, i.e. N = 2, and the target current is compared with at most two reference currents in the first and second stages of reading the data. In the first stage, I ref3 and I ref5 are the two first currents. Thus, I ref3 and I ref5 are divided into three current intervals: a first current interval (including I1, I2and I3) less than I ref3 , a second current interval (including I4and I5) between I ref3 and I ref5 , and a third current interval (including I6, I7and I8) greater than I ref5 .

[0088] Thus, in the first stage, the comparison circuit 11 compares the target current with I ref3 and I ref5 respectively, and generates two first comparison signals indicating the size relationship between the corresponding first current and the target current, so as to indicate one of the first current interval ~ the third current interval as the target current interval, and thus the control circuit 12 can generate the second current dividing the target current interval.

[0089] If the target current is greater than I ref3 and greater than I ref5 (i.e. greater than I ref5 ), the target current interval is the third current interval; in the second stage, two second currents are set, i.e. M = 2, and the control circuit 12 generates two second currents I ref6 and I ref7 according to the two first comparison signals, I ref6 and I ref7 , and the third current interval is divided into three subintervals, i.e. a subinterval 8 (including I8) greater than I ref7 , a subinterval 7 (including I7) greater than I ref6 and less than I ref7 , and a subinterval 6 (including I6) less than I ref6 ; the comparison circuit 11 compares the target current with I ref6 and I ref7 respectively, and generates two second comparison signals indicating the size relationship between the corresponding second current and the target current, so as to indicate one of the subinterval 8 ~ the subinterval 6 as the target subinterval. If the target current is greater than I ref6 and greater than I ref7 (i.e. greater than I ref7, the target sub-interval is sub-interval 8, and the 3-bit data is 111 corresponding to I8; if the target current is greater than I ref6 and less than I ref7 , the target sub-interval is sub-interval 7, and the 3-bit data is 110 corresponding to I7; if the target current is less than I ref6 and less than I ref7 (that is, less than I ref6 ), the target sub-interval is sub-interval 6, and the 3-bit data is 101 corresponding to I6. In the embodiment of the present disclosure, the control circuit 12 can perform logical decoding according to the two first comparison signals and the two second comparison signals, obtain the value of the 3-bit data and output, and complete the 3-bit data reading.

[0090] If the target current is greater than I ref3 and less than I ref5 , the target current interval is the second current interval; enter the second stage, in this case, form 1 second current, that is, M = 1, and the control circuit 12 generates 1 second current I ref4 (or two identical second currents) according to the two first comparison signals. ref4 Divide the second current interval into two sub-intervals, that is, sub-interval 5 (including I5) greater than I ref4 and sub-interval 4 (including I4) less than I ref4 ; the comparison circuit 11 compares the target current with I ref5 respectively, generates a second comparison signal (or two identical second comparison signals), and the second comparison signal is used to indicate the size relationship between the corresponding second current and the target current, so as to be able to indicate one of the sub-interval 5 and the sub-interval 4 as the target sub-interval. If the target current is greater than I ref4 , the target sub-interval is sub-interval 5, and the 3-bit data is 100 corresponding to I5; if the target current is less than I ref4 , the target sub-interval is sub-interval 4, and the 3-bit data is 011 corresponding to I4. In the embodiment of the present disclosure, the control circuit 12 can perform logical decoding according to the two first comparison signals and the one second comparison signal (or the two identical second comparison signals), obtain the value of the 3-bit data and output, and complete the 3-bit data reading.

[0091] If the target current is less than I ref3 and less than I ref5 (that is, less than I ref3 ), the target current interval is the first current interval; enter the second stage, in this case, form 2 second currents, that is, M = 2, and the control circuit 12 generates 2 second currents I ref1 and I ref2 according to the two first comparison signals. ref1and I ref2 The third current interval is divided into three sub-intervals, namely: a sub-interval 3 (including I3) greater than I ref2 , a sub-interval 2 (including I2) greater than I ref1 and less than I ref2 , and a sub-interval 1 (including I1) less than I ref1 ; the comparison circuit 11 compares the target current with I ref1 and I ref2 , respectively, to generate two second comparison signals, which are used to indicate the size relationship between the corresponding second current and the target current, so as to be able to indicate one of the sub-interval 3 to the sub-interval 1 as the target sub-interval. If the target current is greater than I ref1 and greater than I ref2 (that is, greater than I ref2 ), the target sub-interval is the sub-interval 3, and the 3-bit data is 010 corresponding to I3; if the target current is greater than I ref1 and less than I ref2 , the target sub-interval is the sub-interval 2, and the 3-bit data is 001 corresponding to I2; if the target current is less than I ref1 and less than I ref2 (that is, less than I ref1 ), the target sub-interval is the sub-interval 1, and the 3-bit data is 000 corresponding to I1. In the embodiment of the present disclosure, the control circuit 12 can perform logical decoding according to the two first comparison signals and the two second comparison signals to obtain the value of the 3-bit data and output, thereby completing the 3-bit data reading.

[0092] For more bit data, the embodiment of the present disclosure can still adopt a proper interval division manner, set appropriate N value and M value, so that only two stages are needed to read the multi-bit data, without large circuit occupation or time delay.

[0093] That is, in the embodiment of the present disclosure, the N first currents and the M second currents are reference currents for dividing the 2 n possible values of the n-bit data, and the bit number n and the number N of the first currents can have the following relationship: N = n-1.

[0094] Based on FIG. 3, as shown in FIG. 5, in some embodiments, the control circuit 12 includes a logic circuit 121 and a current generation circuit 122;

[0095] The logic circuit 121 is configured to generate a first control signal and send the first control signal to the current generation circuit 122; the first control signal indicates the value of the N first currents;

[0096] The current generating circuit 122 is configured to receive the first control signal and generate N first currents according to the first control signal.

[0097] The logic circuit 121 is further configured to receive the N first comparison signals and generate a second control signal according to the N first comparison signals, and send the second control signal to the current generating circuit 122; the second control signal indicates values of M second currents.

[0098] The current generating circuit 122 is configured to receive the second control signal and generate M second currents according to the second control signal.

[0099] It should be noted that, as shown in FIG. 5, the control circuit 12 can include two parts of the logic circuit 121 and the current generating circuit 122; the logic circuit 121 is configured to implement functions such as logic control and logic decoding, and the current generating circuit 122 is configured to generate reference currents. The logic circuit 121 is connected with the comparison circuit 11 and the current generating circuit 122 respectively; and the current generating circuit 122 is connected with the logic circuit 121 and the comparison circuit 11 respectively.

[0100] In the first stage of reading data, the logic circuit 121 can receive instructions related to reading and generate a first control signal according to the instructions, and send the first control signal to the current generating circuit 122; and the logic circuit 121 can also receive address signals related to addresses of the read storage unit 20, and select the read storage unit 20 according to the address signals; the current generating circuit 122 generates N first currents according to the first control signal and sends the N first currents to the comparison circuit 11; the comparison circuit 11 compares the target current with the N first currents respectively, and generates N first comparison signals and sends the N first comparison signals to the logic circuit 121.

[0101] In the second stage of reading data, the logic circuit 121 generates a second control signal according to the N first comparison signals and sends the second control signal to the current generating circuit 122; the current generating circuit 122 generates M second currents according to the second control signal and sends the M second currents to the comparison circuit 11; the comparison circuit 11 compares the target current with the M second currents respectively, and generates M second comparison signals and sends the M second comparison signals to the logic circuit 121.

[0102] The logic circuit 121 decodes the comparison results (i.e., the N first comparison signals and the M second comparison signals) of the two stages, and can obtain the value of the read data, thereby realizing data reading.

[0103] On the basis of FIG. 5, as shown in FIG. 6 or FIG. 8, in some embodiments, the first control signal includes N first control sub-signals, and the second control signal includes M second control sub-signals; the N first control sub-signals and the N first currents are in one-to-one correspondence, and the M second control sub-signals and the M second currents are in one-to-one correspondence; the current generation circuit 122 includes N current generation sub-circuits 1221, wherein:

[0104] The current generation sub-circuit 1221 is configured to receive the corresponding first control sub-signal, and generate the corresponding first current according to the first control sub-signal.

[0105] The current generation sub-circuit 1221 is further configured to receive the corresponding second control sub-signal, and generate the corresponding second current according to the second control sub-signal.

[0106] As shown in FIG. 6 or FIG. 8, in some embodiments, the comparison circuit 11 includes N comparison sub-circuits 111, wherein:

[0107] The comparison sub-circuit 111 is configured to receive the target current I cell and the corresponding first current, and compare the target current I cell and the corresponding first current in size, to generate the corresponding first comparison signal.

[0108] The comparison sub-circuit 111 is further configured to receive the target current I cell and the corresponding second current, and compare the target current I cell and the corresponding second current in size, to generate the corresponding second comparison signal.

[0109] It should be noted that, in the embodiments of the present disclosure, the comparison sub-circuit 111 can be a circuit with the function of comparing the size of currents, such as a sensitive amplifier SA.

[0110] As shown in FIG. 6 or FIG. 8, in some embodiments, the data reading circuit 10 further includes a current replication circuit 13, wherein:

[0111] The current replication circuit 13 is configured to replicate the target current I cell from the storage unit 20 into N parts, and send the replicated N parts of the target current I cell to each comparison sub-circuit 111 respectively.

[0112] It should be noted that, in the embodiments of the present disclosure, the current replication circuit 13 can be a current mirror.

[0113] Next, taking 3-bit data and 4-bit data as examples, the data reading process of the multi-bit data reading circuit 10 provided in the embodiments of the present disclosure is exemplarily and in detail described in combination with FIG. 6 to FIG. 9.

[0114] Figure 7 shows a schematic diagram of the correspondence between 3-bit data and current and different reading conditions. As shown in Figure 4 or Figure 7, 3-bit data has at most 8 value conditions, and 2 first currents, 2 or 1 second current are set, i.e. N=2, M=1 or 2. The specific value conditions and interval division are described in Figure 4 and related description, which will not be repeated here.

[0115] As shown in Figure 6, in the 3-bit data reading circuit 10, the first control signal includes 2 first control sub-signals (control sub-signals C tr11 and C tr12 ), the control sub-signal C tr11 corresponds to I ref5 , and the control sub-signal C tr12 corresponds to I ref3 ; the second control signal includes 2 second control sub-signals (control sub-signals C tr21 and C tr22 , for the case of M=1, the control sub-signal C tr21 may be regarded as the control sub-signal C tr22 ); in different conditions, the control sub-signal C tr21 and the control sub-signal C tr22 correspond to different second currents, which will be described in detail in the subsequent process.

[0116] The number of first comparison signals is 2, which are first comparison signals C om11 and C om12 ; the number of second comparison signals is 2 or 1, which are second comparison signals C om21 and C om22 , for the case of 1, C om21 may be regarded as C om22 .

[0117] The current generation circuit 122 includes 2 current generation sub-circuits 1221 (current generation sub-circuit 1 and current generation sub-circuit 2); the comparison circuit 11 includes 2 comparison sub-circuits 111 (SA1 and SA2).

[0118] The current replication circuit 13 and the storage unit 20 are connected (through RBL), and the current replication circuit 13 is also connected with SA1 and SA2 respectively, and the current replication circuit 13 is used to replicate the target current I cell twice and send it to SA1 and SA2 respectively.

[0119] In combination with Figures 4, 6 and 7, the working process of the 3-bit data reading circuit 10 is as follows:

[0120] The logic circuit 121 can receive a command or a signal related to reading and generate control sub-signals C tr11 and control sub-signals C tr12 , control sub-signals C tr11 corresponding to I ref5 , control sub-signals C tr12 corresponding to I ref3 ; the logic circuit 121 sends control sub-signals C tr11 to the current generation sub-circuit 1 and control sub-signals C tr12 to the current generation sub-circuit 2.

[0121] The current generation sub-circuit 1 generates I tr11 according to control sub-signals C ref5 and sends it to the SA1, and the current generation sub-circuit 2 generates I tr12 according to control sub-signals C ref3 and sends it to the SA2.

[0122] The SA1 compares the target current I cell and I ref5 , and outputs a first comparison signal C om11 characterizing the comparison result, and the SA2 compares the target current I cell and I ref3 , and outputs a first comparison signal C om12 . In the embodiments of the present disclosure, as an example, for each first comparison signal and second comparison signal, a high level logic 1 represents that the target current is greater than the reference current, and a low level logic 0 represents that the target current is less than the reference current; in practice, it can also be the opposite representation, or any other possible representation, which is not specifically limited.

[0123] As shown in FIG. 7, if the first comparison signal C tr11 and the first comparison signal C tr12 are 11, it corresponds to Case 1 (the target current interval is the third current interval outlined by the dashed line); if the first comparison signal C tr11 and the first comparison signal C tr12 are 01, it corresponds to Case 2 (the target current interval is the second current interval outlined by the dashed line); if the first comparison signal C tr11 and the first comparison signal C tr12 are 00, it corresponds to Case 3 (the target current interval is the first current interval outlined by the dashed line).

[0124] In the second reading phase:

[0125] For Case 1, the logic circuit 121 generates control sub-signals C tr11 and control sub-signals C tr12Perform logical operations to decode and generate the corresponding I. ref7 Control sub-signal C tr21 and corresponding I ref6 Control sub-signal C tr22 , respectively sent to current generating sub-circuit 1 and current generating sub-circuit 2;

[0126] Current generation sub-circuit 1 is based on control sub-signal C tr21 Generate I ref7 The signal is sent to SA1, and the current generation sub-circuit 2 responds to the control sub-signal C. tr22 Generate I ref6 Send to SA2;

[0127] SA1 will target current I cell and I ref7 Compare the magnitudes and output a second comparison signal C representing the comparison result. om21 SA2 will target current I cell and I ref6 Compare the magnitudes and output a second comparison signal C representing the comparison result. om22 If the second comparison signal C tr21 Second comparison signal C tr22 If the value is 11, then the corresponding target sub-interval is sub-interval 8, and the 3-bit data is 111; here, logic circuit 121 can determine the target sub-interval based on the two comparison signals C. tr11 C tr12 C tr21 C tr22 =1111 is decoded to obtain 3 bits of data 111. To ensure timing synchronization, each first comparison signal can be delayed. The specific logic circuit 121 can be obtained by combining logic gates to implement the relevant decoding function. Subsequent cases are decoded similarly and will not be elaborated further. If the second comparison signal C... tr21 Second comparison signal C tr22 If the value is 01, then the corresponding target sub-interval is sub-interval 7, and the 3-bit data is 110; if the second comparison signal C tr21 Second comparison signal C tr22 If the value is 00, then the corresponding target sub-interval is sub-interval 6, and the 3-bit data is 101.

[0128] For Case 2, logic circuit 121 determines the first comparison signal C. tr11 Comparison signal C tr12 Perform logical operations to decode and generate the corresponding I. ref4 The control sub-signal, here, can generate the same control sub-signal C. tr21 and control sub-signal C tr22 All correspond to I ref4 ;

[0129] The current generating sub-circuit 1 generates a current I tr21 I ref4 to the SA1, and / or the current generating sub-circuit 2 generates a current I tr22 I ref4 to the SA2;

[0130] The SA1 and / or the SA2 compares the target current I cell I ref4 and I om21 and / or the second comparison signal C om22 If the second comparison signal C tr21 and the second comparison signal C tr22 is 11, the corresponding target sub-interval is sub-interval 5, and the 3-bit data is 100; if the second comparison signal C tr21 and the first comparison signal C tr22 is 00, the corresponding target sub-interval is sub-interval 4, and the 3-bit data is 011. Here, if only one comparison sub-circuit 111 is used for comparison, another comparison sub-circuit 111 can also be set to output 1 or 0 by default, and the logic circuit 121 is reasonably designed to ensure correct decoding.

[0131] Case 3 is the same as Case 1, which will not be repeated here.

[0132] In the embodiments of the present disclosure, each control sub-signal can be different values, so as to control the corresponding current generating sub-circuit 1221 to generate different reference currents.

[0133] For the reading speed, for example, the actual verification shows that Table 1 shows the TRCD values corresponding to different numbers of reading stages when the number of bits is different.

[0134] Table 1

[0135] As shown in Table 1, for parallel sensing, no matter how many bits of data correspond to one reading stage, the bit line BL (specifically, the read bit line RBL) of the storage unit is connected to (2 n -1) SAs, and since only one reading stage is needed, 1 / 2 / 3-bit data is completed within about 10 ns.

[0136] For serial sensing, 1-bit data corresponds to one read stage (i.e. the reading of 1-bit data is actually no difference between serial and parallel sensing); 2-bit data corresponds to two read stages, the bit line BL of the storage unit is connected with (n-1) SAs, and the serial sensing of 2-bit data is completed in about 15 ns; 3-bit data corresponds to three read stages, the bit line BL of the storage unit is connected with 1 SA, and the serial sensing of 3-bit data is completed in about more than 20 ns (violating the DRAM SPEC). However, the multi-bit data reading circuit provided in the embodiments of the present disclosure needs only two read stages to read 3-bit data, the bit line BL of the storage unit is connected with (n-1) SAs, and the reading of 3-bit data is completed in about 15 ns (complying with the DRAM SPEC). It can be seen that the serial sensing of 3-bit and more multi-bit data will violate the DRAM SPEC, while the multi-bit data reading circuit provided in the embodiments of the present disclosure complies with the DRAM SPEC when reading 3-bit and more multi-bit data.

[0137] For 3-bit data, compared with parallel sensing, parallel sensing needs (2 3 -1) circuits for generating reference currents (equivalent to current generation sub-circuits), 7 circuits for comparing target currents and reference currents (equivalent to comparison sub-circuits), and the target current needs to be copied 7 times; while in the embodiments of the present disclosure, only 2 current generation sub-circuits and 2 comparison sub-circuits are needed, and the circuit occupation area is greatly reduced.

[0138] In the embodiments of the present disclosure, the number n of bits and the number N of SAs (i.e. the number of first currents) can have the following relationship: N=n-1. In the foregoing parallel sensing mode, the number of SAs is 2 n -1, obviously, based on the data reading circuit 10 provided in the embodiments of the present disclosure, the circuit area is significantly reduced, which is beneficial to increase the integration of the memory.

[0139] FIG. 9 shows a schematic diagram of the corresponding relationship between 4-bit data and currents and different reading conditions. As shown in FIG. 9, 4-bit data has at most 16 value conditions, 3 first currents and 3 second currents are set, i.e. N=3, M=3. The 16 values (0000-1111) correspond to 16 preset currents (I 01 -I 16 ) in increasing order; 15 reference currents (I ref01 -I ref15 ) divide the 16 preset currents.

[0140] For 4-bit data, in the first stage and the second stage of reading data, the target current is compared with at most 3 reference currents. In the first stage, I ref04 , I ref08and I ref12 As the 3 first currents, 4 current intervals are divided as follows: a fourth current interval (including I ref04 ~I 01 ) less than I 03 , a fifth current interval (including I ref04 ~I ref08 ) between I 05 and I 07 , a sixth current interval (including I ref08 ~I ref12 ) between I 09 and I 11 , and a seventh current interval (including I ref12 ~I 13 ) greater than I 15 .

[0141] As shown in FIG. 8, in the 4-bit data reading circuit 10, the first control signal includes 3 first control sub-signals (control sub-signals C tr011 , C tr012 , and C tr013 , respectively), the control sub-signal C tr011 corresponds to I ref12 , the control sub-signal C tr012 corresponds to I ref08 , and the control sub-signal C tr013 corresponds to I ref04 ; the second control signal includes 3 second control sub-signals (control sub-signals C tr021 , C tr022 , and C tr023 , respectively), which correspond to different second currents in different cases, which will be described in detail in the subsequent process.

[0142] The number of first comparison signals is 3, which are first comparison signals C om011 , C om012 , and C om013 ; the number of second comparison signals is 3, which are second comparison signals C om021 , C om022 , and C om023 .

[0143] The current generation circuit 122 includes 3 current generation sub-circuits 1221 (current generation sub-circuits 01, 02, and 03, respectively); the comparison circuit 11 includes 3 comparison sub-circuits 111 (SA01, SA02, and SA03, respectively).

[0144] The current copying circuit 13 is connected (through RBL) with the storage unit 20, and is also connected with SA01, SA02 and SA03 respectively, and is used to copy the target current I cell and send to SA01, SA02 and SA03 respectively.

[0145] In combination with FIG. 8 and FIG. 9, the working process of the 4-bit data reading circuit 10 is as follows:

[0146] The logic circuit 121 can receive reading related commands or signals, and generate control sub-signals C tr011 , C tr012 , C tr013 , C tr011 , C ref12 , C tr012 , C ref08 , C tr013 , C ref04 accordingly; the logic circuit 121 sends the control sub-signals C tr011 to the current generating sub-circuit 01, sends the control sub-signals C tr012 to the current generating sub-circuit 02, and sends the control sub-signals C tr013 to the current generating sub-circuit 03.

[0147] The current generating sub-circuit 01 generates I tr011 according to the control sub-signals C ref12 and sends to SA01, the current generating sub-circuit 02 generates I tr012 according to the control sub-signals C ref08 and sends to SA02, and the current generating sub-circuit 03 generates I tr013 according to the control sub-signals C ref04 and sends to SA03.

[0148] SA01 compares the target current I cell and I ref12 , and outputs the first comparison signal C om011 representing the comparison result, SA02 compares the target current I cell and I ref08 , and outputs the first comparison signal C om012 representing the comparison result, and SA03 compares the target current I cell and I ref04 , and outputs the first comparison signal C om013 .

[0149] As shown in FIG. 9, if the first comparison signal C tr011 , the first comparison signal Ctr012 , the first comparison signal C tr013 is 111, Case01 is corresponding; if the first comparison signal C tr011 , the first comparison signal C tr012 , the first comparison signal C tr013 is 011, Case02 is corresponding; if the first comparison signal C tr011 , the first comparison signal C tr012 , the first comparison signal C tr013 is 001, Case03 is corresponding; if the first comparison signal C tr011 , the first comparison signal C tr012 , the first comparison signal C tr013 is 000, Case04 is corresponding.

[0150] In the second reading stage:

[0151] For Case01, the logic circuit 121 decodes the logic operation according to the first comparison signal C tr011 , the first comparison signal C tr012 , the first comparison signal C tr013 , generates the control sub-signal C ref15 corresponding to I tr021 , the control sub-signal C ref14 corresponding to I tr022 , the control sub-signal C ref13 corresponding to I tr023 , respectively sent to the current generation sub-circuit 01, the current generation sub-circuit 02, the current generation sub-circuit 03;

[0152] The current generation sub-circuit 01 generates I tr021 according to the control sub-signal C ref15 and sends it to SA01, the current generation sub-circuit 02 generates I tr022 according to the control sub-signal C ref14 and sends it to SA02, and the current generation sub-circuit 03 generates I tr023 according to the control sub-signal C ref13 and sends it to SA03;

[0153] SA01 compares the target current I cell and I ref15 , outputs the second comparison signal C om021 characterizing the comparison result, SA02 compares the target current I cell and I ref14 , outputs the second comparison signal C om022 characterizing the comparison result, and SA03 compares the target current I cell and I ref13 , outputs the second comparison signal Com023 If the second comparison signal C tr021 , the second comparison signal C tr022 , the second comparison signal C tr023 is 111, the corresponding target sub-interval is sub-interval 16, and the 4-bit data is 1111; here, the logic circuit 121 can decode according to the two comparison signals C tr011 C tr012 C tr013 C tr021 C tr022 C tr023 = 111111 to obtain the 4-bit data 1111, and in order to ensure timing synchronization, the first comparison signals can also be delayed, and the specific logic circuit 121 can be obtained by logic gate combination to realize the related decoding function, and the subsequent each case is decoded in the same way, and will not be described in detail; if the second comparison signal C tr021 , the second comparison signal C tr022 , the second comparison signal C tr023 is 011, the corresponding target sub-interval is sub-interval 15, and the 4-bit data is 1110; if the second comparison signal C tr021 , the second comparison signal C tr022 , the second comparison signal C tr023 is 001, the corresponding target sub-interval is sub-interval 14, and the 4-bit data is 1101; if the second comparison signal C tr021 , the second comparison signal C tr022 , the second comparison signal C tr023 is 000, the corresponding target sub-interval is sub-interval 14, and the 4-bit data is 1100.

[0154] For Case02-Case04, the same reasoning applies, which will not be described here.

[0155] Since the embodiment of the present disclosure only needs two reading stages to read out 4-bit data, the TRCD of the 4-bit data reading is basically the same as the TRCD of the 3-bit data reading in Table 1, thereby meeting the DRAM SPEC.

[0156] In view of the circuit occupation area, for 4-bit data, compared with parallel sensing: parallel sensing needs (2 4 -1=15) circuits for generating reference current (equivalent to current generation sub-circuit), 15 circuits for comparing target current and reference current (equivalent to comparison sub-circuit), and 15 copies of target current are needed; while in the embodiment of the present disclosure, only 3 current generation sub-circuits and 3 comparison sub-circuits are needed, and the circuit occupation area is greatly reduced. For more bits of data, the same reasoning applies, and while ensuring to meet the DRAM SPEC, the circuit occupation area will be greatly reduced.

[0157] In summary, in order to solve the problem of too large circuit area or too slow speed caused by too many stages of reading in multi-bit data reading, the embodiment of the present disclosure proposes a new data reading scheme. Taking a 3-bit storage unit as an example, two SAs are used to divide the reading operation into two stages: as shown in FIG. 7, in the first stage, I ref5 and I ref3 are used as reference currents for SA1 and SA2. According to the data stored in the cell, there can be three cases. For example, if the stored data is one of the highest three levels, it can be attributed to Case 1. In the second stage, according to the result of the first stage, I ref3 ~I ref7 one or both of them are used for SA1 and SA2. In this way, through the above two reading stages, 3-bit data reading can be achieved, so that two SAs are used for each BL (WBL) to meet the DRAM SPEC. Based on this scheme, more bits of data can also be read in two stages.

[0158] In another embodiment of the present disclosure, a data reading method is also provided, as shown in FIG. 10, which can include the following steps:

[0159] S1001: comparing a target current from a storage unit with N first currents respectively to generate N first comparison signals.

[0160] Wherein, the storage unit is used to store the data to be read; the N first currents divide N+1 current intervals; the N first comparison signals indicate a target current interval in the N+1 current intervals.

[0161] S1002: generating M second currents according to the N first comparison signals.

[0162] Wherein, M and N are both integers greater than 0, and M is less than or equal to N; the M second currents divide the target current interval into M+1 subintervals, each subinterval corresponding to a value of multi-bit data.

[0163] S1003: comparing the target current with the M second currents to generate M second comparison signals.

[0164] Wherein; the M second comparison signals indicate a target subinterval in the M+1 subintervals.

[0165] S1004: determining the value of the data to be read according to the N first comparison signals and the M second comparison signals.

[0166] Wherein, the value of the data to be read is the value corresponding to the target subinterval.

[0167] It should be noted that the data reading method provided by the embodiment of the present disclosure is realized by the foregoing data reading circuit 10, and details not disclosed by the embodiment of the present disclosure can be understood by referring to the description of the foregoing embodiment, which will not be described here.

[0168] In still another embodiment of the present disclosure, a memory is also provided, as shown in FIG. 11, the memory 30 includes a storage array 200 and the data reading circuit 10 in the foregoing embodiment; the storage array 200 includes a plurality of storage units 20, and the data reading circuit 10 is connected with the storage units 20;

[0169] The storage unit 20 is configured to store the read data.

[0170] The data reading circuit 10 is configured to read the read data from the storage unit 20.

[0171] It should be noted that the data reading circuit 10 can be addressed according to the received address signal, read command, etc., to open the corresponding storage unit 20, and then read out the data to be read in the manner described in the foregoing embodiment. Wherein, the addressing can be realized by the control circuit 12, or can be realized by an addressing circuit, and the addressing circuit 12 can be integrated in the control circuit 12, which is not specifically limited.

[0172] It should also be noted that the memory 30 can be a DRAM, for example but not limited to a DDR5 DRAM.

[0173] In still another embodiment of the present disclosure, an electronic device is also provided, which includes the memory 30 in the foregoing embodiment.

[0174] It should be noted that the electronic device can be, for example, a notebook computer, a mobile phone, a tablet computer, a server, etc., which is not specifically limited.

[0175] The above is only a preferred embodiment of the present disclosure, and is not used to limit the protection scope of the present disclosure.

[0176] It should be noted that in the present disclosure, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitation, the element defined by the statement “comprises a” does not exclude the presence of another identical element in the process, method, article or device including the element.

[0177] The above embodiment number of the present disclosure is only for description, and does not represent the advantages and disadvantages of the embodiment.

[0178] The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method embodiments.

[0179] The features disclosed in the several product embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new product embodiments.

[0180] The features disclosed in the several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method embodiments or device embodiments.

[0181] The above is merely specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims. Industrial applicability

[0182] The data reading circuit, method, memory and electronic device provided by the embodiments of the present disclosure can complete data reading in two stages for multi-bit data of 3 bits and above, on the one hand, without the need for excessive circuit components, effectively saving circuit area, on the other hand, only two reading stages are needed to read out multi-bit data, avoiding excessive delay, improving reading speed and ensuring that TRCD meets standard requirements.

Claims

A data reading circuit (10) comprises a comparison circuit (11) and a control circuit (12); The comparison circuit (11) is configured to compare a target current from a storage unit (20) with N first currents respectively to generate N first comparison signals; the storage unit (20) is configured to store data to be read; the N first currents divide N+1 current intervals; and the N first comparison signals indicate a target current interval in the N+1 current intervals; The control circuit (12) is configured to receive the N first comparison signals, and generate M second currents according to the N first comparison signals; M and N are both integers greater than 0, and M is less than or equal to N; the M second currents divide the target current interval into M+1 sub-intervals, and each of the sub-intervals corresponds to a value of the data to be read; The comparison circuit (11) is further configured to compare the target current with the M second currents to generate M second comparison signals; and the M second comparison signals indicate a target sub-interval in the M+1 sub-intervals; The control circuit (12) is further configured to determine the value of the data to be read according to the N first comparison signals and the M second comparison signals; and the value of the data to be read is the value corresponding to the target sub-interval. The data reading circuit (10) according to claim 1, wherein The control circuit (12) comprises a logic circuit (121) and a current generation circuit (122); The logic circuit (121) is configured to generate a first control signal, and send the first control signal to the current generation circuit (122); and the first control signal indicates values of the N first currents; The current generation circuit (122) is configured to receive the first control signal, and generate the N first currents according to the first control signal; The logic circuit (121) is further configured to receive the N first comparison signals, generate a second control signal according to the N first comparison signals, and send the second control signal to the current generation circuit (122); and the second control signal indicates values of the M second currents; The current generation circuit (122) is configured to receive the second control signal, and generate the M second currents according to the second control signal. The data reading circuit (10) according to claim 2, wherein The first control signal comprises N first control sub-signals, and the second control signal comprises M second control sub-signals; the N first control sub-signals correspond to the N first currents one by one, and the M second control sub-signals correspond to the M second currents one by one; and the current generation circuit (122) comprises N current generation sub-circuits (1221), wherein: The current generation sub-circuit (1221) is configured to receive a corresponding first control sub-signal, and generate a corresponding first current according to the first control sub-signal; The current generation sub-circuit (1221) is further configured to receive a corresponding second control sub-signal, and generate a corresponding second current according to the second control sub-signal. The data reading circuit (10) according to claim 3, wherein The comparison circuit (11) comprises N comparison sub-circuits (111), wherein: The comparison sub-circuit (111) is configured to receive the target current and the corresponding first current, and compare the target current and the corresponding first current to generate a corresponding first comparison signal. The comparison sub-circuit (111) is further configured to receive the target current and the corresponding second current, and compare the target current and the corresponding second current to generate a corresponding second comparison signal. The data reading circuit (10) according to claim 4, wherein The comparison sub-circuit (111) is a sensitive amplifier. The data reading circuit (10) according to claim 4 or 5, wherein The data reading circuit (10) further comprises a current replication circuit (13); wherein: The current replication circuit (13) is configured to replicate the target current from the storage unit (20) into N parts, and send the replicated N parts of the target current to each comparison sub-circuit (111) respectively. The data reading circuit (10) according to any one of claims 1 to 6, wherein The read data is n-bit data, n is a positive integer, and N = n-1. A data reading method, the method comprising: comparing the target current from the storage unit (20) with N first currents respectively to generate N first comparison signals; The storage unit (20) is configured to store read data; the N first currents divide N+1 current intervals; The N first comparison signals indicate a target current interval in the N+1 current intervals; generating M second currents according to the N first comparison signals; M and N are both integers greater than 0, and M is less than or equal to N; the M second currents divide the target current interval into M+1 sub-intervals, each of the sub-intervals corresponds to a value of the read data; comparing the target current with the M second currents to generate M second comparison signals; the M second comparison signals indicate a target sub-interval in the M+1 sub-intervals; determining the value of the read data according to the N first comparison signals and the M second comparison signals, the value of the read data being the value corresponding to the target sub-interval. A memory (30) comprising a storage array (200) and a data reading circuit (10) according to any one of claims 1 to 7; the storage array (200) comprises a plurality of storage units (20), and the data reading circuit (10) and the storage units (20) are connected; The storage unit (20) is configured to store read data; The data reading circuit (10) is configured to read the read data from the storage unit (20). An electronic device comprising the memory (30) according to claim 9. An electronic device comprising the memory (30) according to claim 9.

Images