Display module and display driving method

Abstract

A display module and a display driving method. The display module comprises: a timing control circuit, a plurality of driving circuits and a display panel; input ends of the driving circuits are electrically connected to output ends of the timing control circuit; output ends of the driving circuits are electrically connected to input ends of the display panel; the plurality of driving circuits are arranged in an array in a first direction, and the plurality of driving circuits are symmetrically distributed about a central axis of the display panel, the central axis extending in a second direction; each first circuit group comprises a first driving circuit and a second driving circuit; each second circuit group is arranged between a first driving circuit and a second driving circuit; a first group of signals refers to second signals sent by the first circuit groups to the display panel, and a second group of signals refers to second signals sent by the second circuit groups to the display panel; and a first moment at which the display panel receives the first group of signals is later than a second moment at which the display panel receives the second group of signals.

Description

Display module and display driving method

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202411323195.3, filed on September 22, 2024, and entitled "A display module and display driving method", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of display, in particular to a display module and display driving method. BACKGROUND

[0004] In a liquid crystal display module, point-to-point signals (P_to_P signals) are often used to transmit data between module units. The point-to-point signals are transmitted in a clock-embedded manner, and control instructions can also be embedded in the signals. For example, a timing controller (TCON) and each connected driving circuit (Source Driver IC) have independent signal lines, and point-to-point signals are used to transmit data.

[0005] Currently, in the driving process of a display panel, a timing controller (TCON) outputs signals to a driving circuit (Source Driver IC), and the Source Driver IC outputs signals to the display panel. The signals are usually transmitted synchronously, and the instantaneous energy is large, which can easily cause Electro-Magnetic Interference (EMI) to exceed the standard.

[0006] EMI is positively correlated with signal energy. Although measures such as using a spread spectrum clock generator (SSCG) to disperse the peak energy of the clock signal, adjusting the peak and valley values of the TCON signal, and reducing the energy spectrum density of the data stream through the disturbance function of the Source Driver IC can be used to improve the situation, the SSCG is limited by the specifications of the TCON and the Source Driver IC, the peak and valley values of the signal must meet the signal quality requirements, and there is a risk of data errors in the disturbance and recovery process. Therefore, the improvement effect is often not good, and even the display effect can be affected. SUMMARY

[0007] The present application provides a display module and display driving method, which can solve the problem that the current EMI improvement measures have poor improvement effect and even affect the display effect.

[0008] In a first aspect, the present application provides a display module, comprising: a time sequence control circuit, a plurality of drive circuits and a display panel connected in sequence;

[0009] An input end of the drive circuit is electrically connected with an output end of the time sequence control circuit, and the time sequence control circuit is configured to identify a first signal sent to the drive circuit and control a time sequence of the first signal;

[0010] An output end of the drive circuit is electrically connected with an input end of the display panel, and the drive circuit is configured to receive and process the first signal to form a second signal input to the display panel;

[0011] The plurality of drive circuits are arranged in an array along a first direction, and the plurality of drive circuits are symmetrically distributed about a central axis of the display panel, the central axis extending along a second direction, and the first direction and the second direction are orthogonal;

[0012] The plurality of drive circuits comprise a first circuit group and a second circuit group, the first circuit group comprises a first drive circuit and a second drive circuit, and the second circuit group is arranged between the first drive circuit and the second drive circuit;

[0013] The second signal comprises a first group of signals and a second group of signals, the first group of signals is the second signal sent by the first circuit group to the display panel, and the second group of signals is the second signal sent by the second circuit group to the display panel, wherein a time when the display panel receives the first group of signals is a first time, a time when the display panel receives the second group of signals is a second time, and the first time is greater than the second time.

[0014] Optionally, there is a first time difference between the first time and the second time;

[0015] The first time difference is greater than or equal to 5 bit widths, and the first time difference is less than or equal to 15 bit widths.

[0016] Optionally, the first group of signals has a first slew rate, and the second group of signals has a second slew rate;

[0017] The first slew rate is less than the second slew rate.

[0018] Optionally, a rising edge time length when the first group of signals changes from a first level to a second level is a first time length, and a rising edge time length when the second group of signals changes from the first level to the second level is a second time length, wherein the second level is greater than the first level;

[0019] The first time length is greater than the second time length.

[0020] Optionally, a difference between the first time length and the second time length is greater than zero and less than 4 bit widths.

[0021] Optionally, the first group of signals has a first time length between a rising edge and a falling edge, and the second group of signals has a second time length between a rising edge and a falling edge, wherein,

[0022] The first time length is less than the second time length.

[0023] Optionally, the second circuit group includes a third driving circuit and a fourth driving circuit, and the plurality of driving circuit groups further include a third circuit group;

[0024] A portion of the third circuit group is located between the first driving circuit and the third driving circuit, and another portion of the third circuit group is located between the second driving circuit and the fourth driving circuit;

[0025] The second signal further includes a third group of signals, the third group of signals being the second signal sent by the third circuit group to the display panel, and a time when the display panel receives the third group of signals being a third time, the third time being less than the second time.

[0026] Optionally, the third circuit group includes a fifth driving circuit and a sixth driving circuit, and the plurality of driving circuit groups further include a fourth circuit group;

[0027] A portion of the fourth circuit group is located between the fifth driving circuit and the third driving circuit, and another portion of the third circuit group is located between the sixth driving circuit and the fourth driving circuit;

[0028] The second signal further includes a fourth group of signals, the fourth group of signals being the second signal sent by the fourth circuit group to the display panel, and a time when the display panel receives the fourth group of signals being a fourth time, the fourth time being less than the third time.

[0029] Optionally, the fourth circuit group includes a seventh driving circuit and an eighth driving circuit, and the third circuit group further includes a ninth driving circuit and a tenth driving circuit, wherein the ninth driving circuit is located between the third driving circuit and the seventh driving circuit, the tenth driving circuit is located between the fourth driving circuit and the eighth driving circuit, the ninth driving circuit and the fifth driving circuit are symmetrical about the seventh driving circuit, and the sixth driving circuit and the tenth driving circuit are symmetrical about the eighth driving circuit,

[0030] and / or,

[0031] The second circuit group further comprises an eleventh driving circuit and a twelfth driving circuit, wherein the eleventh driving circuit is located between the first driving circuit and the seventh driving circuit, the twelfth driving circuit is located between the second driving circuit and the eighth driving circuit, the eleventh driving circuit and the third driving circuit are symmetrical about the seventh driving circuit, and the twelfth driving circuit and the fourth driving circuit are symmetrical about the eighth driving circuit.

[0032] Optionally, the first time difference is a time difference between the first time and the second time, the second time difference is a time difference between the second time and the third time, and the third time difference is a time difference between the third time and the fourth time.

[0033] The first time difference, the second time difference and the third time difference are equal; and / or,

[0034] The third group of signals has a third rate of change of voltage, the fourth group of signals has a fourth rate of change of voltage, the first rate of change of voltage is less than the second rate of change of voltage, the second rate of change of voltage is less than the third rate of change of voltage, and the third rate of change of voltage is less than the fourth rate of change of voltage.

[0035] Optionally, the display module further comprises a plurality of differential signal lines.

[0036] One end of the differential signal line is electrically connected to one output end of the timing control circuit, and the other end of the differential signal line is electrically connected to the input end of the driving circuit.

[0037] The first signal is a differential signal sent by the timing control circuit to the driving circuit, and the timing control circuit sends the differential signal to the plurality of driving circuits at different times.

[0038] Optionally, in the direction away from the central axis, the time difference between the time at which the timing control circuit sends the differential signal to two adjacent driving circuits is P bit widths, wherein P is a positive integer.

[0039] Optionally, the timing control circuit sends the differential signal to the first circuit group at a fifth time, and the timing control circuit sends the differential signal to the second circuit group at a sixth time.

[0040] The time difference between the fifth time and the sixth time is X bit widths, wherein X is a positive integer.

[0041] Optionally, the number of driving circuits is N.

[0042] N is an odd number, and the driving circuit located on the central axis is the driving circuit to which the timing control circuit first sends the differential signal.

[0043] Alternatively, N is an even number, and the two driving circuits closest to the center axis are the driving circuits from which the time sequence control circuit sends the differential signals.

[0044] Optionally, the driving circuit in the plurality of driving circuits that sends the second signal to the display panel is a target driving circuit, and the target driving circuit belongs to the second circuit group.

[0045] The target moment is a moment at which the display panel receives the second signal sent by the target driving circuit, and a time difference between the first moment and the target moment is greater than or equal to 15 bit widths and less than 325 bit widths.

[0046] A time difference between the second moment and the target moment is greater than or equal to 0 and less than 15 bit widths.

[0047] Optionally, the driving circuit further comprises a plurality of signal lines, and the display panel further comprises a plurality of data lines; the plurality of signal lines are electrically connected to the data lines of the display panel to serve as channels for transmitting source signals.

[0048] The moments at which the signal lines in different driving circuits receive the source signals are different, and / or the moments at which the signal lines in different driving circuits send the source signals are different.

[0049] Optionally, the plurality of signal lines are arranged along the first direction.

[0050] The first target signal line is one of the plurality of signal lines, and the moment at which the first target signal line sends the source signal is greater than the moments at which other signal lines in the plurality of signal lines send the source signal.

[0051] In a direction away from the first target signal line, a time difference between adjacent signal lines in sending the source signal is S bit widths, and S is a positive integer.

[0052] Optionally, the plurality of signal lines are sorted along the first direction.

[0053] The first target signal line is a signal line with the largest serial number in the plurality of signal lines, or the first target signal line is a signal line with the smallest serial number in the plurality of signal lines, or the first target signal line is a signal line with an intermediate serial number in the plurality of signal lines.

[0054] Optionally, the first signal line in the plurality of signal lines that sends the source signal to the connection line is a second target signal line.

[0055] The time difference between the first target signal line and the second target signal line for transmitting the source signal is greater than zero and less than 16 bit widths.

[0056] Optionally, the charging duration of the display module is greater than or equal to 1.6 microseconds.

[0057] In a second aspect, the present application provides a display driving method applied to the display module of the first aspect, and the display driving method comprises:

[0058] A first sending process, in which the timing control circuit sends first signals to a plurality of drive circuits according to data of one frame of image, wherein in the first sending process, the delay time difference between the first signals corresponding to adjacent drive circuits is a preset first offset, and / or the first signal corresponding to at least one drive circuit comprises a preset second offset;

[0059] A second sending process, in which the drive circuit sends second signals to a display panel according to the first signals, wherein in the second sending process, the delay time difference between source signals of at least one drive circuit is the second offset;

[0060] The second signal comprises the source signals corresponding to a plurality of channels in the drive circuit, and at least one of the first offset and the second offset is not zero, so that the first time at which the display panel receives a first group of signals is greater than the second time at which the display panel receives a second group of signals;

[0061] The second signal comprises the first group of signals and the second group of signals, the first group of signals being the second signals sent by a first circuit group in the plurality of drive circuits to the display panel, and the second group of signals being the second signals sent by a second circuit group in the plurality of drive circuits to the display panel.

[0062] Optionally, the timing control circuit sends first signals to a plurality of drive circuits according to data of one frame of image, comprising:

[0063] The timing control circuit sends the first signal to a target drive circuit;

[0064] The timing control circuit sends the first signal to adjacent drive circuits in sequence according to a first offset, with the target drive circuit as a reference, wherein the first offset represents the clock offset of the first signal received by adjacent drive circuits.

[0065] Optionally, the timing control circuit sends first signals to a plurality of drive circuits according to data of one frame of image, comprising:

[0066] The timing control circuit sends the first signal with the first configuration parameter embedded to at least one of the driving circuits, and sends the first signal with the second configuration parameter embedded to other driving circuits.

[0067] The signal waveform of the first signal with the first configuration parameter embedded is different from the signal waveform of the first signal with the second configuration parameter embedded, and the first signal with the second configuration parameter embedded is used to control other driving circuits to send the second signal to the display panel at the same time.

[0068] Optionally, before the second sending process, the method further comprises:

[0069] The driving circuit stores the second offset in response to the first signal with the first configuration parameter embedded, wherein the first configuration parameter comprises the second offset.

[0070] The driving circuit sends the second signal to the display panel according to the first signal, comprising:

[0071] The driving circuit delays sending the second signal to the display panel, wherein the delay time difference between the signal rising edges of target second signals in adjacent driving circuits is the second offset, and the target second signal comprises a source signal corresponding to a channel with the same serial number in the plurality of driving circuits.

[0072] Optionally, before the second sending process, the method further comprises:

[0073] The driving circuit stores the second offset in response to the first signal with the first configuration parameter embedded, wherein the first configuration parameter comprises the second offset.

[0074] The driving circuit sends the second signal to the display panel according to the first signal, comprising:

[0075] The driving circuit sends the second signal to the driving circuit according to a preset rising edge duration, wherein the rising edge duration difference between target second signals in adjacent driving circuits is the second offset, and the target second signal comprises a source signal corresponding to a channel with the same serial number in the plurality of driving circuits.

[0076] Optionally, before the second sending process, the method further comprises:

[0077] The driving circuit stores the second offset in response to the first signal with the first configuration parameter embedded, wherein the first configuration parameter comprises the second offset.

[0078] The driving circuit sends a second signal to the display panel according to the first signal, and the second signal includes:

[0079] The driving circuit sequentially sends the source signals to the display panel through the plurality of channels in order of the delay time length from short to long, wherein the delay time difference between the source signals corresponding to adjacent channels is a third offset, and the sum of the third offsets corresponding to the plurality of channels is equal to the second offset.

[0080] Optionally, the timing control circuit sends a first signal to a plurality of driving circuits according to the data of a frame of image, and the first signal includes:

[0081] In a case where the sum of the first delay time length and the second delay time length is less than a preset panel delay time length, the timing control circuit sends a first signal to a plurality of driving circuits according to the data of a frame of image.

[0082] The first delay time length is a total delay time length corresponding to the timing control circuit, the second delay time length is a total delay time length corresponding to the plurality of driving circuits, and the panel delay time length represents a delay time length threshold for driving the display panel to normally display the frame of image.

[0083] The display module and the display driving method provided by the application have at least the following advantages: a timing control circuit, a plurality of driving circuits and a display panel are sequentially connected; an input end of the driving circuit is electrically connected to an output end of the timing control circuit; the timing control circuit is configured to identify a first signal sent to the driving circuit and control the timing of the first signal; an output end of the driving circuit is electrically connected to an input end of the display panel; the driving circuit is configured to receive and process the first signal to form a second signal input to the display panel; the plurality of driving circuits are arranged in an array along a first direction, and the plurality of driving circuits are symmetrically distributed about a central axis of the display panel; the central axis extends along a second direction; the first direction and the second direction are orthogonal; the plurality of driving circuits include a first circuit group and a second circuit group; the first circuit group includes a first driving circuit and a second driving circuit; the second circuit group is arranged between the first driving circuit and the second driving circuit; the second signal includes a first group of signals and a second group of signals, the first group of signals being the second signal sent by the first circuit group to the display panel, and the second group of signals being the second signal sent by the second circuit group to the display panel; wherein the display panel receives the first group of signals at a first time, and receives the second group of signals at a second time, and the first time is greater than the second time. In this way, the display panel receives the first group of signals and the second group of signals at different times, so that the energy is dispersed during the transmission of the second signal, the instantaneous energy is reduced, and the EMI noise of the display module is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0084] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application or related art. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0085] FIG. 1 is a schematic diagram of the effect of suppressing EMI by a spread spectrum clock generator in the related art;

[0086] FIG. 2 is a schematic diagram of an eye diagram and Mask in the related art;

[0087] FIG. 3 is a schematic diagram of the structure of a perturbation function circuit in the related art;

[0088] FIG. 4 is a schematic diagram of the structure of a display module according to an embodiment of the present application;

[0089] FIG. 5 is a schematic diagram of the structure of a display module according to another embodiment of the present application;

[0090] FIG. 6 is a schematic diagram of the data format of a point-to-point signal in the related art;

[0091] FIG. 7 is a schematic diagram of the screen division of a display panel in the related art;

[0092] FIG. 8 is a schematic diagram of the signal waveforms of the charging process of a display panel according to an embodiment of the present application;

[0093] FIG. 9 is a schematic diagram of the connection of a timing control circuit and a driving circuit according to an embodiment of the present application;

[0094] FIG. 10 is a schematic diagram of the hardware interface of a timing controller according to an embodiment of the present application;

[0095] FIG. 11 is a schematic diagram of the grouping of a driving circuit according to an embodiment of the present application;

[0096] FIG. 12 is a schematic diagram of the structure of a display module according to another embodiment of the present application;

[0097] FIG. 13 is a schematic diagram of the clock rising edge of a differential signal in the related art;

[0098] FIG. 14 is a schematic diagram of the position of the rising edge of a signal according to an embodiment of the present application;

[0099] FIG. 15 is a schematic diagram of the synchronous transmission of a driving circuit group according to an embodiment of the present application;

[0100] FIG. 16 is a schematic diagram of the time division transmission of a driving circuit group according to an embodiment of the present application;

[0101] FIG. 17 is a diagram of a signal rising edge and a signal slope according to an embodiment of the present application;

[0102] FIG. 18 is a diagram of a signal rising edge and a signal slope according to an embodiment of the present application;

[0103] FIG. 19 is a diagram of delay time of three channel delay modes according to an embodiment of the present application;

[0104] FIG. 20 is a diagram of time division transmission according to an embodiment of the present application;

[0105] FIG. 21 is a diagram of EMI test result according to the related art;

[0106] FIG. 22 is a diagram of EMI test result after taking EMI improvement measures according to the related art;

[0107] FIG. 23 is a diagram of EMI test result according to an embodiment of the present application;

[0108] FIG. 24 is a flow chart of a display driving method according to an embodiment of the present application;

[0109] FIG. 25 is a diagram of time division transmission of a timing control circuit according to an embodiment of the present application;

[0110] FIG. 26 is a diagram of clock offset between adjacent differential pairs according to an embodiment of the present application;

[0111] FIG. 27 is a diagram of delay time difference of a first clock signal according to an embodiment of the present application;

[0112] FIG. 28 is a flow diagram of a display driving method according to an embodiment of the present application. DETAILED DESCRIPTION

[0113] The technical solutions in the embodiments will be described clearly and completely below with reference to the accompanying drawings in the embodiments. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0114] Currently, for the EMI noise of the TCON back end, a spread spectrum clock generator (SSCG) can be set in the TCON to disperse the peak energy of the clock signal to multiple frequency bands in the spread spectrum area, as shown in FIG. 1, where the curves respectively represent the energy reduction effect of the spread spectrum amplitude of 0% to 4%, to reduce the peak energy of the clock signal, thereby suppressing the EMI effect. However, due to the specification limitation of the TCON and the Source Driver IC, the improvement effect can only be the optimal solution within the specification allowed range, and sometimes the spread spectrum effect cannot completely meet the EMI test requirements even at the optimal state.

[0115] In the related art, the overall energy of the output signal can be reduced by adjusting the peak and valley values of the TCON output signal, thereby reducing the EMI noise. However, the adjustment of the peak and valley values of the TCON signal is limited by the quality requirement of the signal quality, as shown in FIG. 2, the eye diagram of the signal after the peak and valley value adjustment cannot be pressed to the mask, and the signal quality needs to be ensured to be stable, so the improvement effect of this method on EMI is limited.

[0116] In addition, a random display data stream can be transmitted through the scrambling and descrambling functions to reduce the energy spectrum density of the data stream and thereby reduce the EMI noise. For example, a scrambling function circuit can be set in the Source Driver IC, as shown in FIG. 3, including a 24-bit scrambling module, a 24-bit D flip-flop (DFF) and a logic circuit, which outputs 24-bit RGB image data or scrambled data under the control of the RST, PCLK, D_SCR_EN and D_SCR_RST signals sent by the TCON. However, this method involves the scrambling and descrambling process, and may cause data errors due to decoding errors, resulting in the risk of display panel picture abnormalities.

[0117] FIG. 4 exemplarily shows a structural schematic diagram of a display module provided by an embodiment of the present application, as shown in FIG. 4, the display module includes a timing control circuit, a plurality of drive circuits and a display panel connected in sequence;

[0118] The input end of the drive circuit is electrically connected with the output end of the timing control circuit, and the timing control circuit is configured to identify a first signal sent to the drive circuit and control the timing of the first signal;

[0119] The output end of the drive circuit is electrically connected with the input end of the display panel, and the drive circuit is configured to receive and process the first signal to form a second signal input to the display panel;

[0120] The plurality of drive circuits are arrayed along a first direction, and the plurality of drive circuits are symmetrically distributed about a central axis of the display panel, the central axis extends along a second direction, and the first direction and the second direction are orthogonal.

[0121] The plurality of drive circuits comprises a first circuit group and a second circuit group, the first circuit group comprises a first drive circuit and a second drive circuit, and the second circuit group is arranged between the first drive circuit and the second drive circuit;

[0122] The second signals comprise a first group of signals and a second group of signals, the first group of signals being the second signals sent by the first circuit group to the display panel, and the second group of signals being the second signals sent by the second circuit group to the display panel, wherein the display panel receives the first group of signals at a first time point, and receives the second group of signals at a second time point, and the first time point is greater than the second time point.

[0123] In some embodiments, the timing control circuit and each drive circuit can have independent signal lines, that is, the timing control circuit is electrically connected to the plurality of drive circuits respectively. Specifically, the timing control circuit can comprise a plurality of output terminals, each output terminal being electrically connected to an input terminal of a drive circuit through a signal line. The timing control circuit and the drive circuit can transmit data in a point-to-point manner, for example, image data, control instructions, etc. The display module can be a liquid crystal display module that transmits data in a point-to-point manner, and the data transmission process between the timing control circuit and the drive circuit follows a point-to-point signal interface transmission protocol for liquid crystal display screens.

[0124] For example, FIG. 5 is a structural schematic diagram of another display module provided by an embodiment of the present application. As shown in FIG. 5, the timing control circuit is a timing controller (TCON), the timing controller is arranged on a TCON board, the TCON board comprises 1-51 external interfaces, and image data can be received through the external interfaces. The TCON board connects 12 drive circuits through two printed circuit boards (XPCB) for data transmission, the drive circuits are Source Driver ICs, the Source Driver ICs are arranged on Chip on Film (COF) packages, and are marked as XD1-XD12 in FIG. 5. The TCON is connected to each Source Driver IC through independent signal lines, and can transmit data in a point-to-point manner. Each Source Driver IC is further connected to a display panel, and sends a source signal to the display panel to drive the display panel to display an image.

[0125] It should be noted that, as shown in FIG. 6, the complete data format of the point-to-point signal can comprise a regular training clock signal (Training CLK), a configuration signal (Configuration) that can configure parameters of the drive circuit, and a normal image signal such as RGB DATA.

[0126] In the embodiments of the present application, the first signal can adopt the data format of a point-to-point signal as shown in FIG. 6, and the first signal can include a training clock signal, a configuration signal, and an image signal. The timing control circuit can receive image data, generate a plurality of first signals corresponding to the respective driving circuits according to the image data, and then control the timing of the plurality of first signals and send the first signals to the driving circuits, so that the driving circuits obtain the second signals according to the first signals.

[0127] For example, the first signal sent by the timing control circuit to the driving circuit can include the first signal and the image data, the first signal has the clock signal and the control instruction embedded therein, and the remaining part is the image data. The driving circuit can obtain the image data from the first signal as the source signal, and then send the second signal to the display panel in response to the control instruction of the timing control circuit to drive the display panel to display the image.

[0128] For the problem of EMI exceeding the standard caused by the TCON synchronously sending signals to a plurality of Source Driver ICs and the plurality of Source Driver ICs synchronously sending signals to the display panel in the related art, the embodiments of the present application can reduce the instantaneous energy of the signal sending process by time-division sending signals by the timing control circuit to a plurality of driving circuits and / or controlling the signal delay of at least one driving circuit so that the driving circuit time-division sends signals to the display panel, thereby achieving the effect of reducing EMI noise.

[0129] In some embodiments, the plurality of driving circuits in the display module are arranged in an array along a first direction, and the first direction can be a direction parallel to the edge of the display panel. The central axis of the display panel extends along a second direction, and the first direction is orthogonal to the second direction, so that the first direction is perpendicular to the central axis of the display panel. In addition, the plurality of driving circuits are symmetrically distributed about the central axis. If there are an odd number of driving circuits, the middle driving circuit is located on the central axis. If there are an even number of driving circuits, the number of driving circuits on both sides of the central axis is equal.

[0130] In some embodiments, the driving circuits can be grouped to obtain a plurality of driving circuit groups, and the plurality of driving circuit groups at least include a first circuit group and a second circuit group. For example, when the driving circuit groups only include the first circuit group and the second circuit group, the first circuit group includes two driving circuits, i.e., a first driving circuit and a second driving circuit, and the second circuit group includes other driving circuits. The second circuit group is arranged between the first driving circuit and the second driving circuit, so that the first driving circuit and the second driving circuit are driving circuits on the two sides, respectively. For example, referring to FIG. 5, the first circuit group can include two Source Driver ICs XD1 and XD12, and the second circuit group can include other 10 Source Driver ICs.

[0131] In some embodiments, the first circuit group and the second circuit group can be controlled to send the second signals to the display panel in time division manner, so as to reduce the instantaneous energy of the signal sending process and improve the EMI noise of the display module. Specifically, the second signal sent by the first circuit group to the display panel is referred to as the first group signal, and the second signal sent by the second circuit group to the display panel is referred to as the second group signal. The first time at which the display panel receives the first group signal is greater than the second time at which the display panel receives the second group signal, i.e., the display panel receives the first group signal later than the second group signal, so that the number of signals received at the same time can be reduced, and thus the instantaneous energy can be reduced.

[0132] Specifically, the first sending process refers to the process in which the timing control circuit sends a plurality of first signals to the driving circuit, and the second sending process refers to the process in which the driving circuit sends the second signal to the display panel. At least one of the first sending process and the second sending process adopts time division sending manner, and the first circuit group and the second circuit group can be time-divisioned, so that the instantaneous energy can be reduced, and thus the EMI of the display module can be reduced. In the first sending process, the timing control circuit can delay for a period of time after sending the first signal to the driving circuit in the second circuit group, and then send the first signal to the first driving circuit and the second driving circuit in the first circuit group. In the second sending process, the driving circuit in the second circuit group can send the second signal to the display panel, and then the first driving circuit and the second driving circuit in the first circuit group can send the second signal to the display panel.

[0133] In some embodiments, the data sending manner includes synchronous sending manner and time division sending manner, and the EMI of the display module can be reduced. When the timing control circuit corresponds to the first sending process in time division sending manner, the driving circuit corresponds to the second sending process in synchronous sending manner or time division sending manner. When the first sending process is in synchronous sending manner, at least one driving circuit in the second sending process needs to be in time division sending manner. The number of driving circuits in time division sending manner can be determined according to the EMI test requirement, which is not limited in the embodiments of the present application.

[0134] In some embodiments, the plurality of first signals sent by the timing control circuit can be delayed respectively, so that the clocks of the plurality of first signals are not synchronized, and thus the timing control circuit can send the first signals to the plurality of driving circuits in time division manner. The energy peak can be staggered, the instantaneous energy can be reduced, and thus the EMI noise can be reduced.

[0135] In some embodiments, the time division sending manner adopted in the second sending process can include delaying the second signals sent by different driving circuits respectively, and delaying the source signals sent by different channels in the driving circuit respectively. This is only an example, and the embodiments of the present application are not limited thereto.

[0136] In some embodiments, the second signals sent by different driving circuits are respectively delayed. The second signals sent by different driving circuits can be respectively delayed by delaying the data sending time of the second signals of the driving circuits, so that the second signals of the plurality of driving circuits are sent at different times, and the instantaneous energy can be reduced. Alternatively, the second signals sent by different driving circuits can be respectively delayed by adjusting the slew rate of the driving circuits. The slew rate is the slope of the output signal. The second signals of the plurality of driving circuits have different signal slopes, so that the energy spectrum of the second sending process in the frequency domain is dispersed, and the instantaneous energy can be reduced.

[0137] In some embodiments, the source signals sent by different channels of the driving circuit are respectively delayed. The source signals sent by different channels of the driving circuit can be respectively delayed by delaying the signal output time of the plurality of channels of the driving circuit, so that the source signals of the plurality of channels are output at different times, and the instantaneous energy of a single driving circuit in the second sending process can be reduced. In the second sending process, the number of driving circuits using the time-sharing sending mode of the channel can be determined according to the EMI test requirement in actual application, and the embodiments of the present application do not limit this.

[0138] The display module provided by the embodiments of the present application comprises: a time sequence control circuit, a plurality of driving circuits and a display panel connected in sequence; the input end of the driving circuit is electrically connected with the output end of the time sequence control circuit; the time sequence control circuit is configured to identify the first signal sent to the driving circuit and control the time sequence of the first signal; the output end of the driving circuit is electrically connected with the input end of the display panel; the driving circuit is configured to receive and process the first signal to form the second signal input to the display panel; the plurality of driving circuits are arranged in an array along a first direction, and the plurality of driving circuits are symmetrically distributed about the central axis of the display panel; the central axis extends along a second direction; the first direction and the second direction are orthogonal; the plurality of driving circuits comprise a first circuit group and a second circuit group; the first circuit group comprises a first driving circuit and a second driving circuit; the second circuit group is arranged between the first driving circuit and the second driving circuit; the second signal comprises a first group signal and a second group signal, the first group signal being the second signal sent by the first circuit group to the display panel, and the second group signal being the second signal sent by the second circuit group to the display panel; wherein the time when the display panel receives the first group signal is a first time, and the time when the display panel receives the second group signal is a second time, and the first time is greater than the second time. In this way, the display panel receives the first group signal and the second group signal at different times, so that the energy is dispersed in the sending process of the second signal, the instantaneous energy is reduced, and the EMI noise of the display module is reduced.

[0139] FIG. 7 exemplarily shows that due to the excessively long delay time of the second signal sent by the driving circuit, the charging time of the display panel is abnormal, the display areas driven by different driving circuits can have picture segmentation problems, and the display effect of the display panel is affected. Therefore, the premise of reducing the EMI noise of the display module is to ensure the normal picture display of the display panel, and the display panel needs to have sufficient charging time to normally display a frame of image, which limits the maximum delay time of the display module, which is referred to as panel delay time in the embodiment.

[0140] In the embodiment, the panel delay time can be different for different display modules due to the differences in the wiring mode and the structure of the display panel, and needs to be determined in combination with the actual parameters of the display module. The charging time of the display panel can be calculated according to the following formula (1):

[0141] T = t1-t2-t3-t4 (1)

[0142] The meanings of the parameters in formula (1) are shown in FIG. 8, T represents the charging time, t1 is the charging time of one pixel row of the display panel, t2 is the anti-charge (GOE) time, t3 is the corner cutting width, t4 / t5 are the rise time and fall time of the source signal respectively, and t4 in formula (1) can be replaced by t5. The purpose of GOE is to prevent mischarging, because the last pixel row of the display panel cannot be turned off instantaneously, and a falling process is needed, and the next pixel row also needs a process. If the opening speed of the next pixel row exceeds the closing speed of the last pixel row, misoperation is likely to occur, and the signal of the next pixel row will be charged into the last pixel row.

[0143] For the display module shown in FIG. 5, the parameters in formula (1) are shown in Table 1, and the charging time of the display module shown in FIG. 5 is calculated to be 1.85 microseconds (us) according to formula (1).

[0144] Table 1 Actual parameters of display module

[0145] The charging time after delay is defined as Td, and the panel delay time is ΔT, so Td = T-ΔT. Therefore, the charging time corresponding to the source charging circuit with the longest delay time is the shortest, and if the picture display of the display area corresponding to the driving circuit is to be normal, the actual charging time needs to be ensured to be not less than the charging time Td.

[0146] Table 2 exemplarily shows the theoretical charging time and the actual charging time corresponding to the three display modules. As shown in Table 2, when the actual charging time of the three display modules is not less than 1.6us, the picture can be normally displayed. Among them, for the second display module, when the theoretical charging time T is 1.85us and the actual charging time Td is 1.6us, the panel delay time ΔT is 0.25us.

[0147] In some embodiments, the register is usually internally in units of UI, 1UI represents the width of one bit, and UI is the inverse of the baud rate, i.e. Data Rate represents the baud rate, i.e. the data transmission rate. As shown in the timing controller (TCON) of FIG. 10, the data transmission rate (USIT Data Rate) can be calculated according to the following formula (2) through the USIT interface communication with the Source Driver IC.

[0148] Among them, H-total is the total horizontal time length of the signal, V-total is the total vertical time length of the signal, Frame is the refresh rate, Color Depth is the color depth, 3RGB is 3 RGB sub-pixels, 10 / 9 means that the USIT uses 10B / 9B encoding mode, Driver Number is the number of Source Driver ICs, and Input port is the number of Source Driver IC input interfaces (Ports). Taking the display module shown in FIG. 5 as an example, the data transmission rate (USIT Data Rate) is 1.3G, which means that the data bit transmitted per second is 1.3G. Then, the panel delay time converted into units of UI is shown in the following formula (3), and according to ΔT is 0.25us and Data Rate is 1.3G, the obtained ΔUI is 325UI.

[0149] In some embodiments, the TCON can communicate with the Source Driver IC through the Clock Embedded Differential Signaling (CEDS) interface or the high-definition display interface CHPI. The data transmission rates corresponding to the CEDS interface and the CHPI interface can be obtained by referring to formulas (4) and (5).

[0150] In some embodiments, the TCON can communicate with the Source Driver IC through a Clock Embedded Differential Signaling (CEDS) interface or a CHPI interface. The data transmission rates of the CEDS interface and the CHPI interface can be calculated according to Formulas (4) and (5).

[0151] In some embodiments, the second signals sent by different drive circuits can be delayed respectively by grouping the plurality of drive circuits to obtain a plurality of drive circuit groups, and then delaying the second signals corresponding to the plurality of drive circuit groups respectively, so that the plurality of drive circuit groups send the second signals to the display panel in time division. The drive circuits in a drive circuit group can be sent in a synchronous manner, i.e., the second signals are sent to the display panel synchronously.

[0152] In some embodiments, the plurality of drive circuit groups can follow the following grouping principles. First, if the number of drive circuit groups is even, the plurality of drive circuit groups should be symmetrically distributed about the center of the display panel, and if the number of drive circuit groups is odd, the other drive circuit groups in the plurality of drive circuit groups are symmetrically distributed about the middle drive circuit group, which is located at the center of the display panel. Second, adjacent drive circuits can belong to the same drive circuit group or different drive circuit groups, and in the case where adjacent drive circuits belong to different drive circuit groups, the time delay difference between adjacent drive circuits should be as small as possible. Third, the total delay time length corresponding to the second sending process is less than the panel delay time length, and the total delay time length corresponding to the second sending process plus the total delay time length corresponding to the first sending process should be less than the panel delay time length, so as to ensure that the display panel can normally display one frame of image.

[0153] For the second grouping principle, although the greater the signal delay, the smaller the instantaneous energy of the signal, the overall energy is dispersed, but the delay of the source signal is too large, which affects the charging time of the display panel. For the time delay difference between adjacent drive circuits, it should be as small as possible to avoid the display panel boundary problem caused by the time delay difference between adjacent drive circuits being too large.

[0154] For example, for the 12 drive circuits in the display module shown in FIG. 5, they can be divided into two groups of 6+6, or four groups of 3+3+3+3, etc. The drive circuit groups can be evenly grouped, or unevenly grouped, which is not limited by the embodiments of the present application. The XD1-XD12 can be divided into four groups of a, b, c and d according to the grouping mode shown in FIG. 11, and the data sending time instants corresponding to the four groups of a, b, c and d are t4, t3, t2 and t1 respectively. Among them, the group d is the drive circuit group with the longest delay time, and the data sending time instant t1 corresponding to the group d is the latest, and the group a is the drive circuit group with the shortest delay time, and the data sending time instant t4 corresponding to the group a is the earliest. The delay order of the four drive circuit groups corresponding to a, b, c and d from small to large, and the delay time difference between the two drive circuit groups adjacent in the delay order is Δt, which represents the second offset. Δt can be calculated according to the following formula (6).

[0155] The results of grouping XD1-XD12 are shown in FIG. 12. In FIG. 12, the adjacent XD6 and XD7 belong to the group c, the adjacent XD7 and XD8 belong to the group c and the group d respectively, and the group c and the group d are adjacent in the delay order. It should be noted that the display module shown in FIG. 5 is connected by XPCB wiring, and the XPCB itself wiring will also cause a certain delay, and the longer the wiring, the greater the delay. Compared with other COFs, the delay of the TCON signal received by XD1 and XD12 at the edge of the screen is the largest. If XD1 and XD12 are divided into drive circuit groups with smaller delay, the delay caused by the wiring problem and the delay of the source signal may be offset, and the purpose of time division transmission cannot be achieved. As shown in FIG. 12, XD1 and XD12 can be divided into the group d with the largest delay, so that the Source Driver IC corresponding to XD1 and XD12 time-division transmits the second signal to the display panel.

[0156] In some embodiments, as shown in FIG. 13, the sending time instant of the first rising edge of the signal corresponds to the sending time instant of the signal, so that the sending time instant of the first rising edge of the signal is delayed, and the sending time instant of the signal is delayed. As shown in FIG. 14, the rising edges of the four signals are staggered, indicating that the sending time instants of the four signals are different, and correspondingly, the time instants at which the signal receiving end receives the rising edges of the four signals are also different.

[0157] In some embodiments, the plurality of driving circuit groups can correspond to different delay durations, the delay durations can be set as N bit widths, N is a positive integer, and different driving circuit groups correspond to different values of N. The driving circuits belonging to the same driving circuit group can have the same delay duration embedded in the first configuration parameter in the first signal sent by the timing control circuit, so as to store the same delay duration in each driving circuit in the driving circuit group. For the driving circuit groups in adjacent delay orders, the first configuration parameter embedded in the first signal sent by the timing control circuit includes different delay durations, and the delay time difference between the rising edges of the second signal is the second offset.

[0158] In some embodiments, in the second sending process, the driving circuit sends the second signal to the display panel after a delay of N bit widths, so that the delay time difference between the second signal and the second signal corresponding to the adjacent driving circuit group is the second offset. On the signal waveform of the second sending process, the delay time difference between the signal rising edges of the source signals corresponding to the channels with the same serial numbers in the adjacent driving circuit groups is the second offset.

[0159] Optionally, the first driving circuit in the plurality of driving circuits that sends the second signal to the display panel is a target driving circuit, and the target driving circuit belongs to the second circuit group.

[0160] The time difference between the first time and the target time is greater than or equal to 15 bit widths and less than 325 bit widths.

[0161] The time difference between the second time and the target time is greater than or equal to 0 and less than 15 bit widths.

[0162] In some embodiments, the first driving circuit in the second circuit group that sends the second signal to the display panel can be taken as a target driving circuit, and the first time at which the display panel receives the second signal sent by the first driving circuit and the second driving circuit in the first circuit group is later than the target time corresponding to the target driving circuit, i.e., the first time is greater than the target time. The second time includes the target time.

[0163] In some embodiments, the driving circuit can be provided with a register for storing the delay duration, i.e., a first register. The first configuration parameter embedded in the first signal sent by the timing control circuit to the driving circuit can include the first register value, i.e., the first configuration parameter includes the N bit widths corresponding to the delay duration of the signal rising edge of the second signal. After receiving the first configuration parameter, the driving circuit can write the N bit widths into the first register, so that the first register stores the N bit widths.

[0164] Table 2 first register configuration table

[0165] As shown in Table 2, the first register can include CLK1TL0-5 registers, which can store 6-bit binary values, and the 6-bit binary values represent N-bit widths. For the grouping results of XD1-XD12 in FIG. 12, the N-bit width corresponding to the a group is binary 000101, the N-bit width corresponding to the b group is binary 001010, the N-bit width corresponding to the c group is binary 001111, and the N-bit width corresponding to the d group is binary 010100. The N-bit widths corresponding to the a, b, c, and d groups are converted to decimal as 5, 10, 15, and 20, respectively. Referring to equation (6), the second offset Δt = 5UI.

[0166] For the grouping results of XD1-XD12 in FIG. 12, the waveforms before the rising edges of the signals of the driving circuit groups are delayed are shown in FIG. 15, and the waveforms after the rising edges of the signals of the a, b, c, and d driving circuit groups are delayed are shown in FIG. 16. Before the rising edges of the signals are delayed, the first rising edges of the 12 driving circuit output signals of XD1-XD12 are in the same position, indicating that the source signals of the 12 driving circuits are transmitted synchronously. After the rising edges of the signals are delayed, referring to FIG. 16, the first rising edges of the 12 driving circuit output signals of XD1-XD12 are staggered, indicating that the source signals of the 12 driving circuits are transmitted at different times.

[0167] In some embodiments, the target driving circuit is the first driving circuit to transmit the second signal to the display panel, for example, the target driving circuit can be the driving circuit in the a driving circuit group shown in FIG. 12, and the target time can be the target time t4 corresponding to the a driving circuit group shown in FIG. 11. The first driving circuit and the second driving circuit in the first circuit group can be the driving circuits in the d driving circuit group shown in FIG. 12, and the first driving circuit and the second driving circuit are located on the two sides of the display panel, respectively. The second circuit group can include the a, b, and c driving circuit groups, and the second circuit group is located between the first driving circuit and the second driving circuit, as shown in FIG. 12.

[0168] As shown in FIG. 11, the first time corresponding to the first circuit group can be t1 corresponding to the driving circuit group d, and the second time corresponding to the second circuit group can include t2, t3 and t4. For example, if Δt = 5UI, the time difference between the second time and the target time can include the time difference between t2 and t3 and t4, and the time difference between t4 and itself, the minimum time difference being zero and the maximum time difference being no more than 3 times Δt, so the time difference between the second time and the target time is greater than or equal to 0, and the bit width is 15. In addition, the time difference between the first time and the target time can be the time difference between t1 and t4, which is greater than 3 times Δt, i.e. greater than 15UI. And in order to ensure that the display panel displays a normal picture, the time difference between the first time and the target time should be less than the panel delay time ΔT = 0.25us, which is converted to a bit width of 325UI.

[0169] Optionally, the first time difference between the first time and the second time is greater than or equal to 5 bit widths.

[0170] The first time difference is greater than or equal to 5 bit widths, and the first time difference is less than or equal to 15 bit widths.

[0171] In some embodiments, different driving circuits in the second circuit group can synchronously send the second signal to the display panel, or can send the second signal to the display panel in time sharing manner, and the embodiments of the present application do not limit this. If the driving circuits in the second circuit group correspond to the same second time, the driving circuits synchronously send the second signal to the display panel, otherwise the driving circuits correspond to a time in a period of time. For example, as shown in FIG. 11, the first circuit group includes the driving circuit group d, and the first time is t1. The second circuit group includes the driving circuit groups a, b and c, and the second time can be t1, t2 or t3. Since the time difference between the adjacent driving circuit groups is Δt = 5UI, the time difference between the first time and the second time is at least 1 Δt and at most 3 Δt, so the first time difference can be greater than or equal to 5 bit widths, and the first time difference is less than or equal to 15 bit widths.

[0172] Optionally, the first group of signals has a first slew rate, and the second group of signals has a second slew rate.

[0173] The first slew rate is less than the second slew rate.

[0174] In some embodiments, the slew rate of different driving circuits can be adjusted, i.e. the signal slope of the second signal corresponding to different driving circuits is set to different slope values, to disperse the energy spectrum in the frequency domain, thereby reducing the instantaneous energy of the second sending process, and the EMI noise caused by the second sending process can be reduced. The slew rate can be represented as the slope of the output signal of the operational amplifier in the driving circuit.

[0175] In some embodiments, the greater the signal slew rate, the shorter the time required for the signal to rise to the effective level, and the greater the slope of the rising edge of the signal waveform, and the shorter the length of the rising edge of the signal. For example, the greater the slope of the rising edge of the signal, the shorter the time required for the signal to rise from the low level to the high level. The smaller the signal slew rate, the longer the time required for the signal to rise to the effective level, the smaller the slope of the rising edge of the signal waveform, and the shorter the length of the rising edge of the signal.

[0176] In some embodiments, the signal slew rate of the first group of signals corresponding to the first circuit group can be smaller than the signal slew rate of the second group of signals corresponding to the second circuit group, i.e., the first slew rate is smaller than the second slew rate. In this way, even if the second signals of the plurality of drive circuits are transmitted synchronously, because the signal slew rates corresponding to the first circuit group and the second circuit group are different, the energy spectrum in the frequency domain is dispersed during the second transmission process, which can reduce the instantaneous energy of the second transmission process. At the display panel, because the first slew rate is smaller than the second slew rate, the second group of signals received by the display panel rises to the effective level first, and the first group of signals rises to the effective level later, i.e., the first time corresponding to the first group of signals received by the display panel is greater than the second time corresponding to the second group of signals received by the display panel.

[0177] In some embodiments, the signal slope can be changed by changing the length of the rising edge and / or the length of the falling edge of the signal. As shown in FIG. 17, the square wave signal in FIG. 17(a) has an amplitude of 10 volts (V), a frequency of 400 kilohertz (kHz), a duty cycle of 50%, and a rising time (tr) and a falling time (tf) of 10 nanoseconds (ns). The amplitudes of the n-th harmonic and the frequency domain of the square wave signal are shown in FIG. 17(b) and FIG. 17(c), respectively. As shown in FIG. 18, if the rising time (tr) and the falling time (tf) are set to 100 ns, the signal shown in FIG. 18(a) is obtained, which shows that the signal slope has changed. As shown in FIG. 18(b) and FIG. 18(c), the energy spectrum in the frequency domain is dispersed.

[0178] Optionally, the length of the rising edge of the first group of signals changing from the first level to the second level is a first length, and the length of the rising edge of the second group of signals changing from the first level to the second level is a second length, wherein the second level is greater than the first level.

[0179] The first length is greater than the second length.

[0180] In some embodiments, the second signals of the plurality of driving circuit groups can correspond to different signal slopes, and the second signal is high level active. The signal slope can be changed by changing the rising edge length of the signal. The rising edge length of the second signal can be set to M bit widths, where M is a positive integer, and different driving circuit groups correspond to different values of M. The driving circuits in the same driving circuit group can have the same rising edge length of the first configuration parameter embedded in the first signal sent by the timing control circuit, so that the same rising edge length is stored in the driving circuit group. The first configuration parameter embedded in the first signal sent by the timing control circuit includes different rising edge lengths for adjacent driving circuit groups in the delay sequence, and the rising edge length difference between the target second signals is a second offset.

[0181] In some embodiments, the rising edge length of the second signal sent by the driving circuit to the display panel is the M bit widths stored in the driving circuit, so that the rising edge length difference between the second signals corresponding to adjacent driving circuit groups is a second offset. On the signal waveform of the second sending process, the signal rising edge length difference between the second signals corresponding to channels with the same serial number in adjacent driving circuit groups is the second offset.

[0182] In some embodiments, since the second level is greater than the first level, the second signal changing from the first level to the second level can be the level state of the second signal changing from low level to high level, which generates a rising edge on the waveform of the second signal. The rising edge length corresponding to the first group of signals is a first length, and the rising edge length corresponding to the second group of signals is a second length. The first length can be greater than the second length, so that the signal slope of the first group of signals is smaller than the signal slope of the second group of signals.

[0183] Optionally, the difference between the first length and the second length is greater than zero and less than 4 bit widths.

[0184] In some embodiments, a second register for storing the rising edge length of the signal can be provided in the driving circuit. The first configuration parameter embedded in the first signal sent by the timing control circuit to the driving circuit can include the second register value, i.e., the first configuration parameter includes the M bit widths corresponding to the rising edge length of the second signal. After receiving the first configuration parameter, the driving circuit can write the M bit widths to the second register, so that the second register stores the M bit widths.

[0185] Table 3: Second register configuration table

[0186] As shown in Table 3, the second register can include a slew<0, 1, 2> register, which can store a 3-bit binary value, and the 3-bit binary value represents an M-bit bit width. Different register values correspond to different rising edge durations, and the shorter the rising edge duration, the greater the signal slew rate. As shown in Table 3, the slew<0, 1, 2> register can set 8 signal rising edge durations, for example, when the slew<0, 1, 2> is set to 000, the rising edge duration increases by 1UI, when the slew<0, 1, 2> is set to 001, the rising edge duration increases by 2UI, and so on. The second offset is 1UI.

[0187] For the grouping results of XD1-XD12 in FIG. 12, as shown in Table 4, the signal rising edge duration corresponding to the a group is the shortest, so the signal slew rate of the a group is the largest, and the signal slew rates of the b, c, and d groups decrease in turn.

[0188] Table 4: Second register grouping configuration

[0189] In some embodiments, as shown in FIG. 11, the first group of signals can include the second signals sent by the driving circuit group d, and the first duration corresponding to the first group of signals can be increased by 2UI at most. The second group of signals can be the second signals sent by the driving circuit groups a, b, or c, and the second duration corresponding to the second group of signals can be increased by 1UI at least, and then the difference between the first duration and the second duration should be at least 1UI and at most 3UI, that is, the difference is greater than zero and less than 4UI.

[0190] Optionally, the first group of signals has a first duration between the rising edge and the falling edge, and the second group of signals has a second duration between the rising edge and the falling edge, wherein,

[0191] The first duration is less than the second duration.

[0192] In some embodiments, the first duration can represent the duration of the active level of the first group of signals, that is, the first group of signals has a first duration between the rising edge and the falling edge. The second duration can represent the duration of the active level of the second group of signals, that is, the second group of signals has a second duration between the rising edge and the falling edge. In this embodiment, the period of the second signal is determined, and the difference between the half-period duration of the second signal and the first duration represents the total duration of the rising edge and the falling edge of the second signal. The smaller the first duration, the greater the total duration of the rising edge and the falling edge, and the smaller the signal slew rate. The greater the second duration, the smaller the total duration of the rising edge and the falling edge, and the greater the signal slew rate.

[0193] In some embodiments, the rising edge and the falling edge of the second signal can be symmetrical, and since the first time length is less than the second time length, the rising edge time length corresponding to the first group of signals is greater than the rising edge time length corresponding to the second group of signals. In this way, by limiting the size relationship between the first time length and the second time length, the signal slopes corresponding to the first group of signals and the second group of signals can be distinguished, so that there is a time difference between the time when the display panel receives the first group of signals and the time when the display panel receives the second group of signals. Therefore, the signal instantaneous energy can be reduced, thereby reducing the EMI noise of the display module.

[0194] Optionally, the second circuit group includes a third driving circuit and a fourth driving circuit, and the plurality of driving circuit groups further include a third circuit group;

[0195] Part of the third circuit group is located between the first driving circuit and the third driving circuit, and another part of the third circuit group is located between the second driving circuit and the fourth driving circuit;

[0196] The second signal further includes a third group of signals, the third group of signals being the second signal sent by the third circuit group to the display panel, the time when the display panel receives the third group of signals being a third time, and the third time being less than the second time.

[0197] In some embodiments, the second circuit group can be a driving circuit group adjacent to the first circuit group in the delay order, for example, the first circuit group in FIG. 11 can be the driving circuit group d, and the second circuit group can be the driving circuit group c. The driving circuits in the second circuit group should be arranged adjacent to the first circuit group in the first direction, and the time delay difference between the two driving circuit groups adjacent in the delay order is Δt. By setting the value of Δt to be small enough, the problem of picture segmentation between the display areas of the display panels driven by the first circuit group and the second circuit group can be avoided.

[0198] In some embodiments, the driving circuits other than the first circuit group and the second circuit group can be divided into a third circuit group, and the second signal sent by the third circuit group to the display panel can be referred to as a third group of signals. The third time when the display panel receives the third group of signals should be less than the second time when the display panel receives the second group of signals, i.e., the third time is less than the second time, and the second time is less than the first time.

[0199] For example, referring to FIG. 12, the first circuit group can include two Source Driver ICs XD1 and XD12, the second circuit group can include four Source Driver ICs XD2, XD11, XD6 and XD7, and the remaining Source Driver ICs can belong to the third circuit group. As shown in FIG. 12, XD2 is adjacent to XD1, and XD11 is adjacent to XD12.

[0200] In some embodiments, the third circuit group is also adjacent to the second circuit group in the delay sequence, the driving circuits in the third circuit group can be divided into two parts, and the driving circuits in the two parts are arranged separately between the driving circuits in the second circuit group, so that the problem of picture segmentation between the display areas driven by the second circuit group and the third circuit group respectively can also be avoided.

[0201] Specifically, the second circuit group includes a third driving circuit and a fourth driving circuit, the third driving circuit and the fourth driving circuit are located adjacent to each other in the plurality of driving circuits, and the third driving circuit and the fourth driving circuit are not arranged adjacent to the driving circuits in the first circuit group. For example, the third driving circuit and the fourth driving circuit can be XD6 and XD7, respectively, as shown in FIG. 12.

[0202] Specifically, a part of the third circuit group is located between the first driving circuit and the third driving circuit, and a part of the third circuit group is located between the driving circuit of the second circuit group adjacent to the first driving circuit and the third driving circuit. Another part of the third circuit group is located between the second driving circuit and the fourth driving circuit, and another part of the third circuit group is located between the driving circuit in the second circuit group adjacent to the second driving circuit and the fourth driving circuit. For example, as shown in FIG. 12, a part of the third circuit group can include driving ICs between XD2 and XD6, and another part of the third circuit group can include driving ICs between XD7 and XD11. This is only an example, and the embodiments of the present application are not limited thereto.

[0203] In some embodiments, the first circuit group, the second circuit group, and the third circuit group can be controlled to send the second signals to the display panel at different times, so as to reduce the instantaneous energy in the signal sending process, and to improve the EMI noise of the display module. Specifically, the first time is greater than the second time, and the second time is greater than the third time, so that the number of signals received by the display panel at the same time can be reduced, and the instantaneous energy can be reduced.

[0204] Optionally, the third circuit group includes a fifth driving circuit and a sixth driving circuit, and the plurality of driving circuit groups further include a fourth circuit group;

[0205] A part of the fourth circuit group is located between the fifth driving circuit and the third driving circuit, and another part of the third circuit group is located between the sixth driving circuit and the fourth driving circuit.

[0206] The second signal further includes a fourth group of signals, the fourth group of signals is the second signal sent by the fourth circuit group to the display panel, and the display panel receives the fourth group of signals at a fourth time, and the fourth time is less than the third time.

[0207] In some embodiments, the fourth circuit group can be a driving circuit group adjacent to the third circuit group in the delay order, for example, the third circuit group can be driving circuit group b in FIG. 11, and the fourth circuit group can be driving circuit group a. The driving circuits in the fourth circuit group should be arranged adjacent to the third circuit group in the first direction, and the time difference between the two driving circuit groups adjacent in the delay order is Δt. By setting the value of Δt to be small enough, the problem of picture segmentation between the display areas driven by the third circuit group and the fourth circuit group can be avoided.

[0208] In some embodiments, the driving circuits other than the first circuit group, the second circuit group and the third circuit group can be divided into a fourth circuit group, and the second signal sent by the fourth circuit group to the display panel can be referred to as a fourth group signal. The fourth time at which the display panel receives the fourth group signal should be less than the third time at which the display panel receives the third group signal, i.e., the fourth time is less than the fourth time, the third time is less than the second time, and the second time is less than the first time.

[0209] For example, referring to FIG. 12, the first circuit group can include two Source Driver ICs XD1 and XD12, the second circuit group can include four Source Driver ICs XD2, XD11, XD6 and XD7, and the third circuit group can include four Source Driver ICs XD3, XD5, XD8 and XD10. The remaining Source Driver ICs can belong to the fourth circuit group.

[0210] In some embodiments, the driving circuits in the fourth circuit group can be divided into two parts, and the driving circuits in the two parts can be arranged separately between the driving circuits in the third circuit group. In this way, the problem of picture segmentation between the display areas driven by the third circuit group and the fourth circuit group can also be avoided. Specifically, the third circuit group includes a fifth driving circuit and a sixth driving circuit, the fifth driving circuit is arranged adjacent to the driving circuits in the second circuit group in the first direction, and the sixth driving circuit is arranged adjacent to the driving circuits in the second circuit group in the first direction. For example, the fifth driving circuit and the sixth driving circuit can be two Source Driver ICs XD3 and XD10 as shown in FIG. 12.

[0211] Specifically, a part of the fourth circuit group is located between the fifth driving circuit and the third driving circuit, and a part of the fourth circuit group is located between the driving circuit of the third circuit group adjacent to the third driving circuit and the fifth driving circuit. Another part of the fourth circuit group is located between the sixth driving circuit and the fourth driving circuit, and another part of the fourth circuit group is located between the driving circuit in the third circuit group adjacent to the fourth driving circuit and the sixth driving circuit. For example, as shown in FIG. 12, a part of the fourth circuit group can include the Source Driver IC XD4, and another part of the fourth circuit group can include the Source Driver IC XD9. This is only an example, and the embodiments of the present application do not make any limitation.

[0212] In some embodiments, the first circuit group, the second circuit group, the third circuit group and the fourth circuit group can be controlled to send the second signal to the display panel at different times, so as to reduce the instantaneous energy of the signal sending process, thereby improving the EMI noise of the display module. Specifically, the first time is greater than the second time, the second time is greater than the third time, and the third time is greater than the fourth time, so that the number of signals received by the display panel at the same time can be reduced, and the instantaneous energy can be reduced.

[0213] Optionally, the fourth circuit group includes a seventh driving circuit and an eighth driving circuit, and the third circuit group further includes a ninth driving circuit and a tenth driving circuit, wherein the ninth driving circuit is located between the third driving circuit and the seventh driving circuit, the tenth driving circuit is located between the fourth driving circuit and the eighth driving circuit, the ninth driving circuit and the fifth driving circuit are symmetrical about the seventh driving circuit, the sixth driving circuit and the tenth driving circuit are symmetrical about the eighth driving circuit,

[0214] and / or,

[0215] The second circuit group further includes an eleventh driving circuit and a twelfth driving circuit, wherein the eleventh driving circuit is located between the first driving circuit and the seventh driving circuit, the twelfth driving circuit is located between the second driving circuit and the eighth driving circuit, the eleventh driving circuit and the third driving circuit are symmetrical about the seventh driving circuit, and the twelfth driving circuit and the fourth driving circuit are symmetrical about the eighth driving circuit.

[0216] In some embodiments, the seventh driving circuit in the fourth circuit group can be arranged adjacent to one or two driving circuits in the third circuit group, such as the seventh driving circuit can be arranged between the fifth driving circuit and the ninth driving circuit in the third circuit group, and the fifth driving circuit and the ninth driving circuit are symmetrical about the seventh driving circuit. The same applies to the eighth driving circuit, such as the seventh driving circuit can be arranged between the sixth driving circuit and the tenth driving circuit in the third circuit group, and the sixth driving circuit and the tenth driving circuit are symmetrical about the eighth driving circuit.

[0217] In some embodiments, the third driving circuit belongs to the second circuit group, the seventh driving circuit belongs to the fourth circuit group, and the ninth driving circuit belongs to the third circuit group. The third circuit group is located between the second circuit group and the fourth circuit group in the delay sequence, and thus the ninth driving circuit is located between the third driving circuit and the seventh driving circuit. The tenth driving circuit is also located between the fourth driving circuit and the eighth driving circuit.

[0218] For example, referring to FIG. 12, the first circuit group can include two Source Driver ICs XD1 and XD12, the second circuit group can include four Source Driver ICs XD2, XD11, XD6 and XD7, the third circuit group can include four Source Driver ICs XD3, XD5, XD8 and XD10, and the fourth circuit group can include two Source Driver ICs XD4 and XD9. The seventh driving circuit can be XD4, the eighth driving circuit can be XD9, the ninth driving circuit can be XD5, and the tenth driving circuit can be XD10. This is only an example, and embodiments of the present application are not limited in this regard.

[0219] In some embodiments, the eleventh driving circuit is located between the first driving circuit and the seventh driving circuit, and the eleventh driving circuit is located between the first driving circuit and the fifth driving circuit. The first driving circuit and the fifth driving circuit are also symmetrical about the eleventh driving circuit. The twelfth driving circuit is located between the second driving circuit and the eighth driving circuit, and the twelfth driving circuit is located between the second driving circuit and the sixth driving circuit. The first driving circuit and the fifth driving circuit are also symmetrical about the twelfth driving circuit.

[0220] In some embodiments, the second circuit group includes the third driving circuit, the fourth driving circuit, the eleventh driving circuit and the twelfth driving circuit. The third driving circuit and the eleventh driving circuit can be provided with driving circuits in the third circuit group and the fourth circuit group therebetween, and the fourth driving circuit and the twelfth driving circuit are also the same.

[0221] Specifically, the fourth circuit group includes the seventh driving circuit and the eighth driving circuit. The third driving circuit and the seventh driving circuit can be provided with driving circuits in the third circuit group therebetween, the eleventh driving circuit and the seventh driving circuit can also be provided with driving circuits in the third circuit group therebetween, and the twelfth driving circuit is also the same. In order to avoid the problem of picture segmentation of the display panel, the eleventh driving circuit and the third driving circuit are symmetrical about the seventh driving circuit, and the twelfth driving circuit and the fourth driving circuit are symmetrical about the eighth driving circuit. For example, the eleventh driving circuit and the twelfth driving circuit can be two Source Driver ICs XD2 and XD11 as shown in FIG. 12.

[0222] Optionally, the first time difference is a time difference between the first time and the second time, the second time difference is a time difference between the second time and the third time, and the third time difference is a time difference between the third time and the fourth time.

[0223] The first time difference, the second time difference, and the third time difference are equal; and / or,

[0224] The third group of signals has a third rate of change of voltage, the fourth group of signals has a fourth rate of change of voltage, the first rate of change of voltage is less than the second rate of change of voltage, the second rate of change of voltage is less than the third rate of change of voltage, and the third rate of change of voltage is less than the fourth rate of change of voltage.

[0225] In some embodiments, the signal rate of change of voltage of the third group of signals corresponding to the third circuit group is a third rate of change of voltage, the signal rate of change of voltage of the fourth group of signals corresponding to the fourth circuit group is a fourth rate of change of voltage. The first rate of change of voltage is less than the second rate of change of voltage, the second rate of change of voltage is less than the third rate of change of voltage, and the third rate of change of voltage is less than the fourth rate of change of voltage. In this way, even if the second signals of the plurality of drive circuits are transmitted synchronously, because the signal rates of change of voltage corresponding to the first circuit group, the second circuit group, the third circuit group, and the fourth circuit group are different, the energy spectrum in the frequency domain during the second transmission process is dispersed, and the instantaneous energy of the second transmission process can be reduced. At the display panel, because the first rate of change of voltage is less than the second rate of change of voltage, the second rate of change of voltage is less than the third rate of change of voltage, and the third rate of change of voltage is less than the fourth rate of change of voltage, the fourth group of signals received by the display panel rises to the effective voltage first, and the first group of signals rises to the effective voltage last. The first time is greater than the second time, the second time is greater than the third time, and the third time is greater than the fourth time, so the number of signals received by the display panel at the same time can be reduced, and the instantaneous energy can be reduced.

[0226] In some embodiments, the delay order is in the order of the fourth circuit group, the third circuit group, the second circuit group, and the first circuit group, where the delay time of the first circuit group is the longest, and the delay time of the fourth circuit group is the shortest. The first time corresponding to the first circuit group is the largest, and the second time, the third time, and the fourth time decrease in turn. The time difference between the first time and the second time is the first time difference, the time difference between the second time and the third time is the second time difference, and the time difference between the third time and the fourth time is the third time difference. The time difference between the time corresponding to the display panel receiving the second signal of the adjacent drive circuit group in the delay order can be obtained.

[0227] In some embodiments, the time difference of the delay between the driving circuit groups sequentially adjacent to each other can be set to be equal, so that the time difference of the second signals received by the display panel from the driving circuit groups sequentially adjacent to each other is also equal, i.e., the first time difference, the second time difference and the third time difference are equal. In this way, the time difference of the delay between the driving circuit groups sequentially adjacent to each other can be conveniently controlled, and the picture segmentation problem between the display areas driven by the driving circuit groups sequentially adjacent to each other can be avoided. For example, as shown in FIG. 11, the first time difference, the second time difference and the third time difference can be one △t respectively, and the time difference of the delay between the driving circuit groups sequentially adjacent to each other is △t = 5UI.

[0228] Optionally, the display module further comprises a plurality of differential signal lines.

[0229] One end of the differential signal line is electrically connected to one output end of the timing control circuit, and the other end of the differential signal line is electrically connected to the input end of the driving circuit.

[0230] The first signal is a differential signal sent by the timing control circuit to the driving circuit, and the timing control circuit sends the differential signals to the plurality of driving circuits at different times.

[0231] In some embodiments, the driving circuit and the timing control circuit are connected through a differential signal line. The output end of the timing control circuit can include a plurality of differential output ends, and one end of the differential signal line is electrically connected to the differential output end of the timing control circuit. The input end of the driving circuit can be a differential input end, and the other end of the differential signal line is electrically connected to the differential input end of the driving circuit.

[0232] In some embodiments, the timing control circuit sends the first signal to the driving circuit in the form of a differential signal, i.e., the first signal is a differential signal sent by the timing control circuit to the driving circuit. The timing control circuit can send signals to the plurality of driving circuits at different times. Specifically, the timing control circuit sends the differential signals to the plurality of driving circuits at different times, so that the instantaneous energy of the first sending process can be reduced, and the effect of reducing the EMI noise of the display module can be achieved. For example, a plurality of first signals sent by the timing control circuit can be delayed respectively, so that the clocks of the plurality of first signals are not synchronized, thereby realizing the timing control circuit sending the first signals to the plurality of driving circuits at different times.

[0233] In some embodiments, the timing control circuit can be a circuit composed of different functional modules, or an integrated TCON. Similarly, the driving circuit can also be a circuit composed of different functional modules or an integrated Source Driver IC, and the embodiments of the present application do not limit this. As shown in FIG. 6, the TCON is connected to a plurality of Source Driver ICs through independent signal lines, and the TCON and each Source Driver IC can adopt point-to-point signal transmission of data. In FIG. 9, the TCON sends data to the Source Driver IC through a signal line, which can be a differential signal line, and the Source Driver IC can return a lock signal (LOCK) to the TCON.

[0234] FIG. 10 is a schematic diagram of a hardware interface of a timing controller (TCON) according to an embodiment of the present application. As shown in FIG. 10, the TCON can include a television unified standard interface (USIT). The USIT interface of the TCON can be a differential output terminal, and the USIT interface and the Source Driver IC can be electrically connected through a differential signal line. For the display module shown in FIG. 5, the TCON can be connected to XD1-XD12 through 12 interfaces of USIT1P, USIT1N, …, USIT6P, USIT6N, respectively, and communicate with the Source Driver IC on the COF package through the USIT, so as to realize point-to-point signal transmission between the TCON and the Source Driver IC.

[0235] Optionally, in the direction away from the central axis, the timing control circuit sends the time difference of the differential signals to the two adjacent driving circuits is P bit widths, where P is a positive integer.

[0236] In some embodiments, the timing control circuit can send the differential signals to the plurality of driving circuits through clock offset. The timing control circuit can take the driving circuit located on the central axis, or the driving circuit located on both sides of the central axis and closest to the central axis, as the target driving circuit of the clock offset. The time difference of the differential signals sent by the timing control circuit to the two adjacent driving circuits can be the delay time difference between the first signals corresponding to the adjacent driving circuits, which is referred to as the clock offset in the embodiment. The clock offset is P bit widths, where P is a positive integer. The value range of P is 6UI-15UI.

[0237] Optionally, the timing control circuit sends the differential signals to the first circuit group at the fifth time, and the timing control circuit sends the differential signals to the second circuit group at the sixth time.

[0238] The time difference between the fifth and sixth time points is X bits wide, where X is a positive integer.

[0239] In some embodiments, when the timing control circuit sends differential signals to multiple driver circuits, it can set different clock offsets for the differential signals corresponding to different driver circuit groups, so that there is a time difference between the differential signals sent to different driver circuit groups. Specifically, the multiple driver circuits include a first circuit group and a second circuit group. It can delay only the first clock signal embedded in the differential signal corresponding to the first circuit group, or it can clock offset both the first and second circuit groups. However, after the delay, there is a time difference between the differential signals corresponding to the first and second circuit groups, and the time difference is X bits wide, where X is a positive integer. The value of X ranges from 5UI to 15UI.

[0240] In some embodiments, the multiple drive circuit groups may further include a third circuit group and a fourth circuit group. The timing control circuit can set different clock offsets for the first, second, third, and fourth circuit groups, resulting in a time difference between the differential signals sent by the timing control circuit to each drive circuit group. When the time required for different drive circuits to process the first signal to form the second signal is approximately equal, since there is a time difference between the differential signals (i.e., the first signals) sent by the timing control circuit to the first, second, third, and fourth circuit groups, there is also a time difference between the times when the display panel receives the first, second, third, and fourth signals. The time difference caused by the clock offset between adjacent delay sequence drive circuit groups can be equal or different; this application does not impose any limitation on this.

[0241] In some embodiments, the time at which the second signal is received at the display panel includes the first time, second time, third time, and fourth time corresponding to the first group of signals, the second group of signals, the third group of signals, and the fourth group of signals, respectively. Here, the first time difference is the time difference between the first time and the second time, the second time difference is the time difference between the second time and the third time, and the third time difference is the time difference between the third time and the fourth time.

[0242] Specifically, the first time difference, the second time difference and the third time difference are equal, which can be realized by equalizing the time difference between the differential signals sent by the time sequence control circuit to the adjacent driving circuit groups, which is caused by the time sequence control circuit setting different clock offsets for different driving circuit groups. For example, as shown in FIG. 11, the first circuit group is the driving circuit group d, the time sequence control circuit can set the clock offset corresponding to the driving circuit group d as 3 times of Δt, i.e. 15UI, and the second circuit group is the driving circuit group c, the time sequence control circuit can set the clock offset corresponding to the driving circuit group c as 2 times of Δt, i.e. 10UI, and the clock offset corresponding to the third circuit group, i.e. the driving circuit group b, is Δt = 5UI, and the clock offset corresponding to the fourth circuit group, i.e. the driving circuit group a, is 0. In this way, the time difference between the differential signals sent by the time sequence control circuit to the driving circuit groups a, b, c and d is 5UI.

[0243] Optionally, the number of the driving circuits is N;

[0244] N is an odd number, and the driving circuit located on the central axis is the first driving circuit to which the time sequence control circuit sends the differential signal,

[0245] Or, N is an even number, and the two driving circuits located on the two sides of the central axis and closest to the central axis are the first driving circuits to which the time sequence control circuit sends the differential signal.

[0246] In some embodiments, the target driving circuit can be the first driving circuit to which the time sequence control circuit sends the differential signal. The number of the target driving circuits can be one or two, which can be determined according to the total number of the driving circuits in the display module, as long as the number of the driving circuits on the two sides of the central axis of the display panel is equal, so that the driving circuits on the two sides of the central axis are symmetrically distributed.

[0247] Specifically, the number of the driving circuits is N, which can be an odd number or an even number. If N is an odd number, the driving circuit located on the central axis is the target driving circuit. If N is an even number, the two driving circuits located on the two sides of the central axis and closest to the central axis are the target driving circuits. For example, in the 12 driving circuits of the display module shown in FIG. 5, i.e. in the Source Driver IC, XD6 and XD7 located in the middle can be used as the target driving circuits.

[0248] Optionally, the driving circuit further comprises a plurality of signal lines; the display panel further comprises a plurality of data lines; and the plurality of signal lines are electrically connected with the data lines of the display panel to serve as channels for transmitting the source signals.

[0249] The time instants at which the signal lines in different driving circuits receive the source signals are different, and / or the time instants at which different signal lines in the driving circuit send the source signals to the connection lines are different.

[0250] In some embodiments, the signal line in the driving circuit can be a signal line inside the driving circuit connected to the output end of the driving circuit, used for outputting the source signal, and can serve as a signal transmission channel inside the driving circuit. The data line of the display panel can be a data line on the display panel for transmitting the source signal, and the data line can be electrically connected to the pixel circuit in the pixel array of the display panel, used for transmitting the source signal to the pixel circuit. The connection line in the display module is used to connect the signal line of the driving circuit and the data line of the display panel. For example, in the display module shown in FIG. 5, the wire connecting the Source Driver IC on the Chip on Film (COF) package to the display panel can be the connection line in the embodiments.

[0251] In some embodiments, the signal line, the connection line and the data line connected to each other in the display module form a channel for transmitting the source signal. The driving circuit includes a plurality of channels, which can be channels inside the driving circuit for transmitting the source signal, and each channel corresponds to a different serial number. The second signal sent by the driving circuit to the display panel includes the source signal transmitted by the driving circuit to the display panel through each channel.

[0252] In some embodiments, the timing control circuit configures parameters such as the delay duration and the signal slope of the driving circuits in the driving circuit group, so that the multiple driving circuits use the time-division transmission mode in the second sending process. The second signals sent by different driving circuits are respectively delayed, specifically, the source signals corresponding to the channels with the same serial number in the driving circuits of different driving circuit groups are respectively delayed. The second signals sent by different driving circuits are respectively delayed, which is manifested as that the delay time difference between the source signals corresponding to the channels with the same serial number in adjacent driving circuit groups is the second offset, i.e., the delay time difference between the target second signals is the second offset.

[0253] In some embodiments, in the first sending process, the timing control circuit can use the time-division transmission mode, so that different driving circuits receive the first signal at different times. The multiple driving circuits in the display module can use the same internal structure, so that the time for processing the first signal inside the driving circuit is approximately equal, and then the time required for the different driving circuits to generate the second signal is approximately equal. Since different driving circuits receive the first signal at different times, the time for the different driving circuits to send the source signal to the signal line inside is different, i.e., the time for the signal line to receive the source signal is different.

[0254] Optionally, the plurality of signal lines are arranged along a first direction;

[0255] The first target signal line is one of the plurality of signal lines, and the time at which the first target signal line sends the source signal is greater than the time at which other signal lines in the plurality of signal lines send the source signal.

[0256] In a direction away from the first target signal line, a time difference between adjacent signal lines for transmitting the source signal is S bit widths, S being a positive integer.

[0257] In some embodiments, the source signals transmitted by different signal lines in the driving circuit to the connection line are respectively delayed, different time delays can be set for channels of different orders in the driving circuit, so that the source signals output by different signal lines are transmitted at different times. The instantaneous energy of the driving circuit in the second transmission process can be reduced, thereby reducing the EMI noise caused by the second transmission process.

[0258] Specifically, the plurality of signal lines in the driving circuit are arranged along a first direction in which the driving circuit is arranged. The signal line with the maximum time delay in the driving circuit can be determined as the first target signal line. The first target signal line is used as a reference, and the first target signal line transmits the source signal at a time earlier than other signal lines. In a direction away from the first target signal line, a time difference between adjacent signal lines for transmitting the source signal can be a second offset in this embodiment, so that different time delays are set for the plurality of signal lines in the driving circuit. Specifically, the second offset is S bit widths, where S is a positive integer. Wherein, in the case that the delay time of the first target signal line is known, the delay time of the first target signal line divided by the number of signal lines obtains the second offset. Wherein, the product of the value of S and the number of signal lines, that is, the delay time of the first target signal line should be greater than or equal to 4UI and less than or equal to 16UI.

[0259] In some embodiments, the first configuration parameter embedded in the first signal sent by the timing control circuit to the driving circuit can include the first target signal line in the plurality of signal lines and the delay time of the first target signal line. After receiving the first configuration parameter, the driving circuit can determine the order of the delay time of the plurality of signal lines from short to long according to the first target signal line and the delay time of the first target signal line in the second transmission process, and sequentially transmit the source signal to the display panel through the corresponding signal line after the transmission time reaches the delay time. In this way, the source signals corresponding to the plurality of signal lines are transmitted at different times by the driving circuit in the second transmission process, which can reduce the instantaneous energy of the driving circuit in the second transmission process.

[0260] Optionally, the plurality of signal lines are sorted along the first direction.

[0261] The first target signal line is the signal line with the largest order in the plurality of signal lines, or the first target signal line is the signal line with the smallest order in the plurality of signal lines, or the first target signal line is the signal line with an intermediate order in the plurality of signal lines.

[0262] In some embodiments, the plurality of signal lines in the driving circuit can be arranged in a first direction, and each signal line corresponds to a serial number. The driving circuit can be provided with a third register for storing a channel delay mode and a fourth register for storing a channel delay duration. The first configuration parameter embedded in the first signal sent by the timing control circuit to the driving circuit can include the third register value and the fourth register value, i.e., the first configuration parameter includes the channel delay mode corresponding to the position of the first target signal line and the F-bit width corresponding to the delay duration of the first target signal line. After receiving the first configuration parameter, the driving circuit can write the third register value to the third register and the fourth register value to the fourth register.

[0263] In some embodiments, the channel delay mode includes at least three delay modes, i.e., a first delay mode, a second delay mode, and a third delay mode. As shown in FIG. 19, the first delay mode represents that the first target signal line is a signal line with a middle serial number, and corresponds to a V-shift channel delay mode, i.e., the delay duration corresponding to the signal line with the middle serial number is the longest. The second delay mode represents that the first target signal line is a signal line with a minimum serial number, and corresponds to a L-shift channel delay mode, i.e., the delay duration corresponding to the signal line with the minimum serial number is the longest. The third delay mode represents that the first target signal line is a signal line with a maximum serial number, and corresponds to a R-shift channel delay mode, i.e., the delay duration corresponding to the signal line with the maximum serial number is the longest.

[0264] Table 5: Third register configuration table

[0265] As shown in Table 5, the third register can include a DMS_SHIFT<1:0> register, which can store a 2-bit binary value representing an F-bit width. Different register values correspond to different channel delay modes, and the 2-bit binary value includes four results, i.e., V-shift, L-shift, and R-shift channel delay modes, and a default mode without setting channel delay. As shown in Table 5, when the DMS_SHIFT register value is set to 00, it is a V-shift channel delay mode, when the DMS_SHIFT register value is set to 01, it is a L-shift channel delay mode, when the DMS_SHIFT register value is set to 11, it is a R-shift channel delay mode, and when the DMS_SHIFT is set to 11, no channel delay is set.

[0266] Optionally, the first signal line in the plurality of signal lines that sends a source signal to the connection line is a second target signal line.

[0267] The time difference between the first target signal line and the second target signal line for sending a source signal is greater than zero and less than 16-bit width.

[0268] In some embodiments, the first signal line among the plurality of signal lines that sends the source signal to the connection line can be a second target signal line. By controlling the time difference between the first target signal line and the second target signal line in sending the source signal, the problem of picture segmentation in the display area driven by the plurality of signal lines of the driving circuit can be avoided.

[0269] In some embodiments, the time difference between the first target signal line and the second target signal line in sending the source signal can be greater than and less than 16 bit widths. As shown in Table 6, the fourth register can include a DMS_F1<1:0> register that can store a 2-bit binary value, and the 2-bit binary value can represent F bit widths. Different register values correspond to different channel delay durations. As shown in Table 6, when the DMS_F register value is set to 00, the delay duration is 4UI, when the DMS_F register value is set to 01, the delay duration is 8UI, when the DMS_F register value is set to 10, the delay duration is 12UI, and when the DMS_F register value is set to 11, the delay duration is 16UI.

[0270] Table 6: Configuration table of the fourth register

[0271] In some embodiments, the first sending process and the second sending process can both adopt a time-sharing sending mode, or a plurality of delay modes are combined in the second sending process, such as delaying the second signals sent by different driving circuits, and combining the delays of the source signals sent by different channels in the driving circuit. As long as the total delay duration of the first sending process and the second sending process is less than the panel delay duration. At the same time, the rationality of the panel delay duration should also be confirmed in combination with the actual picture display of the display panel to ensure that the display panel normally displays pictures.

[0272] In some embodiments, the first sending process and the second sending process can both adopt a time-sharing sending mode. In the first sending process, a plurality of first signals sent by the timing control circuit are delayed, and in the second sending process, the source signals sent by different signal lines in the driving circuit are delayed. For example, on the basis of delaying a plurality of first signals sent by the timing control circuit, as shown in FIG. 20, the channel delay mode of XD1-6 is set to L-SHIFT, and the channel delay mode of XD7-12 is set to R-SHIFT. The configurations of the DMS_SHIFT<1:0> and DMS_F1<1:0> registers are shown in Table 7.

[0273] Table 7: Configuration of the DMS_SHIFT<1:0> and DMS_F1<1:0> registers

[0274] Each XD corresponds to a plurality of signal lines in the driving circuit, which are divided into four zones, and the delay time of adjacent two zones is 8UI. For the signal lines of XD1-6 or the signal lines of XD7-12, the total delay time is 8UI*4*5=160UI.

[0275] For the display module shown in FIG. 5, without taking the EMI improvement measures, the EMI test result is shown in FIG. 21, and the EMI noise exceeds the EMI test requirement (40dB). After taking the improvement measures of adjusting the peak and valley values of the TCON signal in the related art, the EMI noise is still higher than 40dB near 600MHz as shown in FIG. 22. After taking the EMI improvement measures provided in the embodiment, the EMI noise is less than 40dB as shown in FIG. 23, which can meet the EMI test requirement. It should be noted that in FIGS. 21-23, the noise within 100MHZ is irrelevant to the display module. Therefore, the EMI improvement measures provided in the embodiment can be combined with each other and combined with the EMI improvement measures in the related art, and the effects of reducing the EMI noise of the display panel can be achieved.

[0276] The embodiment of the present application also provides a display driving method, as shown in FIG. 24, applied to the display module shown in the foregoing embodiments, and the display driving method comprises the following steps:

[0277] In step S1, a first sending process, a timing control circuit sends a first signal to a plurality of driving circuits according to the data of one frame of image; in the first sending process, the delay time difference between the first signals corresponding to adjacent driving circuits is a preset first offset, and / or the first signal corresponding to at least one driving circuit is embedded with a first configuration parameter; the first configuration parameter comprises a preset second offset;

[0278] In step S2, a second sending process, the driving circuit sends a source signal to the display panel according to the first signal; in the second sending process, the delay time difference between the source signals of at least one driving circuit is the second offset; the source signal comprises a source signal corresponding to a plurality of channels in the driving circuit; at least one of the first offset and the second offset is not zero, so that the first time at which the display panel receives the first group of signals is greater than the second time at which the display panel receives the second group of signals;

[0279] The second signal comprises the first group of signals and the second group of signals, the first group of signals is the second signal sent by a first circuit group in the plurality of driving circuits to the display panel, and the second group of signals is the second signal sent by a second circuit group in the plurality of driving circuits to the display panel.

[0280] In some embodiments, the delaying of the plurality of first signals can be achieved by clock offset. In the present embodiment, the time difference between the first signals corresponding to the adjacent driving circuits is referred to as clock offset. The first signal is embedded with a first clock signal, and the time difference between the first signals refers to the time difference between the first clock signals. Before the first sending process, the clock offset is preset as a first offset in the timing control circuit, and the first offset is not zero. In the first sending process, the timing control circuit can determine the sending time of each first signal according to the preset first offset, and send the first signal to the corresponding driving circuit after the sending time is reached.

[0281] In this way, for one frame of image, the timing control circuit obtains the first signal corresponding to each driving circuit according to the data of one frame of image, and then sends the plurality of first signals to the driving circuit in time division, so that the first sending process reduces the instantaneous energy, and the effect of reducing EMI noise can be achieved.

[0282] Optionally, the step S1 comprises the following sub-steps:

[0283] Sub-step A1, the timing control circuit sends the corresponding first signal to the target driving circuit;

[0284] Sub-step A2, the timing control circuit sends the corresponding first signal to the adjacent driving circuit in turn according to the first offset based on the target driving circuit, wherein the first offset represents the clock offset of the first signal received by the adjacent driving circuit.

[0285] In some embodiments, the target driving circuit is the reference for the clock offset of the timing control circuit. In the first sending process, the timing control circuit can send the corresponding first signal to the target driving circuit, and then determine the data sending time of the adjacent driving circuit according to the first offset based on the data sending time of the target driving circuit. The corresponding first signal is sent to the driving circuit after the data sending time is reached. In this way, the corresponding first signal is sent to the adjacent driving circuit in turn, so that the first signal is sent to the plurality of driving circuits in time division in the first sending process.

[0286] For example, as shown in FIG. 25, the Source Driver ICs XD6 and XD7 on the COF package in the middle of the 12 drive circuits of the display module shown in FIG. 5 are taken as the target drive circuits. The delay time of the first signal corresponding to the target drive circuits is zero. The drive circuits adjacent to the target drive circuits include the Source Driver ICs XD5 and XD8. The delay time difference between the first signals corresponding to the Source Driver ICs XD8 and XD7 is 6UI, that is, the first skew is 6UI. As shown in FIG. 25, the total delay time of the timing control circuit in the first sending process is 30UI, that is, the delay time corresponding to XD1 and XD12 respectively. As shown in FIG. 25, the number of Source Driver ICs is even, and the delay time of different Source Driver ICs is symmetrically arranged in the display module. In the case where the first skew is known, the total delay time corresponding to the TCON can be calculated according to the following formula (7).

[0287] Wherein, Tskew sum represents the total delay time, and Tskew represents the first skew.

[0288] For the timing controller shown in FIG. 10, FIG. 26 shows the clock skew (Tskew) between the adjacent differential pairs of signals output by the adjacent USIT interfaces USIT0 and USIT1. FIG. 27 shows the first signals sent by the timing control circuit to the adjacent drive circuits. The two first signals respectively embed a first clock signal. The first clock signal can be the training clock signal shown in FIG. 6. As shown in FIG. 27, the first clock signals corresponding to the adjacent drive circuits are obviously misaligned. The delay time difference between the two first clock signals is the first skew.

[0289] Compared with the measure of improving EMI by using a spread spectrum clock generator in the related art, the clock skew method is not limited by device specifications and has stronger universality.

[0290] Optionally, the step S1 includes the following sub-steps:

[0291] In sub-step A3, the timing control circuit sends the first signal embedding the first configuration parameter to at least one drive circuit, and sends the first signal embedding the second configuration parameter to other drive circuits. The signal waveform of the first signal embedding the first configuration parameter is different from the signal waveform of the first signal embedding the second configuration parameter. The first signal embedding the second configuration parameter is used to control other drive circuits to send the second signal to the display panel at the same time.

[0292] Optionally, before step S2, the display driving method further includes:

[0293] In step S3, the driving circuit stores the second offset in response to the first signal in which the first configuration parameter is embedded; wherein the first configuration parameter comprises the second offset.

[0294] Step S2 comprises the following sub-steps:

[0295] In sub-step B1, the driving circuit delays sending the second signal to the display panel, wherein the time difference between the rising edges of the target second signals in adjacent driving circuits is the second offset, and the target second signal comprises the source signals corresponding to the channels with the same serial number in the plurality of driving circuits.

[0296] In some embodiments, after the second signals sent by different driving circuits are respectively delayed, the source signals corresponding to the channels with the same serial number in different driving circuits have a time delay difference, and the time delay difference is the second offset preset in the first configuration parameter. At this time, the second offset is not zero, indicating that the second sending process corresponding to the plurality of driving circuits adopts a time-division sending mode.

[0297] Step S2 comprises the following sub-steps:

[0298] In sub-step B2, the driving circuit sends the second signal to the driving circuit according to the preset rising edge length, wherein the time difference between the rising edges of the target second signals in adjacent driving circuits is the second offset, and the target second signal comprises the source signals corresponding to the channels with the same serial number in the plurality of driving circuits.

[0299] Step S2 comprises the following sub-steps:

[0300] In sub-step B3, the driving circuit sequentially sends the source signals to the display panel through the plurality of channels in the order from short to long delay length, wherein the time delay difference between the source signals corresponding to adjacent serial numbers of channels is the third offset, and the sum of the third offsets corresponding to the plurality of channels is equal to the second offset.

[0301] In the embodiments of the present application, the driving circuit can obtain the image data, i.e., the second signal, from the first signal under the control of the control instruction embedded in the first signal, and send the second signal to the display panel according to the data sending mode indicated by the control instruction, so as to drive the display panel to display the image through the second signal. The control instruction embedded in the first signal can be the first configuration parameter or the second configuration parameter. The first configuration parameter is used to control the driving circuit to send the second signal to the display panel in a time-division manner in the second sending process, and the second configuration parameter is used to control the driving circuit to send the second signal to the display panel in a synchronous manner in the second sending process.

[0302] Specifically, for the driving circuit adopting the time-division transmission mode, the timing control circuit can embed the first configuration parameter in the first signal, and control the driving circuit to transmit the source signal to the display panel in a time-division manner through the first configuration parameter. For the driving circuit adopting the synchronous transmission mode, the timing control circuit can embed the second configuration parameter in the first signal, and control the driving circuit to transmit the source signal to the display panel in a synchronous manner through the second configuration parameter.

[0303] In some embodiments, the first configuration parameter and the second configuration parameter have different instructions due to different functions, and the instructions are different in signal waveforms. Even if the first configuration parameters are different, if the delay modes corresponding to the first configuration parameters are different, the instructions are different, and the signal waveforms are different. For example, the first configuration parameter and the second configuration parameter include different configuration parameters, and the configuration parameters are used to configure the registers in the driving circuit. As shown in the configuration signal waveform in FIG. 6, the signal waveforms of the first configuration parameter and the second configuration parameter are different in signal amplitude, frequency, or phase.

[0304] In the embodiments of the present application, the instantaneous energy of the second transmission process is reduced, thereby reducing the EMI noise caused by the second transmission process. Compared with the EMI improvement mode of scrambling and descrambling in the related art, the mode of controlling at least one driving circuit to transmit the source signal in a time-division manner by the timing control circuit does not need to set additional scrambling and descrambling circuits, the complexity of the data transmission process is low, the risk of display panel image abnormality can be avoided, and the safety is high.

[0305] Optionally, the step S1 includes the following sub-steps:

[0306] In a case where the sum of the first delay duration and the second delay duration is less than a preset panel delay duration, the timing control circuit transmits the first signal to the plurality of driving circuits according to the data of one frame of image, wherein the first delay duration is the total delay duration corresponding to the timing control circuit, the second delay duration is the total delay duration corresponding to the plurality of driving circuits, and the panel delay duration represents a delay duration threshold for normally displaying one frame of image by the display panel.

[0307] In the embodiments of the present application, the panel delay duration represents a delay duration threshold for the display panel to normally display one frame of image, for example, the △T=0.25us calculated according to Table 2 in the foregoing embodiments, or the △UI=325UI after conversion. The first delay duration is the total delay duration corresponding to the timing control circuit, that is, the total delay duration of the plurality of first signals in the first sending process. The second delay duration is the total delay duration corresponding to the plurality of driving circuits, that is, the total delay duration of the plurality of second signals in the second sending process. The sum of the first delay duration and the second delay duration should be less than the preset panel delay duration, so that the display panel has sufficient charging time, thereby ensuring that the display panel normally displays one frame of image, and the abnormal phenomenon of the display panel can be avoided.

[0308] FIG. 28 is a flowchart of a display driving method according to an embodiment of the present application. As shown in FIG. 28, for any display module, the parameters of the display module are substituted into formula (1) to calculate the charging time, and then the panel delay duration is calculated according to the charging time. The plurality of driving circuits are grouped to obtain a plurality of driving circuit groups, and the time division sending mode is adopted for at least one of the first sending process and the second sending process, so as to drive the display panel to display one frame of image. In actual application, the data sending mode of the first sending process and the second sending process can be adjusted by checking the display panel quality, so as to ensure that the display panel normally displays one frame of image.

[0309] Compared with the current improvement measures, the display module and the display driving method provided by the embodiments of the present application are not limited by the specifications of the timing control circuit and the driving circuit, and are only related to the data sending mode adopted by the timing control circuit and the driving circuit, without changing the signal peak and valley values, so as not to affect the signal quality, and without the disturbance and recovery process, so as to improve the EMI effect of the display module without affecting the display effect of the display module.

[0310] Each of the embodiments in the present specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0311] Each of the embodiments in the present specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0312] Although the preferred embodiments of the present application have been described, those skilled in the art can make other changes and modifications to the embodiments once they know the basic creative concept. Therefore, the appended claims are intended to include the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present application.

[0313] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. is used by way of example, and is merely used to distinguish one from another entity or action without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0314] The display module and the display driving method provided by the present application are described in detail above, and the principles and implementation manners of the present application are described by using specific examples in the present text. The above description of the examples is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will all have changes, and the above description of the content of the present specification should not be understood as a limitation on the present application.

Claims

1. A display module, wherein, The display module comprises a time sequence control circuit, a plurality of drive circuits and a display panel connected in sequence; an input end of the drive circuit is electrically connected with an output end of the time sequence control circuit, and the time sequence control circuit is configured to identify a first signal sent to the drive circuit and control a time sequence of the first signal; an output end of the drive circuit is electrically connected with an input end of the display panel, and the drive circuit is configured to receive and process the first signal to form a second signal input to the display panel; the plurality of drive circuits are arranged in an array along a first direction, and the plurality of drive circuits are symmetrically distributed about a central axis of the display panel, the central axis extending along a second direction, the first direction being orthogonal to the second direction; the plurality of drive circuits comprise a first circuit group and a second circuit group, the first circuit group comprising a first drive circuit and a second drive circuit, and the second circuit group being arranged between the first drive circuit and the second drive circuit; the second signal comprises a first group of signals and a second group of signals, the first group of signals being the second signal sent by the first circuit group to the display panel, and the second group of signals being the second signal sent by the second circuit group to the display panel, wherein a time when the display panel receives the first group of signals is a first time, and a time when the display panel receives the second group of signals is a second time, the first time being greater than the second time.

2. The display module of claim 1, wherein, the first time and the second time have a first time difference; the first time difference is greater than or equal to 5 bit widths, and the first time difference is less than or equal to 15 bit widths.

3. The display module of claim 1, wherein, the first group of signals has a first slew rate, and the second group of signals has a second slew rate; the first slew rate is less than the second slew rate.

4. The display module of claim 1, wherein, a rising edge time length of the first group of signals from a first level to a second level is a first time length, and a rising edge time length of the second group of signals from the first level to the second level is a second time length, wherein the second level is greater than the first level; the first time length is greater than the second time length.

5. The display module of claim 4, wherein, a difference between the first time length and the second time length is greater than zero and less than 4 bit widths.

6. The display module of claim 1, wherein, a rising edge and a falling edge of the first group of signals have a first time length, and a rising edge and a falling edge of the second group of signals have a second time length, wherein the first time length is less than the second time length.

7. The display module of any one of claims 1-6, wherein, the second circuit group comprises a third drive circuit and a fourth drive circuit, and the plurality of drive circuit groups further comprise a third circuit group; a part of the third circuit group is located between the first drive circuit and the third drive circuit, and another part of the third circuit group is located between the second drive circuit and the fourth drive circuit; the second signal further comprises a third group of signals, the third group of signals being the second signal sent by the third circuit group to the display panel, and a time when the display panel receives the third group of signals being a third time, the third time being less than the second time.

8. The display module of claim 7, wherein, the third circuit group comprises a fifth drive circuit and a sixth drive circuit, and the plurality of drive circuit groups further comprise a fourth circuit group; Part of the fourth circuit group is located between the fifth driving circuit and the third driving circuit, and another part of the fourth circuit group is located between the sixth driving circuit and the fourth driving circuit; The second signal further includes a fourth group of signals, the fourth group of signals being the second signal sent by the fourth circuit group to the display panel, and the display panel receives the fourth group of signals at a fourth time point, which is less than the third time point.

9. The display module of claim 8, wherein, The fourth circuit group includes a seventh driving circuit and an eighth driving circuit, and the third circuit group further includes a ninth driving circuit and a tenth driving circuit, wherein the ninth driving circuit is located between the third driving circuit and the seventh driving circuit, the tenth driving circuit is located between the fourth driving circuit and the eighth driving circuit, the ninth driving circuit and the fifth driving circuit are symmetrical about the seventh driving circuit, the sixth driving circuit and the tenth driving circuit are symmetrical about the eighth driving circuit, and / or, The second circuit group further includes an eleventh driving circuit and a twelfth driving circuit, wherein the eleventh driving circuit is located between the first driving circuit and the seventh driving circuit, and the twelfth driving circuit is located between the second driving circuit and the eighth driving circuit, the eleventh driving circuit and the third driving circuit are symmetrical about the seventh driving circuit, and the twelfth driving circuit and the fourth driving circuit are symmetrical about the eighth driving circuit.

10. The display module of claim 8, wherein, The first time difference is the time difference between the first time point and the second time point, the second time difference is the time difference between the second time point and the third time point, and the third time difference is the time difference between the third time point and the fourth time point; The first time difference, the second time difference and the third time difference are equal; and / or, The third group of signals has a third slew rate, the fourth group of signals has a fourth slew rate, the first slew rate is less than the second slew rate, the second slew rate is less than the third slew rate, and the third slew rate is less than the fourth slew rate.

11. The display module of any one of claims 1-6, wherein, The display module further includes a plurality of differential signal lines; One end of the differential signal line is electrically connected to one output end of the timing control circuit, and the other end of the differential signal line is electrically connected to the input end of the driving circuit; The first signal is a differential signal sent by the timing control circuit to the driving circuit, and the timing control circuit sends the differential signal to the plurality of driving circuits at different time points.

12. The display module of claim 11, wherein, In the direction away from the central axis, the time difference between the timing control circuit sending the differential signal to two adjacent driving circuits is P bit widths, where P is a positive integer.

13. The display module of claim 11, wherein, The timing control circuit sends the differential signal to the first circuit group at a fifth time point, and sends the differential signal to the second circuit group at a sixth time point; The time difference between the fifth time point and the sixth time point is X bit widths, where X is a positive integer.

14. The display module of claim 11, wherein, The number of driving circuits is N. N is an odd number, and the driving circuit located on the middle axis is the driving circuit that first sends the differential signal by the timing control circuit, Or, N is an even number, and the two driving circuits located on both sides of the middle axis and closest to the middle axis are the driving circuits that first send the differential signal by the timing control circuit.

15. The display module of any one of claims 1-6, wherein, The driving circuit that first sends the second signal to the display panel in the plurality of driving circuits is a target driving circuit, and the target driving circuit belongs to the second circuit group; The time when the display panel receives the second signal sent by the target driving circuit is a target time, and the time difference between the first time and the target time is greater than or equal to 15 bit widths and less than 325 bit widths; The time difference between the second time and the target time is greater than or equal to 0 and less than 15 bit widths.

16. The display module of any one of claims 1-6, wherein, The driving circuit further comprises a plurality of signal lines; the display panel further comprises a plurality of data lines; the plurality of signal lines are electrically connected with the data lines of the display panel to serve as channels for transmitting source signals; The time when the signal lines in different driving circuits receive the source signals is different, and / or the time when the signal lines in different driving circuits send the source signals is different.

17. The display module of claim 16, wherein, The plurality of signal lines are arranged along the first direction; The first target signal line is one of the plurality of signal lines, and the time when the first target signal line sends the source signal is greater than the time when other signal lines in the plurality of signal lines send the source signal; In the direction away from the first target signal line, the time difference between adjacent signal lines in sending the source signal is S bit widths, and S is a positive integer.

18. The display module of claim 17, wherein, The plurality of signal lines are sorted along the first direction; The first target signal line is the signal line with the largest serial number in the plurality of signal lines, or the first target signal line is the signal line with the smallest serial number in the plurality of signal lines, or the first target signal line is the signal line with an intermediate serial number in the plurality of signal lines.

19. The display module of claim 17, wherein, The first signal line in the plurality of signal lines that sends the source signal to the connecting line is a second target signal line; The time difference between the first target signal line and the second target signal line in sending the source signal is greater than 0 and less than 16 bit widths.

20. The display module of claim 1, wherein, The charging duration of the display module is greater than or equal to 1.6 microseconds.

21. A display driving method, wherein, The method is applied to the display module as claimed in any one of claims 1-20, and the method comprises: A first sending process, in which a timing control circuit sends first signals to a plurality of driving circuits according to the data of one frame of image, wherein in the first sending process, the delay time difference between the first signals corresponding to adjacent driving circuits is a preset first offset, and / or the first signal corresponding to at least one driving circuit comprises a preset second offset; A second sending process, in which the driving circuit sends second signals to a display panel according to the first signals, wherein in the second sending process, the delay time difference between the source signals of at least one driving circuit is the second offset. The second signal includes the source signals corresponding to the plurality of channels in the driving circuit, and at least one of the first offset and the second offset is not zero, so that a first time at which the display panel receives a first group of signals is greater than a second time at which the display panel receives a second group of signals. The second signal includes the first group of signals and the second group of signals, the first group of signals being the second signal sent by a first group of circuits in the plurality of driving circuits to the display panel, and the second group of signals being the second signal sent by a second group of circuits in the plurality of driving circuits to the display panel.

22. The display driving method according to claim 21, wherein The timing control circuit sends a first signal to a plurality of driving circuits according to data of a frame of image, including: The timing control circuit sends the first signal to a target driving circuit; The timing control circuit sends the first signal to adjacent driving circuits in sequence according to a first offset, taking the target driving circuit as a reference, wherein the first offset represents a clock offset of the first signal received by the adjacent driving circuits.

23. The display driving method according to claim 21, wherein The timing control circuit sends a first signal to a plurality of driving circuits according to data of a frame of image, including: The timing control circuit sends the first signal with embedded first configuration parameters to at least one of the driving circuits, and sends the first signal with embedded second configuration parameters to other driving circuits; Wherein, the signal waveform of the first signal with embedded first configuration parameters is different from the signal waveform of the first signal with embedded second configuration parameters, and the first signal with embedded second configuration parameters is used to control other driving circuits to send the second signal to the display panel at the same time.

24. The display driving method according to any one of claims 21-23, wherein, Before the second sending process, the method further includes: The driving circuit stores the second offset in response to the first signal with embedded first configuration parameters, wherein the first configuration parameters include the second offset; The driving circuit sends a second signal to the display panel according to the first signal, including: The driving circuit delays sending the second signal to the display panel, wherein the delay time difference between the signal rising edges of target second signals in adjacent driving circuits is the second offset, and the target second signal includes source signals corresponding to channels with the same serial number in the plurality of driving circuits.

25. The display driving method according to any one of claims 21-23, wherein, Before the second sending process, the method further includes: The driving circuit stores the second offset in response to the first signal with embedded first configuration parameters, wherein the first configuration parameters include the second offset; The driving circuit sends a second signal to the display panel according to the first signal, including: The driving circuit sends the second signal to the driving circuit according to a preset rising edge duration, wherein the rising edge duration difference between target second signals in adjacent driving circuits is the second offset, and the target second signal includes source signals corresponding to channels with the same serial number in the plurality of driving circuits.

26. The display driving method according to any one of claims 21-23, wherein Before the second sending process, the method further includes: The driving circuit stores the second offset in response to the first signal in response to a first configuration parameter embedded, wherein the first configuration parameter comprises the second offset; The driving circuit sends a second signal to the display panel according to the first signal, comprising: The driving circuit sequentially sends the source signals to the display panel through the plurality of channels in order of delay duration from short to long, wherein the delay time difference between the source signals corresponding to adjacent sequence numbers of channels is a third offset, and the sum of the third offsets corresponding to the plurality of channels is equal to the second offset.

27. The display driving method according to claim 21, wherein The timing control circuit sends a first signal to a plurality of driving circuits according to the data of a frame image, comprising: In the case that the sum of the first delay duration and the second delay duration is less than the preset panel delay duration, the timing control circuit sends a first signal to a plurality of driving circuits according to the data of a frame image is executed. The first delay duration is the total delay duration corresponding to the timing control circuit, the second delay duration is the total delay duration corresponding to the plurality of driving circuits, and the panel delay duration represents a delay duration threshold for driving the display panel to normally display the frame image.

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