A method for testbench replication of an assertion counterexample in hierarchical c++ high level synthesis designs

The method provides a gcc compiled executable with a gdb debugger and a pre-populated database to replicate counterexample behavior in hierarchical C++ designs, addressing inefficiencies in debugging assertion counterexamples and ensuring accurate logic sequence replication.

WO2026062412A1PCT designated stage Publication Date: 2026-03-26SIEMENS INDUSTRY SOFTWARE INC
View PDF 0 Cites 0 Cited by

Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Filing Date
2024-09-20
Publication Date
2026-03-26

AI Technical Summary

Technical Problem

Existing methods for debugging assertion counterexamples in hierarchical C++ high level synthesis designs are inefficient and cumbersome, particularly when using traditional gcc compilers and gdb debuggers, as they fail to replicate the concurrent execution semantics of hierarchical designs, leading to ineffective debugging of large and complex designs.

Method used

A method involving a gcc compiled executable with a gdb based debugger, which creates a pre-populated database with ac_channel operation data values from the counterexample, allowing serial execution to replicate the counterexample behavior and facilitate effective debugging of falsified assertions in hierarchical C++ designs.

Benefits of technology

Enables efficient replication and debugging of assertion counterexamples in hierarchical C++ designs, overcoming scalability issues and ensuring accurate replication of logic sequences that generate falsified assertions, thereby improving the debugging process.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure IB2024059135_26032026_PF_FP_ABST
    Figure IB2024059135_26032026_PF_FP_ABST
Patent Text Reader

Abstract

The present invention discloses a method and a system for testbench replication of an assertion counterexample in hierarchical C++ high level synthesis designs, comprising: - defining a high level synthesis (HLS) design for an integrated chip wherein the design of the integrated chip is programmed as a C++ hierarchical design; - verifying the HLS design and reporting inline assertions that are added via calls to an assert function of the high level synthesis design; - using a high level verification engine to debug a falsified assertion thereby providing an executable of the C++ hierarchical design that is built with a gcc compiler along with a gdb based debugger and that is used for the replication of a counterexample to remedy the falsified assertation which is referred to as testbench; - using the counterexample of the high level verification engine to drive the debugging of the falsified assertion with input values of the counterexample that will address the debugging at ac_channel operation level; - creating a database within the testbench being pre-populated with every ac_channel's read / nb_read operations data value being calculated in the counterexample that exist in cone of the falsified property where a falsified assertion has been generated for; - during the execution of the testbench when a read / nb_read operation of an internal ac_channel is performed using the pre-populated ac_channel's read / nb_read operations data value as input value for performing a read / nb_read operation during the debugging of the falsified assertion.
Need to check novelty before this filing date? Find Prior Art