Display device

Abstract

A display device is provided. The display device comprises: a substrate; a pixel electrode disposed on the substrate; a first type light-emitting element disposed on the pixel electrode and having a contact electrode connected to the pixel electrode; a second type light-emitting element disposed on the pixel electrode and having a non-contact electrode; a filling layer filled between the first type light-emitting element and the second type light-emitting element; a connection electrode connecting the first type light-emitting element and the second type light-emitting element in series; and a common electrode disposed on the first type light-emitting element and the second type light-emitting element and electrically connected to the second type light-emitting element.

Description

display device

[0001] The present invention relates to a display device.

[0002] The importance of display devices is increasing along with the development of multimedia. In response to this, various types of display devices, such as Organic Light Emitting Diode Displays (OLEDs) and Liquid Crystal Displays (LCDs), are being used.

[0003] A device for displaying images of a display device includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. Among these, as a light-emitting display panel, it may include a light-emitting element; for example, in the case of a light-emitting diode (LED), there are organic light-emitting diodes (OLEDs) that use organic materials as light-emitting materials, and inorganic light-emitting diodes that use inorganic materials as light-emitting materials.

[0004] The problem that the present invention aims to solve is to provide a display device capable of reducing power consumption by connecting light-emitting elements in series.

[0005] In addition, the invention provides a display device that can sufficiently secure the width of the active layer of series-connected light-emitting elements and reduce or minimize the number of process steps.

[0006] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.

[0007] A display device according to one embodiment for solving the above problem may include a substrate, a pixel electrode disposed on the substrate, a first type light-emitting element having a contact electrode disposed on the pixel electrode and connected to the pixel electrode, a second type light-emitting element having a non-contact electrode disposed on the pixel electrode, a filling layer filled between the first type light-emitting element and the second type light-emitting element, a connect electrode connecting the first type light-emitting element and the second type light-emitting element in series, and a common electrode disposed on the first type light-emitting element and the second type light-emitting element and electrically connected to the second type light-emitting element.

[0008] The first type light-emitting element and the second type light-emitting element each include a first semiconductor layer, an active layer, and a second semiconductor layer, and the second semiconductor layer of the first type light-emitting element is divided into a first portion having a first thickness and a second portion having a second thickness thinner than the first thickness, and the active layer and the first semiconductor layer of the first type light-emitting element can overlap with the first portion.

[0009] The above-mentioned first type light-emitting element is

[0010] A protective layer further comprising, in a planar view, surrounding the sides of the first semiconductor layer, active layer, and second semiconductor layer of the first type light-emitting element, defining a first opening that exposes the first semiconductor layer of the first type light-emitting element, and defining a second opening that exposes the second semiconductor layer of the first type light-emitting element in the second portion.

[0011] The second type light-emitting element may further include a protective layer that surrounds the sides of the first semiconductor layer, active layer, and second semiconductor layer of the second type light-emitting element in a planar view, and defines a third opening that exposes the first semiconductor layer of the second type light-emitting element.

[0012] The above contact electrode is electrically connected to the first semiconductor layer through the first opening, and the above connect electrode can electrically connect the second semiconductor layer of the first type light-emitting element and the first semiconductor layer of the second type light-emitting element through the second opening and the third opening.

[0013] The contact electrode and the non-contact electrode can be formed at the same height.

[0014] The above display device may further include an organic layer that covers both the first type light-emitting element and the second type light-emitting element and defines a fourth opening that exposes the second semiconductor layer of the second type light-emitting element.

[0015] The above common electrode is electrically connected to the second semiconductor layer of the second type light-emitting element exposed through the fourth opening, and may overlap with the first type light-emitting element in the thickness direction but be spaced apart. The width of the active layer of the first type light-emitting element may be the same as the width of the active layer of the second type light-emitting element.

[0016] The above non-contact electrode can be placed on a protective layer disposed on one surface of the above second type light-emitting element.

[0017] The above-mentioned charging layer includes an insulating material, and the surface of the charging layer may include a light-reflecting surface or a light-absorbing surface.

[0018] The first type light-emitting element and the second type light-emitting element may include a reflective layer that surrounds at least a portion of their sides on a plane.

[0019] The upper portions of the first type light-emitting element and the second type light-emitting element may include a concave light extraction pattern having a shape of a hemisphere or a semi-elliptical sphere.

[0020] The above common electrode can come into contact with the concave light extraction pattern of the second type light-emitting element.

[0021] A display device according to one embodiment comprises a substrate, a first pixel electrode and a second pixel electrode spaced apart from each other and disposed on the substrate, a first type light-emitting element having a contact electrode disposed on the first pixel electrode and electrically connected to the pixel electrode, a bonding electrode disposed between the first pixel electrode and the contact electrode, a second type light-emitting element disposed on the second pixel electrode, a filling layer filled between the first type light-emitting element and the second type light-emitting element, a connect electrode serially connecting the first type light-emitting element and the second type light-emitting element, and a common electrode disposed on the first type light-emitting element and the second type light-emitting element and electrically connected to the second type light-emitting element, wherein the height of the second pixel electrode may be equal to the sum of the height of the first pixel electrode, the height of the bonding electrode, and the height of the contact electrode.

[0022] The first type light-emitting element and the second type light-emitting element each include a first semiconductor layer, an active layer, and a second semiconductor layer, and the second semiconductor layer of the first type light-emitting element is divided into a first portion having a first thickness and a second portion having a second thickness thinner than the first thickness, and the active layer and the first semiconductor layer of the first type light-emitting element can overlap with the first portion.

[0023] The above contact electrode is electrically connected to the first semiconductor layer of the first type light-emitting element, and the above connect electrode can connect the second semiconductor layer of the second part of the first type light-emitting element and the first semiconductor layer of the second type light-emitting element.

[0024] The above display device further includes an organic layer having an opening that covers both the first type light-emitting element and the second type light-emitting element and exposes the second semiconductor layer of the second type light-emitting element, and the common electrode is connected to the second semiconductor layer of the second type light-emitting element and may overlap with the first type light-emitting element in the thickness direction but may not be connected.

[0025] The width of the active layer of the first type light-emitting element may be the same as the width of the active layer of the second type light-emitting element.

[0026] The above-mentioned charging layer includes an insulating material, and the surface of the charging layer may be a light-reflecting surface or a light-absorbing surface.

[0027] An electronic device comprising a display device according to one embodiment, wherein the display device comprises a substrate, a first pixel electrode and a second pixel electrode spaced apart from each other and disposed on the substrate, a first type light-emitting element having a contact electrode disposed on the first pixel electrode and electrically connected to the pixel electrode, a bonding electrode disposed between the first pixel electrode and the contact electrode, a second type light-emitting element disposed on the second pixel electrode, a filling layer filled between the first type light-emitting element and the second type light-emitting element, a connect electrode serially connecting the first type light-emitting element and the second type light-emitting element, and a common electrode disposed on the first type light-emitting element and the second type light-emitting element and electrically connected to the second type light-emitting element, wherein the height of the second pixel electrode may be equal to the sum of the height of the first pixel electrode, the height of the bonding electrode, and the height of the contact electrode.

[0028] Specific details of other embodiments are included in the detailed description and drawings.

[0029] According to the display device and the method of manufacturing the same according to the embodiments, power consumption can be reduced by connecting light-emitting elements in series.

[0030] In addition, the width of the active layer of the series-connected light-emitting elements can be sufficiently secured, and the number of process steps can be minimized.

[0031] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification.

[0032] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0033] FIG. 2 is a layout diagram showing a display device according to one embodiment.

[0034] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0035] FIG. 4 is an equivalent circuit diagram showing a subpixel according to one embodiment.

[0036] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0037] FIG. 6 is a cross-sectional view showing an example of a cross-section of a display panel cut along the line I1-I1' of FIG. 5.

[0038] Figure 7 is a cross-sectional view showing in detail an example of area A of Figure 6.

[0039] Figure 8 is a cross-sectional view showing another example of area A of Figure 7 in detail.

[0040] FIG. 9 is a cross-sectional view showing in detail an example of area A of FIG. 6 according to another embodiment.

[0041] FIG. 10 is a cross-sectional view showing in detail an example of area A of FIG. 6 according to another embodiment.

[0042] FIG. 11 is a cross-sectional view showing in detail an example of area A of FIG. 6 according to another embodiment.

[0043] FIG. 12 is a flowchart showing a method for manufacturing a display device according to one embodiment.

[0044] FIGS. 13 to 25 are drawings for explaining a method of manufacturing a display device according to one embodiment.

[0045] FIG. 26 is an example drawing showing a smart watch including a display device according to one embodiment.

[0046] FIGS. 27 and FIGS. 28 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0047] FIG. 29 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment.

[0048] FIG. 30 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment.

[0049] FIG. 31 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0050] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0051] Elements or layers referred to as "on" another element or layer include cases where another layer or element is interposed directly above or in the middle of another element. Likewise, "below," "left," and "right" refer to cases where they are interposed immediately adjacent to another element or where another layer or material is interposed in the middle. Throughout the specification, the same reference numerals refer to the same components.

[0052] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0053] Hereinafter, embodiments will be described with reference to the attached drawings.

[0054] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0055] Referring to FIG. 1, the display device (10) is a device for displaying video or still images and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0056] The display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). Hereinafter, the display device (10) has been described with a focus on being a micro light-emitting display device, but the present invention is not limited thereto. Meanwhile, for convenience of explanation, a micro light-emitting diode has been described as a light-emitting element below.

[0057] The display device (10) includes a display panel (100), a display driving circuit (250), a circuit board (300), and a power supply circuit (500).

[0058] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) that intersects the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display panel (100) is not limited to a rectangle and may be formed as other polygons, circles, or ellipses. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include curved surfaces formed at the left and right ends that have a constant curvature or a changing curvature. In addition, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0059] The substrate (SUB) of the display panel (100) may include a main area (MA) and a sub area (SBA).

[0060] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) which is a surrounding area of ​​the display area (DA). The display area (DA) may include a plurality of pixels that display an image. Each of the pixels may include a plurality of subpixels. For example, each of the pixels may include a first subpixel emitting light of a first color, a second subpixel emitting light of a second color, and a third subpixel emitting light of a third color, but the embodiments of the present specification are not limited thereto.

[0061] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). Although FIG. 1 illustrates a sub-region (SBA) unfolded, the sub-region (SBA) may be bent, in which case it may be placed on the lower surface of the display panel (100). When the sub-region (SBA) is bent, it may overlap with the main region (MA) in a third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (250) may be placed in the sub-region (SBA).

[0062] The display driving circuit (250) can generate signals and voltages to drive the display panel (100). The display driving circuit (250) may be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. As an example, the display driving circuit (250) may be attached to the circuit board (300) using a COF (chip on film) method.

[0063] A circuit board (300) can be attached to one end of a sub-region (SBA) of a display panel (100). As a result, the circuit board (300) can be electrically connected to the display panel (100) and the display driving circuit (250). The display panel (100) and the display driving circuit (250) can receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0064] The power supply circuit (500) can generate multiple panel driving voltages according to the power supply voltage from an external source. The power supply circuit (500) can be formed as an integrated circuit (IC) and attached to the circuit board (300) in a COF manner.

[0065] FIG. 2 is a layout diagram showing a display device according to one embodiment. FIG. 2 illustrates a sub-region (SBA) that is unfolded without being bent.

[0066] Referring to FIG. 2, the display panel (100) may include a main area (MA) and a sub area (SBA).

[0067] The main area (MA) may include a display area (DA) for displaying an image and a non-display area (NDA) which is the surrounding area of ​​the display area (DA). The display area (DA) may occupy most of the main area (MA). The display area (DA) may be positioned in the center of the main area (MA).

[0068] A display area (DA) includes a plurality of pixels (PX) for displaying an image, and each of the plurality of pixels (PX) may include a plurality of subpixels (SPX). A pixel (PX) may be defined as a minimum unit of subpixel group capable of expressing a white gradation.

[0069] The non-display area (NDA) may be positioned adjacent to the display area (DA). The non-display area (NDA) may be an outer area of ​​the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0070] The first scan drive unit (SDC1) and the second scan drive unit (SDC2) may be placed in a non-display area (NDA). The first scan drive unit (SDC1) may be placed on one side (e.g., the left side) of the display panel (100), and the second scan drive unit (SDC2) may be placed on the other side (e.g., the right side) of the display panel, but the embodiments of the present specification are not limited thereto.

[0071] Each of the first scan driver (SDC1) and the second scan driver (SDC2) can be electrically connected to the display driver circuit (250) through scan fan out lines. Each of the first scan driver (SDC1) and the second scan driver (SDC2) receives a scan control signal from the display driver circuit (250) and can generate scan signals according to the scan control signal and output them to the scan lines.

[0072] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). The length of the second direction (DR2) of the sub-region (SBA) may be shorter than the length of the second direction (DR2) of the main region (MA). The length of the first direction (DR1) of the sub-region (SBA) may be shorter than the length of the first direction (DR1) of the main region (MA) or substantially equal to the length of the first direction (DR1) of the main region (MA). The sub-region (SBA) may be bent and may be positioned at the bottom of the display panel (100). In this case, the sub-region (SBA) may overlap with the main region (MA) in a third direction (DR3).

[0073] The sub-region (SBA) may include a connection region (CA), a pad region (PA), and a bending region (BA).

[0074] The connection area (CA) is an area protruding in a second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) is in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0075] The pad area (PA) is an area where pads (PDs) and a display driving circuit (250) are placed. The display driving circuit (250) can be attached to the driving pads of the pad area (PA) using a conductive adhesive material such as an anisotropic conductive film. The circuit board (300) can be attached to the pads (PDs) of the pad area (PA) using a conductive adhesive material such as an anisotropic conductive film. One side of the pad area (PA) may be in contact with the bending area (BA).

[0076] The bending area (BA) is a bending area. When the bending area (BA) is bent, the pad area (PA) may be positioned below the connecting area (CA) and below the main area (MA). The bending area (BA) may be positioned between the connecting area (CA) and the pad area (PA). One side of the bending area (BA) is in contact with the connecting area (CA), and the other side of the bending area (BA) may be in contact with the pad area (PA).

[0077] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0078] Referring to FIG. 3, the display area (DA) includes a plurality of pixels (PX), a plurality of scan lines (SL), a plurality of light emission control lines (EL), and a plurality of data lines (DL).

[0079] Multiple pixels (PX) may be arranged in a matrix form in a first direction (DR1) and a second direction (DR2). Multiple scan lines (SL) and multiple light emission control lines (EL) may extend in the first direction (DR1) and be arranged in the second direction (DR2). Multiple data lines (DL) may extend in the second direction (DR2) and be arranged in the first direction (DR1). Multiple scan lines (SL) include multiple write scan lines (GWL), multiple control scan lines (GCL), multiple initialization scan lines (GIL), and multiple bias scan lines (GBL).

[0080] Each of the plurality of subpixels (SPX) can be connected to one of the plurality of write scan lines (GWL), one of the plurality of control scan lines (GCL), one of the plurality of initialization scan lines (GIL), one of the plurality of bias scan lines (GBL), one of the plurality of light emission control lines (EL), and one of the plurality of data lines (DL). Each of the plurality of subpixels (SPX) receives a data voltage of the data line (DL) according to the write scan signal of the write scan line (GWL), and can emit light from the light-emitting element according to the data voltage.

[0081] The non-display area (NDA) includes a first scan drive unit (SDC1), a second scan drive unit (SDC2), and a display drive circuit (250).

[0082] Each of the first scan drive unit (SDC1) and the second scan drive unit (SDC2) may include a write scan signal output unit (611), an initial scan signal output unit (612), a bias scan signal output unit (613), and a light emission signal output unit (614). Each of the write scan signal output unit (611), the initial scan signal output unit (612), the bias scan signal output unit (613), and the light emission signal output unit (614) may receive a scan timing control signal (SCS) from the timing control circuit (400). The write scan signal output unit (611) may generate write scan signals according to the scan timing control signal (SCS) of the timing control circuit (400) and output them sequentially to the write scan lines (GWL). The initial scan signal output unit (612) may generate initial scan signals according to the scan timing control signal (SCS) and output them sequentially to the initial scan lines (GIL). The bias scan signal output unit (613) can generate bias scan signals according to the scan timing control signal (SCS) and output them sequentially to the bias scan lines (EBL). The light emission signal output unit (614) can generate light emission control signals according to the scan timing control signal (SCS) and output them sequentially to the light emission control lines (EL).

[0083] The display driving circuit (250) includes a timing control circuit (251) and a data driving circuit (252).

[0084] The data driving circuit (252) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control circuit (251). The data driving circuit (252) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs them to the data lines (DL). In this case, subpixels (SPX) are selected by the write scan signals of the first scan driving unit (SDC1) and the second scan driving unit (SDC2), and data voltages can be supplied to the selected subpixels (SPX).

[0085] The timing control circuit (251) can receive digital video data and timing signals from an external source. The timing control circuit (251) can generate a scan timing control signal (SCS) and a data timing control signal (DCS) to control the display panel (100) according to the timing signals. The timing control circuit (400) can output the scan timing control signal (SCS) to the first scan driving unit (SDC1) and the second scan driving unit (SDC2). The timing control circuit (251) can output digital video data (DATA) and the data timing control signal (DCS) to the data driving circuit (252).

[0086] The power supply circuit (500) can generate a plurality of panel driving voltages according to the power supply voltage from an external source. For example, the power supply circuit (500) can generate a first driving voltage (VDD), a second driving voltage (VSS), and a third driving voltage (VINT) and supply them to the display panel (100).

[0087] FIG. 4 is an equivalent circuit diagram showing a subpixel according to one embodiment.

[0088] Referring to FIG. 4, a subpixel (SPX) according to one embodiment may be connected to scan lines (GWL, GIL, GCL, GBL), an emitting line (EL), and a data line (DL). For example, the subpixel (SPX) may be connected to a write scan line (GWL), an initialization scan line (GIL), a control scan line (GCL), a bias scan line (GBL), an emitting line (EL), and a data line (DL).

[0089] A subpixel (SPX) according to one embodiment includes a driving transistor (DT), switching elements, a capacitor (C1), and a light-emitting element (LE). The switching elements include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0090] The driving transistor (DT) includes a gate electrode, a conductive layer, and a second electrode. The driving transistor (DT) controls the drain-source current (Ids, hereinafter referred to as "driving current") flowing between the conductive layer and the second electrode according to the data voltage applied to the gate electrode.

[0091] The light-emitting element (LE) can be a micro light-emitting diode.

[0092] The light-emitting element (LE) emits light according to the driving current (Ids). The amount of light emitted by the light-emitting element (LE) may be proportional to the driving current (Ids). The anode electrode of the light-emitting element (LE) is connected to the conductive layer of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode may be connected to the second power line (VSL) to which the second power supply voltage is applied.

[0093] A capacitor (C1) is formed between the second electrode of a driving transistor (DT) and a first power line (VDL) to which a first power supply voltage is applied. The first power supply voltage may be a voltage level higher than the second power supply voltage. One electrode of the capacitor (C1) may be connected to the second electrode of the driving transistor (DT), and the other electrode may be connected to the first power line (VDL).

[0094] As shown in FIG. 4, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can all be formed as p-type MOSFETs. In this case, the active layer of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can be formed of polysilicon.

[0095] The gate electrode of the first transistor (ST1) and the gate electrode of the second transistor (ST2) may be connected to the write scan line (GWL), the gate electrode of the third transistor (ST3) may be connected to the initialization scan line (GIL), and the gate electrode of the fourth transistor (ST4) may be connected to the bias scan line (GBL). Since the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) are formed as p-type MOSFETs, they may be turned on when a scan signal of gate low voltage and a light emission signal are applied to the control scan line (GCL), the initialization scan line (GIL), the write scan line (GWL), the bias scan line (GBL), and the light emission line (EL), respectively. One electrode of the third transistor (ST3) and one electrode of the fourth transistor (ST4) may be connected to the initialization voltage line (VIL).

[0096] Alternatively, the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) may be formed as p-type MOSFETs, and the first transistor (ST1) and the third transistor (ST3) may be formed as n-type MOSFETs. The active layer of each of the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) formed as p-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor (ST1) and the third transistor (ST3) formed as n-type MOSFETs may be formed of an oxide semiconductor.

[0097] In this case, since the first transistor (ST1) and the third transistor (ST3) are formed as n-type MOSFETs, the first transistor (ST1) can be turned on when a gate high voltage scan signal is applied, and the third transistor (ST3) can be turned on when an initialization scan signal of a gate high voltage is applied. In contrast, since the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are formed as p-type MOSFETs, they can be turned on when a gate low voltage scan signal and a light emission signal are applied.

[0098] Alternatively, the fourth transistor (ST4) is formed as an n-type MOSFET, and thus the active layer of each of the fourth transistors (ST4) can be formed as an oxide semiconductor. When the fourth transistor (ST4) is formed as an n-type MOSFET, it can be turned on when a scan signal of gate high voltage is applied.

[0099] Alternatively, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as n-type MOSFETs. In this case, the active layer of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may be formed as an oxide semiconductor.

[0100] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0101] Referring to FIG. 5, each of the plurality of pixels (PX) of the display area (DA) may include three subpixels (SPX1, SPX2, SPX3), but the embodiments of the present specification are not limited thereto and may include four subpixels. When each of the plurality of pixels (PX) includes three subpixels (SPX1, SPX2, SPX3), it may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3).

[0102] Multiple pixels (PX) can be arranged in a matrix form. In each of the multiple pixels (PX), the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) can be arranged in a first direction (DR1).

[0103] In the case where each of the plurality of pixels (PX) includes three subpixels (SPX1, SPX2, SPX3), the first subpixel (SPX1) may emit light of a first color, the second subpixel (SPX2) may emit light of a second color, and the third subpixel (SPX3) may emit light of a third color. Here, the first color light may be light in the green wavelength band, the second color light may be light in the red wavelength band, and the third color light may be light in the blue wavelength band. For example, the blue wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 370 nm to 460 nm, the green wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 480 nm to 560 nm, and the red wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 600 nm to 750 nm.

[0104] Alternatively, if each of the plurality of pixels (PX) includes four subpixels, the first subpixel may emit light of a first color, the second subpixel and the fourth subpixel may emit light of a second color, and the third subpixel may emit light of a third color. Alternatively, the first subpixel may emit light of a first color, the second subpixel may emit light of a second color, the third subpixel may emit light of a third color, and the fourth subpixel may emit light of a fourth color. In this case, the light of the fourth color may be white light.

[0105] A first subpixel (SPX1) comprises a first pixel electrode (PXE1), one or more light-emitting elements (LE), and a first light-converting layer (QDL1). A second subpixel (SPX2) comprises a second pixel electrode (PXE2), one or more light-emitting elements (LE), and a second light-converting layer (QDL2). A third subpixel (SPX3) comprises a third pixel electrode (PXE3), one or more light-emitting elements (LE), and a third light-converting layer (QDL3).

[0106] Each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2). The area of ​​the first subpixel (SPX1), the area of ​​the second subpixel (SPX2), and the area of ​​the third subpixel (SPX3) may be set according to the light conversion efficiency of the first light conversion layer (QDL1) and the light conversion efficiency of the second light conversion layer (QDL2). For example, the area of ​​the subpixel may be larger as the light conversion efficiency decreases.

[0107] For example, as shown in FIG. 5, if the light conversion efficiency of the second light conversion layer (QDL2) is lower than the light conversion efficiency of the first light conversion layer (QDL1), the area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1). Additionally, while the light transmission layer (TPL) transmits the light of the light-emitting element (LE) as is, the first light conversion layer (QDL1) must convert the light, so the area of ​​the first pixel electrode (PXE1) may be larger than the area of ​​the third pixel electrode (PXE3).

[0108] If the light conversion efficiency of the second light conversion layer (QDL2) is lower than the light conversion efficiency of the first light conversion layer (QDL1), the number of light-emitting elements disposed on the second pixel electrode (PXE2) may be greater than the number of light-emitting elements disposed on the first pixel electrode (PXE1). For example, one light-emitting element may be disposed on the first pixel electrode (PXE1), and two light-emitting elements, a first type light-emitting element (LE1T) and a second type light-emitting element (LE2T), may be disposed on the second pixel electrode (PXE2). The first type light-emitting element (LE1T) and the second type light-emitting element (LE2T) may be connected in series. The embodiments of this specification are not limited thereto. For example, the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T) may be disposed in series on each of the pixel electrodes (PXE1, PXE2, PXE3).

[0109] Each of the plurality of light-emitting elements (LEs) may have a rectangular planar shape, but the embodiments of this specification are not limited thereto. For example, each of the plurality of light-emitting elements (LEs) may have a circular planar shape.

[0110] Each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to at least one transistor through a pixel connection hole (CT1 / CT2 / CT3). For example, each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to the second electrode of the fourth transistor (ST4 in FIG. 4) and the second electrode of the sixth transistor (ST6 in FIG. 4) of the corresponding subpixel.

[0111] The first light conversion layer (QDL1) can completely overlap with the plurality of light-emitting elements (LE) of the first pixel electrode (PXE1) and the first subpixel (SPX1). The area of ​​the first light conversion layer (QDL1) may be larger than the area of ​​the first pixel electrode (PXE1). The first light conversion layer (QDL1) can convert or shift the peak wavelength of incident light to light of another specific peak wavelength and emit it. For example, the first light conversion layer (QDL1) can convert or shift third light emitted from the plurality of light-emitting elements (LE) of the first subpixel (SPX1) into first light.

[0112] The second light conversion layer (QDL2) can completely overlap with the plurality of light-emitting elements (LE) of the second pixel electrode (PXE2) and the second subpixel (SPX2). The area of ​​the second light conversion layer (QDL2) may be larger than the area of ​​the second pixel electrode (PXE2). The second light conversion layer (QDL2) can convert or shift the peak wavelength of the incident light to light of another specific peak wavelength and emit it. For example, the second light conversion layer (QDL2) can convert or shift the third light emitted from the plurality of light-emitting elements (LE) of the second subpixel (SPX2) into the second light.

[0113] The light-transmitting layer (TPL) can completely overlap with the plurality of light-emitting elements (LE) of the third pixel electrode (PXE3) and the third subpixel (SPX3). The light-transmitting layer (TPL) can transmit incident light as is. For example, the light-transmitting layer (TPL) can transmit the third light emitted from the plurality of light-emitting elements (LE) of the third subpixel (SPX3) as is.

[0114] When the light-emitting element (LE) of the first subpixel (SPX1) emits light of the first color, the light-emitting element (LE) of the second subpixel (SPX2) emits light of the second color, and the light-emitting element (LE) of the third subpixel (SPX3) emits light of the third color, the light conversion layers (QDL1, QDL2) and the light transmission layer (TPL) may be omitted.

[0115] FIG. 6 is a cross-sectional view showing an example of a cross-section of a display panel cut along the line I1-I1' of FIG. 5. FIG. 7 is a cross-sectional view showing in detail an example of area A of FIG. 6. FIG. 8 is a cross-sectional view showing in detail another example of area A of FIG. 7.

[0116] Referring to FIGS. 6 and FIGS. 7, the substrate (SUB) may be made of an insulating material such as glass or a polymer resin. If the substrate (SUB) is made of a polymer resin, it may be a stretchable flexible substrate. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0117] A barrier film (BR) may be disposed on the substrate (SUB). The barrier film (BR) is a film for protecting the transistors of the thin-film transistor layer (TFTL) and the light-emitting layer (172) of the light-emitting element layer (EML) from moisture penetrating through the substrate (SUB), which is susceptible to moisture permeability. The barrier film (BR) may be composed of a plurality of inorganic films that are alternately stacked.

[0118] A thin-film transistor (TFT1) may be disposed on the barrier film (BR). The thin-film transistor (TFT1) may be either the fourth transistor (ST4) or the sixth transistor (ST6) shown in FIG. 4. The thin-film transistor (TFT1) may include a first active layer (ACT1) and a first gate electrode (G1).

[0119] A first active layer (ACT1) of a thin-film transistor (TFT1) may be disposed on a barrier film (BR). The first active layer (ACT1) of the thin-film transistor (TFT1) may include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, or amorphous silicon. Alternatively, the first active layer (ACT1) of the thin-film transistor (TFT1) may be made of an oxide semiconductor including IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0120] The first active layer (ACT1) may include a first channel region (CHA1), a first source region (S1), and a first drain region (D1). The first channel region (CHA1) may be a region that overlaps with the first gate electrode (G1) in the third direction (DR3), which is the thickness direction of the substrate (SUB). The first source region (S1) may be disposed on one side of the first channel region (CHA1), and the first drain region (D1) may be disposed on the other side of the first channel region (CHA1). The first source region (S1) and the first drain region (D1) may be regions that do not overlap with the first gate electrode (G1) in the third direction (DR3). The first source region (S1) and the first drain region (D1) may be regions that have conductivity by doping ions into a semiconductor material.

[0121] A first gate insulating film (131) may be disposed on the first channel region (CHA1), the first source region (S1), and the first drain region (D1) of the thin film transistor (TFT1).

[0122] A first gate metal layer may be disposed on the first gate insulating film (131). The first gate metal layer may include a first gate electrode (G1) and a first capacitor electrode (CAE1) of a thin-film transistor (TFT1). The first gate electrode (G1) may overlap with the first active layer (ACT1) in the third direction (DR3). Although the first gate electrode (G1) and the first capacitor electrode (CAE1) are shown as being separated from each other in FIG. 6, the first gate electrode (G1) and the first capacitor electrode (CAE1) may be connected to each other.

[0123] A second gate insulating film (132) may be disposed on the first gate electrode (G1) and the first capacitor electrode (CAE1) of the thin-film transistor (TFT1).

[0124] A second gate metal layer may be disposed on the second gate insulating film (132). The second gate metal layer may include a second capacitor electrode (CAE2). The second capacitor electrode (CAE2) may overlap with the first capacitor electrode (CAE1) of the thin film transistor (TFT1) in the third direction (DR3). Since the second gate insulating film (132) has a predetermined dielectric constant, a capacitor (C1 in FIG. 4) may be formed by the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), and the second gate insulating film (132) disposed between them.

[0125] A first interlayer insulating film (141) may be disposed on the second capacitor electrode (CAE2).

[0126] A first data metal layer may be disposed on the interlayer insulating film (141). The first data metal layer may include a first source connection electrode (PCE1). The first source connection electrode (PCE1) may be connected to a first drain region (D) of a first active layer (ACT1) through a first source contact hole (PCT1) penetrating the first gate insulating film (131), the second gate insulating film (132), and the interlayer insulating film (141).

[0127] A first flattening organic film (160) for flattening the step difference caused by a thin film transistor (TFT1) may be disposed on the first source connection electrode (PCE1).

[0128] A second data metal layer may be disposed on the first planarization organic film (160). The second data metal layer may include a second source connection electrode (PCE2). The second source connection electrode (PCE2) may be connected to the first source connection electrode (PCE1) through a second pixel contact hole (PCT2) that penetrates the first planarization organic film (160).

[0129] A second planarizing organic film (180) may be placed on the second source connection electrode (PCE2).

[0130] The barrier film (BR), the first gate insulating film (131), the second gate insulating film (132), the third gate insulating film (133), and the interlayer insulating film (141) are inorganic films, for example, silicon nitride (SiN x ), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x It can be formed as ).

[0131] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0132] The first flattening organic film (160) and the second flattening organic film (180) can be formed from organic films such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0133] A light-emitting element layer may be disposed on the second planarized organic film (180). The light-emitting element layer may include pixel electrodes (PXE1, PXE2, PXE3), light-emitting elements (LE), a common electrode (CE), and an organic layer (190).

[0134] A pixel electrode layer may be disposed on the second planarizing organic film (180). The pixel electrode layer may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3). Each of the pixel electrodes (PXE1, PXE2, PXE3) may be connected to a second source connection electrode (PCE2) through a connection hole (CT1 / CT2 / CT3 in FIG. 5) penetrating the second planarizing organic film (180). Each of the pixel electrodes (PXE1, PXE2, PXE3) may be connected to a first source region (S1) or a first drain region (D1) of a thin film transistor (TFT1) through the first source connection electrode (PCE1) and the second source connection electrode (PCE2). Therefore, a voltage controlled by the thin film transistor (TFT1) may be applied to each of the pixel electrodes (PXE1, PXE2, PXE3).

[0135] The pixel electrode layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. For example, to lower the resistance of each of the pixel electrodes (PXE1, PXE2, PXE3), the pixel electrode layer may be made of copper (Cu), which has low sheet resistance.

[0136] One or more light-emitting elements may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3).

[0137] One light-emitting element (LE) may be disposed on the first pixel electrode (PXE1) and the third pixel electrode (PXE3), and two light-emitting elements (LE1T, LE2T) may be disposed on the second pixel electrode (PXE2). The light-emitting element (LE) disposed on the first pixel electrode (PXE1) and the third pixel electrode (PXE3) may be referred to as a third type light-emitting element (LE) to clearly distinguish it from the two light-emitting elements (LE1T, LE2T) disposed on the second pixel electrode (PXE2). The first to third type light-emitting elements (LE) are exemplified as vertical type micro LEDs extended in the third direction (DR3). A vertical type micro LED refers to an LED having a structure in which a first semiconductor layer (SEM1), an active layer (MQW), and a second semiconductor layer (SEM2) are sequentially disposed in the third direction (DR3), which is a vertical direction.

[0138] Each of the plurality of light-emitting elements (LE1T, LE2T, LE) may be formed of an inorganic material such as gallium nitride (GaN). Each of the plurality of light-emitting elements (LE1T, LE2T, LE) may have a length in a first direction (DR1), a length in a second direction (DR2), and a length in a third direction (DR3) of several to several hundred μm. For example, each of the plurality of light-emitting elements (LE1T, LE2T, LE) may have a length in a first direction (DR1), a length in a second direction (DR2), and a length in a third direction (DR3) of approximately 100 μm or less.

[0139] Each of the plurality of light-emitting elements (LE1T, LE2T, LE) can be formed by growing on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The plurality of light-emitting elements (LE1T, LE2T, LE) can be transferred directly from the semiconductor substrate onto the pixel electrodes (PXE1, PXE2, PXE3) of the display panel (100). Alternatively, the plurality of light-emitting elements (LE1T, LE2T, LE) can be transferred onto the pixel electrodes (PXE1, PXE2, PXE3) of the display panel (100) via an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS or silicon as a transfer substrate.

[0140] Each of the plurality of light-emitting elements (LE1T, LE2T, LE) may include a first semiconductor layer (SEM1), an active layer (MQW), and a second semiconductor layer (SEM2) that are commonly arranged sequentially. Additionally, each of the plurality of light-emitting elements (LE1T, LE2T, LE) may further include a protective layer (INS). The protective layer (INS) is a film for protecting the outer surface of the plurality of light-emitting elements (LE1T, LE2T, LE), and the protective layer (INS) may surround the first semiconductor layer (SEM1), the active layer (MQW), and the second semiconductor layer (SEM2). For example, the protective layer (INS) may be disposed on one side and the side of the first semiconductor layer (SEM1), the active layer (MQW), and the second semiconductor layer (SEM2).

[0141] The first type light-emitting element (LE1) and the third type light-emitting element (LE3) may further include a contact electrode (CTE). The contact electrode (CTE) may be disposed on one side of the light-emitting element and, for example, on the lower surface of the first semiconductor layer (SEM1). If a conductive layer is disposed on one side of the first semiconductor layer (SEM1), the contact electrode (CTE) may be disposed on the conductive layer.

[0142] The contact electrode (CTE) can be connected to the first semiconductor layer (SEM1) (or on the conductive layer) which is exposed and not covered by the protective layer (INS).

[0143] The contact electrode (CTE) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Specifically, to increase reflectivity, the plurality of contact electrodes (CTE) may be formed into a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of ITO (Indium Tin Oxide), silver (Ag), and ITO (Indium Tin Oxide).

[0144] A bonding electrode (BOD) may be disposed between the contact electrode (CTE) and the pixel electrodes (PXE1, PXE2). The bonding electrode (BOD) may serve as a bonding metal for bonding the pixel electrodes (PXE1, PXE2) and a plurality of light-emitting elements (LE1T, LE2T, LE) during the manufacturing process. For example, the bonding electrode (BOD) may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the bonding electrode (BOD) may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin.

[0145] Although not illustrated, a conductive layer may be further disposed on the first semiconductor layer (SEM1). The conductive layer may be disposed on a portion of one surface of the first semiconductor layer (SEM1). The conductive layer (E1) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0146] The first semiconductor layer (SEM1) may be composed of a semiconductor material layer doped with a first conductivity type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc., for example, gallium nitride (GaN).

[0147] The active layer (MQW) can be placed on the first semiconductor layer (SEM1). The active layer (MQW) can emit light through the coupling of electron-hole pairs according to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0148] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of indium gallium nitride (InGaN), and the barrier layers may be formed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), but the embodiments of this specification are not limited thereto.

[0149] Alternatively, the active layer (MQW) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, or it may include different group 3 to group 5 semiconductor materials depending on the wavelength of the emitted light.

[0150] For example, when the active layer (MQW) contains indium gallium nitride (InGaN), the color of the emitted light may vary depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer shifts to a red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer shifts to a blue wavelength band. For example, the content of indium (In) in the active layer (MQW) of a light-emitting device (LE) that emits a third light (light in the blue wavelength band) may be approximately 10 wt% to 20 wt%.

[0151] A second semiconductor layer (SEM2) may be disposed on a first semiconductor layer (SEM1). The second semiconductor layer (SEM2) may be a semiconductor material layer doped with a second conductivity type dopant, such as silicon (Si), germanium (Ge), tin (Sn), etc., for example, gallium nitride (GaN).

[0152] An electron blocking layer may be placed between the first semiconductor layer (SEM1) and the active layer (MQW). The electron blocking layer may be a layer for suppressing or preventing too many electrons from flowing into the active layer (MQW). For example, the electron blocking layer may be aluminum gallium nitride (AlGaN) or p-type aluminum gallium nitride (AlGaN) doped with p-type magnesium (Mg). The electron blocking layer may be omitted.

[0153] A superlattice layer may be disposed between the active layer (MQW) and the second semiconductor layer (SEM2). The superlattice layer may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer may be formed of indium gallium nitride (InGaN) or gallium nitride (GaN). The superlattice layer may be omitted.

[0154] A light extraction pattern (LEP) can be formed on the upper surface of the second semiconductor layer (SEM2).

[0155] Light extraction patterns (LEPs) may be patterns for increasing the efficiency of light emitted to the upper surface of a light-emitting element (LE). Light extraction patterns (LEPs) may be concave patterns formed as hemispheres or semi-ellipses. Light extraction patterns (LEPs) may be concave patterns having a cross-sectional shape of a semicircle or semi-ellipse. The maximum length (Lmax) of the third direction (DR3) of the light extraction patterns (LEPs) may be approximately 100 nm. Additionally, the distance between adjacent light extraction patterns (LEPs) may be approximately 100 nm or less.

[0156] The light extraction pattern (LEP) can be omitted as shown in Fig. 8.

[0157] Referring to FIGS. 6 and 7, the second semiconductor layer (SEM2) of the first type light-emitting element (LE1T) may include a first portion (SEM2_1) having a first thickness (d1) and a second portion (SEM2_2) having a second thickness (d2). The second thickness (d2) may be thinner than the first thickness (d1).

[0158] An active layer (MQW) can be disposed on one side of the first part (SEM2_1).

[0159] The protective layer (INS1) of the first type light-emitting element (LE1T) may include a first opening (OP1) and a second opening (OP2). The first opening (OP1) may overlap with a first portion (SEM2_1) in the thickness direction (DR3), and the second opening (OP2) may overlap with a second portion (SEM2_2) in the thickness direction (DR3). The first opening (OP1) may expose one side of the first semiconductor layer (SEM1) (or conductive layer), and the second opening (OP2) may expose one side of a second portion (SEM2_2) of the second semiconductor layer (SEM2).

[0160] The contact electrode (CTE) overlaps with the first opening (OP1) and is connected to one side of the first semiconductor layer (SEM1) (or conductive layer) exposed through the first opening (OP1).

[0161] One side of the second portion (SEM2_2) of the second semiconductor layer (SEM2) exposed through the second opening (OP2) can be connected to the connect electrode (CNE) described later.

[0162] The second type light-emitting element (LE2T) may have a rectangular cross-sectional shape in which the width of the top surface is nearly equal to the width of the bottom surface, but is not limited thereto, and the light-emitting element (LE) may have an inversely tapered cross-sectional shape in which the width of the top surface is wider than the width of the bottom surface.

[0163] The width of the active layer (MQW) of the first type light-emitting element (LE1T) and the width of the active layer (MQW) of the second type light-emitting element (LE2T) can be nearly the same.

[0164] The protective layer (INS) of the second type light-emitting element (LE2T) may have an opening (third opening (OP3)) on one side of the first semiconductor layer (SEM1). One side of the first semiconductor layer (SEM1) (or conductive layer) exposed through the second opening (OP2) may be connected to a connect electrode (CNE) described later. That is, the connect electrode (CNE) can electrically connect the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T). For example, the connect electrode (CNE) can connect the first type light-emitting element (LE2T) and the second type light-emitting element (LE2T) in series by connecting the second semiconductor layer (SEM2) of the first type light-emitting element (LE1T) and the first semiconductor layer (SEM1) of the second type light-emitting element (LE2T).

[0165] The second type light-emitting element (LE2T) further includes a dummy electrode (DE) disposed on a protective layer (INS). The dummy electrode (DE) may be formed from the same material as the contact electrode (CTE). The thickness of the dummy electrode (DE) may be the same as the thickness of the contact electrode (CTE). The dummy electrode (DE) may be disposed on the second pixel electrode (PXE2). The dummy electrode (DE) is disposed on one side of the first semiconductor layer (SEM1) where the third opening (OP3) is disposed, and is disposed spaced apart from the third opening (OP3). Accordingly, the dummy electrode (DE) is not electrically connected to the semiconductor layer of the second type light-emitting element (LE2T) and serves only to compensate for the height difference with the first type light-emitting element (LE1T) so that the second type light-emitting element (LE2T) does not tilt. The dummy electrode (DE) may also be referred to as a non-contact electrode in the sense that it is not electrically connected to the semiconductor layer of the second type light-emitting element (LE2T).

[0166] The width of the dummy electrode (DE) may be smaller than the width of the contact electrode (CTE).

[0167] A bonding electrode (BOD) may be placed between a dummy electrode (DE) and a pixel electrode (PXE2). The bonding electrode (BOD) may serve as a bonding metal for bonding the pixel electrode (PXE2) and the second type light-emitting element (LE2T) during the manufacturing process. For example, the bonding electrode (BOD) may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the bonding electrode (BOD) may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin.

[0168] The connect electrode (CNE) may be formed of a transparent conductive oxide (TCO), such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), but is not limited thereto, and may include one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0169] A filling layer (e.g., a filling material) (FM) is disposed between the side walls of a first type light-emitting element (LE1T) and a second type light-emitting element (LE2T). The filling layer (FM) contacts the side (SF1) of the first type light-emitting element (LE1T) and the side (SF2) of the second type light-emitting element (LE2T) that face each other.

[0170] The filling layer (FM) can increase the structural support of the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T). The filling layer (FM) may be a material having insulating properties. The filling layer (FM) may include, for example, inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (AlxOy), aluminum nitride (AlN), etc. Alternatively, the filling layer (FM) may include organic insulating materials such as, for example, epoxy resin, acrylic resin, cardo resin, or imide resin. The surface of the filling layer (FM) (the surface in contact with the side (S1) of the first type light-emitting element (LE1T) and the side (S2) of the second type light-emitting element (LE2T)) may be provided with a reflective material to form a light-reflecting surface. When a light-reflecting surface is formed on the surface of the filling layer (FM), the light emission efficiency of the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T) can be improved. In some embodiments, the filling layer (FM) may include a light-absorbing material (e.g., an inorganic black pigment such as carbon black or an organic black pigment). When a light-absorbing surface is formed on the surface of the filling layer (FM), interference between light emitted from the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T) can be reduced or prevented.

[0171] Each of the third type light-emitting elements (LE) may have a rectangular cross-sectional shape in which the width of the top surface is approximately equal to the width of the bottom surface, but is not limited thereto, and the light-emitting element (LE) may have an inversely tapered cross-sectional shape in which the width of the top surface is wider than the width of the bottom surface.

[0172] The protective layer (INS) of the third type light-emitting element (LE) may include an opening on one side facing the pixel electrodes (PXE1, PXE3). The first semiconductor layer (SEM1) of the third type light-emitting element (LE) is exposed through the opening. A contact electrode (CTE) is placed on the exposed first semiconductor layer (SEM1) of the third type light-emitting element (LE).

[0173] A bonding electrode (BOD) can be placed between the pixel electrodes (PXE1, PXE3) and the contact electrode (CTE).

[0174] The third organic layer (190) is a layer for flattening the step difference caused by a plurality of light-emitting elements (LE). The third organic layer (190) may be arranged to cover a plurality of light-emitting elements (LE1T, LE2T, LE). In one embodiment, the third organic layer (190) is arranged to cover a plurality of light-emitting elements (LE1T, LE2T, LE), but is not limited thereto. If the third organic layer (190) is arranged to cover only a part of the side of a plurality of light-emitting elements (LE1T, LE2T, LE), an additional organic film may be placed on the third organic layer (190) to cover all of the plurality of light-emitting elements (LE1T, LE2T, LE). Meanwhile, it may include a fourth opening (OP4) that exposes at least a part of the upper surface (other surface) of the second type light-emitting element (LE2T) and the third type light-emitting element (LE1T).

[0175] The third organic layer (190) can be formed from an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0176] The common electrode (CE) is disposed on the third organic layer (190) and can be connected by contacting the upper surface (other surface) of the second type light-emitting element (LE2T) and the third type light-emitting element (LE1T) exposed through the fourth opening (OP4). On the other hand, the first type light-emitting element (LE) does not come into direct contact with the common electrode (CE).

[0177] The common electrode (CE) may be a common layer formed in common on the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3). The common electrode (CE) may be made of a transparent conductive material (TCO) such as Indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO) that can transmit light.

[0178] Meanwhile, pixel electrodes (PXE1, PXE2, PXE3) may be referred to as anode electrodes or first electrodes, and a common electrode (CE) may be referred to as cathode electrodes or second electrodes.

[0179] The first capping layer (CAP1) can be placed on the common electrode (CE).

[0180] A light-blocking layer (BM), a first light-converting layer (QDL1), a second light-converting layer (QDL2), and a light-transmitting layer (TPL) may be disposed on the first capping layer (CAP1). The first light-converting layer (QDL1), the second light-converting layer (QDL2), and the light-transmitting layer (TPL) may be formed by the partitions of the light-blocking layer (BM). Therefore, the first light-converting layer (QDL1) may be disposed on the first capping layer (CAP1) in the first subpixel (SPX1), the second light-converting layer (QDL2) may be disposed on the first capping layer (CAP1) in the second subpixel (SPX2), and the light-transmitting layer (TPL) may be disposed on the first capping layer (CAP1) in the third subpixel (SPX3). The light-blocking layer (BM) may overlap with the third organic layer (190) in the third direction (DR3) and may not overlap with the plurality of light-emitting elements (LE).

[0181] The first light conversion layer (QDL1) can convert a portion of the third light (light in the blue wavelength band) incident from the light-emitting element (LE) into the first light (light in the green wavelength band). The first light conversion layer (QDL1) may include a first base resin (BRS1) and a first wavelength conversion particle (WCP1). The first base resin (BRS1) may include a light-transmitting organic material. The first wavelength conversion particle (WCP1) can convert a portion of the third light (light in the blue wavelength band) incident from the light-emitting element (LE) into the first light (light in the green wavelength band).

[0182] The second light conversion layer (QDL2) can convert a portion of the third light (light in the blue wavelength band) incident from the light-emitting element (LE) into second light (light in the red wavelength band). It may include a second base resin (BRS2) and a second wavelength conversion particle (WCP2). The second base resin (BRS2) may include a transparent organic material. The second wavelength conversion particle (WCP2) can convert a portion of the third light (light in the blue wavelength band) incident from the light-emitting element (LE) into second light (light in the red wavelength band).

[0183] The light-transmitting layer (TPL) may include a light-transmitting organic material.

[0184] For example, the first base resin (BRS1), the second base resin (BRS2), and the light-transmitting layer (TPL) may include epoxy resin, acrylic resin, cardo resin, or imide resin, etc. The first and second wavelength conversion particles (WCP1, WCP2) may be quantum dots (QD), quantum rods, fluorescent materials, or phosphorescent materials.

[0185] The light-blocking layer (BM) may include a first light-blocking layer (BM1) and a second light-blocking layer (BM2) that are sequentially stacked. The length of the first direction (DR1) or the length of the second direction (DR2) of the first light-blocking layer (BM1) may be wider than the length of the first direction (DR1) or the length of the second direction (DR2) of the second light-blocking layer (BM2). The first light-blocking layer (BM1) and the second light-blocking layer (BM2) may be formed from organic films such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The first light-blocking layer (BM1) and the second light-blocking layer (BM2) may include a light-blocking material to prevent light from a light-emitting element (LE) of one subpixel from proceeding to an adjacent subpixel. For example, the first light-blocking layer (BM1) and the second light-blocking layer (BM2) may include an inorganic black pigment such as carbon black or an organic black pigment.

[0186] The second capping layer (CAP2) may be disposed on the first capping layer (CAP1) and the light-blocking layer (BM). The second capping layer (CAP2) may be disposed on the side and top surface of the light-blocking layer (BM). For example, the second capping layer (CAP2) may be disposed on the side of the first light-blocking layer (BM1) and on the side and top surface of the second light-blocking layer (BM2).

[0187] A reflective film (RF) may be disposed between the light-blocking layer (BM) and the first light-converting layer (QDL1), between the light-blocking layer (BM) and the second light-converting layer (QDL2), and between the light-blocking layer (BM) and the light-transmitting layer (TPL). The reflective film (RF) may be disposed on a second capping layer (CAP2) disposed on the side of the first light-blocking layer (BM1) and the side of the second light-blocking layer (BM2). The reflective film (RF) serves to reflect light traveling in a lateral direction from the first light-converting layer (QDL1), the second light-converting layer (QDL2), and the light-transmitting layer (TPL).

[0188] The reflective film (RF) may include a highly reflective metallic material such as aluminum (Al). The thickness of the reflective film (RF) may be approximately 0.1 μm.

[0189] Alternatively, the reflective film (RF) may include a pair of first and second layers (M, where M is an integer greater than or equal to 2) having different refractive indices to serve as distributed Bragg reflectors (DBR). In this case, M first layers and M second layers may be arranged alternately. The first and second layers may be formed of inorganic films, for example, silicon nitride (SiNx), silicon nitride oxide (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx).

[0190] The third capping layer (CAP3) can be disposed on the second capping layer (CAP2), the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmission layer (TPL).

[0191] The first capping layer (CAP1), the second capping layer (CAP2), and the third capping layer (CAP3) may be formed of an inorganic film, for example, silicon nitride (SiNx), silicon nitride oxide (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx). The first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmission layer (TPL) may be encapsulated by the first capping layer (CAP1), the second capping layer (CAP2), and the third capping layer (CAP3).

[0192] A fifth organic film (213) may be disposed on the third capping layer (CAP3). A plurality of color filters (CF1, CF2, CF3) may be disposed on the fifth organic film (213). The plurality of color filters (CF1, CF2, CF3) may include first color filters (CF1), second color filters (CF2), and third color filters (CF3).

[0193] A first color filter (CF1) placed in a first subpixel (SPX1) can transmit a first light (light in the green wavelength band) and absorb or block a third light (light in the blue wavelength band). Therefore, the first color filter (CF1) can transmit the first light (light in the green wavelength band) converted by the first light conversion layer (QDL1) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and can absorb or block the third light (light in the blue wavelength band) that is not converted by the first light conversion layer (QDL1). Accordingly, the first subpixel (SPX1) can emit the first light (light in the green wavelength band).

[0194] A second color filter (CF2) placed in the second subpixel (SPX2) can transmit second light (light in the red wavelength band) and absorb or block third light (light in the blue wavelength band). Therefore, the second color filter (CF2) can transmit second light (light in the red wavelength band) converted by the first light conversion layer (QDL1) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and can absorb or block third light (light in the blue wavelength band) that is not converted by the first light conversion layer (QDL1). Accordingly, the second subpixel (SPX2) can emit second light (light in the red wavelength band).

[0195] A third color filter (CF3) placed in a third subpixel (SPX3) can transmit third light (light in the blue wavelength band). Therefore, the third color filter (CF3) can transmit third light (light in the blue wavelength band) emitted from a light-emitting element (LE) passing through a light-transmitting layer (TPL). Accordingly, the third subpixel (SPX3) can emit third light (light in the blue wavelength band).

[0196] The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) that overlap in the third direction (DR3) can overlap with the light-blocking layer (BM) in the third direction (DR3).

[0197] A sixth organic film (214) for flattening can be placed on a plurality of color filters (CF1, CF2, CF3).

[0198] The fifth organic film (213) and the sixth organic film (214) can be formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0199] FIG. 9 is a cross-sectional view showing in detail an example of area A of FIG. 6 according to another embodiment.

[0200] The embodiment of FIG. 9 differs from the embodiment of FIG. 7 in that a first reflective layer (RF1) is disposed on at least one surface of a first type light-emitting element (LE1T) and at least one surface of a second type light-emitting element (LE2T). In the embodiment of FIG. 9, descriptions that overlap with the embodiment of FIG. 7 are omitted.

[0201] A first reflective layer (RF1) may be disposed on at least one side surface of a first type light-emitting element (LE1T) and at least one side surface of a second type light-emitting element (LE2T). For example, the first reflective layer (RF1) may be disposed on a surface other than the surface where the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T) face each other.

[0202] The first reflective layer (RF1) serves to reflect light emitted from the active layer (MQW) of the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T) and propagates in a lateral direction.

[0203] The first reflective layer (RF1) may include a metallic material with high reflectivity, such as aluminum (Al). The thickness of the first reflective layer (RF1) may be approximately 0.1 μm.

[0204] Alternatively, the first reflective layer (RF1) may include a pair of first and second layers (M, where M is an integer greater than or equal to 2) having different refractive indices to serve as distributed Bragg reflectors (DBR). In this case, M first layers and M second layers may be arranged alternately. The first and second layers may be formed of inorganic films, for example, silicon nitride (SiNx), silicon nitride oxide (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx).

[0205] In another embodiment, a first reflective layer (RF1) may be disposed on the entire side of a first type light-emitting element (LE1T) and on the entire side of a second type light-emitting element (LE2T).

[0206] FIG. 10 is a cross-sectional view showing in detail an example of area A of FIG. 6 according to another embodiment.

[0207] The embodiment of FIG. 10 differs from the embodiment of FIG. 7 in that the second type light-emitting element (LE2T) does not have a dummy electrode (DE) and the second type light-emitting element (LE2T) and the first type light-emitting element (LE1T) do not come into contact with a single pixel electrode (PXE2). In the embodiment of FIG. 10, descriptions that overlap with the embodiment of FIG. 7 are omitted.

[0208] The first type light-emitting element (LE1T) may be identical to the first type light-emitting element (LE1T) described in FIG. 7. The second type light-emitting element (LE2T) may be identical to the second type light-emitting element (LE2T) described in FIG. 7, except for the dummy electrode (DE).

[0209] A first type light-emitting element (LE1T) may be placed on a second-1 pixel electrode (PXE2-1), and a second type light-emitting element (LE2T) may be placed on a second-2 pixel electrode (PXE2-2).

[0210] The second-1 pixel electrode (PXE2-1) may be formed with a first height (h1), and the second-2 pixel electrode (PXE2-2) may be formed with a second height (h2). The second height (h2) is higher than the first height (h1). The second-2 pixel electrode (PXE2-2) may compensate for the thickness of the contact electrode (CTE) and the bonding electrode (BOD) of the first type light-emitting element (LE1T). For example, the height of the second-2 pixel electrode (PXE2-2) may be equal to the sum of the height of the contact electrode (CTE) of the first type light-emitting element (LE1T), the height of the bonding electrode (BOD), and the height of the second-1 pixel electrode (PXE2-1). Accordingly, the upper surfaces of the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T) may be arranged at the same height.

[0211] FIG. 11 is a cross-sectional view showing in detail an example of area A of FIG. 6 according to another embodiment.

[0212] The embodiment of FIG. 11 differs from the embodiment of FIG. 10 in that a first reflective layer (RF1) is disposed on at least one surface of a first type light-emitting element (LE1T) and at least one surface of a second type light-emitting element (LE2T). In the embodiment of FIG. 11, descriptions that overlap with the embodiment of FIG. 10 are omitted.

[0213] A first reflective layer (RF1) may be disposed on at least one side surface of a first type light-emitting element (LE1T) and at least one side surface of a second type light-emitting element (LE2T). For example, the first reflective layer (RF1) may be disposed on a surface other than the surface where the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T) face each other.

[0214] The first reflective layer (RF1) serves to reflect light emitted from the active layer (MQW) of the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T) and propagates in a lateral direction.

[0215] The first reflective layer (RF1) may include a metallic material with high reflectivity, such as aluminum (Al). The thickness of the first reflective layer (RF1) may be approximately 0.1 μm.

[0216] Alternatively, the first reflective layer (RF1) may include a pair of first and second layers (M, where M is an integer greater than or equal to 2) having different refractive indices to serve as distributed Bragg reflectors (DBR). In this case, M first layers and M second layers may be arranged alternately. The first and second layers may be formed of inorganic films, for example, silicon nitride (SiNx), silicon nitride oxide (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx).

[0217] In another embodiment, a first reflective layer (RF1) may be disposed on the entire side of a first type light-emitting element (LE1T) and on the entire side of a second type light-emitting element (LE2T). The first reflective layer (RF1) may surround the side of the first type light-emitting element (LE1T), and the first reflective layer (RF1) may surround the side of the second type light-emitting element (LE2T).

[0218] Hereinafter, the manufacturing process of a display device (10) according to one embodiment will be described with reference to other drawings.

[0219] FIG. 12 is a flowchart showing a method for manufacturing a display device according to one embodiment. FIG. 13 to 25 are drawings for explaining a method for manufacturing a display device according to one embodiment.

[0220] FIGS. 13 to 25 illustrate the structure of each layer of the display device (10) according to the formation order, respectively, in cross-sectional views. FIGS. 13 to 25 focus on illustrating the manufacturing process of the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T) of the display device (10), which can generally correspond to the cross-sectional view of FIG. 7. Additionally, the second subpixel (SPX2) of the display device (10) is shown in detail below. Below, the manufacturing method of the display device illustrated in FIGS. 13 to 25 will be explained in conjunction with FIG. 12.

[0221] First, referring to FIGS. 13 to 15, a plurality of semiconductor material layers stacked on a base substrate (BSUB) are stacked and mesa patterned to form a plurality of semiconductor layer stacks. (S100 of FIG. 12)

[0222] Referring to FIG. 13, a base substrate (BSUB) is prepared. The base substrate (BSUB) may be a sapphire substrate (Al2O3) or a silicon wafer containing silicon. However, it is not limited thereto, and in one embodiment, the case where the base substrate (BSUB) is a sapphire substrate is described as an example.

[0223] A plurality of semiconductor material layers (USEL, SEM2L, MQWL, SEM1L) are formed on a base substrate (BSUB). The plurality of semiconductor material layers grown by the epitaxial method can be formed by growing a seed crystal. Here, the method for forming the semiconductor material layers may be electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal-organic chemical vapor deposition (MOCVD), etc., and preferably, they may be formed by metal-organic chemical vapor deposition (MOCVD). However, they are not limited thereto.

[0224] The precursor material for forming multiple semiconductor material layers is not particularly limited within the range that can typically be selected to form the target material. For example, the precursor material may be a metal precursor containing an alkyl group such as a methyl group or an ethyl group. For example, it may be a compound such as trimethyl gallium (Ga(CH3)3), trimethyl aluminum (Al(CH3)3), or triethyl phosphate ((C2H5)3PO4), but is not limited thereto.

[0225] Specifically, a second semiconductor material layer (SEM2L), an active material layer (MQWL), and a first semiconductor material layer (SEM1L) are sequentially formed on a base substrate (BSUB). In some embodiments, a conductive layer may be further formed on the first semiconductor material layer (SEM1L).

[0226] Next, referring to FIGS. 13 and 14, a downwardly concave groove (H) is formed on a plurality of semiconductor material layers by an etching process.

[0227] A concave groove (H) penetrates the first semiconductor material layer (SEM1L) and the active layer (MQWL) and is formed up to at least a portion of the second semiconductor material layer (SEM2L). To this end, a plurality of first mask patterns are formed on the first semiconductor material layer (SEM1L). The first mask pattern may be a hard mask containing an inorganic material or a photoresist mask containing an organic material. The first mask pattern prevents the lower plurality of semiconductor material layers (USEL, SEM2L, MQWL, SEM1L) from being etched. Subsequently, using the plurality of first mask patterns as a mask, a portion of the plurality of semiconductor material layers is etched (1 st A groove (H) can be formed by etching. Accordingly, the second semiconductor layer (SEM2) includes a first part (SEM2_1) having a first thickness (d1) and a second part (SEM2_2) having a second thickness (d2) that overlaps with the groove (H).

[0228] Semiconductor material layers can be etched by conventional methods. For example, the process for etching semiconductor material layers may be dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc. In the case of dry etching, anisotropic etching is possible, making it suitable for vertical etching. When using the etching methods described above, the etchant may be Cl2 or O2, etc. However, it is not limited thereto.

[0229] Next, referring to FIG. 15, a plurality of semiconductor material layers (SEM2L, MQWL, SEM1L) are etched into a mesa shape to form a plurality of semiconductor layer stacks (SEM2, MQW, SEM1). The plurality of semiconductor layer stacks may include a configuration in which a second semiconductor layer (SEM2), an active layer (MQW), and a first semiconductor layer (SEM1) are sequentially stacked.

[0230] To this end, a plurality of second mask patterns are formed on the first semiconductor layer (SEM1). The second mask patterns may be a hard mask containing an inorganic material or a photoresist mask containing an organic material. The second mask patterns prevent the lower plurality of semiconductor material layers (SEM2L, MQWL, SEM1L) from being etched. Then, using the plurality of second mask patterns as masks, a portion of the plurality of semiconductor material layers is etched (2 st A semiconductor layer stack is formed by etching.

[0231] On the base substrate (BSUB), a plurality of semiconductor material layers (SEM2L, MQWL, SEM1L) that do not overlap with the second mask pattern are etched and removed, and the portion that overlaps with the second mask pattern and is not etched can be formed into a plurality of semiconductor layer stacks.

[0232] A semiconductor stack has a first type stack (1TS) comprising both a first part (SEM2_1) having a first thickness (d1) and a second part (SEM2_2) having a second thickness (d2), and a second type stack (2TS) comprising only the first part (SEM2_1) having the first thickness (d1). The first type stack (1TS) and the second type stack (2TS) are arranged adjacent to each other.

[0233] Next, referring to FIGS. 16 and 17, a protective layer (INS) having openings (OP1, OP2, OP3) is formed. (S110 of FIG. 12)

[0234] For example, an insulating material layer is formed on the outer surface of the semiconductor layer stack (1TS, 2TS). The insulating material layer is formed on the front surface of the base substrate (BSUB), and can be formed not only on the semiconductor layer stack (1TS, 2TS) but also on the upper surface of the base substrate (BSUB) exposed by the semiconductor layer stack (1TS, 2TS).

[0235] Next, an etch is performed to partially remove the insulating material layer, thereby forming a protective layer (INS) having openings (OP1, OP2, OP3) on the upper surface of the semiconductor layer stack (1TS, 2TS).

[0236] A protective layer (INS) is formed surrounding a first type stack (1TS), having a first opening (OP1) that overlaps with the first part (SEM2_1) in the thickness direction and a second opening (OP2) that overlaps with the second part (SEM2_2) in the thickness direction. The first semiconductor layer (SEM1) is exposed through the first opening (OP1), and the second semiconductor layer (SEM2) is exposed through the second opening (OP2). A protective layer (INS) is formed surrounding a second type stack (2TS), having a third opening (OP3) on the upper surface. The first semiconductor layer (SEM1) is exposed through the third opening (OP3).

[0237] The process of partially removing the insulating material layer can be performed by processes such as dry etching and etch-back, which is anisotropic etching, but is not limited thereto.

[0238] Next, a charging layer (FM) and a connect electrode (CNE) are formed (S120 in FIG. 12).

[0239] Referring to FIG. 17, a filling layer (FM) is formed by filling the space between the first type stack (1TS) and the second type stack (2TS) with an insulating filling material. The filling layer (FM) can be formed by applying using a solution process such as inkjet printing and patterning through an exposure process. The filling layer (FM) reduces the step difference between the first type stack (1TS) and the second type stack (2TS) and lowers the difficulty of manufacturing the subsequent connect electrode (CNE).

[0240] Referring to FIG. 18, for example, an electrode material layer is laminated on the front surface of a base substrate (BSUB) to cover the upper surface of a first type stack (ITS) and a second type stack (2TS), and then a portion of the electrode material layer is etched through an etching process to form a connect electrode (CNE) that connects a second semiconductor layer (SEM2) exposed by a second opening (OP2) of the first type stack (1TS) and a first semiconductor layer (SEM1) exposed by a third opening (OP3) of the second type stack (2TS). The first type stack (1TS) and the second type stack (2TS) are connected in series by the connect electrode (CNE).

[0241] Next, a contact electrode (CTE) and a non-contact electrode (DE) are formed (S130 in FIG. 12).

[0242] Referring to FIG. 19, a contact electrode (CTE) electrically connected to a first semiconductor layer (SEM1) is formed on the first opening (OP1) of the first type stack (ITS). A non-contact electrode (DE) is formed on the protective layer (INS) of the second type stack (2TS).

[0243] For example, a mask covering the upper surface of a connect electrode (CME) is formed, and then, an electrode material layer is laminated on the front surface of a base substrate (BSUB) to cover the upper surfaces of a first type stack (ITS) and a second type stack (2TS), and then a portion of the electrode material layer is etched through an etching process. In this way, a contact electrode (CTE) is formed on the first type stack (1TS), and a non-contact electrode (DE) is formed on the second type stack (2TS).

[0244] Since the non-contact electrode (DE) can be formed at the same height when forming the contact electrode (CTE), the number of process steps can be reduced compared to a process where the non-contact electrode (DE) is formed at a different height when forming the contact electrode (CTE).

[0245] Thus, the first type stack (1TS) becomes the first type light-emitting element (LE1T) and the second type stack (2TS) becomes the second type light-emitting element (LE2T).

[0246] Next, a bonding electrode (BOD) is formed, and light-emitting elements (LE1T, LE2T) are transferred onto the pixel electrode (PXE2) of the circuit board. (S140 of FIG. 12)

[0247] Referring to FIG. 20, an electrode material layer for a bonding electrode is laminated on the front surface of a base substrate (BSUB) to cover a first type light-emitting element (LE1T) and a second type light-emitting element (LE2T), and then a portion of the electrode material layer is etched through an etching process. In this way, a bonding electrode (BOD) can be formed by overlapping a contact electrode (CTE) and a non-contact electrode (DE).

[0248] Referring to FIG. 21, a first type light-emitting element (LE1T) and a second type light-emitting element (LE2T) can be separated from a base substrate (BSUB).

[0249] The process of separating the base substrate (BSUB) can be performed, for example, by a laser lift-off (LLO) process. The laser lift-off process uses a laser, and a KrF excimer laser (248 nm wavelength) can be used as the source, but is not limited thereto. By irradiating the base substrate (BSUB) with a laser, the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T) can be separated from the base substrate (BSUB).

[0250] Referring to FIGS. 22 and 23, a first type light-emitting element (LE1T) and a second type light-emitting element (LE2T) are placed on a pixel electrode (PXE2), and heat and pressure are applied to a bonding electrode (BOD) to bond the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T) onto the pixel electrode (PXE2).

[0251] Next, a common electrode in contact with the second type light-emitting element (LE2T) is formed. (S150 in FIG. 12)

[0252] Referring to FIG. 24, a third organic layer (190) is formed on a substrate (110) to which a first type light-emitting element (LE1T) and a second type light-emitting element (LE2T) are bonded. The third organic layer (190) can fill the space between the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T) and can be formed to cover both the first type light-emitting element (LE1T) and the second type light-emitting element (LE2T).

[0253] A mask is used to form a fourth opening (OP4) in the third organic layer (190) that overlaps with the second type light-emitting element (LE2T). At least a portion of the second semiconductor layer (SEM2) of the second type light-emitting element (LE2T) may be exposed by the fourth opening (OP4). The common electrode (CE) does not come into direct contact with the first type light-emitting element (LE1T).

[0254] Referring to FIG. 25, the common electrode (CE) covers the first type light-emitting element (LE1T), the second type light-emitting element (LE2T), and the third organic layer (190), and can be formed to be in direct contact with the second type light-emitting element (LE2T) through the fourth opening (OP4). The common electrode (CE) can be formed along the irregularities on the upper surface of the third semiconductor (SEM3) of the light-emitting element (LE). The common electrode (CE) can be formed continuously over the entire display area.

[0255] Subsequently, as shown in FIGS. 6 and 7, a capping layer, a partition, a wavelength conversion layer, a light transmission layer, and a color filter layer are formed sequentially.

[0256] FIG. 26 is an example drawing showing a smart watch including a display device according to one embodiment.

[0257] Referring to FIG. 26, a display device (10_1) according to one embodiment can be applied to a smart watch (1000_1), which is one of the smart devices.

[0258] FIGS. 27 and FIGS. 28 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0259] Referring to FIGS. 27 and 28, a head-mounted display device (1000_2) according to one embodiment includes a first display device (10_2), a second display device (10_3), a display device storage unit (1100), a storage unit cover (1200), a first eyepiece (1210), a second eyepiece (1220), a head-mounted band (1300), a middle frame (1400), a first optical member (1510), a second optical member (1520), and a control circuit board (1600).

[0260] The first display device (10_2) provides an image to the user's left eye, and the second display device (10_3) provides an image to the user's right eye. Since each of the first display device (10_2) and the second display device (10_3) is substantially the same as the display device (10) described in conjunction with FIG. 1 and FIG. 2, the description of the first display device (10_2) and the second display device (10_3) is omitted.

[0261] The first optical member (1510) may be positioned between the first display device (10_2) and the first eyepiece (1210). The second optical member (1520) may be positioned between the second display device (10_3) and the second eyepiece (1220). Each of the first optical member (1510) and the second optical member (1520) may include at least one convex lens.

[0262] The middle frame (1400) is positioned between the first display device (10_2) and the control circuit board (1600), and may be positioned between the second display device (10_3) and the control circuit board (1600). The middle frame (1400) serves to support and fix the first display device (10_2), the second display device (10_3), and the control circuit board (1600).

[0263] The control circuit board (1600) may be placed between the middle frame (1400) and the display device housing (1100). The control circuit board (1600) may be connected to the first display device (10_2) and the second display device (10_3) through a connector. The control circuit board (1600) may convert an image source input from the outside into digital video data (DATA) and transmit the digital video data (DATA) to the first display device (10_2) and the second display device (10_3) through the connector.

[0264] The control circuit board (1600) can transmit digital video data (DATA) corresponding to a left-eye image optimized for the user's left eye to the first display device (10_2) and digital video data (DATA) corresponding to a right-eye image optimized for the user's right eye to the second display device (10_3). Alternatively, the control circuit board (1600) can transmit the same digital video data (DATA) to the first display device (10_2) and the second display device (10_3).

[0265] The display device housing (1100) serves to house the first display device (10_2), the second display device (10_3), the middle frame (1400), the first optical member (1510), the second optical member (1520), and the control circuit board (1600). The housing cover (1200) is positioned to cover an open side of the display device housing (1100). The housing cover (1200) may include a first eyepiece (1210) in which the user's left eye is positioned and a second eyepiece (1220) in which the user's right eye is positioned. Although FIGS. 37 and 38 illustrate the first eyepiece (1210) and the second eyepiece (1220) being positioned separately, the embodiments of this specification are not limited thereto. The first eyepiece (1210) and the second eyepiece (1220) may be combined into one.

[0266] The first eyepiece (1210) is aligned with the first display device (10_2) and the first optical member (1510), and the second eyepiece (1220) can be aligned with the second display device (10_3) and the second optical member (1520). Accordingly, the user can view an image of the first display device (10_2) magnified into a virtual image by the first optical member (1510) through the first eyepiece (1210), and can view an image of the second display device (10_3) magnified into a virtual image by the second optical member (1520) through the second eyepiece (1220).

[0267] The head mounting band (1300) serves to secure the display device storage unit (1100) to the user's head so that the first eyepiece (1210) and the second eyepiece (1220) of the storage unit cover (1200) can be positioned on the user's left and right eyes, respectively. When the display device storage unit (1200) is implemented as a lightweight and compact unit, the head-mounted display device (1000) may be equipped with an eyeglass frame instead of the head mounting band (800), as shown in FIG. 35.

[0268] In addition, the head-mounted display device (1000) may further be equipped with a battery for supplying power, an external memory slot for storing external memory, an external connection port for receiving video sources, and a wireless communication module. The external connection port may be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0269] FIG. 29 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment. FIG. 29 shows a virtual reality device (1000_3) to which a display device (10_4) according to one embodiment is applied.

[0270] Referring to FIG. 29, a virtual reality device (1000_3) according to one embodiment may be a device in the form of glasses. A virtual reality device (1000_3) according to one embodiment may have a display device (10_4), a left eye lens (10a), a right eye lens (10b), a support frame (20), eyeglass frame legs (30a, 30b), a reflective member (40), and a display device housing (50).

[0271] FIG. 29 illustrates a virtual reality device (1000_3) that is an eyeglass-type display device including eyeglass frame temples (30a, 30b). That is, the virtual reality device (1000_3) according to one embodiment is not limited to that shown in FIG. 29 and can be applied in various forms in various other electronic devices.

[0272] The display device housing (50) may include a display device (10_4) and a reflective member (40). An image displayed on the display device (10_4) may be reflected from the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user can view the virtual reality image displayed on the display device (10_4) through their right eye.

[0273] FIG. 29 illustrates that the display device housing (50) is positioned at the right end of the support frame (20), but the embodiments of this specification are not limited thereto. For example, the display device housing (50) may be positioned at the left end of the support frame (20), in which case the image displayed on the display device (10_4) may be reflected from the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user can view the virtual reality image displayed on the display device (10_4) through the left eye. Alternatively, the display device housing (50) may be positioned at both the left end and the right end of the support frame (20), in which case the user can view the virtual reality image displayed on the display device (10_4) through both the left eye and the right eye.

[0274] FIG. 30 is an exemplary drawing showing an automobile instrument panel and a center fascia including display devices according to one embodiment. FIG. 30 shows an automobile with display devices (10_a, 10_b, 10_c, 10_d, 10_e) according to one embodiment applied.

[0275] Referring to FIG. 30, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to an instrument panel of a vehicle, to a center fascia of a vehicle, or to a Center Information Display (CID) placed on the dashboard of a vehicle. Additionally, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0276] FIG. 31 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0277] Referring to FIG. 31, a display device (10_5) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light simultaneously. Therefore, a user located in front of the transparent display device can not only view the image (IM) displayed on the display device (10_5) but also see an object (RS) or background located on the back of the transparent display device. When the display device (10_5) is applied to a transparent display device, the substrate of the display device (10_5) may include a light-transmitting portion capable of transmitting light or be formed of a material capable of transmitting light.

[0278] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

1. Substrate; Pixel electrodes disposed on the above substrate; A first type light-emitting element having a contact electrode disposed on the pixel electrode and electrically connected to the pixel electrode; A second type light-emitting element having a non-contact electrode disposed on the pixel electrode above; A filling layer filled between the first type light-emitting element and the second type light-emitting element; A connect electrode that serially connects the first type light-emitting element and the second type light-emitting element; and A display device comprising a common electrode disposed on the first type light-emitting element and the second type light-emitting element and electrically connected to the second type light-emitting element.

2. In Paragraph 1, The first type light-emitting element and the second type light-emitting element each include a first semiconductor layer, an active layer, and a second semiconductor layer, and The second semiconductor layer of the first type light-emitting element is divided into a first portion having a first thickness and a second portion having a second thickness thinner than the first thickness, and A display device in which the active layer and the first semiconductor layer of the first type light-emitting element overlap with the first portion.

3. In Paragraph 2, The first type light-emitting element further includes a protective layer that surrounds the sides of the first semiconductor layer, active layer, and second semiconductor layer of the first type light-emitting element in a planar view, defines a first opening that exposes the first semiconductor layer of the first type light-emitting element, and defines a second opening that exposes the second semiconductor layer of the first type light-emitting element in the second portion. A display device comprising a second type light-emitting element, a first semiconductor layer, an active layer, and a second semiconductor layer surrounding the sides of the second type light-emitting element in a planar view, and further including a protective layer defining a third opening that exposes the first semiconductor layer of the second type light-emitting element.

4. In Paragraph 3, The above contact electrode is electrically connected to the first semiconductor layer through the first opening, and A display device in which the above-mentioned connect electrode connects the second semiconductor layer of the first type light-emitting element to the first semiconductor layer of the second type light-emitting element through the second opening and the third opening.

5. In Paragraph 3, The above non-contact electrode is a display device disposed on a protective layer disposed on one surface of the above second type light-emitting element.

6. In Paragraph 2, A display device further comprising an organic layer that covers both the first type light-emitting element and the second type light-emitting element and defines a fourth opening that exposes the second semiconductor layer of the second type light-emitting element.

7. In Paragraph 6, The above common electrode is electrically connected to the second semiconductor layer of the second type light-emitting element exposed through the fourth opening, and is a display device that overlaps with but is spaced apart from the first type light-emitting element in the thickness direction.

8. In Paragraph 2, A display device in which the width of the active layer of the first type light-emitting element is the same as the width of the active layer of the second type light-emitting element.

9. In Paragraph 2, A display device in which the contact electrode and the non-contact electrode are formed at the same height.

10. In Paragraph 1, The above-mentioned charging layer includes an insulating material, but, A display device in which the surface of the above-mentioned filling layer includes a light-reflecting surface or a light-absorbing surface.

11. In Paragraph 1, A display device comprising a first type light-emitting element and a second type light-emitting element, each including a reflective layer that surrounds at least a portion of their sides on a plane.

12. In Paragraph 1, A display device comprising a concave light extraction pattern having a hemispherical or semi-elliptical shape on the upper portion of the first type light-emitting element and the second type light-emitting element.

13. In Paragraph 12, The above common electrode is a display device that contacts the above concave light extraction pattern of a second type light-emitting element.

14. Substrate; A first pixel electrode and a second pixel electrode spaced apart from each other and disposed on the substrate; A first type light-emitting element having a contact electrode disposed on the first pixel electrode and electrically connected to the pixel electrode; A bonding electrode disposed between the first pixel electrode and the contact electrode; A second type light-emitting element disposed on the second pixel electrode; A filling layer filled between the first type light-emitting element and the second type light-emitting element; A connect electrode that serially connects the first type light-emitting element and the second type light-emitting element; and It includes a common electrode disposed on the first type light-emitting element and the second type light-emitting element and electrically connected to the second type light-emitting element, A display device in which the height of the second pixel electrode is equal to the sum of the height of the first pixel electrode, the height of the bonding electrode, and the height of the contact electrode.

15. In Paragraph 14, The first type light-emitting element and the second type light-emitting element each include a first semiconductor layer, an active layer, and a second semiconductor layer, and The second semiconductor layer of the first type light-emitting element is divided into a first portion having a first thickness and a second portion having a second thickness thinner than the first thickness, and A display device in which the active layer and the first semiconductor layer of the first type light-emitting element overlap with the first portion.

16. In Paragraph 15, The above contact electrode is electrically connected to the first semiconductor layer of the first type light-emitting element, and The above-mentioned connect electrode is a display device that connects the second semiconductor layer of the second part of the first type light-emitting element and the first semiconductor layer of the second type light-emitting element.

17. In Paragraph 15, The organic layer further includes an opening that covers both the first type light-emitting element and the second type light-emitting element and exposes the second semiconductor layer of the second type light-emitting element. A display device in which the above common electrode is electrically connected to the second semiconductor layer of the second type light-emitting element and overlaps with the first type light-emitting element in the thickness direction but is spaced apart.

18. In Paragraph 15, A display device in which the width of the active layer of the first type light-emitting element is the same as the width of the active layer of the second type light-emitting element.

19. In Paragraph 14, A display device wherein the above-mentioned charging layer comprises an insulating material, and the surface of the above-mentioned charging layer is a light-reflecting surface or a light-absorbing surface.

20. Includes a display device, The above display device is, Substrate; Pixel electrodes disposed on the above substrate; A first type light-emitting element having a contact electrode disposed on the pixel electrode and electrically connected to the pixel electrode; A second type light-emitting element having a non-contact electrode disposed on the pixel electrode above; A filling layer filled between the first type light-emitting element and the second type light-emitting element; A connect electrode that serially connects the first type light-emitting element and the second type light-emitting element; and An electronic device comprising a common electrode disposed on the first type light-emitting element and the second type light-emitting element and electrically connected to the second type light-emitting element.

Images