Buck-boost power converter and control method

Abstract

An apparatus includes a clock generator configured to generate a set signal fed into a set input of a latch, an error amplifier configured to generate a COMP signal, an offset generator configured to generate different offset voltages, and a comparator configured to generate a reset signal fed into a reset input of the latch, wherein a non-inverting input of the comparator is configured to receive a signal equal to a sum of a current sense signal and a slope compensation signal, and wherein the current sense signal is equal to a current flowing through a power converter times an adjustable gain, and an inverting input of the comparator is configured to receive an error signal, and wherein the error signal is equal to the COMP signal minus an offset voltage generated by the offset generator.

Description

BUCK-BOOST POWER CONVERTER AND CONTROL METHOD CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims priority to, and specifically, is a continuation of, U.S. Application No.18 / 889,133, filed on September 18, 2024, and entitled “Buck-Boost Power Converter and Control Method,” which is hereby incorporated by reference herein as if reproduced in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates generally to the field of power converters, and in particular embodiments, to techniques and mechanisms for a buck-boost power converter. BACKGROUND

[0003] A power converter transforms an input voltage into a regulated output voltage and delivers the required current to an external load, such as integrated circuits. Power converters can be classified into two types: isolated and non-isolated, based on whether a transformer is used. Isolated power converters utilize various topologies, including flyback, forward, half-bridge, full-bridge, push- pull, and inductor-inductor-capacitor (LLC) resonant converters. Similarly, non-isolated power converters employ topologies such as buck, boost, buck-boost converters, linear regulators, and their combinations.

[0004] As the demand for battery-powered applications has increased, there is a growing need for converters that can generate a regulated output voltage from an input voltage that may be higher, equal to, or lower than the output voltage. For instance, in a battery-powered system, a fresh battery may provide a voltage higher than the output voltage of a power converter, while a depleted battery may provide a voltage lower than the output voltage of the power converter. Buck-boost converters have proven to be an efficient solution for delivering a tightly regulated output voltage across a wide input voltage range. These converters can generate an output voltage either higher or lower than the input voltage by operating in different modes. Specifically, the buck-boost converter operates in a buck operating mode when the input voltage exceeds the output voltage. The buck-boost converter operates in in a boost operating mode when the input voltage is lower than the output voltage. The buck-boost converter operates in in a buck-boost operating mode when the input voltage is approximately equal to the output voltage.

[0005] Control schemes like peak current mode control allow power converters to regulate the output effectively. This method uses both voltage and current feedback to control the peak inductor current during each switching cycle. The output voltage is compared to a reference, generating an error signal that sets the peak current threshold. Once the inductor current reaches this threshold, the high-side 2024-064-A-WO -1-switch turns off. This process repeats for each cycle. This approach offers faster transient response, simpler compensation design, and improved current limiting compared to voltage-mode control. However, at high duty cycles, it may become unstable, requiring slope compensation for proper operation.

[0006] In buck-boost converters using peak current mode control, the error signal temporarily drops during a transition between two different operating modes. The COMP signal, responsible for stabilization, cannot quickly adjust through a standard feedback and compensation circuit, leading to instability in the output voltage during operating mode transitions. An apparatus or method that allows a smooth operating mode transition in four-switch buck-boost converters with peak current mode control would be highly beneficial, and this disclosure addresses that need. SUMMARY

[0007] Technical advantages are generally achieved, by embodiments of this disclosure which describe a buck-boost power converter.

[0008] In accordance with an embodiment, an apparatus comprises a clock generator configured to generate a set signal fed into a set input of a latch, an error amplifier configured to generate a COMP signal, an offset generator configured to generate different offset voltages in response to different operating modes, and a comparator configured to generate a reset signal fed into a reset input of the latch, wherein a non-inverting input of the comparator is configured to receive a signal equal to a sum of a current sense signal and a slope compensation signal, and wherein the current sense signal is equal to a current flowing through a power converter times an adjustable gain, and an inverting input of the comparator is configured to receive an error signal, and wherein the error signal is equal to the COMP signal minus an offset voltage generated by the offset generator.

[0009] In accordance with another embodiment, a system comprises a four-switch buck-boost converter comprising a first high-side switch, a first low-side switch, a second high-side switch, a second low-side switch and an inductor, and a controller configured to generate four gate drive signals for controlling four switches of the four-switch buck-boost converter, respectively, wherein the controller comprises a clock generator configured to generate a set signal fed into a set input of a latch, an error amplifier configured to generate a COMP signal, an offset generator configured to generate different offset voltages, and a comparator configured to generate a reset signal fed into a reset input of the latch, wherein a non-inverting input of the comparator is configured to receive a signal equal to a sum of a current sense signal and a slope compensation signal, and wherein the current sense signal is equal to a current flowing through the inductor times an adjustable gain, and an inverting input of the comparator is configured to receive an error signal, and wherein the error signal is equal to the COMP signal minus an offset voltage generated by the offset generator. 2024-064-A-WO -2-

[0010] In accordance with yet another embodiment, a method comprises feeding a clock signal into a set input of a latch, generating a COMP signal based on a comparison between a detected output voltage signal and a predetermined reference, in response to an operating mode of a four-switch buck- boost converter, subtracting a corresponding offset voltage from the COMP signal to obtain an error signal, generating a reset signal based on a comparison between the error signal and a current signal, wherein the current signal is equal to a sum of a current sense signal generated by a variable gain amplifier and a slope compensation signal, and based on an output signal of the latch, generating four gate drive signals for controlling four switches of the four-switch buck-boost converter, respectively.

[0011] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 illustrates a block diagram of a power converter in accordance with various embodiments of the present disclosure;

[0014] Figure 2 illustrates a schematic diagram of a four-switch buck-boost converter with peak current mode control in accordance with various embodiments of the present disclosure;

[0015] Figure 3 illustrates the variation of the error signal under different operating modes in accordance with various embodiments of the present disclosure;

[0016] Figure 4 illustrates various waveforms associated with the buck operating mode of the four-switch buck-boost converter in accordance with various embodiments of the present disclosure;

[0017] Figure 5 illustrates various waveforms associated with the buck-boost operating mode of the four-switch buck-boost converter in accordance with various embodiments of the present disclosure;

[0018] Figure 6 illustrates various waveforms associated with the boost operating mode of the four-switch buck-boost converter in accordance with various embodiments of the present disclosure; 2024-064-A-WO -3-

[0019] Figure 7 illustrates a schematic diagram of a four-switch buck-boost converter and a peak current mode controller in accordance with various embodiments of the present disclosure;

[0020] Figure 8 illustrates the variations of the COMP signal and the error signal under different operating modes in accordance with various embodiments of the present disclosure; and

[0021] Figure 9 illustrates a flow chart of a method for controlling the four-switch buck-boost converter shown in Figure 7 in accordance with various embodiments of the present disclosure.

[0022] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0023] The making and using of embodiments of this disclosure are discussed in detail below. It should be appreciated, however, that the concepts disclosed herein can be embodied in a wide variety of specific contexts, and that the specific embodiments discussed herein are merely illustrative and do not serve to limit the scope of the claims. Further, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0024] Further, one or more features from one or more of the following described embodiments may be combined to create alternative embodiments not explicitly described, and features suitable for such combinations are understood to be within the scope of this disclosure. It is therefore intended that the appended claims encompass any such modifications or embodiments.

[0025] The present disclosure will be described with respect to embodiments in a specific context, namely a four-switch buck-boost power converter. The disclosure may also be applied, however, to a variety of power converters. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.

[0026] Figure 1 illustrates a block diagram of a power converter in accordance with various embodiments of the present disclosure. The power converter 100 is connected between an input volage bus VINand an output voltage bus VOUT. In some embodiments, the power converter 100 is a four-switch buck-boost converter. Throughout the description, the power converter 100 may be alternatively referred to as a four-switch buck-boost converter. A controller 200 is configured to receive an input voltage, an output voltage and a current sense signal IS. Based on the received signals, the controller 200 is able to generate four gate drive signals GA, GB, GCand GDfor controller the four switches of the power converter 100, respectively. 2024-064-A-WO -4-

[0027] In some embodiments, the power converter 100 comprises a first high-side switch, a first low-side switch, a second high-side switch, a second low-side switch, an inductor and a current sense device. In some embodiments, the current sense device is implemented as a current sense resistor. The first high-side switch and the first low-side switch are connected in series between VINand ground. The second high-side switch and the second low-side switch are connected in series between VOUT and ground. The inductor and the current sense device are connected in series between a common node of the first high-side switch and the first low-side switch, and a common node of the second high-side switch and the second low-side switch.

[0028] In some embodiments, the controller 200 comprises a clock generator, an error amplifier, an offset generator and a comparator. The clock generator is configured to generate a set signal fed into a set input of a latch. The error amplifier is configured to generate a COMP signal. The offset generator is configured to generate different offset voltages. The comparator is configured to generate a reset signal fed into a reset input of the latch. A non-inverting input of the comparator is configured to receive a signal equal to a sum of a current sense signal and a slope compensation signal. The current sense signal is equal to a current flowing through the inductor times an adjustable gain. An inverting input of the comparator is configured to receive an error signal. The error signal is equal to the COMP signal minus an offset voltage generated by the offset generator. More particularly, in a buck operating mode of the power converter 100, the offset voltage is set to zero. The error signal is equal to the COMP signal. In a buck- boost operating mode of the power converter 100, the error signal is equal to the COMP signal minus a first offset voltage generated by the offset generator. In a boost operating mode of the power converter 100, the error signal is equal to the COMP signal minus a sum of a first offset voltage and a second offset voltage generated by the offset generator.

[0029] The power converter 100 further comprises a variable gain amplifier. The variable gain amplifier is employed to amplify the current sense signal to a level that can be processed by the controller 200. In some embodiments, the variable gain amplifier is integrated with the controller 200. In alternative embodiments, the variable gain amplifier is a separate device located outside the controller 200.

[0030] A non-inverting input of the variable gain amplifier is connected to a first terminal of the current sense resistor. An inverting input of the variable gain amplifier is connected to a second terminal of the current sense resistor. An output of the variable gain amplifier is configured to generate the current sense signal.

[0031] The controller 200 further comprises a control logic unit. An input of the control logic unit is connected to an output of the latch. The control logic unit is configured to generate the four gate drive signals GA, GB, GCand GDfor controlling four switches of the power converter 100, respectively. Furthermore, the control logic unit is configured to receive an input voltage and an output voltage of the 2024-064-A-WO -5-power converter 100. Based on the received input and output voltages, the control logic unit is able to generate a first control signal indicative of a buck-boost operating mode of the power converter 100 and a second control signal indicative of a boost operating mode of the power converter 100.

[0032] The offset generator comprises a first offset processing unit and a first control switch connected in series, and a second offset processing unit and a second control switch connected in series. The first offset processing unit is configured to receive the output voltage and generate a first offset voltage. The second offset processing unit is configured to receive the output voltage and generate a second offset voltage.

[0033] The power converter 100 is configured to operate in three different operating modes. According to the voltage transfer function of each operating mode, the error signal comprises three variables including the current flowing through the inductor, the output voltage and a constant. By applying different current sense gains, the current variable can be excluded from the error signal. Once the current variable is removed, the error signal is simplified to only include the output voltage and the constant. As a result, an ideal error signal can be achieved by subtracting an offset voltage from the COMP signal during transitions between operating modes.

[0034] In operation, in response to a buck operating mode of the four-switch buck-boost converter, the variable gain amplifier is configured to amplify the current flowing through the inductor to generate a first amplified current sense signal having a first gain. In response to a buck-boost operating mode of the four-switch buck-boost converter, the variable gain amplifier is configured to amplify the current flowing through the inductor to generate a second amplified current sense signal having a second gain. In response to a boost operating mode of the four-switch buck-boost converter, the variable gain amplifier is configured to amplify the current flowing through the inductor to generate a third amplified current sense signal having a third gain.

[0035] In operation, in response to the buck operating mode of the power converter 100, both the first control switch and the second control switch are turned off. As a result of turning off both the first control switch and the second control switch, the error signal fed into the comparator is equal to the COMP signal generated by the error amplifier. In response to the buck-boost operating mode of the power converter 100, the first control switch is turned on and the second control switch is turned off. As a result of turning on the first control switch and turning off the second control switch, the first offset voltage is subtracted from the COMP signal to obtain the error signal fed into the comparator. In response to the boost operating mode, both the first control switch and the second control switch are turned on. As a result of turning on both the first control switch and the second control switch, a sum of the first offset voltage and the second offset voltage is subtracted from the COMP signal to obtain the error signal fed into the comparator. 2024-064-A-WO -6-

[0036] Figure 2 illustrates a schematic diagram of a four-switch buck-boost converter with peak current mode control in accordance with various embodiments of the present disclosure. The four-switch buck-boost converter 100 comprises an input capacitor CIN, a first high-side switch SWA, a first low-side switch SWB, a second low-side switch SWC, a second high-side switch SWD, an inductor and a current sense resistor RS and an output capacitor CO.

[0037] A dc voltage source is connected between an input voltage bus VINand ground. The input capacitor CINis connected in parallel with the dc voltage source. A load 106 is connected between an output voltage bus VOUT and ground. The output capacitor CO is connected in parallel with the load 106.

[0038] The first high-side switch SWA and the first low-side switch SWB are connected in series between VIN and ground. The first high-side switch SWA is controlled by a gate drive signal GA. The first low-side switch SWB is controlled by a gate drive signal GB. The second high-side switch SWD and the second low-side switch SWC are connected in series between VOUT and ground. The second high-side switch SWD is controlled by a gate drive signal GD. The second low-side switch SWC is controlled by a gate drive signal GC. The inductor and the current sense resistor RS are connected in series between a common node of the first high-side switch SWA and the first low-side switch SWB, and a common node of the second high-side switch SWD and the second low-side switch SWC.

[0039] In some embodiments, the controller 200 is a peak current mode PWM controller. As shown in Figure 2, the controller 200 comprises a feedback control unit 202, a comparator 206, a summing point 216, a slope compensation unit 208, a clock generator 210, a latch 212 and a control logic unit 214.

[0040] The feedback control unit 202 comprises an error amplifier 204 and a compensation network. The compensation network comprises one resistor R3 and two capacitors C1, C2. The compensation network can create both a zero and a pole in the frequency response of the power converter 100. As shown in Figure 2, the resistor R3 is connected in series with the capacitor C2 to form a series RC network. The capacitor C1 is connected in parallel with the series RC network. This compensation network is employed to stabilize the feedback loop of the power converter 100 by appropriately placing the zero and pole in the complex plane.

[0041] As shown in Figure 2, an inverting input of the error amplifier 204 is connected to the output of the power converter 100 through a resistor divider formed by R1 and R2. A non-inverting input of the error amplifier 204 is configured to receive a predetermined reference VREF. The error amplifier 204 is configured to generate a COMP signal VCOMP.

[0042] A current sense amplifier 104 has inputs connected to the terminals of the current sense resistor RS, respectively. The current sense amplifier 104 is configured to generate a current sense signal 2024-064-A-WO -7-IS. ISis equal to IL×KP. ILis the current flowing through the inductor of the power converter. KPis a predetermined current sense gain.

[0043] At the summing point 216, the current sense signal ISand a slope compensation signal CSLOgenerated by the slope compensation unit 208 are added together and further fed into a non-inverting input of the comparator 206. An inverting input of the comparator 206 is configured to receive an error signal VER. In some embodiments, as shown in Figure 2, the error signal VERis equal to the COMP signal VCOMP.

[0044] In operation, the clock signal CLK generated by the clock generator 210 is fed into the set input of the latch 212 to set the latch 212. Once the non-inverting input of the comparator 206 exceeds the inverting input of the comparator 206, the comparator 206 generates a logic high signal to reset the latch 212. The latch 212 generates a PWM signal DON fed into the control logic 214. Based on the PWM signal DON and the input and output voltages of the power converter 100, the control logic unit 214 is configured to generate the four gate drive signals GA, GB, GC and GD for controlling four switches SWA, SWB, SWC and SWD of the power converter 100, respectively.

[0045] Figure 3 illustrates the variation of the error signal under different operating modes in accordance with various embodiments of the present disclosure. The horizontal axis represents the voltage gain of the power converter. M is a ratio of the output voltage VOUT to the input voltage VIN. The vertical axis represents the error signal VER. M1 and M2 are predetermined constants. As shown in Figure 3, M1 is less than 1, and M2 is greater than 1.

[0046] In operation, when M is less than M1, the power converter 100 is configured to operate in a buck operating mode. The error signal VER and M has a linear relationship in the buck operating mode. The error signal in the buck operating mode is denoted as VER_BU(M) as shown in Figure 3.

[0047] In operation, when M is less than M2 and greater than M1, the power converter 100 is configured to operate in a buck-boost operating mode. The error signal VER and M has a linear relationship in the buck-boost operating mode. The error signal in the buck-boost operating mode is denoted as VER_BB(M) as shown in Figure 3. The operating mode transition occurs at M1. At M1, the error signal drops significantly as shown in Figure 3. The voltage drop of the error signal at M1 is denoted as ΔVER1.

[0048] In operation, when M is greater than M2, the power converter 100 is configured to operate in a boost operating mode. The error signal VERand M has a linear relationship in the boost operating mode. The error signal in the boost operating mode is denoted as VER_BO(M) as shown in Figure 3. The operating mode transition occurs at M2. At M2, the error signal drops significantly as shown in Figure 3. The voltage drop of the error signal at M2 is denoted as ΔVER2. 2024-064-A-WO -8-

[0049] Based on the error signal shown in Figure 3, the VER(M) equations under each operating modes will be derived below with respect to Figures 4-6. Based on the VER(M) equations, the voltage drops ΔVER1and ΔVER2can be obtained. After having ΔVER1and ΔVER2, a compensation method can be used to modify the COMP signal. More particularly, during a transition from the buck operating mode to the buck-boost operating mode at M1, ΔVER1 is subtracted from the COMP signal to obtain the starting point of the error signal VER_BB(M). Likewise, during a transition from the buck-boost operating mode to the boost operating mode at M2, a sum of ΔVER1and ΔVER2is subtracted from the COMP signal to obtain the starting point of the error signal VER_BO(M). Such modifications help to achieve an ideal VER(M).

[0050] Figure 4 illustrates various waveforms associated with the buck operating mode of the four-switch buck-boost converter in accordance with various embodiments of the present disclosure. The horizontal axis represents intervals of time. There are eight rows. The first row represents the clock signal CLK. The second row represents the slope compensation signal CSLO. The third row represents the current sense signal KP_BU×IL under the buck operating mode. The fourth row represents the error signal VER_BU and a sum of the current sense signal KP_BU×IL and the slope compensation signal CSLO. The fifth row represents the gate drive signal GA of the first high-side switch SWA. The sixth row represents the gate drive signal GB of the first low-side switch SWB. The seventh row represents the gate drive signal GC of the second low-side switch SWC. The eighth row represents the gate drive signal GD of the second high-side switch SWD.

[0051] In the buck operating mode, the current sense amplifier has a first gain. This gain is denoted as KP_BU. The gate drive signal GA is the same as the PWM signal DON. As shown in Figure 4, the gate drive signal GB is complementary with the gate drive signal GA. The gate drive signal GC is always low, and the gate drive signal GD is always high.

[0052] At t0, when the clock signal CLK triggers the latch 212, the PWM signal DON turns high. In response to the change of the PWM signal DON, the gate drive signal GA turns high, and the gate drive signal GB turns low. Consequently, SWA is turned on, and SWB is turned off. From t0 to t1, the voltage VL across the inductor is equal to the difference between the input voltage and the output voltage. From t0 to t1, this voltage difference magnetizes the inductor so that the current IL flowing through the inductor increases in a linear manner. From t0 to t1, the slope compensation signal CSLOand the current sense signal KP_BU× ILare added together. At t1, when the sum of the slope compensation signal CSLOand the current sense signal KP_BU× ILis greater than the error signal VER_BU, the comparator triggers the latch 212. The PWM signal DONturns low at t1. In response to the change of the PWM signal DON, the gate drive signal GAturns low, and the gate drive signal GBturns high. Consequently, SWAis turned off, and SWBis turned on. At this time, the voltage VLacross the inductor is equal to -1×VOUT. From t1 to t2, the 2024-064-A-WO -9-output voltage demagnetizes the inductor so that the current ILflowing through the inductor decreases in a linear manner.

[0053] Based on the voltage-second balance theory, the equation of the error signal VER_BU(M) can be expressed as: ^^^_^^(^) = ^^_^^ ^^^ + (^^^^^)^^^^ + ^^ ^^^^^^^^^ ^^^ ! (1), buck-boost converter. FSW is the switching frequency of the four-switch buck-boost converter. L is the inductance of the inductor.

[0055] Figure 5 illustrates various waveforms associated with the buck-boost operating mode of the four-switch buck-boost converter in accordance with various embodiments of the present disclosure. The horizontal axis represents intervals of time. There are eight rows. The first row represents the clock signal CLK. The second row represents the slope compensation signal CSLO. The third row represents the current sense signal KP_BB×IL under the buck-boost operating mode. The fourth row represents the error signal VER_BB and a sum of the current sense signal KP_BB×IL and the slope compensation signal CSLO. The fifth row represents the gate drive signal GA of the first high-side switch SWA. The sixth row represents the gate drive signal GB of the first low-side switch SWB. The seventh row represents the gate drive signal GC of the second low-side switch SWC. The eighth row represents the gate drive signal GD of the second high-side switch SWD.

[0056] In the buck-boost operating mode, the current sense amplifier has a second gain. This gain is denoted as KP_BB. The gate drive signal GCis the same as the PWM signal DON. As shown in Figure 5, the gate drive signal GDis complementary with the gate drive signal GC. The leading edge of the gate drive signal GAis aligned with the leading edge of the gate drive signal GC. The gate drive signal GAturns low after a fixed bypass time Tbycounting from the falling edge of the gate drive signal GC. The gate drive signal GBis complementary with the gate drive signal GA.

[0057] At t0, when the clock signal CLK triggers the latch 212, the PWM signal DONturns high. In response to the change of the PWM signal DON, the gate drive signal GCand gate drive signal GAturn high. The gate drive signal GDand the gate drive signal GBturn low. Consequently, SWCand SWAare turned on. SWDand SWBare turned off. From t0 to t1, the voltage VLacross the inductor is equal to the input voltage. The input voltage magnetizes the inductor so that the current ILflowing through the inductor increases in a linear manner. From t0 to t1, the slope compensation signal CSLOand the current sense signal KP_BB× ILare added together. At t1, when the sum of the slope compensation signal CSLOand the current sense signal KP_BB× ILis greater than the error signal VER_BB, the comparator triggers the latch 212. The PWM signal DONturns low. In response to the change of the PWM signal DON, the gate drive 2024-064-A-WO -10-signal GCturns low, and the gate drive signal GDturns high at t1. Consequently, SWCis turned off, and SWDis turned on.

[0058] From t1 to t2, the voltage VLacross the inductor is equal to the difference between the input voltage and the output voltage. From t1 to t2, this voltage difference magnetizes the inductor so that the current IL flowing through the inductor increases in a linear manner. At t2, the fixed bypass time Tby ends. The gate drive signal GAturns low, and the gate drive signal GBturns high. Consequently, SWAis turned off, and SWBis turned on. From t2 to t3, the voltage VLacross the inductor is equal to -VOUT. The output voltage demagnetizes the inductor so that the current IL flowing through the inductor decreases in a linear manner from t2 to t3.

[0059] Based on the voltage-second balance theory, the equation of the error signal V (M)ER_BB can be expressed as: ^^^_^^(^) = ^^_^^ " #^ ^ ^^^%^^^^^^^^^&'() %^^^&'(),%^^^^^^^^^^&'()(^^^ ) + ^^^^^ ^^^^ $ ^^^*^^^&'( − ^(^^^^^)%^^^*^^^&'() −, can 6^^ ×&^^ '( / = 0 × 3 = (3)^^ ^^1 45 ^*6

[0061] Figure 6 illustrates various waveforms associated with the boost operating mode of the four-switch buck-boost converter in accordance with various embodiments of the present disclosure. There are eight rows. The first row represents the clock signal CLK. The second row represents the slope compensation signal CSLO. The third row represents the current sense signal KP_BO×ILunder the boost operating mode. The fourth row represents the error signal VER_BOand a sum of the current sense signal KP_BO×ILand the slope compensation signal CSLO. The fifth row represents the gate drive signal GAof the first high-side switch SWA. The sixth row represents the gate drive signal GBof the first low-side switch SWB. The seventh row represents the gate drive signal GCof the second low-side switch SWC. The eighth row represents the gate drive signal GDof the second high-side switch SWD.

[0062] In the boost operating mode, the current sense amplifier has a third gain. This gain is denoted as KP_BO. The gate drive signal GCis the same as the PWM signal DON. As shown in Figure 6, the gate drive signal GDis complementary with the gate drive signal GC. The gate drive signal GBis always low, and the gate drive signal GAis always high.

[0063] At t0, when the clock signal CLK triggers the latch 212, the PWM signal DONturns high. In response to the change of the PWM signal DON, the gate drive signal GCturns high, and the gate drive 2024-064-A-WO -11-signal GDturns low. Consequently, SWCis turned on, and SWDis turned off. At this time, the voltage VLacross the inductor is equal to the input voltage. From t0 to t1, the input voltage magnetizes the inductor so that the current ILflowing through the inductor increases in a linear manner. From t0 to t1, the slope compensation signal CSLOand the current sense signal KP_BO× ILare added together. At t1, when the sum of the slope compensation signal CSLO and the current sense signal KP_BO × IL is greater than the error signal VER_BO, the comparator triggers the latch 212. The PWM signal DONturns low at t1. In response to the change of the PWM signal DON, the gate drive signal GCturns low, and the gate drive signal GDturns high. Consequently, SWC is turned off, and SWD is turned on. At this time, the voltage VL across the inductor is equal to the difference between the input voltage and the output voltage. From t1 to t2, the difference (VIN-VOUT) demagnetizes the inductor so that the current IL flowing through the inductor decreases in a linear manner.

[0064] Based on the voltage-second balance theory, the equation of the error signal VER_BO(M) can be expressed as: ^^^_^^(^) = ^^_^^ 7 #^ ^^^(^^^^^)^^^^ ^^ ^^^^^^^^^ − ^^^^^ + ^^^ 8 (4), can / ^^ = 0^^1 × 345 = 1 − ^6 (5)

[0066] Referring back to Figure 3, ΔVER1 is the voltage difference between VER_BU(M1) and the VER_BB(M1). According to Equations (1) and (2), ΔVER1 can be expressed as: :^^^^ = ^^^_^^(^^) − ^^^_^^(^^) = ;^^^ + <^^^^& + =^ ^^ ^^^^ (6)

[0067] In Equation (6), ;^can be expressed as: ;^ = A >C?D_^^B ^^^'( − ^^_^^ (7)

[0068] In Equation (6), <^can be expressed as: ^ABCD^^^'( @^^ABCD^^^'( ^^^^&'(F (^^^&'(),@^^^ABCD^^^'( ^^^^&'(F−2024-064-A-WO -12-

[0069] In Equation (6), =^can be expressed as: =^ = ^^_^^ 6B^^^^&'(^*6B − ^^_^^^^ (9)(M2) and the VER_BO(M2). According to equations (2) and (4), ΔVER2 can be expressed as: :^ = ^ ( ) ( ) ^^ ^^^^ ^^_^^ ^^ − ^^^_^^ ^^ = ;^^^ + <^^^^& + =^ ^^^ (10), ;^ = ^^_^^ − >G_^@^^A,CD ^^^^BEA '( (11), F, >? A,CB ^A,CD^^^'( A,CD^^^'(<_^^^ = A,, − >G_^^ HBEA, @^^ ^^^^&'(F^^^BEA,'^^ ^^ ^

[0073] In Equation (10), = can be expressed as:^6 ^^ & ^ , ^^ '( = = ^ (1 − ) − ^ (13)^ ^_^^ ^_^^6 ^*6, ,

[0074] In order to eliminate IOin equations (6) and (10) so as to simplify ΔVER1and ΔVER2, KP_BBand KP_BOcan be defined as: ^*^ &^^ '( ^ = ^ = ^ ^

[0075] Based on equations (6), (7) and (14), ΔV can be simplified as:ER1 :^ = < ^ + = (16)^^^ ^JKL ^^& ^JKL2024-064-A-WO -13-

[0076] In Equation (16), <^JKLcan be expressed as: <^JKL = >?_^^ N^^^AB(^^^^^AB),*^^^AB^^^&'(%^^^&'(*O^^^AB^P)*^^^&'(%^^^^^&'()^^^^^ M^^^AB*^^^&'( − 1 + ^^Q^JKL ^^^ − −, / ^^6^ = 6B^^^^&'(^*6B (19)

[0079] Based on equations (10), (11) and (15), ΔVER2can be simplified as follow: :^ = < ^ + = (20)^^^ ^JKL ^^& ^JKL

[0080] In Equation (20), <^JKLcan be expressed as: <^JKL = >?_^^^^^^^ M 6,^^6,T(^^^^^A,) −

[0081] In Equation (20), = can be expressed as:^JKL=^JKL = ^^ ^ 76,^,^^^^ 6, / ^^6^ − / ^^6^8 (22)

[0082] In Equations (21) and (22), / can be expressed as:^^6^6 ^^ &, ^^ '( / = (23)^^6^ ^*6,

[0083] In order to achieve an ideal error signal during operating mode transitions, a variable gain amplifier is employed to replace the current sense amplifier 104. The variable gain amplifier is able to provide different current sense gains according to Equations (14) and (15). Furthermore, an offset generator is employed to provide ΔV and ΔV .ER1 ER2

[0084] In operation, when M is less than M1, the four-switch buck-boost converter is configured to operate in the buck operating mode. The current sense gain is equal to K . The offset voltage isP_BU equal to zero. The error signal is equal to the COMP signal. 2024-064-A-WO -14-

[0085] In operation, when M is greater than M1 and less than M2, the four-switch buck-boost converter is configured to operate in the buck-boost operating mode. The current sense gain is equal to KP_BBsimas defined by Equation (14). The offset voltage is equal to ΔVER1. The error signal is equal to the COMP signal minus ΔVER1.

[0086] In operation, when M is greater than M2, the four-switch buck-boost converter is configured to operate in the boost operating mode. The current sense gain is equal to KP_BOsimas defined by Equation (15). The offset voltage is equal to a sum of ΔVER1and ΔVER2. The error signal is equal to the COMP signal minus the sum of ΔVER1 and ΔVER2.

[0087] Figure 7 illustrates a schematic diagram of a four-switch buck-boost converter and a peak current mode controller in accordance with various embodiments of the present disclosure. The schematic diagram shown in Figure 7 is similar to that shown in Figure 2 except that a variable gain amplifier 704 is employed to replace the current sense amplifier 104 shown in Figure 2. Furthermore, an offset generator 203 is employed to generate ΔVER1 and ΔVER2. A summing point 218 is also added. At the summing point 218, the offset voltage VOFFSET is subtracted from the COMP signal to achieve the ideal error signal (shown in Figure 8). More particularly, during an operating mode transition from a buck operating mode to a buck-boost operating mode, ΔVER1 is subtracted from the COMP signal to obtain the error signal VER fed into the inverting input of the comparator 206. During an operating mode transition from a buck-boost operating mode to a boost operating mode, a sum of ΔVER1 and ΔVER2 is subtracted from the COMP signal to obtain the error signal VER fed into the inverting input of the comparator 206.

[0088] The control logic unit 214 has an input connected to an output of the latch 212. In operation, the control logic unit 214 is configured to generate four gate drive signals for controlling four switches SWA, SWB, SWC and SWD, respectively. Furthermore, the control logic unit 214 is configured to receive an input voltage VIN and an output voltage VOUT of the four-switch buck-boost converter, and generate a first control signal BB indicative of a buck-boost operating mode of the four-switch buck-boost converter, and a second control signal BO indicative of a boost operating mode of the four-switch buck- boost converter.

[0089] The offset generator 203 comprises a first offset processing unit 222, a first control switch S1, a second offset processing unit 224, a second control switch S2 and a summing point 220. As shown in Figure 7, the first offset processing unit 222 and the first control switch S1 are connected in series. The first control switch S1 is controlled by the first control signal BB generated by the control logic unit 214. The second offset processing unit 224 and the second control switch S2 are connected in series. The second control switch S2 is controlled by the second control signal BO generated by the control logic unit 214. 2024-064-A-WO -15-

[0090] As shown in Figure 7, an input of the first offset processing unit 222 is configured to receive the output voltage VOUTof the four-switch buck-boost converter. The output of the first offset processing unit 222 is configured to generate a first offset voltage ΔVER1according to Equation (16). The output of the first offset processing unit 222 is connected to a first input of the summing point 220 through the first control switch S1. An input of the second offset processing unit 224 is configured to receive the output voltage VOUTof the four-switch buck-boost converter. An output of the second offset processing unit 224 is configured to generate a second offset voltage ΔVER2according to Equation (20). The output of the second offset processing unit 224 is connected to a second input of the summing point 220 through the second control switch S2.

[0091] In operation, in response to a buck operating mode of the four-switch buck-boost converter, both the first control switch S1 and the second control switch S2 are turned off. As a result of turning off both the first control switch S1 and the second control switch S2, the offset voltage VOFFSET generated by the offset generator 203 is equal to zero. The error signal VER is equal to the COMP signal.

[0092] In operation, in response to a buck-boost operating mode of the four-switch buck-boost converter, the first control switch S1 is turned on and the second control switch S2 is turned off. As a result of turning on the first control switch S1 and turning off the second control switch S2, the offset voltage VOFFSET generated by the offset generator 203 is equal to the first offset voltage ΔVER1. The first offset voltage ΔVER1 is subtracted from the COMP signal to obtain the error signal VER in the buck-boost operating mode.

[0093] In operation, in response to a boost operating mode of the four-switch buck-boost converter, both the first control switch S1 and the second control switch S2 are turned on. As a result of turning on both the first control switch S1 and the second control switch S2, the offset voltage VOFFSET generated by the offset generator 203 is equal to a sum of the first offset voltage ΔVER1 and the second offset voltage ΔVER2. The sum of the first offset voltage ΔVER1 and the second offset voltage ΔVER2 is subtracted from the COMP signal to obtain the error signal in the boost operating mode.

[0094] The variable gain amplifier 704 has a non-inverting input connected to a first terminal of the current sense resistor RS, an inverting input connected to a second terminal of the current sense resistor RS, and an output configured to generate the current sense signal IS. As shown in Figure 7, the variable gain amplifier 704 is controlled by the first control signal BB and the second control signal BO. The first control signal BB and the second control signal BO are configured such that the variable gain amplifier 704 is able to generate three different gains in response to three different operating modes.

[0095] In operation, in response to the buck operating mode of the four-switch buck-boost converter, the variable gain amplifier 704 is configured to amplify the current flowing through current 2024-064-A-WO -16-sense resistor RSto generate a first amplified current sense signal having a first gain. The first gain is KP_BU.

[0096] In operation, in response to the buck-boost operating mode of the four-switch buck-boost converter, the variable gain amplifier 704 is configured to amplify the current flowing through current sense resistor RS to generate a second amplified current sense signal having a second gain. The second gain is the current sense gain defined by Equation (14).

[0097] In operation, in response to the boost operating mode of the four-switch buck-boost converter, the variable gain amplifier 704 is configured to amplify the current flowing through current sense resistor RS to generate a third amplified current sense signal having a third gain. The third gain is the current sense gain defined by Equation (15).

[0098] Figure 8 illustrates the variations of the COMP signal and the error signal under different operating modes in accordance with various embodiments of the present disclosure. The horizontal axis represents the voltage gain of the power converter. M is a ratio of the output voltage to the input voltage. The vertical axis represents the error signal VER. M1 and M2 are predetermined constants. As shown in Figure 8, M1 is less than 1, and M2 is greater than 1.

[0099] In operation, when M is less than M1, the power converter is configured to operate in a buck operating mode. The error signal VER and M has a linear relationship in the buck operating mode. The error signal in the buck operating mode is denoted as VER_BU(M) as shown in Figure 8. In the buck operating mode, the error signal and the COMP signal overlap each other. The offset is equal to zero.

[0100] In operation, when M is less than M2 and greater than M1, the power converter is configured to operate in a buck-boost operating mode. The error signal VER and M has a linear relationship in the buck-boost operating mode. The error signal in the buck-boost operating mode is denoted as VER_BB(M) as shown in Figure 8. In the buck-boost operating mode, there is a voltage drop between the COMP signal and error signal. The voltage drop is equal to ΔVER1.

[0101] In operation, when M is greater than M2, the power converter is configured to operate in a boost operating mode. The error signal VER and M has a linear relationship in the boost operating mode. The error signal in the boost operating mode is denoted as VER_BO(M) as shown in Figure 8. In the boost operating mode, there is a voltage drop between the COMP signal and error signal. The voltage drop is equal to a sum of ΔVER1and ΔVER2.

[0102] In order to achieve an ideal error signal, in the buck-boost operating mode, ΔVER1is subtracted from the COMP signal to obtain the ideal error signal. Likewise, in the boost operating mode, a sum of ΔVER1and ΔVER2is subtracted from the COMP signal to obtain the ideal error signal.

[0103] Figure 9 illustrates a flow chart of a method for controlling the four-switch buck-boost converter shown in Figure 7 in accordance with various embodiments of the present disclosure. This 2024-064-A-WO -17-flowchart shown in Figure 9 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps illustrated in Figure 9 may be added, removed, replaced, rearranged and repeated.

[0104] At step 902, a clock signal is fed into a set input of a latch.

[0105] At step 904, a COMP signal is generated based on a comparison between a detected output voltage signal and a predetermined reference.

[0106] At step 906, in response to an operating mode of a four-switch buck-boost converter, a corresponding offset voltage is subtracted from the COMP signal to obtain an error signal.

[0107] At step 908, a reset signal is generated based on a comparison between the error signal and a current signal, wherein the current signal is equal to a sum of a current sense signal generated by a variable gain amplifier and a slope compensation signal.

[0108] At step 910, based on an output signal of the latch, four gate drive signals for controlling four switches of the four-switch buck-boost converter, respectively are generated.

[0109] The offset generator comprises a first offset processing unit, a first control switch, a second offset processing unit and a second control switch, and wherein the first offset processing unit and the first control switch are connected in series, the second offset processing unit and the second control switch are connected in series, an input of the first offset processing unit is configured to receive the output voltage of the power converter, an output of the first offset processing unit is configured to generate a first offset voltage, an input of the second offset processing unit is configured to receive the output voltage of the power converter, and an output of the second offset processing unit is configured to generate a second offset voltage.

[0110] The method further comprises in response to a buck operating mode, turning off both the first control switch and the second control switch, and wherein as a result of turning off both the first control switch and the second control switch, the error signal is equal to the COMP signal in the buck operating mode, in response to a buck-boost operating mode, turning on the first control switch and turning off the second control switch, and wherein as a result of turning on the first control switch and turning off the second control switch, the first offset voltage is subtracted from the COMP signal to obtain the error signal in the buck-boost operating mode, and in response to a boost operating mode, turning on both the first control switch and the second control switch, and wherein as a result of turning on both the first control switch and the second control switch, a sum of the first offset voltage and the second offset voltage is subtracted from the COMP signal to obtain the error signal in the boost operating mode.

[0111] The four-switch buck-boost converter comprises a first high-side switch, a first low-side switch, a second high-side switch, a second low-side switch, an inductor and a current sense resistor, and wherein the inductor and the current sense resistor are connected in series between a common node of the 2024-064-A-WO -18-first high-side switch and the first low-side switch, and a common node of the second high-side switch and the second low-side switch, and the variable gain amplifier has a non-inverting input connected to a first terminal of the current sense resistor, an inverting input connected to a second terminal of the current sense resistor, and an output configured to generate the current sense signal.

[0112] The method further comprises in response to a buck operating mode of the four-switch buck-boost converter, configuring the variable gain amplifier to amplify a current flowing through the current sense resistor to generate a first amplified current sense signal having a first gain, in response to a buck-boost operating mode of the four-switch buck-boost converter, configuring the variable gain amplifier to amplify the current flowing through the current sense resistor to generate a second amplified current sense signal having a second gain, and in response to a boost operating mode of the four-switch buck-boost converter, configuring the variable gain amplifier to amplify the current flowing through the current sense resistor to generate a third amplified current sense signal having a third gain.

[0113] Although the description has been described in detail, it should be understood that various changes, substitutions and alterations can be made without departing from the spirit and scope of this disclosure as defined by the appended claims. Moreover, the scope of the disclosure is not intended to be limited to the particular embodiments described herein, as one of ordinary skill in the art will readily appreciate from this disclosure that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, which may perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. 2024-064-A-WO -19-

Claims

WHAT IS CLAIMED IS:

1. An apparatus comprising: a clock generator configured to generate a set signal fed into a set input of a latch; an error amplifier configured to generate a COMP signal; an offset generator configured to generate different offset voltages; and a comparator configured to generate a reset signal fed into a reset input of the latch, wherein: a non-inverting input of the comparator is configured to receive a signal equal to a sum of a current sense signal and a slope compensation signal, and wherein the current sense signal is equal to a current flowing through a power converter times an adjustable gain; and an inverting input of the comparator is configured to receive an error signal, and wherein the error signal is equal to the COMP signal minus an offset voltage generated by the offset generator.

2. The apparatus of claim 1, wherein the power converter is a four-switch buck-boost converter comprising: a first high-side switch and a first low-side switch connected in series between an input voltage bus and ground; a second high-side switch and a second low-side switch connected in series between an output voltage bus and ground; and an inductor and a current sense resistor connected in series between a common node of the first high-side switch and the first low-side switch, and a common node of the second high-side switch and the second low-side switch.

3. The apparatus of claim 2, further comprising: a variable gain amplifier having a non-inverting input connected to a first terminal of the current sense resistor, an inverting input connected to a second terminal of the current sense resistor, and an output configured to generate the current sense signal.

4. The apparatus of claim 3, wherein: in response to a buck operating mode of the power converter, the variable gain amplifier is configured to amplify the current flowing through the power converter to generate a first amplified current sense signal having a first gain; in response to a buck-boost operating mode of the power converter, the variable gain amplifier is configured to amplify the current flowing through the power converter to generate a second amplified current sense signal having a second gain; and 2024-064-A-WO -20-in response to a boost operating mode of the power converter, the variable gain amplifier is configured to amplify the current flowing through the power converter to generate a third amplified current sense signal having a third gain.

5. The apparatus of any one of claims 1-4, further comprising: a control logic unit having an input connected to an output of the latch, wherein the control logic unit is configured to generate four gate drive signals for controlling four switches of the power converter, respectively.

6. The apparatus of claim 5, wherein: the control logic unit is configured to receive an input voltage and an output voltage of the power converter, and generate a first control signal indicative of a buck-boost operating mode of the power converter and a second control signal indicative of a boost operating mode of the power converter.

7. The apparatus of claim 6, wherein: the offset generator comprises a first offset processing unit, a first control switch, a second offset processing unit, a second control switch and a summing point, and wherein: the first offset processing unit and the first control switch are connected in series, wherein the first control switch is controlled by the first control signal generated by the control logic unit; the second offset processing unit and the second control switch are connected in series, wherein the second control switch is controlled by the second control signal generated by the control logic unit; an input of the first offset processing unit is configured to receive the output voltage of the power converter; an output of the first offset processing unit is configured to generate a first offset voltage, and wherein the output of the first offset processing unit is connected to a first input of the summing point through the first control switch; an input of the second offset processing unit is configured to receive the output voltage of the power converter; and an output of the second offset processing unit is configured to generate a second offset voltage, and wherein the output of the second offset processing unit is connected to a second input of the summing point through the second control switch. 2024-064-A-WO -21-8. The apparatus of claim 7, wherein: in response to a buck operating mode, both the first control switch and the second control switch are turned off, and wherein as a result of turning off both the first control switch and the second control switch, the error signal is equal to the COMP signal in the buck operating mode; in response to the buck-boost operating mode, the first control switch is turned on and the second control switch is turned off, and wherein as a result of turning on the first control switch and turning off the second control switch, the first offset voltage is subtracted from the COMP signal to obtain the error signal in the buck-boost operating mode; and in response to the boost operating mode, both the first control switch and the second control switch are turned on, and wherein as a result of turning on both the first control switch and the second control switch, a sum of the first offset voltage and the second offset voltage is subtracted from the COMP signal to obtain the error signal in the boost operating mode.

9. The apparatus of any one of claims 1-8, further comprising: a first summing point at which the current sense signal and the slope compensation signal are added together; and a second summing point at which the offset voltage is subtracted from the COMP signal.

10. The apparatus of any one of claims 1-9, wherein: an inverting input of the error amplifier is connected to an output of the power converter through a resistor divider; a non-inverting input of the error amplifier is configured to receive a predetermined reference voltage; and a compensation network is connected between the inverting input of the error amplifier and an output of the error amplifier.

11. A system comprising: a four-switch buck-boost converter comprising a first high-side switch, a first low-side switch, a second high-side switch, a second low-side switch and an inductor; and a controller configured to generate four gate drive signals for controlling four switches of the four-switch buck-boost converter, respectively, wherein the controller comprises: a clock generator configured to generate a set signal fed into a set input of a latch; an error amplifier configured to generate a COMP signal; an offset generator configured to generate different offset voltages; and 2024-064-A-WO -22-a comparator configured to generate a reset signal fed into a reset input of the latch, wherein: a non-inverting input of the comparator is configured to receive a signal equal to a sum of a current sense signal and a slope compensation signal, and wherein the current sense signal is equal to a current flowing through the inductor times an adjustable gain; and an inverting input of the comparator is configured to receive an error signal, and wherein the error signal is equal to the COMP signal minus an offset voltage generated by the offset generator.

12. The system of claim 11, further comprising a current sense resistor, wherein: the first high-side switch and the first low-side switch are connected in series between an input voltage bus and ground; the second high-side switch and the second low-side switch are connected in series between an output voltage bus and ground; and the inductor and the current sense resistor connected in series between a common node of the first high-side switch and the first low-side switch, and a common node of the second high-side switch and the second low-side switch.

13. The system of claim 11, further comprising: a variable gain amplifier having a non-inverting input connected to a first terminal of the current sense resistor, an inverting input connected to a second terminal of the current sense resistor, and an output configured to generate the current sense signal, wherein: in response to a buck operating mode of the four-switch buck-boost converter, the variable gain amplifier is configured to amplify the current flowing through the inductor to generate a first amplified current sense signal having a first gain; in response to a buck-boost operating mode of the four-switch buck-boost converter, the variable gain amplifier is configured to amplify the current flowing through the inductor to generate a second amplified current sense signal having a second gain; and in response to a boost operating mode of the four-switch buck-boost converter, the variable gain amplifier is configured to amplify the current flowing through the inductor to generate a third amplified current sense signal having a third gain.

14. The system of any one of claims 11-13, further comprising: a control logic unit having an input connected to an output of the latch, wherein the control logic unit is configured to generate the four gate drive signals for controlling four switches of the four-switch buck-boost converter, respectively, wherein the control logic unit is configured to receive an input voltage 2024-064-A-WO -23-and an output voltage of the four-switch buck-boost converter, and generate a first control signal indicative of a buck-boost operating mode of the four-switch buck-boost converter and a second control signal indicative of a boost operating mode of the four-switch buck-boost converter.

15. The system of any one of claims 11-14, wherein: the offset generator comprises a first offset processing unit and a first control switch connected in series, and a second offset processing unit and a second control switch connected in series, and wherein: in response to a buck operating mode of the four-switch buck-boost converter, both the first control switch and the second control switch are turned off, and wherein as a result of turning off both the first control switch and the second control switch, the error signal is equal to the COMP signal in the buck operating mode; in response to a buck-boost operating mode of the four-switch buck-boost converter, the first control switch is turned on and the second control switch is turned off, and wherein as a result of turning on the first control switch and turning off the second control switch, a first offset voltage generated by the first offset processing unit is subtracted from the COMP signal to obtain the error signal in the buck-boost operating mode; and in response to a boost operating mode of the four-switch buck-boost converter, both the first control switch and the second control switch are turned on, and wherein as a result of turning on both the first control switch and the second control switch, a sum of the first offset voltage generated by the first offset processing unit and a second offset voltage generated by the second offset processing unit is subtracted from the COMP signal to obtain the error signal in the boost operating mode.

16. A method comprising: feeding a clock signal into a set input of a latch; generating a COMP signal based on a comparison between a detected output voltage signal and a predetermined reference; in response to an operating mode of a four-switch buck-boost converter, subtracting a corresponding offset voltage from the COMP signal to obtain an error signal; generating a reset signal based on a comparison between the error signal and a current signal, wherein the current signal is equal to a sum of a current sense signal generated by a variable gain amplifier and a slope compensation signal; and based on an output signal of the latch, generating four gate drive signals for controlling four switches of the four-switch buck-boost converter, respectively. 2024-064-A-WO -24-17. The method of claim 16, wherein: the offset generator comprises a first offset processing unit, a first control switch, a second offset processing unit and a second control switch, and wherein: the first offset processing unit and the first control switch are connected in series; the second offset processing unit and the second control switch are connected in series; an input of the first offset processing unit is configured to receive the output voltage of the power converter; an output of the first offset processing unit is configured to generate a first offset voltage; an input of the second offset processing unit is configured to receive the output voltage of the power converter; and an output of the second offset processing unit is configured to generate a second offset voltage.

18. The method of claim 17, further comprising: in response to a buck operating mode, turning off both the first control switch and the second control switch, and wherein as a result of turning off both the first control switch and the second control switch, the error signal is equal to the COMP signal in the buck operating mode; in response to a buck-boost operating mode, turning on the first control switch and turning off the second control switch, and wherein as a result of turning on the first control switch and turning off the second control switch, the first offset voltage is subtracted from the COMP signal to obtain the error signal in the buck-boost operating mode; and in response to a boost operating mode, turning on both the first control switch and the second control switch, and wherein as a result of turning on both the first control switch and the second control switch, a sum of the first offset voltage and the second offset voltage is subtracted from the COMP signal to obtain the error signal in the boost operating mode.

19. The method of any one of claims 16-18, wherein: the four-switch buck-boost converter comprises a first high-side switch, a first low-side switch, a second high-side switch, a second low-side switch, an inductor and a current sense resistor, and wherein the inductor and the current sense resistor are connected in series between a common node of the first high-side switch and the first low-side switch, and a common node of the second high-side switch and the second low-side switch; and the variable gain amplifier has a non-inverting input connected to a first terminal of the current sense resistor, an inverting input connected to a second terminal of the current sense resistor, and an output configured to generate the current sense signal. 2024-064-A-WO -25-20. The method of claim 19, further comprising: in response to a buck operating mode of the four-switch buck-boost converter, configuring the variable gain amplifier to amplify a current flowing through the current sense resistor to generate a first amplified current sense signal having a first gain; in response to a buck-boost operating mode of the four-switch buck-boost converter, configuring the variable gain amplifier to amplify the current flowing through the current sense resistor to generate a second amplified current sense signal having a second gain; and in response to a boost operating mode of the four-switch buck-boost converter, configuring the variable gain amplifier to amplify the current flowing through the current sense resistor to generate a third amplified current sense signal having a third gain.

21. The method of any one of claims 16-20, further comprising: generating a first control signal indicative of a buck-boost operating mode of the four-switch buck-boost converter and a second control signal indicative of a boost operating mode of the four-switch buck-boost converter using a control logic unit, wherein the control logic unit is configured to generate the four gate drive signals, receive an input voltage and an output voltage of the four-switch buck-boost converter, and has an input connected to an output of the latch.

22. The method of claim 21, wherein: the first control switch of the offset generator is controlled by the first control signal generated by the control logic unit; and the second control switch the offset generator is controlled by the second control signal generated by the control logic unit; 23. The method of any one of claims 16-22, further comprising generating the COMP signal using an error amplifier, wherein: an inverting input of the error amplifier is connected to an output of the power converter through a resistor divider; a non-inverting input of the error amplifier is configured to receive a predetermined reference voltage; and a compensation network is connected between the inverting input of the error amplifier and an output of the error amplifier. 2024-064-A-WO -26-

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