Safety controller integration

Abstract

Aspects presented herein relate to methods and devices for communication including an apparatus, e.g., a device or vehicle. The apparatus may monitor a set of signals associated with a regulation of the device. The apparatus may also determine, in at least one of a system-in-package (SiP) of the device, a system on-chip (SoC) of the device, or a power management integrated circuit (PMIC) of the device, whether a range for the set of signals is within a threshold range for signals. The apparatus may also output, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals.

Description

Qualcomm Ref. No. 2404558WO 1SAFETY CONTROLLER INTEGRATIONCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Non-Provisional Patent Application Serial No. 18 / 887,755, entitled “SAFETY CONTROLLER INTEGRATION” and filed on September 17, 2024, which is expressly incorporated by reference herein in its entirety.TECHNICAL FIELD

[0002] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for automotive systems.INTRODUCTION

[0003] Computing devices often perform graphics and / or display processing (e.g., utilizing a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones such as smartphones, embedded systems, personal computers, tablet computers, and video game consoles. GPUs are configured to execute a graphics processing pipeline that includes one or more processing stages, which operate together to execute graphics processing commands and output a frame. A central processing unit (CPU) may control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern day CPUs are typically capable of executing multiple applications concurrently, each of which may need to utilize the GPU during execution. A display processor is configured to convert digital information received from a CPU to analog values and may issue commands to a display panel for displaying the visual content. A device that provides content for visual presentation on a display may utilize a GPU and / or a display processor.

[0004] A GPU of a device may be configured to perform the processes in a graphics processing pipeline. Further, a display processor or display processing unit (DPU) may be configured to perform the processes of display processing. However, there has developed an increased need for improved automotive systems.129025-2381WO01Qualcomm Ref. No. 2404558WO 2BRIEF SUMMARY

[0005] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0006] In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a device, a vehicle, a vehicle component, a safety controller, a printed circuit board (PCB), a system-on-chip (SoC), an electronic control unit (ECU), a user equipment (UE), a graphics processing unit (GPU), a central processing unit (CPU), or any apparatus that may perform communication. The apparatus may obtain an indication of a threshold range for signals prior to monitoring a set of signals. The apparatus may also monitor a set of signals associated with a regulation of a device. Additionally, where the set of signals is a set of analog signals, the apparatus may convert or translate the set of analog signals to a set of digital signals prior to the determination. The apparatus may also measure the range of the set of analog signals based on converting or translating the set of analog signals to the set of digital signals. The apparatus may also determine, in at least one of a system-in-package (SiP) of the device, a system on-chip (SoC) of the device, or a power management integrated circuit (PMIC) of the device, whether a range for the set of signals is within a threshold range for signals. Moreover, the apparatus may output, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals.

[0007] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. l is a diagram illustrating an example of a wireless communications system and an access network.

[0009] FIG. 2A is a diagram illustrating an example of a first frame, in accordance with various aspects of the present disclosure.129025-2381WO01Qualcomm Ref. No. 2404558WO 3

[0010] FIG. 2B is a diagram illustrating an example of downlink (DL) channels within a subframe, in accordance with various aspects of the present disclosure.

[0011] FIG. 2C is a diagram illustrating an example of a second frame, in accordance with various aspects of the present disclosure.

[0012] FIG. 2D is a diagram illustrating an example of uplink (UL) channels within a subframe, in accordance with various aspects of the present disclosure.

[0013] FIG. 3 is a diagram illustrating an example of a base station and user equipment (UE) in an access network.

[0014] FIG. 4 is a diagram illustrating example processing for various components.

[0015] FIG. 5 is a diagram illustrating an example of a vehicle performing road object detection.

[0016] FIG. 6 is a diagram illustrating an example of a vehicle performing a map over-the- air process.

[0017] FIG. 7 is a diagram illustrating an example printed circuit board (PCB) and system- on-chip (SoC).

[0018] FIG. 8 is a diagram illustrating an example printed circuit board (PCB) and system- on-chip (SoC).

[0019] FIG. 9 is a diagram illustrating an example printed circuit board (PCB) and system- on-chip (SoC).

[0020] FIG. 10 is a diagram illustrating an example printed circuit board (PCB) and system- on-chip (SoC).

[0021] FIG. 11 is a diagram illustrating an example printed circuit board (PCB) and system- on-chip (SoC).

[0022] FIG. 12 is a diagram illustrating an example printed circuit board (PCB) and system- on-chip (SoC).

[0023] FIG. 13 is a communication flow diagram illustrating example communications between a vehicle, a vehicle component, and a memory.

[0024] FIG. 14 is a flowchart of an example method of communication.

[0025] FIG. 15 is a flowchart of an example method of communication.

[0026] FIG. 16 is a diagram illustrating an example of a hardware implementation for an example apparatus and / or network entity.129025-2381WO01Qualcomm Ref. No. 2404558WO 4DETAILED DESCRIPTION

[0027] PCBs and SoCs in automotive systems that include an increase in control and safety monitoring interfaces may lead to a corresponding increase in power consumption for PCBs and SoCs, as well as an increase in cost. For instance, new and complex power mode architectures may lead to a strong increase in control and safety monitoring interfaces, which may be supported by several power management integrated circuits (PMICs) and related pre-regulators. Further, the increased number of control and monitoring interfaces of SoCs and the parallel complexity increase of the product electronic control units (ECUs) themselves may lead to more expensive microcontroller units (MCUs) to provide enough interfaces. The actual generation of SoCs and system-in-packages (SiPs) may not be able to handle all relevant functional safety interfaces without an external MCU. At the same time the amount of interfaces has significantly increased, which results in higher costs for SiP modules. For example, an increase in the number of interfaces may lead to a corresponding increase in the amount of pins that are utilized by SiP components, which results in an increased cost. As indicated herein, automotive systems can include a number of different components (e.g., integrated circuits (ICs) and SoCs) that include an increased number of connections and complex communication, which results in an increase in power consumption, as well as an increase in cost. Aspects presented herein may introduce a component that can reduce the number of connections utilized in automotive systems including SoCs and SiPs. Also, aspects presented herein may introduce a component that can reduce the power consumption in automotive systems including SoCs and SiPs.

[0028] Aspects of the present disclosure may include a number of benefits or advantages. For instance, aspects presented herein may provide a microprocessor or microcontroller (i.e., a safety controller) to reduce the number of connections utilized in automotive systems including SoCs and SiPs. Aspects presented herein may also reduce the power consumption in automotive systems including SoCs and SiPs. Indeed, aspects presented herein may utilize a microprocessor or microcontroller (i.e., a safety controller) to reduce the power consumption in automotive systems including SoCs and SiPs. Further, aspects presented herein may introduce a component that can reduce cost of operating automotive systems including SoCs and SiPs. For example, aspects presented herein may utilize a microprocessor or microcontroller (i.e., a safety controller) to reduce the cost of operating automotive systems including SoCs and129025-2381WO01Qualcomm Ref. No. 2404558WO 5SiPs. That is, the integration of a safety controller to simplify communication within SoCs and SiPs allows aspects presented herein to reduce the cost of operating automotive systems including SoCs and SiPs.

[0029] Various aspects of systems, apparatuses, computer program products, and methods are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of this disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of, or combined with, other aspects of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of a claim.

[0030] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of aspects of this disclosure are mentioned, the scope of this disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the figures and in the following description. The detailed description and drawings are merely illustrative of this disclosure rather than limiting, the scope of this disclosure being defined by the appended claims and equivalents thereof.

[0031] Several aspects are presented with reference to various apparatus and methods. These apparatus and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, and the like (collectively referred to as “elements”). These elements may be implemented using electronic hardware, computer software, or any129025-2381WO01Qualcomm Ref. No. 2404558WO 6 combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

[0032] By way of example, an element, or any portion of an element, or any combination of elements may be implemented as a “processing system” that includes one or more processors (which may also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems-on-chip (SOC), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. One or more processors in the processing system may execute software. Software may be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The term application may refer to software. As described herein, one or more techniques may refer to an application, i.e., software, being configured to perform one or more functions. In such examples, the application may be stored on a memory, e.g., on-chip memory of a processor, system memory, or any other memory. Hardware described herein, such as a processor may be configured to execute the application. For example, the application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more techniques described herein. As an example, the hardware may access the code from a memory and execute the code accessed from the memory to perform one or more techniques described herein. In some examples, components are identified in this disclosure. In such examples, the components may be hardware, software, or a combination thereof. The components may be separate components or sub-components of a single component.

[0033] Accordingly, in one or more examples described herein, the functions described may be implemented in hardware, software, or any combination thereof. If implemented129025-2381WO01Qualcomm Ref. No. 2404558WO 7 in software, the functions may be stored on or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise a random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the aforementioned types of computer-readable media, or any other medium that may be used to store computer executable code in the form of instructions or data structures that may be accessed by a computer.

[0034] In general, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices, improving the rendering of graphical content, and / or reducing the load of a processing unit, i.e., any processing unit configured to perform one or more techniques described herein, such as a GPU. For example, this disclosure describes techniques for graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0035] As used herein, instances of the term “content” may refer to “graphical content,” “image,” and vice versa. This is true regardless of whether the terms are being used as an adjective, noun, or other parts of speech. In some examples, as used herein, the term “graphical content” may refer to a content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term “graphical content” may refer to a content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term “graphical content” may refer to a content produced by a graphics processing unit.

[0036] In some examples, as used herein, the term “display content” may refer to content generated by a processing unit configured to perform displaying processing. In some examples, as used herein, the term “display content” may refer to content generated by a display processing unit. Graphical content may be processed to become display content. For example, a graphics processing unit may output graphical content, such as a frame, to a buffer (which may be referred to as a framebuffer). A display processing unit may read the graphical content, such as one or more frames from the buffer, and perform one or more display processing techniques thereon to generate display content. For example, a display processing unit may be configured to perform129025-2381WO01Qualcomm Ref. No. 2404558WO 8 composition on one or more rendered layers to generate a frame. As another example, a display processing unit may be configured to compose, blend, or otherwise combine two or more layers together into a single frame. A display processing unit may be configured to perform scaling, e.g., upscaling or downscaling, on a frame. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have already been blended together to form the frame, i.e., the frame includes two or more layers, and the frame that includes two or more layers may subsequently be blended.

[0037] While aspects, implementations, and / or use cases are described in this application by illustration to some examples, additional or different aspects, implementations and / or use cases may come about in many different arrangements and scenarios. Aspects, implementations, and / or use cases described herein may be implemented across many differing platform types, devices, systems, shapes, sizes, and packaging arrangements. For example, aspects, implementations, and / or use cases may come about via integrated chip implementations and other non-module-component based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / purchasing devices, medical devices, artificial intelligence (Al)-enabled devices, etc.). While some examples may or may not be specifically directed to use cases or applications, a wide assortment of applicability of described examples may occur. Aspects, implementations, and / or use cases may range a spectrum from chip-level or modular components to non-modular, non-chip- level implementations and further to aggregate, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more techniques herein. In some practical settings, devices incorporating described aspects and features may also include additional components and features for implementation and practice of claimed and described aspect. For example, transmission and reception of wireless signals necessarily includes a number of components for analog and digital purposes (e.g., hardware components including antenna, RF-chains, power amplifiers, modulators, buffer, processor(s), interleaver, adders / summers, etc.). Techniques described herein may be practiced in a wide variety of devices, chip-level components, systems, distributed arrangements, aggregated or disaggregated components, end-user devices, etc. of varying sizes, shapes, and constitution.

[0038] Deployment of communication systems, such as 5G NR systems, may be arranged in multiple manners with various components or constituent parts. In a 5G NR system,129025-2381WO01Qualcomm Ref. No. 2404558WO 9 or network, a network node, a network entity, a mobility element of a network, a radio access network (RAN) node, a core network node, a network element, or a network equipment, such as a base station (BS), or one or more units (or one or more components) performing base station functionality, may be implemented in an aggregated or disaggregated architecture. For example, a BS (such as a Node B (NB), evolved NB (eNB), NR BS, 5GNB, access point (AP), a transmission reception point (TRP), or a cell, etc.) may be implemented as an aggregated base station (also known as a standalone BS or a monolithic BS) or a disaggregated base station.

[0039] An aggregated base station may be configured to utilize a radio protocol stack that is physically or logically integrated within a single RAN node. A disaggregated base station may be configured to utilize a protocol stack that is physically or logically distributed among two or more units (such as one or more central or centralized units (CUs), one or more distributed units (DUs), or one or more radio units (RUs)). In some aspects, a CU may be implemented within a RAN node, and one or more DUs may be co-located with the CU, or alternatively, may be geographically or virtually distributed throughout one or multiple other RAN nodes. The DUs may be implemented to communicate with one or more RUs. Each of the CU, DU and RU can be implemented as virtual units, i.e., a virtual central unit (VCU), a virtual distributed unit (VDU), or a virtual radio unit (VRU).

[0040] Base station operation or network design may consider aggregation characteristics of base station functionality. For example, disaggregated base stations may be utilized in an integrated access backhaul (IAB) network, an open radio access network (O- RAN (such as the network configuration sponsored by the O-RAN Alliance)), or a virtualized radio access network (vRAN, also known as a cloud radio access network (C-RAN)). Disaggregation may include distributing functionality across two or more units at various physical locations, as well as distributing functionality for at least one unit virtually, which can enable flexibility in network design. The various units of the disaggregated base station, or disaggregated RAN architecture, can be configured for wired or wireless communication with at least one other unit.

[0041] FIG. 1 is a diagram 100 illustrating an example of a wireless communications system and an access network. The illustrated wireless communications system includes a disaggregated base station architecture. The disaggregated base station architecture may include one or more CUs 110 that can communicate directly with a core network 120 via a backhaul link, or indirectly with the core network 120 through one or more129025-2381WO01Qualcomm Ref. No. 2404558WO 10 disaggregated base station units (such as a Near-Real Time (Near-RT) RAN Intelligent Controller (RIC) 125 via an E2 link, or a Non-Real Time (Non-RT) RIC 115 associated with a Service Management and Orchestration (SMO) Framework 105, or both). A CU 110 may communicate with one or more DUs 130 via respective midhaul links, such as an Fl interface. The DUs 130 may communicate with one or more RUs 140 via respective fronthaul links. The RUs 140 may communicate with respective UEs 104 via one or more radio frequency (RF) access links. In some implementations, the UE 104 may be simultaneously served by multiple RUs 140.

[0042] Each of the units, i.e., the CUs 110, the DUs 130, the RUs 140, as well as the Near- RT RICs 125, the Non-RT RICs 115, and the SMO Framework 105, may include one or more interfaces or be coupled to one or more interfaces configured to receive or to transmit signals, data, or information (collectively, signals) via a wired or wireless transmission medium. Each of the units, or an associated processor or controller providing instructions to the communication interfaces of the units, can be configured to communicate with one or more of the other units via the transmission medium. For example, the units can include a wired interface configured to receive or to transmit signals over a wired transmission medium to one or more of the other units. Additionally, the units can include a wireless interface, which may include a receiver, a transmitter, or a transceiver (such as an RF transceiver), configured to receive or to transmit signals, or both, over a wireless transmission medium to one or more of the other units.

[0043] In some aspects, the CU 110 may host one or more higher layer control functions. Such control functions can include radio resource control (RRC), packet data convergence protocol (PDCP), service data adaptation protocol (SDAP), or the like. Each control function can be implemented with an interface configured to communicate signals with other control functions hosted by the CU 110. The CU 110 may be configured to handle user plane functionality (i.e., Central Unit - User Plane (CU-UP)), control plane functionality (i.e., Central Unit - Control Plane (CU-CP)), or a combination thereof. In some implementations, the CU 110 can be logically split into one or more CU-UP units and one or more CU-CP units. The CU-UP unit can communicate bidirectionally with the CU-CP unit via an interface, such as an El interface when implemented in an O-RAN configuration. The CU 110 can be implemented to communicate with the DU 130, as necessary, for network control and signaling.129025-2381WO01Qualcomm Ref. No. 2404558WO 11

[0044] The DU 130 may correspond to a logical unit that includes one or more base station functions to control the operation of one or more RUs 140. In some aspects, the DU 130 may host one or more of a radio link control (RLC) layer, a medium access control (MAC) layer, and one or more high physical (PHY) layers (such as modules for forward error correction (FEC) encoding and decoding, scrambling, modulation, demodulation, or the like) depending, at least in part, on a functional split, such as those defined by 3 GPP. In some aspects, the DU 130 may further host one or more low PHY layers. Each layer (or module) can be implemented with an interface configured to communicate signals with other layers (and modules) hosted by the DU 130, or with the control functions hosted by the CU 110.

[0045] Lower-layer functionality can be implemented by one or more RUs 140. In some deployments, an RU 140, controlled by a DU 130, may correspond to a logical node that hosts RF processing functions, or low-PHY layer functions (such as performing fast Fourier transform (FFT), inverse FFT (iFFT), digital beamforming, physical random access channel (PRACH) extraction and filtering, or the like), or both, based at least in part on the functional split, such as a lower layer functional split. In such an architecture, the RU(s) 140 can be implemented to handle over the air (OTA) communication with one or more UEs 104. In some implementations, real-time and non-real-time aspects of control and user plane communication with the RU(s) 140 can be controlled by the corresponding DU 130. In some scenarios, this configuration can enable the DU(s) 130 and the CU 110 to be implemented in a cloud-based RAN architecture, such as a vRAN architecture.

[0046] The SMO Framework 105 may be configured to support RAN deployment and provisioning of non-virtualized and virtualized network elements. For non-virtualized network elements, the SMO Framework 105 may be configured to support the deployment of dedicated physical resources for RAN coverage requirements that may be managed via an operations and maintenance interface (such as an 01 interface). For virtualized network elements, the SMO Framework 105 may be configured to interact with a cloud computing platform (such as an open cloud (O-Cloud) 190) to perform network element life cycle management (such as to instantiate virtualized network elements) via a cloud computing platform interface (such as an 02 interface). Such virtualized network elements can include, but are not limited to, CUs 110, DUs 130, RUs 140 and Near-RT RICs 125. In some implementations, the SMO Framework 105 can communicate with a hardware aspect of a 4G RAN, such as an open eNB (O-129025-2381WO01Qualcomm Ref. No. 2404558WO 12 eNB) 111, via an 01 interface. Additionally, in some implementations, the SMO Framework 105 can communicate directly with one or more RUs 140 via an 01 interface. The SMO Framework 105 also may include a Non-RT RIC 115 configured to support functionality of the SMO Framework 105.

[0047] The Non-RT RIC 115 may be configured to include a logical function that enables non-real-time control and optimization of RAN elements and resources, artificial intelligence (Al) / machine learning (ML) (AI / ML) workflows including model training and updates, or policy-based guidance of applications / features in the Near- RT RIC 125. The Non-RT RIC 115 may be coupled to or communicate with (such as via an Al interface) the Near-RT RIC 125. The Near-RT RIC 125 may be configured to include a logical function that enables near-real-time control and optimization of RAN elements and resources via data collection and actions over an interface (such as via an E2 interface) connecting one or more CUs 110, one or more DUs 130, or both, as well as an O-eNB, with the Near-RT RIC 125.

[0048] In some implementations, to generate AI / ML models to be deployed in the Near-RT RIC 125, the Non-RT RIC 115 may receive parameters or external enrichment information from external servers. Such information may be utilized by the Near-RT RIC 125 and may be received at the SMO Framework 105 or the Non-RT RIC 115 from non-network data sources or from network functions. In some examples, the Non-RT RIC 115 or the Near-RT RIC 125 may be configured to tune RAN behavior or performance. For example, the Non-RT RIC 115 may monitor long-term trends and patterns for performance and employ AI / ML models to perform corrective actions through the SMO Framework 105 (such as reconfiguration via 01) or via creation of RAN management policies (such as Al policies).

[0049] At least one of the CU 110, the DU 130, and the RU 140 may be referred to as a base station 102. Accordingly, a base station 102 may include one or more of the CU 110, the DU 130, and the RU 140 (each component indicated with dotted lines to signify that each component may or may not be included in the base station 102). The base station 102 provides an access point to the core network 120 for a UE 104. The base station 102 may include macrocells (high power cellular base station) and / or small cells (low power cellular base station). The small cells include femtocells, picocells, and microcells. A network that includes both small cell and macrocells may be known as a heterogeneous network. A heterogeneous network may also include Home Evolved Node Bs (eNBs) (HeNBs), which may provide service to a restricted group129025-2381WO01Qualcomm Ref. No. 2404558WO 13 known as a closed subscriber group (CSG). The communication links between the RUs 140 and the UEs 104 may include uplink (UL) (also referred to as reverse link) transmissions from a UE 104 to an RU 140 and / or downlink (DL) (also referred to as forward link) transmissions from an RU 140 to a UE 104. The communication links may use multiple-input and multiple-output (MIMO) antenna technology, including spatial multiplexing, beamforming, and / or transmit diversity. The communication links may be through one or more carriers. The base station 102 / UEs 104 may use spectrum up to X MHz (e.g., 5, 10, 15, 20, 100, 400, etc. MHz) bandwidth per carrier allocated in a carrier aggregation of up to a total of Ex MHz (x component carriers) used for transmission in each direction. The carriers may or may not be adjacent to each other. Allocation of carriers may be asymmetric with respect to DL and UL (e.g., more or fewer carriers may be allocated for DL than for UL). The component carriers may include a primary component carrier and one or more secondary component carriers. A primary component carrier may be referred to as a primary cell (PCell) and a secondary component carrier may be referred to as a secondary cell (SCell).

[0050] Certain UEs 104 may communicate with each other using device-to-device (D2D) communication link 158. The D2D communication link 158 may use the DL / UL wireless wide area network (WWAN) spectrum. The D2D communication link 158 may use one or more sidelink channels, such as a physical sidelink broadcast channel (PSBCH), a physical sidelink discovery channel (PSDCH), a physical sidelink shared channel (PSSCH), and a physical sidelink control channel (PSCCH). D2D communication may be through a variety of wireless D2D communications systems, such as for example, Bluetooth™ (Bluetooth is a trademark of the Bluetooth Special Interest Group (SIG)), Wi-Fi™ (Wi-Fi is a trademark of the Wi-Fi Alliance) based on the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard, LTE, or NR.

[0051] The wireless communications system may further include a Wi-Fi AP 150 in communication with UEs 104 (also referred to as Wi-Fi stations (STAs)) via communication link 154, e.g., in a 5 GHz unlicensed frequency spectrum or the like. When communicating in an unlicensed frequency spectrum, the UEs 104 / AP 150 may perform a clear channel assessment (CCA) prior to communicating in order to determine whether the channel is available.

[0052] The electromagnetic spectrum is often subdivided, based on frequency / wavelength, into various classes, bands, channels, etc. In 5GNR, two initial operating bands have129025-2381WO01Qualcomm Ref. No. 2404558WO 14 been identified as frequency range designations FR1 (410 MHz - 7.125 GHz) and FR2 (24.25 GHz - 52.6 GHz). Although a portion of FR1 is greater than 6 GHz, FR1 is often referred to (interchangeably) as a “sub-6 GHz” band in various documents and articles. A similar nomenclature issue sometimes occurs with regard to FR2, which is often referred to (interchangeably) as a “millimeter wave” band in documents and articles, despite being different from the extremely high frequency (EHF) band (30 GHz - 300 GHz) which is identified by the International Telecommunications Union (ITU) as a “millimeter wave” band.

[0053] The frequencies between FR1 and FR2 are often referred to as mid-band frequencies. Recent 5G NR studies have identified an operating band for these mid-band frequencies as frequency range designation FR3 (7.125 GHz - 24.25 GHz). Frequency bands falling within FR3 may inherit FR1 characteristics and / or FR2 characteristics, and thus may effectively extend features of FR1 and / or FR2 into midband frequencies. In addition, higher frequency bands are currently being explored to extend 5GNR operation beyond 52.6 GHz. For example, three higher operating bands have been identified as frequency range designations FR2-2 (52.6 GHz - 71 GHz), FR4 (71 GHz - 114.25 GHz), and FR5 (114.25 GHz - 300 GHz). Each of these higher frequency bands falls within the EHF band.

[0054] With the above aspects in mind, unless specifically stated otherwise, the term “sub-6 GHz” or the like if used herein may broadly represent frequencies that may be less than 6 GHz, may be within FR1, or may include mid-band frequencies. Further, unless specifically stated otherwise, the term “millimeter wave” or the like if used herein may broadly represent frequencies that may include mid-band frequencies, may be within FR2, FR4, FR2-2, and / or FR5, or may be within the EHF band.

[0055] The base station 102 and the UE 104 may each include a plurality of antennas, such as antenna elements, antenna panels, and / or antenna arrays to facilitate beamforming. The base station 102 may transmit a beamformed signal 182 to the UE 104 in one or more transmit directions. The UE 104 may receive the beamformed signal from the base station 102 in one or more receive directions. The UE 104 may also transmit a beamformed signal 184 to the base station 102 in one or more transmit directions. The base station 102 may receive the beamformed signal from the UE 104 in one or more receive directions. The base station 102 / UE 104 may perform beam training to determine the best receive and transmit directions for each of the base station 102 / UE 104. The transmit and receive directions for the base station 102 may or may not129025-2381WO01Qualcomm Ref. No. 2404558WO 15 be the same. The transmit and receive directions for the UE 104 may or may not be the same.

[0056] The base station 102 may include and / or be referred to as a gNB, Node B, eNB, an access point, a base transceiver station, a radio base station, a radio transceiver, a transceiver function, a basic service set (BSS), an extended service set (ESS), a TRP, network node, network entity, network equipment, or some other suitable terminology. The base station 102 can be implemented as an integrated access and backhaul (IAB) node, a relay node, a sidelink node, an aggregated (monolithic) base station with a baseband unit (BBU) (including a CU and a DU) and an RU, or as a disaggregated base station including one or more of a CU, a DU, and / or an RU. The set of base stations, which may include disaggregated base stations and / or aggregated base stations, may be referred to as next generation (NG) RAN (NG-RAN).

[0057] The core network 120 may include an Access and Mobility Management Function (AMF) 161, a Session Management Function (SMF) 162, a User Plane Function (UPF) 163, a Unified Data Management (UDM) 164, one or more location servers 168, and other functional entities. The AMF 161 is the control node that processes the signaling between the UEs 104 and the core network 120. The AMF 161 supports registration management, connection management, mobility management, and other functions. The SMF 162 supports session management and other functions. The UPF 163 supports packet routing, packet forwarding, and other functions. The UDM 164 supports the generation of authentication and key agreement (AKA) credentials, user identification handling, access authorization, and subscription management. The one or more location servers 168 are illustrated as including a Gateway Mobile Location Center (GMLC) 165 and a Location Management Function (LMF) 166. However, generally, the one or more location servers 168 may include one or more location / positioning servers, which may include one or more of the GMLC 165, the LMF 166, a position determination entity (PDE), a serving mobile location center (SMLC), a mobile positioning center (MPC), or the like. The GMLC 165 and the LMF 166 support UE location services. The GMLC 165 provides an interface for clients / applications (e.g., emergency services) for accessing UE positioning information. The LMF 166 receives measurements and assistance information from the NG-RAN and the UE 104 via the AMF 161 to compute the position of the UE 104. The NG-RAN may utilize one or more positioning methods in order to determine the position of the UE 104. Positioning the UE 104 may involve signal measurements,129025-2381WO01Qualcomm Ref. No. 2404558WO 16 a position estimate, and an optional velocity computation based on the measurements. The signal measurements may be made by the UE 104 and / or the base station 102 serving the UE 104. The signals measured may be based on one or more of a satellite positioning system (SPS) 170 (e.g., one or more of a Global Navigation Satellite System (GNSS), global position system (GPS), non-terrestrial network (NTN), or other satellite position / location system), LTE signals, wireless local area network (WLAN) signals, Bluetooth signals, a terrestrial beacon system (TBS), sensor-based information (e.g., barometric pressure sensor, motion sensor), NR enhanced cell ID (NRE-CID) methods, NR signals (e.g., multi-round trip time (Multi-RTT), DL angle- of-departure (DL-AoD), DL time difference of arrival (DL-TDOA), UL time difference of arrival (UL-TDOA), and UL angle-of-arrival (UL-AoA) positioning), and / or other systems / signals / sensors.

[0058] Examples of UEs 104 include a cellular phone, a smart phone, a session initiation protocol phone, a laptop, a personal digital assistant (PDA), a satellite radio, a global positioning system, a multimedia device, a video device, a digital audio player (e.g., MP3 player), a camera, a game console, a tablet, a smart device, a wearable device, a vehicle, an electric meter, a gas pump, a large or small kitchen appliance, a healthcare device, an implant, a sensor / actuator, a display, or any other similar functioning device. Some of the UEs 104 may be referred to as loT devices (e.g., parking meter, gas pump, toaster, vehicles, heart monitor, etc.). The UE 104 may also be referred to as a station, a mobile station, a subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a mobile device, a wireless device, a wireless communications device, a remote device, a mobile subscriber station, an access terminal, a mobile terminal, a wireless terminal, a remote terminal, a handset, a user agent, a mobile client, a client, or some other suitable terminology. In some scenarios, the term UE may also apply to one or more companion devices such as in a device constellation arrangement. One or more of these devices may collectively access the network and / or individually access the network.

[0059] Referring again to FIG. 1 , in certain aspects, the UE 104 may have a safety component 198 that may be configured to obtain an indication of a threshold range for signals prior to monitoring a set of signals. Safety component 198 may also be configured to monitor a set of signals associated with a regulation of a device. Safety component 198 may also be configured to, where the set of signals is a set of analog signals, convert or translate the set of analog signals to a set of digital signals prior to the129025-2381WO01Qualcomm Ref. No. 2404558WO 17 determination. Safety component 198 may also be configured to measure the range of the set of analog signals based on converting or translating the set of analog signals to the set of digital signals. Safety component 198 may also be configured to determine, in at least one of a system-in-package (SiP) of the device, a system on- chip (SoC) of the device, or a power management integrated circuit (PMIC) of the device, whether a range for the set of signals is within a threshold range for signals. Safety component 198 may also be configured to output, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals.

[0060] FIG. 2A is a diagram 200 illustrating an example of a first subframe within a 5GNR frame structure. FIG. 2B is a diagram 230 illustrating an example of DL channels within a 5G NR subframe. FIG. 2C is a diagram 250 illustrating an example of a second subframe within a 5G NR frame structure. FIG. 2D is a diagram 280 illustrating an example of UL channels within a 5GNR subframe. The 5G NR frame structure may be frequency division duplexed (FDD) in which for a particular set of subcarriers (carrier system bandwidth), subframes within the set of subcarriers are dedicated for either DL or UL, or may be time division duplexed (TDD) in which for a particular set of subcarriers (carrier system bandwidth), subframes within the set of subcarriers are dedicated for both DL and UL. In the examples provided by FIGs. 2A, 2C, the 5G NR frame structure is assumed to be TDD, with subframe 4 being configured with slot format 28 (with mostly DL), where D is DL, U is UL, and F is flexible for use between DL / UL, and subframe 3 being configured with slot format 1 (with all UL). While subframes 3, 4 are shown with slot formats 1, 28, respectively, any particular subframe may be configured with any of the various available slot formats 0-61. Slot formats 0, 1 are all DL, UL, respectively. Other slot formats 2-61 include a mix of DL, UL, and flexible symbols. UEs are configured with the slot format (dynamically through DL control information (DCI), or semi- statically / statically through radio resource control (RRC) signaling) through a received slot format indicator (SFI). Note that the description infra applies also to a 5G NR frame structure that is TDD.

[0061] FIGs. 2A-2D illustrate a frame structure, and the aspects of the present disclosure may be applicable to other wireless communication technologies, which may have a different frame structure and / or different channels. A frame (10 ms) may be divided into 10 equally sized subframes (1 ms). Each subframe may include one or more time129025-2381WO01Qualcomm Ref. No. 2404558WO 18 slots. Subframes may also include mini-slots, which may include 7, 4, or 2 symbols. Each slot may include 14 or 12 symbols, depending on whether the cyclic prefix (CP) is normal or extended. For normal CP, each slot may include 14 symbols, and for extended CP, each slot may include 12 symbols. The symbols on DL may be CP orthogonal frequency division multiplexing (OFDM) (CP-OFDM) symbols. The symbols on UL may be CP-OFDM symbols (for high throughput scenarios) or discrete Fourier transform (DFT) spread OFDM (DFT-s-OFDM) symbols (for power limited scenarios; limited to a single stream transmission). The number of slots within a subframe is based on the CP and the numerology. The numerology defines the subcarrier spacing (SCS) (see Table 1). The symbol length / duration may scale with 1 / SCS.Table 1 : Numerology, SCS, and CP

[0062] For normal CP (14 symbols / slot), different numerologies p 0 to 4 allow for 1, 2, 4, 8, and 16 slots, respectively, per subframe. For extended CP, the numerology 2 allows for 4 slots per subframe. Accordingly, for normal CP and numerology p, there are 14 symbols / slot and 2^ slots / subframe. The subcarrier spacing may be equal to 2 * 15 kHz, where g is the numerology 0 to 4. As such, the numerology p=0 has a subcarrier spacing of 15 kHz and the numerology p=4 has a subcarrier spacing of 240 kHz. The symbol length / duration is inversely related to the subcarrier spacing. FIGs. 2A-2D provide an example of normal CP with 14 symbols per slot and numerology p=2 with 4 slots per subframe. The slot duration is 0.25 ms, the subcarrier spacing is 60 kHz, and the symbol duration is approximately 16.67 ps. Within a set of frames, there may be one or more different bandwidth parts (BWPs) (see FIG. 2B) that are129025-2381WO01Qualcomm Ref. No. 2404558WO 19 frequency division multiplexed. Each BWP may have a particular numerology and CP (normal or extended).

[0063] A resource grid may be used to represent the frame structure. Each time slot includes a resource block (RB) (also referred to as physical RBs (PRBs)) that extends 12 consecutive subcarriers. The resource grid is divided into multiple resource elements (REs). The number of bits carried by each RE depends on the modulation scheme.

[0064] As illustrated in FIG. 2A, some of the REs carry reference (pilot) signals (RS) for the UE. The RS may include demodulation RS (DM-RS) (indicated as R for one particular configuration, but other DM-RS configurations are possible) and channel state information reference signals (CSI-RS) for channel estimation at the UE. The RS may also include beam measurement RS (BRS), beam refinement RS (BRRS), and phase tracking RS (PT-RS).

[0065] FIG. 2B illustrates an example of various DL channels within a subframe of a frame. The physical downlink control channel (PDCCH) carries DCI within one or more control channel elements (CCEs) (e.g., 1, 2, 4, 8, or 16 CCEs), each CCE including six RE groups (REGs), each REG including 12 consecutive REs in an OFDM symbol of an RB. A PDCCH within one BWP may be referred to as a control resource set (CORESET). A UE is configured to monitor PDCCH candidates in a PDCCH search space (e.g., common search space, UE-specific search space) during PDCCH monitoring occasions on the CORESET, where the PDCCH candidates have different DCI formats and different aggregation levels. Additional BWPs may be located at greater and / or lower frequencies across the channel bandwidth. A primary synchronization signal (PSS) may be within symbol 2 of particular subframes of a frame. The PSS is used by a UE 104 to determine subframe / symbol timing and a physical layer identity. A secondary synchronization signal (SSS) may be within symbol 4 of particular subframes of a frame. The SSS is used by a UE to determine a physical layer cell identity group number and radio frame timing. Based on the physical layer identity and the physical layer cell identity group number, the UE can determine a physical cell identifier (PCI). Based on the PCI, the UE can determine the locations of the DM-RS. The physical broadcast channel (PBCH), which carries a master information block (MIB), may be logically grouped with the PSS and SSS to form a synchronization signal (SS)ZPBCH block (also referred to as SS block (SSB)). The MIB provides a number of RBs in the system bandwidth and a system frame number (SFN). The physical downlink shared channel (PDSCH) carries user129025-2381WO01Qualcomm Ref. No. 2404558WO 20 data, broadcast system information not transmitted through the PBCH such as system information blocks (SIBs), and paging messages.

[0066] As illustrated in FIG. 2C, some of the REs carry DM-RS (indicated as R for one particular configuration, but other DM-RS configurations are possible) for channel estimation at the base station. The UE may transmit DM-RS for the physical uplink control channel (PUCCH) and DM-RS for the physical uplink shared channel (PUSCH). The PUSCH DM-RS may be transmitted in the first one or two symbols of the PUSCH. The PUCCH DM-RS may be transmitted in different configurations depending on whether short or long PUCCHs are transmitted and depending on the particular PUCCH format used. The UE may transmit sounding reference signals (SRS). The SRS may be transmitted in the last symbol of a subframe. The SRS may have a comb structure, and a UE may transmit SRS on one of the combs. The SRS may be used by a base station for channel quality estimation to enable frequencydependent scheduling on the UL.

[0067] FIG. 2D illustrates an example of various UL channels within a subframe of a frame. The PUCCH may be located as indicated in one configuration. The PUCCH carries uplink control information (UCI), such as scheduling requests, a channel quality indicator (CQI), a precoding matrix indicator (PMI), a rank indicator (RI), and hybrid automatic repeat request (HARQ) acknowledgment (ACK) (HARQ-ACK) feedback (i.e., one or more HARQ ACK bits indicating one or more ACK and / or negative ACK (NACK)). The PUSCH carries data, and may additionally be used to carry a buffer status report (BSR), a power headroom report (PHR), and / or UCI.

[0068] FIG. 3 is a block diagram of a base station 310 in communication with a UE 350 in an access network. In the DL, Internet protocol (IP) packets may be provided to a controller / processor 375. The controller / processor 375 implements layer 3 and layer 2 functionality. Layer 3 includes a radio resource control (RRC) layer, and layer 2 includes a service data adaptation protocol (SDAP) layer, a packet data convergence protocol (PDCP) layer, a radio link control (RLC) layer, and a medium access control (MAC) layer. The controller / processor 375 provides RRC layer functionality associated with broadcasting of system information (e.g., MIB, SIBs), RRC connection control (e.g., RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release), inter radio access technology (RAT) mobility, and measurement configuration for UE measurement reporting; PDCP layer functionality associated with header compression / 129025-2381WO01Qualcomm Ref. No. 2404558WO 21 decompression, security (ciphering, deciphering, integrity protection, integrity verification), and handover support functions; RLC layer functionality associated with the transfer of upper layer packet data units (PDUs), error correction through ARQ, concatenation, segmentation, and reassembly of RLC service data units (SDUs), re-segmentation of RLC data PDUs, and reordering of RLC data PDUs; and MAC layer functionality associated with mapping between logical channels and transport channels, multiplexing of MAC SDUs onto transport blocks (TBs), demultiplexing of MAC SDUs from TBs, scheduling information reporting, error correction through HARQ, priority handling, and logical channel prioritization.

[0069] The transmit (TX) processor 316 and the receive (RX) processor 370 implement layer 1 functionality associated with various signal processing functions. Layer 1, which includes a physical (PHY) layer, may include error detection on the transport channels, forward error correction (FEC) coding / decoding of the transport channels, interleaving, rate matching, mapping onto physical channels, modulation / demodulation of physical channels, and MIMO antenna processing. The TX processor 316 handles mapping to signal constellations based on various modulation schemes (e.g., binary phase-shift keying (BPSK), quadrature phase-shift keying (QPSK), M-phase-shift keying (M-PSK), M-quadrature amplitude modulation (M-QAM)). The coded and modulated symbols may then be split into parallel streams. Each stream may then be mapped to an OFDM subcarrier, multiplexed with a reference signal (e.g., pilot) in the time and / or frequency domain, and then combined together using an Inverse Fast Fourier Transform (IFFT) to produce a physical channel carrying a time domain OFDM symbol stream. The OFDM stream is spatially precoded to produce multiple spatial streams. Channel estimates from a channel estimator 374 may be used to determine the coding and modulation scheme, as well as for spatial processing. The channel estimate may be derived from a reference signal and / or channel condition feedback transmitted by the UE 350. Each spatial stream may then be provided to a different antenna 320 via a separate transmitter 318Tx. Each transmitter 318Tx may modulate a radio frequency (RF) carrier with a respective spatial stream for transmission.

[0070] At the UE 350, each receiver 354Rx receives a signal through its respective antenna 352. Each receiver 354Rx recovers information modulated onto an RF carrier and provides the information to the receive (RX) processor 356. The TX processor 368 and the RX processor 356 implement layer 1 functionality associated with various129025-2381WO01Qualcomm Ref. No. 2404558WO 22 signal processing functions. The RX processor 356 may perform spatial processing on the information to recover any spatial streams destined for the UE 350. If multiple spatial streams are destined for the UE 350, they may be combined by the RX processor 356 into a single OFDM symbol stream. The RX processor 356 then converts the OFDM symbol stream from the time-domain to the frequency domain using a Fast Fourier Transform (FFT). The frequency domain signal includes a separate OFDM symbol stream for each subcarrier of the OFDM signal. The symbols on each subcarrier, and the reference signal, are recovered and demodulated by determining the most likely signal constellation points transmitted by the base station 310. These soft decisions may be based on channel estimates computed by the channel estimator 358. The soft decisions are then decoded and deinterleaved to recover the data and control signals that were originally transmitted by the base station 310 on the physical channel. The data and control signals are then provided to the controller / processor 359, which implements layer 3 and layer 2 functionality.

[0071] The controller / processor 359 can be associated with at least one memory 360 that stores program codes and data. The at least one memory 360 may be referred to as a computer-readable medium. In the UL, the controller / processor 359 provides demultiplexing between transport and logical channels, packet reassembly, deciphering, header decompression, and control signal processing to recover IP packets. The controller / processor 359 is also responsible for error detection using an ACK and / or NACK protocol to support HARQ operations.

[0072] Similar to the functionality described in connection with the DL transmission by the base station 310, the controller / processor 359 provides RRC layer functionality associated with system information (e.g., MIB, SIBs) acquisition, RRC connections, and measurement reporting; PDCP layer functionality associated with header compression / decompression, and security (ciphering, deciphering, integrity protection, integrity verification); RLC layer functionality associated with the transfer of upper layer PDUs, error correction through ARQ, concatenation, segmentation, and reassembly of RLC SDUs, re-segmentation of RLC data PDUs, and reordering of RLC data PDUs; and MAC layer functionality associated with mapping between logical channels and transport channels, multiplexing of MAC SDUs onto TBs, demultiplexing of MAC SDUs from TBs, scheduling information reporting, error correction through HARQ, priority handling, and logical channel prioritization.129025-2381WO01Qualcomm Ref. No. 2404558WO 23

[0073] Channel estimates derived by a channel estimator 358 from a reference signal or feedback transmitted by the base station 310 may be used by the TX processor 368 to select the appropriate coding and modulation schemes, and to facilitate spatial processing. The spatial streams generated by the TX processor 368 may be provided to different antenna 352 via separate transmitters 354Tx. Each transmitter 354Tx may modulate an RF carrier with a respective spatial stream for transmission.

[0074] The UL transmission is processed at the base station 310 in a manner similar to that described in connection with the receiver function atthe UE 350. Each receiver 318Rx receives a signal through its respective antenna 320. Each receiver 318Rx recovers information modulated onto an RF carrier and provides the information to a RX processor 370.

[0075] The controller / processor 375 can be associated with at least one memory 376 that stores program codes and data. The at least one memory 376 may be referred to as a computer-readable medium. In the UL, the controller / processor 375 provides demultiplexing between transport and logical channels, packet reassembly, deciphering, header decompression, control signal processing to recover IP packets. The controller / processor 375 is also responsible for error detection using an ACK and / or NACK protocol to support HARQ operations.

[0076] At least one of the TX processor 368, the RX processor 356, and the controller / processor 359 may be configured to perform aspects in connection with the component 198 of FIG. 1.

[0077] Instructions executed by a CPU (e.g., software instructions) or a display processor may cause the CPU or the display processor to search for and / or generate a composition strategy for composing a frame based on a dynamic priority and runtime statistics associated with one or more composition strategy groups. A frame to be displayed by a physical display device, such as a display panel, may include a plurality of layers. Also, composition of the frame may be based on combining the plurality of layers into the frame (e.g., based on a frame buffer). After the plurality of layers are combined into the frame, the frame may be provided to the display panel for display thereon. The process of combining each of the plurality of layers into the frame may be referred to as composition, frame composition, a composition procedure, a composition process, or the like.

[0078] A frame composition procedure or composition strategy may correspond to a technique for composing different layers of the plurality of layers into a single frame.129025-2381WO01Qualcomm Ref. No. 2404558WO 24The plurality of layers may be stored in doubled data rate (DDR) memory. Each layer of the plurality of layers may further correspond to a separate buffer. A composer or hardware composer (HWC) associated with a block or function may determine an input of each layer / buffer and perform the frame composition procedure to generate an output indicative of a composed frame. That is, the input may be the layers and the output may be a frame composition procedure for composing the frame to be displayed on the display panel.

[0079] In some aspects, a display device may present frames at different frame rates on the first display panel and the second display panel. For instance, a display panel may present frames at 60 frames per second (FPS) on both the first display panel and the second display panel, 45 FPS on both the first display panel and the second display panel, etc. The display device may synchronize frame rates of content with refresh rates of the display panels (via a vertical synchronization process, which may be referred to as vsync, Vsync, VSync, or VSYNC). For instance, content may be available at 60 FPS and the first display panel and the second display panel may have a refresh rate of 95 Hz. Via Vsync, the refresh rate of the first display panel and the second display panel may be set to 60 Hz to match the 60 FPS content.

[0080] As indicated herein, VSync is a graphics technology that synchronizes the frame rate of an application / game with a refresh rate at a display (e.g., a display on a client device). Vsync may be utilized as a manner in which to deal with screen tearing (i.e., the screen displays portions of multiple frames at once). That can result in the display appearing to be split along a line. Tearing may occur when the display refresh rate (i.e., how many times the display updates per second) is not in synchronization with the frames per second (FPS). VSync signals may synchronize the display pipeline (e.g., the pipeline including application rendering, compositor, and a hardware composer (HWC) that presents images on the display). For instance, VSync signals may help to synchronize the time in which applications wake up to start rendering, the time the compositor wakes up to composite the screen, and the display refresh cycle. This synchronization may help to eliminate display refresh issues and improve visual performance. In some examples, the HWC may generates VSync events / signals and send the events / signals to the compositor.

[0081] FIG. 4 is a diagram 400 that illustrates processing components, such as a processing unit 430 and the system memory 440, as may be identified in connection with a device for processing data. In aspects, the processing unit 430 may include a CPU 402 and129025-2381WO01Qualcomm Ref. No. 2404558WO 25 a GPU 412. The GPU 412 and the CPU 402 may be formed as an integrated circuit (e.g., a system-on-a-chip (SOC)) and / or the GPU 412 may be incorporated onto a motherboard with the CPU 402. Alternatively, the CPU 402 and the GPU 412 may be configured as distinct processing units that are communicatively coupled to each other. For example, the GPU 412 may be incorporated on a graphics card that is installed in a port of the motherboard that includes the CPU 402.

[0082] The CPU 402 may be configured to execute a software application that causes graphical content to be displayed (e.g., on a display(s) of a device) based on one or more operations of the GPU 412. The software application may issue instructions to a graphics application program interface (API) 404, which may be a runtime program that translates instructions received from the software application into a format that is readable by a GPU driver 410. After receiving instructions from the software application via the graphics API 404, the GPU driver 410 may control an operation of the GPU 412 based on the instructions. For example, the GPU driver 410 may generate one or more command streams that are placed into the system memory 440, where the GPU 412 is instructed to execute the command streams (e.g., via one or more system calls). A command engine 414 included in the GPU 412 is configured to retrieve the one or more commands stored in the command streams. The command engine 414 may provide commands from the command stream for execution by the GPU 412. The command engine 414 may be hardware of the GPU 412, software / firmware executing on the GPU 412, or a combination thereof. While the GPU driver 410 is configured to implement the graphics API 404, the GPU driver 410 is not limited to being configured in accordance with any particular API. The system memory 440 may store the code for the GPU driver 410, which the CPU 402 may retrieve for execution. In examples, the GPU driver 410 may be configured to allow communication between the CPU 402 and the GPU 412, such as when the CPU 402 offloads graphics or non-graphics processing tasks to the GPU 412 via the GPU driver 410.

[0083] The system memory 440 may further store source code for one or more of an early preamble shader 424, a feedback shader 425, or a main shader 426. In such configurations, a shader compiler 408 executing on the CPU 402 may compile the source code of the shaders 424-426 to create object code or intermediate code executable by a shader core 416 of the GPU 412 during runtime (e.g., at the time when the shaders 424-426 are to be executed on the shader core 416). In some examples,129025-2381WO01Qualcomm Ref. No. 2404558WO 26 the shader compiler 408 may pre-compile the shaders 424-426 and store the object code or intermediate code of the shader programs in the system memory 440. The shader compiler 408 (or in another example the GPU driver 410) executing on the CPU 402 may build a shader program with multiple components including the early preamble shader 424, the feedback shader 425, and the main shader 426. The main shader 426 may correspond to a portion or the entirety of the shader program that does not include the early preamble shader 424 or the feedback shader 425. The shader compiler 408 may receive instructions to compile the shader(s) 424-426 from a program executing on the CPU 402. The shader compiler 408 may also identify constant load instructions and common operations in the shader program for including the common operations within the early preamble shader 424 (rather than the main shader 426). The shader compiler 408 may identify such common instructions, for example, based on (presently undetermined) constants 406 to be included in the common instructions. The constants 406 may be defined within the graphics API 404 to be constant across an entire draw call. The shader compiler 408 may utilize instructions such as a preamble shader start to indicate a beginning of the early preamble shader 424 and a preamble shader end to indicate an end of the early preamble shader 424. Similar instructions may be used for the feedback shader 425 and the main shader 426. The feedback shader 425 will be described in further detail below.

[0084] The shader core 416 included in the GPU 412 may include general purpose registers (GPRs) 418 and constant memory 420. The GPRs 418 may correspond to a single GPR, a GPR file, and / or a GPR bank. Each GPR in the GPRs 418 may store data accessible to a single thread. The software and / or firmware executing on GPU 412 may be a shader program 424-426, which may execute on the shader core 416 of GPU 412. The shader core 416 may be configured to execute many instances of the same instructions of the same shader program in parallel. For example, the shader core 416 may execute the main shader 426 for each pixel that defines a given shape. The shader core 416 may transmit and receive data from applications executing on the CPU 402. In examples, constants 406 used for execution of the shaders 424-426 may be stored in a constant memory 420 (e.g., a read / write constant RAM) or the GPRs 418. The shader core 416 may load the constants 406 into the constant memory 420. In further examples, execution of the early preamble shader 424 or the feedback shader 425 may cause a constant value or a set of constant values to be stored in on-chip memory such129025-2381WO01Qualcomm Ref. No. 2404558WO 27 as the constant memory 420 (e.g., constant RAM), the GPU memory 422, or the system memory 440. The constant memory 420 may include memory accessible by all aspects of the shader core 416 rather than just a particular portion reserved for a particular thread such as values held in the GPRs 418.

[0085] In recent years, vehicle manufacturers have been developing vehicles with assisted driving and / or autonomous driving capabilities. Assisted driving, which may also be called advanced driver assistance systems (ADAS), may refer to a set of technologies designed to enhance vehicle safety and improve the driving experience by providing assistance and automation to the driver. These technologies may use various sensor(s), such as camera(s), radar(s), light detection and ranging (lidar(s) or lidar sensor(s)), etc., and other components to monitor a vehicle’s surroundings and assist the driver of the vehicle with certain driving tasks. For example, some features of assisted driving systems may include: (1) adaptive cruise control (ACC) (e.g., a system that automatically adjusts a vehicle’s speed to maintain a safe following distance from the vehicle ahead), (2) lane-keeping assist (LKA) (e.g., a system that uses cameras to detect lane markings and helps keep the vehicle centered within the lane, and provides steering inputs to prevent unintentional lane departure), (3) autonomous emergency braking (AEB) (e.g., a system that detects potential collisions with obstacles or pedestrians and automatically apply the brakes to avoid or mitigate the impact), (4) blind spot monitoring (BSM) (e.g., a system that uses sensors to detect vehicles in a driver’s blind spots and provides visual or audible alerts to avoid potential collisions during lane changes), (5) parking assistance (e.g., a system that assists drivers in parking their vehicles by using camera(s) and sensor(s) to help with parallel parking or maneuvering into tight spaces), and / or traffic sign recognition (e.g., camera(s) and image processing are used to recognize and display traffic signs such as speed limits, stop signs, and other road regulations on the vehicle’s dashboard).

[0086] Autonomous driving, which may also be called as self-driving or driverless technology, may refer to the ability of a vehicle to navigate and operate itself without specifying human intervention (e.g., travelling from one place to another place without a human controlling the vehicle). The goal of the autonomous driving is to create vehicles that are capable of perceiving their surroundings, making decisions, and controlling their movements, all without the direct involvement of a human driver. To achieve or improve the autonomous driving, a vehicle may be specified to use a map (or map data) with detailed information, such as a high-definition (HD)129025-2381WO01Qualcomm Ref. No. 2404558WO 28 map. An HD map may refer to a highly detailed and accurate digital map designed for use in autonomous driving and ADAS. In one example, HD maps may typically include one or more of: (1) geometric information (e.g., precise road geometry, including lane boundaries, curvature, slopes, and detailed 3D models of the surrounding environment), (2) lane-level information (e.g., information about individual lanes on the road, such as lane width, lane type (e.g., driving, turning, or parking lanes), and lane connectivity), (3) road attributes (e.g., data on road features like traffic signs, signals, traffic lights, speed limits, and road markings), (4) topology (e.g., information about the relationships between different roads, intersections, and connectivity patterns), (5) static objects (e.g., locations and details of fixed objects along the road, such as buildings, traffic barriers, and poles), (6) dynamic objects (e.g., real-time or frequently updated data about moving objects, like other vehicles, pedestrians, and cyclists), and / or (7) localization and positioning: precise reference points and landmarks that help in accurate vehicle localization on the map, etc.

[0087] Note while some assisted / autonomous driving systems may demand the use of HD map data, there are also assisted / autonomous driving systems and information systems that may be configured not to use HD map data (e.g., due to costs). For example, the Society of Automotive Engineers (SAE) has defined six levels of driving automation, from Level 0 (no automation) to Level 5 (full automation). For Level 0 (no automation), the human driver may be responsible for all aspects of driving, and the system may provide warnings or momentary assistance but does not take control of the vehicle. Example features for SAE Level 0 may include automatic emergency braking, blind spot warnings, and lane departure warnings, etc. As such, SAE Level 0 may not specify using HD map data. For Level 1 (driver assistance), the vehicle may assist with either steering or acceleration / deceleration (but may not perform both simultaneously). The human driver is still responsible for most driving tasks and may need to be ready to take over at any time. Example features for SAE Level 1 may include adaptive cruise control or lane-keeping assistance (e.g., lane centering), etc. For Level 2 (partial automation), the vehicle may control both steering and acceleration / deceleration under certain conditions, but the human driver is requested to remain engaged and monitor the driving environment at all times. Example features for SAE Level 2 may include ADAS, adaptive cruise control and lane-keeping assistance at the same time, etc. For Level 3 (conditional automation), the vehicle may perform all driving tasks under specific conditions, and the human driver may not be129025-2381WO01Qualcomm Ref. No. 2404558WO 29 specified to monitor the environment but may need to be ready to take over when requested by the system. Example features for SAE Level 3 may include traffic jam chauffeur, where the vehicle is capable of handling driving in traffic jams without driver intervention. For Level 4 (high automation), the vehicle is capable of handling all driving tasks within certain conditions or environments (geofenced areas). The system may operate without human intervention but may specify a human driver outside its operational domain. Example features for SAE Level 4 may include local driverless taxi and pedal s / steering, etc. For Level 5 (full automation), the vehicle is capable of performing all driving tasks under all conditions, and does not specify the human driver at any time. Example features for SAE Level 5 may include fully autonomous vehicles with no steering wheel or pedals. In summary, SAE Level 0 may be defined as features to provide warnings and assistance. ADAS is usually SAE Level 1 and 2, while AD is considered SAE level 3 to 5. Aspects presented herein (described below) may apply to all levels of SAE, including SAE Level 0 (e.g., for speed warning). For purposes of the present disclosure, a system or information system that is used in associated with SAE Level 0 to Level 5 may collectively be referred to as a “vehicle system,” which may encompass the assisted driving and the autonomous driving.

[0088] To enable a vehicle to be capable of providing assisted driving and / or autonomous driving, the vehicle may be configured to use various machine learning (ML) and / or neural network (NN) frameworks. An ML / NN framework may refer to a set of tools, libraries, and / or software components that are configured to provide a structured way to design, build, and deploy ML / NN models and applications. These frameworks may be able to simplify the process of developing ML / NN algorithms and applications by providing a foundation of pre-built functions, algorithms, and utilities. They may typically include features for data preprocessing, model training, evaluation, and / or deployment, etc. ML / NN frameworks may come in various programming languages, and they may be configured to cater to different types of machine learning tasks, including supervised learning, unsupervised learning, and / or reinforcement learning, etc. An ML / NN model may refer to a mathematical representation of a real-world process or problem, created using ML / NN algorithms and techniques. These ML / NN models may be configured to make predictions, classify data, and / or solve specific tasks based on patterns and relationships learned from input data. A deep learning framework may refer to a specialized software library or toolset that provides129025-2381WO01Qualcomm Ref. No. 2404558WO 30 specified components and abstractions for building, training, and deploying deep neural networks. Deep learning frameworks may be designed to facilitate the development of complex neural network models, especially deep neural networks with multiple layers. These frameworks may offer a wide range of pre-implemented layers, optimizers, loss functions, and other components, making it easier for researchers and developers to work with deep learning models.

[0089] FIG. 5 is a diagram 500 illustrating an example of a vehicle performing road object detection using different types of sensors in accordance with various aspects of the present disclosure. In some implementations, a vehicle system may be configured to perform road object detections using multiple types of sensors (and also one or more ML / NN models). For purposes of the present disclosure, a road object or a traffic participant may refer to an object that is related to roads and driving, and is typically / commonly used / considered by the vehicle system in providing assisted driving or performing autonomous driving. In some examples, the road object / traffic participant may also be referred to as a traffic-related object. For example, a road object / traffic participant may be another vehicle, a pedestrian, a cyclist / bicycle, an animal, a traffic cone, a traffic sign, a traffic light, traffic, a traffic lane, a traffic line, a vulnerable road user (VRU), an object that is within a threshold distance of the vehicle, and / or any objects that may typically present on the roads (e.g., on the driving paths of vehicles), etc. On the other hand, a non-road object or a non-traffic participant (which may also be referred to as a non-traffic related object) may refer to an object that is not related to roads and driving, and is typically / commonly not used / considered by the vehicle system in providing assisted driving or performing autonomous driving. For example, a non-road object / non-traffic participant may be an object that is not within a threshold distance of the vehicle (e.g., a house on the side of the road, a mountain that is far away), an object that is not typically presented on a driving path / road (an airplane, a fire hydrant, a tree, etc.), a structure that is typically not traversed by vehicles (e.g., a pedestrian bridge), etc. An ML / NN model may be trained to identify whether an object is a road object or a non-road object.

[0090] For example, as shown by the diagram 500, a vehicle or a vehicle system (collectively as a “UE 502”) may be configured to use different types of sensors, such as a set of cameras 504 and / or a set of radars 506 for detecting road objects. For purposes of the present disclosure, the term “radar” may broadly refer to a device / component that is capable of detecting at least the presence and / or the distance of a physical object.129025-2381WO01Qualcomm Ref. No. 2404558WO 31Examples of radar may include an RF radar, a sonar, an ultrasonic sensor, a light detection and ranging (lidar), etc. In some implementations, the UE 502 may also use different MN / NN models for identifying different types of road objects. For example, a first ML / NN model may be trained / used to detect and track polylines from sensor output(s) (e.g., images captured by the camera(s) of the vehicle, point clouds generated from radar(s) / lidar(s), etc.), while a second ML / NN model may be trained / used to detect and track objects in a three-dimensional (3D) space (e.g., to perform 3D object detection (3D0D) tasks). Then, the outputs of different types of sensors (e.g., from the set of cameras 504 and the set of radars 506) may be processed and used by the ADAS or the autonomous driving system (e.g., for assisted / autonomous driving). A point cloud may refer to a discrete set of data points in space, where these points may represent a 3D shape or object. In some implementations, each point position may be associated with a set of Cartesian coordinates (X, Y, Z). Point clouds may be produced by radar(s) / lidar(s) by detecting multiple points on the external surfaces of objects.

[0091] As described in connection with FIG. 5, various applications (e.g., use cases) such as assisted driving and / or autonomous driving, may specify the use of map data. To keep the map data up-to-date, these applications (or devices running these applications) may be configured to download updated map data from a server from time to time or based on certain pre-defined conditions (e.g., when travelling to an area that is without map data). In some implementations, downloading map data from a server may be referred to as “map over the air” (MOTA).

[0092] FIG. 6 is a diagram 600 illustrating an example of a vehicle performing map over the air in accordance with various aspects of the present disclosure. In one example, map over the air may refer to a process of a server 604 sending (real-time) map data 606 to a UE 602 (e.g., a vehicle, a vehicle system, an on-board unit (OBU) of the vehicle, a device running a navigation application, etc.) over a wireless network / communication (e.g., an LTE network, a 5G network, etc.), enabling the UE 602 to make decisions based on the latest information about the road and traffic conditions. Depending on implementations and conditions, different amount of map data 606 may be downloaded by the UE 602 from the server 604. For example, in some scenarios, the UE 602 may be configured to (1) download map data before driving, (2) download just updates for road conditions (e.g., traffic jams, construction work, etc.) while driving, (3) continuously download updated map data whenever129025-2381WO01Qualcomm Ref. No. 2404558WO 32 available, or (4) a combination thereof (e.g., the UE 602 may download map data before driving, and continuously to download the updates while driving, including changes in map data (e.g., newly opened or closed street / highway, short term construction work). In some scenarios, the UE 602 may also be configured to stream the map data 606, which means the UE 602 does not download the map data before driving (e.g., the map data is streamed in real-time while the UE 602 is driving).

[0093] In a typical implementation, the map data 606 is transmitted from the server 604 (e.g., a cloud-based system), where the server 604 may utilize sensors and other data sources to collect and analyze information about the road network and traffic patterns. For example, the server 604 may receive and gather traffic / road information provided by a group of UEs (e.g., vehicles, roadside units (RSUs), etc.). In some examples, the information / data collected by a server from multiple UEs may be referred to as “fleet data” or “crowdsourced / crowdsourcing data.” This data may be processed and combined with other data, such as GPS / GNSS and / or camera data from multiple users (e.g., from other UEs / vehicles and / or the UE 602) to create a detailed map of the environment in real-time. Then, an application (e.g., for autonomous driving, navigation, positioning, etc.) of the UE 602 may access the map data 606 over a wireless network (e.g., a cellular or satellite network), and use the map data 606 to make decisions about speed, route, and other factors, etc. For example, the UE 602 may use the map data 606 to avoid road construction, traffic congestion, or accidents, and to optimize its route for efficiency and safety, etc. In some examples, as shown at 610, the UE 602 may also be configured to receive (additional) road / map information from another road entity 608, such as from another vehicle / UE, a roadside unit (RSU), or a traffic / road infrastructure (e.g., traffic lights), such as based on vehicle-to- everything (V2X) communication protocol / technology.

[0094] Map data with lane-level information, such as road-maps with lane-level connectivity, may play a crucial role in enhancing the safety, the efficiency, and / or the overall performance of autonomous driving systems and ADAS systems, and may also contribute to the realization of a safer and more connected transportation future. For purposes of the present disclosure, a map data with lane-level information / connectivity may be referred to as a “lane-map,” a “lane-level map,” “lane-map data,” and / or “lane-level map data,” etc., which may indicate that the map data includes information related to different lanes of a road. In addition, depending on the context, the term “map data” may be used interchangeably with the term “map.”129025-2381WO01Qualcomm Ref. No. 2404558WO 33

[0095] In some aspects, driving systems for vehicles (e.g., autonomous driving systems) may include a number of circuits or components. For instance, driving systems may include a system-on-chip (SoC), which is an integrated circuit that may integrate most or all of the components of a computer system or electronic system. These components in the system may include an on-chip central processing unit (CPU), memory interfaces, input / output devices and interfaces, and / or secondary storage interfaces. An SoC may also include other components, such as modems and a graphics processing unit (GPU). SoCs may also contain digital functions, analog functions, mixed-signal functions, and / or signal processing functions. An SoC may also integrate a microcontroller, a microprocessor, or several processor cores with peripherals (e.g., a GPU, Wi-Fi and cellular network radio modems, and / or one or more processors). Additionally, an SoC may integrate a microcontroller with advanced peripherals. Compared to a multi-chip architecture, an SoC with equivalent functionality may have reduced power consumption.

[0096] As used herein, the term system-on-a-chip (SoC) may refer to an integrated electronic device comprising one or more integrated circuit (IC) dies (e.g., chiplets), which combines multiple electronic components (e.g., processors and / or memory) on a single substrate or in a single package. An SoC may contain circuitry for digital, analog, mixed-signal, and / or radio-frequency functions. An SoC may also include any number of general purpose and / or specialized processors (digital signal processors, modem processors, video processors, etc.), memory blocks (e.g., ROM, RAM, DRAM, flash, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.). An SoC may also include software for controlling the integrated resources and processors, as well as for controlling peripheral devices.

[0097] In addition, driving systems for vehicles may include an electronic control unit (ECU), which may also be referred to as an electronic control module (ECM). An ECU is an embedded system in automotive electronics that may control one or more of the electrical systems or subsystems in a vehicle. An ECU’s main function may be to keep the engine working smoothly. For example, an ECU may control everything in the engine, including the wheel speed, braking power, ignition timing, idle speed, the air / fuel mixture, etc. On vehicles with an electronic fuel injection, an ECU may control the amount of fuel that enters the engine’s cylinders. Modem vehicles have a number of different ECUs, which can include one or more of: an ECM, a powertrain control module (PCM), a transmission control module (TCM), a brake control module129025-2381WO01Qualcomm Ref. No. 2404558WO 34(BCM), a central control module (CCM), a central timing module (CTM), a general electronic module (GEM), a body control module (BCM), and a suspension control module (SCM). These ECUs may be referred to as a vehicle’s computer, although technically they are all separate computers. An ECU may also include one or more SoCs. Some modern vehicles may have a large number of ECUs (e.g., up to 150 ECUs). Further, software may be embedded in ECUs. Managing the increasing complexity and number of ECUs in a vehicle is a challenge for original equipment manufacturers (OEMs). Also, automated driving may include certain technologies (e.g., advanced driver-assistance systems (ADAS) technologies) that assist drivers with the safe operation of a vehicle. Through a human-machine interface, these features (e.g., ADAS features) may increase car and road safety. ADAS features may use automated technology, such as sensors and cameras, to detect nearby obstacles or driver errors, and respond accordingly. ADAS features may enable various levels of autonomous driving.

[0098] Recently, automobiles have been transformed from a self-propelled mechanical vehicle into a powerful and complex electro-mechanical system that includes a large number of sensors and processors that control many of the vehicle's functions, features, and operations. Vehicles may be equipped with a vehicle control system, which may be configured to collect and use information from the vehicle’s various systems and sensors to automate all or a portion of the vehicle's operations. For example, an advanced driver assistance system (ADAS) may automate, adapt, or enhance the vehicle’ s operations. The ADAS may use information collected from the sensors (e.g., accelerometer, radar, lidar, geospatial positioning, etc.) to automatically detect a potential road hazard, and assume control over all or a portion of the vehicle’s operations (e.g., braking, steering, etc.) to avoid detected hazards. Features and functions commonly associated with an ADAS include adaptive cruise control, automated lane detection, lane departure warning, automated steering, automated braking, and automated collision avoidance. The vehicle monitors for errors associated with the control system, and the vehicle may notify the operator of such errors, shut down certain systems, or operate in a degraded state in response to detecting certain errors. Additionally, there are a number of different automotive safety integrity levels (ASILs), which is a risk classification system for functional safety of road vehicles. Different ASILs may correspond to different automotive components. For example, ASIL A (ASILA or ASIL-A) may correspond to rear129025-2381WO01Qualcomm Ref. No. 2404558WO 35 lights, heating and cooling, body control units, ASIL B (ASILB or ASIL-B) may correspond to brake lights, rear view camera, instrument cluster, ASIL C (ASILC or ASIL-C) may correspond to adaptive cruise control, battery management, suspension, and ASIL D (ASILD or ASIL-D) may correspond to airbags, antilock braking, electric power steering.

[0099] Some types of automotive systems may utilize a system-on-a-chip (SoC). In automotive systems and products that include an SoC, these systems and products may also utilize components to meet certain functional safety conditions / specifications (e.g., assumptions of use (AoU) conditions / specifications). For example, automotive systems and products may utilize a microcontroller unit (MCU) or an external MCU for functional safety reasons and / or to meet functional safety AoU conditions. MCUs may be particularly utilized in system-in-packages (SiPs), such as with integrated power management integrated circuit (PMICs), without integrated PMICs, and / or with pre-regulators. In some instances, there may be several types of interfaces that are needed for safety interconnection and monitoring. For instance, there may be different types of interfaces for safety interconnection and monitoring between an SoC and a PMIC, between a PMIC and a pre-regulator to the external MCU. Example interfaces may utilize a number of different components (e.g., a single point, input-outputs (10s), general purpose inputoutputs (GPIOs), analog-digital converters (ADCs), inter-integrated circuits (I2Cs), serial peripheral interface (SPI), and / or universal asynchronous receiver transmitter (UART).

[0100] Most iterations of SoCs shows a significant increase in feature capabilities, as well as an increase in overall performance compared to power consumption. In order to support new power modes and lower power consumption for specific product configurations, some feature clusters (e.g., image signal processor (ISP), graphics processing unit (GPU), central processing unit (CPU) clusters, neural processing unit (NPU) clusters, display processing unit (DPU), etc.) may need to work independent of others. For instance, these clusters may need to work independent of others to be activated, in reset, on hold, and / or completely disabled. Additionally, the increased power consumption of SoCs may lead to an increase in control and safety monitoring interfaces. For instance, new and complex power mode architectures may lead to a strong increase in control and safety monitoring interfaces, which may be supported by several PMICs and related pre-regulators.129025-2381WO01Qualcomm Ref. No. 2404558WO 36

[0101] FIG. 7 is a diagram 700 illustrating an example PCB and SoC. More specifically, diagram 700 depicts a PCB and SoC that are utilized in automotive systems. As shown in FIG. 7, diagram 700 includes PCB 702 including different random access memories (RAMs) (e.g., RAM 711 and RAM 712), SoC 720 including main domain (MD) 721 and safety island 722, MCU PMIC 730, MCU 731, MD ASILB PMIC master 740, MD ASILB PMIC slave 741, safety ASILD PMIC master 742, preregulator 750, and pre-regulator 751. FIG. 7 display a number of different connections and interfaces between the different components in PCB 702. For example, MD 721 can communicate with MD ASILB PMIC master 740 and MD ASILB PMIC slave 741. Safety island 722 can communicate with safety ASILD PMIC master 742. MCU 731 can communicate with MD ASILB PMIC master 740, MD ASILB PMIC slave 741, safety ASILD PMIC master 742, pre-regulator 750, and pre-regulator 751. Further, pre-regulator 750 can communicate with MD ASILB PMIC master 740 and pre-regulator 751 can communicate with safety ASILD PMIC master 742.

[0102] FIG. 8 is a diagram 800 illustrating an example PCB, SoC, and SiP. More specifically, diagram 800 depicts a PCB, SoC, and SiP that are utilized in automotive systems. As shown in FIG. 8, diagram 800 includes PCB 802 including SiP 810 with different random access memories (RAMs) (e.g., RAM 811 and RAM 812), SoC 820 including MD 821 and safety island 822, MCU PMIC 830, MCU 831, MD ASILB PMIC master 840, MD ASILB PMIC slave 841, safety ASILD PMIC master 842, pre-regulator 850, and pre-regulator 851. FIG. 8 display a number of different connections and interfaces between the different components in PCB 802. For example, MD 821 can communicate with MD ASILB PMIC master 840 and MD ASILB PMIC slave 841. Safety island 822 can communicate with safety ASILD PMIC master 842. MCU 831 can communicate with MD ASILB PMIC master 840, MD ASILB PMIC slave 841, safety ASILD PMIC master 842, pre-regulator 850, and pre-regulator 851. Also, preregulator 850 can communicate with MD ASILB PMIC master 840 and pre-regulator 851 can communicate with safety ASILD PMIC master 842.

[0103] FIG. 9 is a diagram 900 illustrating an example PCB, SoC, and SiP. More specifically, diagram 900 depicts a PCB, SoC, and SiP that are utilized in automotive systems. As shown in FIG. 9, diagram 900 includes PCB 902 including SiP 910 with different random access memories (RAMs) (e.g., RAM 911 and RAM 912), SoC 920 including MD 921 and safety island 922, MCU PMIC 930, MCU 931, MD ASILB PMIC master129025-2381WO01Qualcomm Ref. No. 2404558WO 37940, MD ASILB PMIC slave 941, safety ASILD PMIC master 942, pre-regulator 950, and pre-regulator 951. FIG. 9 display a number of different connections and interfaces between the different components in PCB 902. For example, MD 921 can communicate with MD ASILB PMIC master 940 and MD ASILB PMIC slave 941. Safety island 922 can communicate with safety ASILD PMIC master 942. MCU 931 can communicate with MD ASILB PMIC master 940, MD ASILB PMIC slave 941, safety ASILD PMIC master 942, pre-regulator 950, and pre-regulator 951. Moreover, pre-regulator 950 can communicate with MD ASILB PMIC master 940 and preregulator 951 can communicate with safety ASILD PMIC master 942.

[0104] FIG. 10 is a diagram 1000 illustrating an example PCB, SoC, and SiP. More specifically, diagram 1000 depicts a PCB, SoC, and SiP that are utilized in automotive systems. As shown in FIG. 10, diagram 1000 includes PCB 1002 including SiP 1010 with different random access memories (RAMs) (e.g., RAM 1011 and RAM 1012), SoC 1020 including MD 1021 and safety island 1022, MCU PMIC 1030, MCU 1031, MD ASILB PMIC master 1040, MD ASILB PMIC slave 1041, safety ASILD PMIC master 1042, pre-regulator 1050, and pre-regulator 1051. FIG. 10 display a number of different connections and interfaces between the different components in PCB 1002. For example, MD 1021 can communicate with MD ASILB PMIC master 1040 and MD ASILB PMIC slave 1041. Safety island 1022 can communicate with safety ASILD PMIC master 1042. MCU 1031 can communicate with MD ASILB PMIC master 1040, MD ASILB PMIC slave 1041, safety ASILD PMIC master 1042, preregulator 1050, and pre-regulator 1051. Further, pre-regulator 1050 can communicate with MD ASILB PMIC master 1040 and pre-regulator 1051 can communicate with safety ASILD PMIC master 1042.

[0105] FIGs. 7-10 show different example PCBs and SoCs that are utilized in automotive systems. FIG. 7 displays a chip-on-board (CoB) without a SiP module. FIG. 8 illustrate a SiP module with an intergraded SoC, SoC-RAM, which may be referred to as a near DRAM package instead of a SiP. FIG. 9 depicts a SiP module with an integrated SoC, SoC-RAM and SoC related PMICs for different safety areas / instances of an automotive SoC. FIG. 10 shows a SiP module with additional integrated SoC related pre-regulators. As shown in FIGs. 7-10, the MDs and safety islands may be separate safety instances. Referring to FIG. 9, there may be a control and monitoring interface to assist with the safety controls and monitoring of components. FIG. 9 may also include MCU 931 to cover functional safety AoUs from SoC safety manuals.129025-2381WO01Qualcomm Ref. No. 2404558WO 38

[0106] The automotive system PCBs and SoCs in FIGs. 7-10 show that an increase in control and safety monitoring interfaces may lead to a corresponding increase in power consumption of PCBs and SoCs, as well as an increase in cost. For instance, new and complex power mode architectures may lead to a strong increase in control and safety monitoring interfaces, which may be supported by several PMICs and related preregulators. Further, the increased number of control and monitoring interfaces of SoCs and the parallel complexity increase of the product ECUs themselves may lead to more expensive MCUs to provide enough interfaces. The actual generation of SoCs and SiPs may not be able to handle all relevant functional safety interfaces without an external MCU. At the same time the amount of interfaces has significantly increased, which results in higher costs for SiP modules. For example, an increase in the number of interfaces may lead to a corresponding increase in the amount of pins that are utilized by SiP components, which results in an increased cost. As indicated herein, automotive systems can include a number of different components (e.g., ICs and SoCs) that include an increased number of connections and complex communication, which results in an increase in power consumption, as well as an increase in cost. Based on the above, it may be beneficial to introduce a component that can reduce the number of connections utilized in automotive systems including SoCs and SiPs. Also, it may be beneficial to introduce a component that can reduce the power consumption in automotive systems including SoCs and SiPs. It may also be beneficial to introduce a component that can reduce cost of operating automotive systems including SoCs and SiPs.

[0107] Aspects of the present disclosure may include components that can reduce the number of connections utilized in automotive systems including SoCs and SiPs. For instance, aspects presented herein may provide a microprocessor or microcontroller (i.e., a safety controller) to reduce the number of connections utilized in automotive systems including SoCs and SiPs. Aspects presented herein may also reduce the power consumption in automotive systems including SoCs and SiPs. That is, aspects presented herein may utilize a microprocessor or microcontroller (i.e., a safety controller) to reduce the power consumption in automotive systems including SoCs and SiPs. Additionally, aspects presented herein may introduce a component that can reduce cost of operating automotive systems including SoCs and SiPs. For example, aspects presented herein may utilize a microprocessor or microcontroller (i.e., a safety controller) to reduce the cost of operating automotive systems including SoCs and129025-2381WO01Qualcomm Ref. No. 2404558WO 39SiPs. Indeed, the integration of a safety controller to simplify communication within SoCs and SiPs allows aspects presented herein to reduce the cost of operating automotive systems including SoCs and SiPs.

[0108] Aspects presented herein may utilize different components (e.g., a microprocessor, a microcontroller, or a safety controller) in order to manage and control the communications within PCBs, SoCs, and / or SiPs. Aspects presented herein may utilize a certain component (e.g., a microprocessor, a microcontroller, or a safety controller) depending on a safety level (e.g., an ASIL level) that is desired to be achieved. That is, aspects presented herein may utilize different components (e.g., a microprocessor, a microcontroller, or a safety controller) to handle safety management or functional safety management. In some instances, a safety control may be a microcontroller with a CPU, which can function lockstep depending on the safety level we are targeting. Indeed, safety controllers according to the present disclosure may be able to handle a number of different operations, such as double calculations and / or operations for different power levels or voltage levels. For example, safety controllers herein may utilize a voltage monitor and a voltage input in order to compare that the voltage is on a certain level. Safety controllers herein may utilize voltage control interfaces to ensure that the voltage does not drop below a certain level, or that ensure that the voltage does not rise above a certain level. Also, a safety controller may keep interfaces and checks these interfaces regularly. For example, safety controllers may control a timing or a clock (e.g., a clock of a PMIC) within automotive PCBs, SoCs, and / or SiPs.

[0109] Aspects presented herein may utilize a microprocessor or microcontroller (i.e., a safety controller) to utilize a SiP integrated safety controller. Safety controllers described herein may be a microprocessor or a microcontroller with a CPU within an automotive chip (including a SiP, an SoC, and / or a PMIC)). Microprocessors or microcontrollers (i.e., safety controllers) herein may empower the SoC to be fully functional on a certain safety level (e.g., ASIL-D level). Also, microprocessors or microcontrollers (i.e., safety controllers) herein may allow the SoC to be fully functional on a certain safety level without the need of an additional safety microcontroller (e.g., MCU). Microprocessors or microcontrollers (i.e., safety controllers) herein can significantly lower the costs of an SoC, compared to a normal MCU that contains additional features, such as more CPUs that are not utilized for an intended use. Additionally, microprocessors or microcontrollers (i.e., safety129025-2381WO01Qualcomm Ref. No. 2404558WO 40 controllers) herein may allow aspects presented herein to be fully integrated into a certain safety level (e.g., SoC safety island). Further, microprocessors or microcontrollers (i.e., safety controllers) herein can significantly reduce the amount of SiP interface that is needed to support an additional safety monitoring component (e.g., an additional MCU as a safety monitor). Microprocessors or microcontrollers (i.e., safety controllers) herein can be utilized with all SiP-related use cases, such as those use cases with SiP integrated PMICs and / or pre-regulators.

[0110] Some types of safety components or MCUs may utilize a large amount of connections or CPUs in order to handle all of the safety functions needed. Microprocessors or microcontrollers (i.e., safety controllers) utilized herein may allow for a reduced amount of connections or CPUs in order to handle all of the safety functions in an automotive system. Further, with an increased number of interfaces, some safety components or MCUs may also increase the number of CPUs. In contrast, microprocessors or microcontrollers (i.e., safety controllers) utilized herein may handle an increased number of interfaces with a reduced number of CPUs. Moreover, microprocessors or microcontrollers (i.e., safety controllers) utilized herein may reduce the need to integrate additionally interfaces. Indeed, microprocessors or microcontrollers (i.e., safety controllers) utilized herein may allow aspects presented herein to reduce the number of connections utilized in automotive systems including SoCs and SiPs. By doing so, microprocessors or microcontrollers (i.e., safety controllers) utilized herein may allow aspects presented herein to reduce the power consumption and / or the cost of operating automotive systems including SoCs and SiPs. That is, aspects presented herein may add a microcontroller or microprocessor (i.e., safety controller) to automotive systems including SoCs and SiPs in order to reduce the necessary complexity of other CPUs and / or MCUs.

[0111] Aspects presented herein may provide microcontrollers or microprocessors (i.e., safety controllers) that allow for many interfaces to be directly handled on a certain level. For instance, microcontrollers or microprocessors (i.e., safety controllers) herein may allow for many interfaces to be directly handled on a SoC or SIP level. In one example, aspects presented herein may integrate the microcontroller or microprocessor (i.e., safety controller) at the SIP outside of the SoC. Further, aspects presented herein may integrate the microcontroller or microprocessor (i.e., safety controller) within the SoC. Aspects presented herein may also split this integration and integrate a portion of the functionality into the SoC and integrate a portion of the129025-2381WO01Qualcomm Ref. No. 2404558WO 41 functionality into the PMIC. Aspects presented herein may also leverage the PMIC functionalities for the microcontroller or microprocessor (i.e., safety controller). From a safety perspective, it may be beneficial to distribute the functions between different modules (e.g., PMIC and SoC). In one instance, aspects presented herein may split the different needs of the components and try to leverage and improve the PMIC to have a reduced number of control interfaces and the remaining functionalities may be handled by the SoC. Indeed, microcontrollers or microprocessors (i.e., safety controllers) herein may split the different needs and features of the safety components and integrate them between different modules (e.g., PMIC and SoC).

[0112] In some instances, current automotive SoCs may utilize external safety microcontroller units (MCUs) for functional safety reasons to meet the functional safety AoU conditions. With more complex SoCs, the number of necessary control and monitoring interfaces of the SoCs may increase, which leads to more expensive MCUs to provide enough interfaces. For example, the SiPs with PMICs and preregulators may need several interfaces for safety inter-connection and monitoring between the SoC and PMIC and / or the PMIC and pre-regulator to the external MCU. Aspects presented herein propose to integrate a safety controller within a SiP, which enables the SoC to be ASIL compliant (e.g., ASIL-D compliant) without the need of an additional safety MCU. The safety controller according to aspects presented herein may lower the cost to produce automotive chips. Also, aspects presented herein may eliminate the SiP interfaces for an external PMIC, pre-regulator control and monitoring, lower SiP module costs, and / or lower the SiP integration complexity and costs.

[0113] FIG. 11 is a diagram 1100 illustrating an example PCB and SoC. More specifically, diagram 1100 depicts a PCB, a SiP, and an SoC that are utilized in automotive systems. As shown in FIG. 11, diagram 1100 includes PCB 1102 including SiP 1110 with different random access memories (RAMs) (e.g., RAM 1111 and RAM 1112), SoC 1120 including MD 1121 and safety island 1122, safety controller 1130, MD ASILB PMIC master 1140, MD ASILB PMIC slave 1141, safety ASILD PMIC master 1142, pre-regulator 1150, and pre-regulator 1151. FIG. 11 display a number of different connections and interfaces between the different components in PCB 1102. For example, MD 1121 can communicate with MD ASILB PMIC master 1140 and MD ASILB PMIC slave 1141. Safety island 1122 can communicate with safety129025-2381WO01Qualcomm Ref. No. 2404558WO 42ASILD PMIC master 1142. Safety controller 1130 can communicate with MD ASILB PMIC master 1140, MD ASILB PMIC slave 1141, safety ASILD PMIC master 1142, pre-regulator 1150, and pre-regulator 1151. Further, pre-regulator 1150 can communicate with MD ASILB PMIC master 1140 and pre-regulator 1151 can communicate with safety ASILD PMIC master 1142.

[0114] As shown in FIG. 11, SiP 1110 may include safety controller 1130, which may be connected to MD ASILB PMIC master 1140, MD ASILB PMIC slave 1141, safety ASILD PMIC master 1142, pre-regulator 1150, and pre-regulator 1151. Safety controller 1130 (e.g., a microprocessor or microcontroller) may empower the SoC to be fully functional on a certain safety level (e.g., ASIL-D level). Safety controller 1130 (e.g., a microprocessor or microcontroller) may allow a high number of control and monitoring interfaces to remain inside the SiP 1110, thus lowering the integration costs of SiP 1110. Moreover, safety controller 1130 (e.g., a microprocessor or microcontroller) may allow for a reduced number of interfaces between SiP 1110 and PCB 1102. In addition, safety controller 1130 (e.g., a microprocessor or microcontroller) herein may allow the SiP 1110 and SoC 1120 to be fully functional on a certain safety level without the need of an additional safety microcontroller (e.g., MCU). Safety controller 1130 (e.g., a microprocessor or microcontroller) can lower the costs of a SiP or SoC (e.g., SiP 1110 or SoC 1120), compared to a normal MCU that contains additional features. Also, safety controller 1130 (e.g., a microprocessor or microcontroller) may significantly reduce the amount of SiP interface that is needed to support an additional safety monitoring component (e.g., an additional MCU as a safety monitor). Safety controller 1130 (e.g., a microprocessor or microcontroller) can be utilized with all SiP-related use cases, such as those use cases with SiP integrated PMICs and / or pre-regulators.

[0115] Safety controller 1130 (e.g., a microprocessor or microcontroller) may allow for a reduced amount of connections or CPUs in order to handle all of the necessary safety functions in an automotive system. That is, safety controller 1130 (e.g., a microprocessor or microcontroller) may handle an increased number of interfaces with a reduced number of CPUs. Further, safety controller 1130 (e.g., a microprocessor or microcontroller) may reduce the need to integrate additionally interfaces. Safety controller 1130 (e.g., a microprocessor or microcontroller) may allow aspects presented herein to reduce the number of connections utilized in automotive systems including SiP 1110 and SoC 1120. By doing so, safety controller129025-2381WO01Qualcomm Ref. No. 2404558WO 431130 (e.g., a microprocessor or microcontroller) may allow aspects presented herein to reduce the power consumption and / or the cost of operating automotive systems including SiP 1110 and SoC 1120. Indeed, aspects presented herein may include safety controller 1130 (e.g., a microprocessor or microcontroller) in automotive systems including SiP 1110 and SoC 1120 in order to reduce the necessary complexity of other CPUs and / or MCUs.

[0116] FIG. 12 is a diagram 1200 illustrating an example PCB and SoC. More specifically, diagram 1200 depicts a PCB, a SiP, and an SoC that are utilized in automotive systems. As shown in FIG. 12, diagram 1200 includes PCB 1202 including SiP 1210 with different random access memories (RAMs) (e.g., RAM 1211 and RAM 1212), SoC 1220 including MD 1221 and safety island 1222, safety controller 1230, MD ASILB PMIC master 1240, MD ASILB PMIC slave 1241, safety ASILD PMIC master 1242, pre-regulator 1250, and pre-regulator 1251. FIG. 12 display a number of different connections and interfaces between the different components in PCB 1202. For example, MD 1221 can communicate with MD ASILB PMIC master 1240 and MD ASILB PMIC slave 1241. Safety island 1222 can communicate with safety ASILD PMIC master 1242. Safety controller 1230 can communicate with MD ASILB PMIC master 1240, MD ASILB PMIC slave 1241, safety ASILD PMIC master 1242, pre-regulator 1250, and pre-regulator 1251. Also, pre-regulator 1250 can communicate with MD ASILB PMIC master 1240 and pre-regulator 1251 can communicate with safety ASILD PMIC master 1242.

[0117] As shown in FIG. 12, SiP 1210 may include safety controller 1230, which may be connected to MD ASILB PMIC master 1240, MD ASILB PMIC slave 1241, safety ASILD PMIC master 1242, pre-regulator 1250, and pre-regulator 1251. Safety controller 1230 (e.g., a microprocessor or microcontroller) may empower the SoC to be fully functional on a certain safety level (e.g., ASIL-D level). Safety controller 1230 (e.g., a microprocessor or microcontroller) may allow a high number of control and monitoring interfaces to remain inside the SiP 1210, thus lowering the integration costs of SiP 1210. Further, safety controller 1230 (e.g., a microprocessor or microcontroller) may allow for a reduced number of interfaces between SiP 1210 and PCB 1202. Additionally, safety controller 1230 (e.g., a microprocessor or microcontroller) may allow the total number of interfaces between SoC 1220 and PMICs (e.g., MD ASILB PMIC master 1240, MD ASILB PMIC slave 1241, safety ASILD PMIC master 1242) to be reduced, such as by the integration of the safety129025-2381WO01Qualcomm Ref. No. 2404558WO 44 controller 1230 function to safety island 1222 and / or SoC 1220 and PMICs (e.g., MD ASILB PMIC master 1240, MD ASILB PMIC slave 1241, safety ASILD PMIC master 1242). In addition, safety controller 1230 (e.g., a microprocessor or microcontroller) herein may allow the SiP 1210 and SoC 1220 to be fully functional on a certain safety level without the need of an additional safety microcontroller (e.g., MCU). Safety controller 1230 (e.g., a microprocessor or microcontroller) can lower the costs of a SiP or SoC (e.g., SiP 1210 or SoC 1220), compared to a normal MCU that contains additional features. Moreover, safety controller 1230 (e.g., a microprocessor or microcontroller) may significantly reduce the amount of SiP interface that is needed to support an additional safety monitoring component (e.g., an additional MCU as a safety monitor). Safety controller 1230 (e.g., a microprocessor or microcontroller) can be utilized with SiP-related use cases, such as those use cases with SiP integrated PMICs and / or pre-regulators.

[0118] As shown in FIGs. 11 and 12, safety controller 1130 in FIG. 11 may include functionalities that are similar to safety controller 1230 in FIG. 12. In some aspects, safety controller 1230 (e.g., a microprocessor or microcontroller) may allow for a reduced amount of connections and / or CPUs in order to handle all of the necessary safety functions in an automotive system. That is, safety controller 1230 (e.g., a microprocessor or microcontroller) may handle an increased number of interfaces with a reduced number of CPUs. Further, safety controller 1230 (e.g., a microprocessor or microcontroller) may reduce the need to integrate additionally interfaces. Safety controller 1230 (e.g., a microprocessor or microcontroller) may allow aspects presented herein to reduce the number of connections utilized in automotive systems including SiP 1210 and SoC 1220. By doing so, safety controller 1230 (e.g., a microprocessor or microcontroller) may allow aspects presented herein to reduce the power consumption and / or the cost of operating automotive systems including SiP 1210 and SoC 1220. Indeed, aspects presented herein may include safety controller 1230 (e.g., a microprocessor or microcontroller) in automotive systems including SiP 1210 and SoC 1220 in order to reduce the necessary complexity of other CPUs and / or MCUs.

[0119] Safety controller 1130 and safety controller 1230 may include a microprocessor or a microcontroller with a CPU. Additionally, safety controller 1130 and safety controller 1230 may include a number of features for SiPs and SoCs (e.g., SiP 1110, SoC 1120, SiP 1210, and SoC 1220). Safety controller 1130 and safety controller 1230 may129025-2381WO01Qualcomm Ref. No. 2404558WO 45 allow SiPs and SoCs (e.g., SiP 1110, SoC 1120, SiP 1210, and SoC 1220) to obtain an indication of a threshold range for signals prior to monitoring a set of signals. Safety controller 1130 and safety controller 1230 may also allow SiPs and SoCs (e.g., SiP 1110, SoC 1120, SiP 1210, and SoC 1220) to monitor a set of signals associated with a regulation of a device. Additionally, safety controller 1130 and safety controller 1230 may allow SiPs and SoCs (e.g., SiP 1110, SoC 1120, SiP 1210, and SoC 1220), where the set of signals is a set of analog signals, to convert or translate the set of analog signals to a set of digital signals prior to the determination. Safety controller 1130 and safety controller 1230 may also allow SiPs and SoCs (e.g., SiP 1110, SoC 1120, SiP 1210, and SoC 1220) to measure the range of the set of analog signals based on converting or translating the set of analog signals to the set of digital signals. Safety controller 1130 and safety controller 1230 may also allow SiPs and SoCs (e.g., SiP 1110, SoC 1120, SiP 1210, and SoC 1220) to determine whether a range for the set of signals is within a threshold range for signals. Moreover, safety controller 1130 and safety controller 1230 may allow SiPs and SoCs (e.g., SiP 1110, SoC 1120, SiP 1210, and SoC 1220) to output, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals.

[0120] In some instances, aspects presented herein may utilize microprocessors or microcontrollers (i.e., safety controllers) to make SiPs independent of MCUs. In one aspect, a low cost SiP integrated safety controller (e.g., safety controller 1130) according to aspects presented herein may reduce a significant the amount of external SiP interfaces for the control and monitoring of the PMICs and pre-regulators. Additionally, a low cost SoC integrated safety controller (e.g., safety controller 1230) according to aspects presented herein may extend the functionality of safety island 1222 and make the product independently usable without any MCUs. Further, a low cost SoC integrated safety controller (e.g., safety controller 1230) according to aspects presented herein may make the product fully safety compliant without any MCUs. Aspects presented herein may improve certain types of vehicle architectures (e.g., decentral architecture, centralized architecture, zonal architecture) by using the microprocessors or microcontrollers (i.e., safety controllers) herein. Also, aspects presented herein may also allow microprocessors or microcontrollers (i.e., safety controllers) herein to be used for development or pre-development for design validation of a final full integration, as a risk mitigation. Moreover, aspects presented129025-2381WO01Qualcomm Ref. No. 2404558WO 46 herein may also utilize microprocessors or microcontrollers (i.e., safety controllers) herein to integrate pre-regulators and the control of SiPs.

[0121] Aspects of the present disclosure may include a number of benefits or advantages. For instance, aspects presented herein may provide a microprocessor or microcontroller (i.e., a safety controller) to reduce the number of connections utilized in automotive systems including SoCs and SiPs. Aspects presented herein may also reduce the power consumption in automotive systems including SoCs and SiPs. Indeed, aspects presented herein may utilize a microprocessor or microcontroller (i.e., a safety controller) to reduce the power consumption in automotive systems including SoCs and SiPs. Further, aspects presented herein may introduce a component that can reduce cost of operating automotive systems including SoCs and SiPs. For example, aspects presented herein may utilize a microprocessor or microcontroller (i.e., a safety controller) to reduce the cost of operating automotive systems including SoCs and SiPs. That is, the integration of a safety controller to simplify communication within SoCs and SiPs allows aspects presented herein to reduce the cost of operating automotive systems including SoCs and SiPs.

[0122] FIG. 13 is a communication flow diagram 1300 of frame processing in accordance with one or more techniques of this disclosure. As shown in FIG. 13, diagram 1300 includes example communications between device 1302 (e.g., a device, a vehicle, a vehicle component, a microprocessor, a microcontroller, a safety controller, a printed circuit board (PCB), a system-on-chip (SoC), an electronic control unit (ECU), a user equipment (UE), a graphics processing unit (GPU), a central processing unit (CPU), or any apparatus that may perform communication), vehicle component 1304 (e.g., a device, a vehicle, a vehicle component, a safety controller, a printed circuit board (PCB), a system-on-chip (SoC), an electronic control unit (ECU), a user equipment (UE), a graphics processing unit (GPU), a central processing unit (CPU), or any apparatus that may perform communication), and memory 1306 (e.g., a memory or a cache), in accordance with one or more techniques of this disclosure.

[0123] At 1310, device 1302 may obtain an indication of a threshold range for signals prior to monitoring a set of signals. For example, device 1302 may obtain indication 1312 from vehicle component 1304. In some aspects, the set of signals may include a set of signals for at least one of a power level at the device, a temperature sensor at the device, or an analog clock at the device. Also, the temperature sensor may correspond129025-2381WO01Qualcomm Ref. No. 2404558WO 47 to a resistance at the device, and where the analog clock is at a power management integrated circuit (PMIC) of the device.

[0124] At 1320, device 1302 may monitor a set of signals associated with a regulation of a device. In some aspects, monitoring the set of signals may comprise monitoring a translation or a modulation of the set of signals associated with the regulation of the device, and where the regulation of the device comprises a regulation of a temperature or power at the device. In some aspects, at least one of the SoC or the PMIC may include a set of error pins, where monitoring the set of signals associated with the regulation of the device comprises: monitoring the set of error pins for a change in state of the device; and monitoring the set of signals associated with the regulation of the device.

[0125] At 1330, where the set of signals is a set of analog signals, device 1302 may convert or translate the set of analog signals to a set of digital signals prior to the determination. In some aspects, converting or translating the set of analog signals to the set of digital signals may comprise: converting or translating, via a set of analog- to-digital converters, the set of analog signals to the set of digital signals.

[0126] At 1340, where the set of signals is a set of analog signals, device 1302 may measure the range of the set of analog signals based on converting or translating the set of analog signals to the set of digital signals. In some aspects, the range may include at least one of a level, the range, or an input, and where the threshold range comprises a minimum target value or a maximum target value for the signals. Also, at least one of a power level at the device, a temperature sensor at the device, or an analog clock at the device may be less than or equal to a threshold level.

[0127] At 1350, device 1302 may determine, in at least one of a system-in-package (SiP) of the device, a system on-chip (SoC) of the device, or a power management integrated circuit (PMIC) of the device, whether a range for the set of signals is within a threshold range for signals. In some aspects, determining whether the range for the set of signals is within the threshold range for signals may comprise: determining, at a microcontroller in at least one of the SiP, the SoC, or the PMIC, whether the range for the set of signals is within the threshold range for signals. Also, where the microcontroller is a safety controller, determining whether the range for the set of signals is within the threshold range for signals may comprise: determining, at the safety controller in at least one of the SiP, the SoC, or the PMIC, whether the range for the set of signals is within the threshold range for signals. Further, determining129025-2381WO01Qualcomm Ref. No. 2404558WO 48 whether the range for the set of signals is within the threshold range for signals may comprise: determining, at a sensor or a temperature sensor in at least one of the SoC or the PMIC, whether the range for the set of signals is within the threshold range for signals. Moreover, determining whether the range for the set of signals is within the threshold range for signals may comprise: determining, at a clock or an analog clock in at least one of the SiP or the SoC, whether the range for the set of signals is within the threshold range for signals. Additionally, determining whether the range for the set of signals is within the threshold range for signals may comprise: comparing at least one of the level, the range, or the input for the set of signals to a reference level, a reference range, or a reference input for signals. Also, determining whether the range for the set of signals is within the threshold range for signals may comprise: determining, at an input of a power supply, an output of the power supply, or a reference power signal in at least one of the SiP or the SoC, whether the range for the set of signals is within the threshold range for signals.

[0128] At 1360, device 1302 may output, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals. For example, device 1302 may transmit indication 1362 to vehicle component 1304. Also, device 1302 may store indication 1364 in memory 1306. In some aspects, outputting the indication to configure the source may comprise outputting, based on the range for the set of signals being outside of the threshold range, an indication to adjust the source for the set of signals. Also, outputting the indication to adjust the source for the set of signals comprise: adjusting the source for the set of signals; or outputting an indication to power down the device, stop the device, or restart the device. In some aspects, the indication may include a set of interrupt signals, and outputting the indication to power down the device, stop the device, or restart the device may comprise: outputting a set of interrupt signals to power down a system on-chip (SoC) of the device or a power management integrated circuit (PMIC) of the device, stop the SoC or the PMIC, or restart the SoC or the PMIC. In some aspects, at 1360, device 1302 may measure, within a time window prior to outputting the indication to adjust the source, the set of signals for determining that the range for the set of signals is outside of the threshold range; and monitor, within the time window and subsequent to the measurement, the set of signals. Additionally, outputting the indication to configure the source may comprise: outputting, based on the range for the set of signals being within the threshold range,129025-2381WO01Qualcomm Ref. No. 2404558WO 49 an indication to maintain the source for the set of signals. Further, outputting the indication to maintain the source for the set of signals comprise: maintaining the source for the set of signals.

[0129] FIG. 14 is a flowchart 1400 of an example method of image processing in accordance with one or more techniques of this disclosure. The method may be performed by a device, a vehicle, a vehicle component, a microprocessor, a microcontroller, a safety controller, a printed circuit board (PCB), a system-on-chip (SoC), an electronic control unit (ECU), a user equipment (UE), a graphics processing unit (GPU), a central processing unit (CPU), or any apparatus that may perform communication, and / or any apparatus that may perform communication as used in connection with the examples of FIGs. 1-13.

[0130] At 1404, the device may monitor a set of signals associated with a regulation of a device, as described in connection with the examples in FIGs. 1-13. For example, as described in 1320 of FIG. 13, device 1302 may monitor a set of signals associated with a regulation of a device. Further, step 1404 may be performed by component 198 in FIG. 1. In some aspects, monitoring the set of signals may comprise monitoring a translation or a modulation of the set of signals associated with the regulation of the device, and where the regulation of the device comprises a regulation of a temperature or power at the device. In some aspects, at least one of the SoC or the PMIC may include a set of error pins, where monitoring the set of signals associated with the regulation of the device comprises: monitoring the set of error pins for a change in state of the device; and monitoring the set of signals associated with the regulation of the device.

[0131] At 1410, the device may determine, in at least one of a system-in-package (SiP) of the device, a system on-chip (SoC) of the device, or a power management integrated circuit (PMIC) of the device, whether a range for the set of signals is within a threshold range for signals, as described in connection with the examples in FIGs. 1- 13. For example, as described in 1350 of FIG. 13, device 1302 may determine, in at least one of a system-in-package (SiP) of the device, a system on-chip (SoC) of the device, or a power management integrated circuit (PMIC) of the device, whether a range for the set of signals is within a threshold range for signals. Further, step 1410 may be performed by component 198 in FIG. 1. In some aspects, determining whether the range for the set of signals is within the threshold range for signals may comprise: determining, at a microcontroller in at least one of the SiP, the SoC, or the PMIC,129025-2381WO01Qualcomm Ref. No. 2404558WO 50 whether the range for the set of signals is within the threshold range for signals. Also, where the microcontroller is a safety controller, determining whether the range for the set of signals is within the threshold range for signals may comprise: determining, at the safety controller, in at least one of the SiP, the SoC, or the PMIC, whether the range for the set of signals is within the threshold range for signals. Further, determining whether the range for the set of signals is within the threshold range for signals may comprise: determining, at a sensor or a temperature sensor in at least one of the SoC or the PMIC, whether the range for the set of signals is within the threshold range for signals. Moreover, determining whether the range for the set of signals is within the threshold range for signals may comprise: determining, at a clock or an analog clock in at least one of the SiP or the SoC, whether the range for the set of signals is within the threshold range for signals. Additionally, determining whether the range for the set of signals is within the threshold range for signals may comprise: comparing at least one of the level, the range, or the input for the set of signals to a reference level, a reference range, or a reference input for signals. Also, determining whether the range for the set of signals is within the threshold range for signals may comprise: determining, at an input of a power supply, an output of the power supply, or a reference power signal in at least one of the SiP or the SoC, whether the range for the set of signals is within the threshold range for signals.

[0132] At 1412, the device may output, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals, as described in connection with the examples in FIGs. 1-13. For example, as described in 1360 of FIG. 13, device 1302 may output, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals. Further, step 1412 may be performed by component 198 in FIG. 1. For example, device 1302 may transmit indication 1362 to vehicle component 1304. Also, device 1302 may store indication 1364 in memory 1306. In some aspects, outputting the indication to configure the source may comprise outputting, based on the range for the set of signals being outside of the threshold range, an indication to adjust the source for the set of signals. Also, outputting the indication to adjust the source for the set of signals comprise: adjusting the source for the set of signals; or outputting an indication to power down the device, stop the device, or restart the device. In some aspects, the indication may include a set of interrupt signals, and outputting the indication to power down the device, stop the129025-2381WO01Qualcomm Ref. No. 2404558WO 51 device, or restart the device may comprise: outputting a set of interrupt signals to power down a system on-chip (SoC) of the device or a power management integrated circuit (PMIC) of the device, stop the SoC or the PMIC, or restart the SoC or the PMIC. In some aspects, at 1360, device 1302 may measure, within a time window prior to outputting the indication to adjust the source, the set of signals for determining that the range for the set of signals is outside of the threshold range; and monitor, within the time window and subsequent to the measurement, the set of signals. Additionally, outputting the indication to configure the source may comprise: outputting, based on the range for the set of signals being within the threshold range, an indication to maintain the source for the set of signals. Further, outputting the indication to maintain the source for the set of signals comprise: maintaining the source for the set of signals.

[0133] FIG. 15 is a flowchart 1500 of an example method of image processing in accordance with one or more techniques of this disclosure. The method may be performed by a device, a vehicle, a vehicle component, a microprocessor, a microcontroller, a safety controller, a printed circuit board (PCB), a system-on-chip (SoC), an electronic control unit (ECU), a user equipment (UE), a graphics processing unit (GPU), a central processing unit (CPU), or any apparatus that may perform communication, and / or any apparatus that may perform communication as used in connection with the examples of FIGs. 1-13.

[0134] At 1502, the device may obtain an indication of a threshold range for signals prior to monitoring a set of signals, as described in connection with the examples in FIGs. 1- 13. For example, as described in 1310 of FIG. 13, device 1302 may obtain an indication of a threshold range for signals prior to monitoring a set of signals. Further, step 1502 may be performed by component 198 in FIG. 1. For example, device 1302 may obtain indication 1312 from vehicle component 1304. In some aspects, the set of signals may include a set of signals for at least one of a power level at the device, a temperature sensor at the device, or an analog clock at the device. Also, the temperature sensor may correspond to a resistance at the device, and where the analog clock is at a power management integrated circuit (PMIC) of the device.

[0135] At 1504, the device may monitor a set of signals associated with a regulation of a device, as described in connection with the examples in FIGs. 1-13. For example, as described in 1320 of FIG. 13, device 1302 may monitor a set of signals associated with a regulation of a device. Further, step 1504 may be performed by component129025-2381WO01Qualcomm Ref. No. 2404558WO 52198 in FIG. 1. In some aspects, monitoring the set of signals may comprise monitoring a translation or a modulation of the set of signals associated with the regulation of the device, and where the regulation of the device comprises a regulation of a temperature or power at the device. In some aspects, at least one of the SoC or the PMIC may include a set of error pins, where monitoring the set of signals associated with the regulation of the device comprises: monitoring the set of error pins for a change in state of the device; and monitoring the set of signals associated with the regulation of the device.

[0136] At 1506, where the set of signals is a set of analog signals, the device may convert or translate the set of analog signals to a set of digital signals prior to the determination, as described in connection with the examples in FIGs. 1-13. For example, as described in 1330 of FIG. 13, device 1302 may convert or translate the set of analog signals to a set of digital signals prior to the determination. Further, step 1506 may be performed by component 198 in FIG. 1. In some aspects, converting or translating the set of analog signals to the set of digital signals may comprise: converting or translating, via a set of analog-to-digital converters, the set of analog signals to the set of digital signals.

[0137] At 1508, where the set of signals is a set of analog signals, the device may measure the range of the set of analog signals based on converting or translating the set of analog signals to the set of digital signals, as described in connection with the examples in FIGs. 1-13. For example, as described in 1340 of FIG. 13, device 1302 may measure the range of the set of analog signals based on converting or translating the set of analog signals to the set of digital signals. Further, step 1508 may be performed by component 198 in FIG. 1. In some aspects, the range may include at least one of a level, the range, or an input, and where the threshold range comprises a minimum target value or a maximum target value for the signals. Also, at least one of a power level at the device, a temperature sensor at the device, or an analog clock at the device may be less than or equal to a threshold level.

[0138] At 1510, the device may determine, in at least one of a system-in-package (SiP) of the device, a system on-chip (SoC) of the device, or a power management integrated circuit (PMIC) of the device, whether a range for the set of signals is within a threshold range for signals, as described in connection with the examples in FIGs. 1- 13. For example, as described in 1350 of FIG. 13, device 1302 may determine, in at least one of a system-in-package (SiP) of the device, a system on-chip (SoC) of the129025-2381WO01Qualcomm Ref. No. 2404558WO 53 device, or a power management integrated circuit (PMIC) of the device, whether a range for the set of signals is within a threshold range for signals. Further, step 1510 may be performed by component 198 in FIG. 1. In some aspects, determining whether the range for the set of signals is within the threshold range for signals may comprise: determining, at a microcontroller in at least one of the SiP, the SoC, or the PMIC, whether the range for the set of signals is within the threshold range for signals. Also, where the microcontroller is a safety controller, determining whether the range for the set of signals is within the threshold range for signals may comprise: determining, at the safety controller in at least one of the SiP, the SoC, or the PMIC, whether the range for the set of signals is within the threshold range for signals. Further, determining whether the range for the set of signals is within the threshold range for signals may comprise: determining, at a sensor or a temperature sensor in at least one of the SoC or the PMIC, whether the range for the set of signals is within the threshold range for signals. Moreover, determining whether the range for the set of signals is within the threshold range for signals may comprise: determining, at a clock or an analog clock in at least one of the SiP or the SoC, whether the range for the set of signals is within the threshold range for signals. Additionally, determining whether the range for the set of signals is within the threshold range for signals may comprise: comparing at least one of the level, the range, or the input for the set of signals to a reference level, a reference range, or a reference input for signals. Also, determining whether the range for the set of signals is within the threshold range for signals may comprise: determining, at an input of a power supply, an output of the power supply, or a reference power signal in at least one of the SiP or the SoC, whether the range for the set of signals is within the threshold range for signals.

[0139] At 1512, the device may output, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals, as described in connection with the examples in FIGs. 1-13. For example, as described in 1360 of FIG. 13, device 1302 may output, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals. Further, step 1512 may be performed by component 198 in FIG. 1. For example, device 1302 may transmit indication 1362 to vehicle component 1304. Also, device 1302 may store indication 1364 in memory 1306. In some aspects, outputting the indication to configure the source may comprise outputting, based on the range for the set of signals being outside of the threshold129025-2381WO01Qualcomm Ref. No. 2404558WO 54 range, an indication to adjust the source for the set of signals. Also, outputting the indication to adjust the source for the set of signals comprise: adjusting the source for the set of signals; or outputting an indication to power down the device, stop the device, or restart the device. In some aspects, the indication may include a set of interrupt signals, and outputting the indication to power down the device, stop the device, or restart the device may comprise: outputting a set of interrupt signals to power down a system on-chip (SoC) of the device or a power management integrated circuit (PMIC) of the device, stop the SoC or the PMIC, or restart the SoC or the PMIC. In some aspects, at 1360, device 1302 may measure, within a time window prior to outputting the indication to adjust the source, the set of signals for determining that the range for the set of signals is outside of the threshold range; and monitor, within the time window and subsequent to the measurement, the set of signals. Additionally, outputting the indication to configure the source may comprise: outputting, based on the range for the set of signals being within the threshold range, an indication to maintain the source for the set of signals. Further, outputting the indication to maintain the source for the set of signals comprise: maintaining the source for the set of signals.

[0140] The subject matter described herein may be implemented to realize one or more benefits or advantages. For instance, the described processing techniques may be used by a device, a vehicle, a vehicle component, a safety controller, a printed circuit board (PCB), a system-on-chip (SoC), an electronic control unit (ECU), a user equipment (UE), a graphics processing unit (GPU), a central processing unit (CPU), or any apparatus that may perform communication, or some other processor that may perform communication to implement the safety controller techniques described herein. This may also be accomplished at a low cost compared to other communication techniques. Moreover, the communication techniques herein may improve or speed up data processing or execution. Further, the communication techniques herein may improve resource or data utilization and / or resource efficiency. Additionally, aspects of the present disclosure may utilize the safety controller techniques in order to improve memory bandwidth efficiency and / or increase processing speed at a vehicle, a vehicle component, a system-on-chip (SoC), an electronic control unit (ECU), a user equipment (UE), a graphics processing unit (GPU), a central processing unit (CPU).129025-2381WO01Qualcomm Ref. No. 2404558WO 55

[0141] FIG. 16 is a diagram 1600 illustrating an example of a hardware implementation for an apparatus 1604. The apparatus 1604 may be a UE, a component of a UE, a vehicle, a component of a vehicle, a device, a safety controller, a PCB, an SoC, an ECU, or may implement UE or vehicle functionality. In some aspects, the apparatus 1604 may include at least one cellular baseband processor 1624 (also referred to as a modem) coupled to one or more transceivers 1622 (e.g., cellular RF transceiver). The cellular baseband processor(s) 1624 may include at least one on-chip memory 1624'. In some aspects, the apparatus 1604 may further include one or more subscriber identity modules (SIM) cards 1620 and at least one application processor 1606 coupled to a secure digital (SD) card 1608 and a screen 1610. The application processor(s) 1606 may include on-chip memory 1606'. In some aspects, the apparatus 1604 may further include a Bluetooth module 1612, a WLAN module 1614, an SPS module 1616 (e.g., GNSS module), one or more sensor modules 1618 (e.g., barometric pressure sensor / altimeter; motion sensor such as inertial measurement unit (IMU), gyroscope, and / or accelerometer(s); light detection and ranging (LIDAR), radio assisted detection and ranging (RADAR), sound navigation and ranging (SONAR), magnetometer, audio and / or other technologies used for positioning), additional memory modules 1626, a power supply 1630, and / or a camera 1632. The Bluetooth module 1612, the WLAN module 1614, and the SPS module 1616 may include an on-chip transceiver (TRX) (or in some cases, just a receiver (RX)). The Bluetooth module 1612, the WLAN module 1614, and the SPS module 1616 may include their own dedicated antennas and / or utilize the antennas 1680 for communication. The cellular baseband processor(s) 1624 communicates through the transceiver(s) 1622 via one or more antennas 1680 with the UE 104 and / or with an RU associated with a network entity 1602. The cellular baseband processor(s) 1624 and the application processor(s) 1606 may each include a computer-readable medium / memory 1624', 1606', respectively. The additional memory modules 1626 may also be considered a computer-readable medium / memory. Each computer-readable medium / memory 1624', 1606', 1626 may be non-transitory. The cellular baseband processor(s) 1624 and the application processor(s) 1606 are each responsible for general processing, including the execution of software stored on the computer-readable medium / memory. The software, when executed by the cellular baseband processor(s) 1624 / application processor(s) 1606, causes the cellular baseband processor(s) 1624 / application processor(s) 1606 to perform the various functions described supra. The cellular baseband processor(s)129025-2381WO01Qualcomm Ref. No. 2404558WO 561624 and the application processor(s) 1606 are configured to perform the various functions described supra based at least in part of the information stored in the memory. That is, the cellular baseband processor(s) 1624 and the application processor(s) 1606 may be configured to perform a first subset of the various functions described supra without information stored in the memory and may be configured to perform a second subset of the various functions described supra based on the information stored in the memory. The computer-readable medium / memory may also be used for storing data that is manipulated by the cellular baseband processor(s) 1624 / application processor(s) 1606 when executing software. The cellular baseband processor(s) 1624 / application processor(s) 1606 may be a component of the UE 350 and may include the at least one memory 360 and / or at least one of the TX processor 368, the RX processor 356, and the controller / processor 359. In one configuration, the apparatus 1604 may be at least one processor chip (modem and / or application) and include just the cellular baseband processor(s) 1624 and / or the application processor(s) 1606, and in another configuration, the apparatus 1604 may be the entire UE (e.g., see UE 350 of FIG. 3) and include the additional modules of the apparatus 1604.

[0142] As discussed supra, the component 198 may be configured to monitor a set of signals associated with a regulation of the device; determine whether a range for the set of signals is within a threshold range for signals; output, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals; convert or translate, where the set of signals is a set of analog signals, the set of analog signals to a set of digital signals prior to the determination; measure the range of the set of analog signals based on converting or translating the set of analog signals to the set of digital signals; and obtain an indication of the threshold range for signals prior to monitoring the set of signals. The component 198 may be within the cellular baseband processor(s) 1624, the application processor(s) 1606, or both the cellular baseband processor(s) 1624 and the application processor(s) 1606. The component 198 may be one or more hardware components specifically configured to carry out the stated processes / algorithm, implemented by one or more processors configured to perform the stated processes / algorithm, stored within a computer-readable medium for implementation by one or more processors, or some combination thereof. When multiple processors are implemented, the multiple processors may perform the stated processes / algorithm129025-2381WO01Qualcomm Ref. No. 2404558WO 57 individually or in combination. As shown, the apparatus 1604 may include a variety of components configured for various functions. In one configuration, the apparatus 1604, and in particular the cellular baseband processor(s) 1624 and / or the application processor(s) 1606, may include means for monitoring a set of signals associated with a regulation of the device; means for determining whether a range for the set of signals is within a threshold range for signals; means for outputting, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals; means for converting or translating, where the set of signals is a set of analog signals, the set of analog signals to a set of digital signals prior to the determination; means for measuring the range of the set of analog signals based on converting or translating the set of analog signals to the set of digital signals; and means for obtaining an indication of the threshold range for signals prior to monitoring the set of signals. The means may be the component 198 of the apparatus 1604 configured to perform the functions recited by the means. As described supra, the apparatus 1604 may include the TX processor 368, the RX processor 356, and the controller / processor 359. As such, in one configuration, the means may be the TX processor 368, the RX processor 356, and / or the controller / processor 359 configured to perform the functions recited by the means.

[0143] It is understood that the specific order or hierarchy of blocks in the processes / flowcharts disclosed is an illustration of example approaches. Based upon design preferences, it is understood that the specific order or hierarchy of blocks in the processes / flowcharts may be rearranged. Further, some blocks may be combined or omitted. The accompanying method claims present elements of the various blocks in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

[0144] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or129025-2381WO01Qualcomm Ref. No. 2404558WO 58 illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0145] Unless specifically stated otherwise, the term “some” refers to one or more and the term “or” may be interpreted as “and / or” where context does not dictate otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof’ include any combination of A, B, and / or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof’ may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combinations may contain one or more member or members of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. The words “module,” “mechanism,” “element,” “device,” and the like may not be a substitute for the word “means.” As such, no claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for.”

[0146] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” has been used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique described herein, or other module is implemented in software, the function, processing unit, technique described herein, or other module may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.

[0147] In accordance with this disclosure, the term “or” may be interpreted as “and / or” where context does not dictate otherwise. Additionally, while phrases such as “one or more” or “at least one” or the like may have been used for some features disclosed herein but not others, the features for which such language was not used may be interpreted to have such a meaning implied where context does not dictate otherwise.129025-2381WO01Qualcomm Ref. No. 2404558WO 59

[0148] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” has been used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique described herein, or other module is implemented in software, the function, processing unit, technique described herein, or other module may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media may include computer data storage media or communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally may correspond to (1) tangible computer- readable storage media, which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that may be accessed by one or more computers or one or more processors to retrieve instructions, code and / or data structures for implementation of the techniques described in this disclosure. By way of example, and not limitation, such computer- readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

[0149] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Also, the techniques could be fully implemented in one or more circuits or logic elements.

[0150] The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs, e.g., a chip set. Various components, modules or units are described in this disclosure129025-2381WO01Qualcomm Ref. No. 2404558WO 60 to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need realization by different hardware units. Rather, as described above, various units may be combined in any hardware unit or provided by a collection of inter-operative hardware units, including one or more processors as described above, in conjunction with suitable software and / or firmware. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Also, the techniques may be fully implemented in one or more circuits or logic elements.

[0151] The following aspects are illustrative only and may be combined with other aspects or teachings described herein, without limitation.

[0152] Aspect 1 is an apparatus for communication at a device, including at least one memory; and at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor, individually or in any combination, is configured to: monitor a set of signals associated with a regulation of the device; determine, in at least one of a system-in-package (SiP) of the device, a system on-chip (SoC) of the device, or a power management integrated circuit (PMIC) of the device, whether a range for the set of signals is within a threshold range for signals; and output, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals.

[0153] Aspect 2 is the apparatus of aspect 1, wherein to determine whether the range for the set of signals is within the threshold range for signals, the at least one processor, individually or in any combination, is configured to: determine, at a microcontroller in at least one of the SiP, the SoC, or the PMIC, or a power management integrated circuit (PMIC) of the device, whether the range for the set of signals is within the threshold range for signals.

[0154] Aspect 3 is the apparatus of aspect 2, wherein the microcontroller is a safety controller, and wherein to determine whether the range for the set of signals is within the threshold range for signals, the at least one processor, individually or in any combination, is configured to: determine, at the safety controller in at least one of the SiP, the SoC, or the PMIC, whether the range for the set of signals is within the threshold range for signals.129025-2381WO01Qualcomm Ref. No. 2404558WO 61

[0155] Aspect 4 is the apparatus of any of aspects 1 to 3, wherein to determine whether the range for the set of signals is within the threshold range for signals, the at least one processor, individually or in any combination, is configured to: determine, at a sensor or a temperature sensor in at least one of the SoC or the PMIC, whether the range for the set of signals is within the threshold range for signals.

[0156] Aspect 5 is the apparatus of any of aspects 1 to 4, wherein to determine whether the range for the set of signals is within the threshold range for signals, the at least one processor, individually or in any combination, is configured to: determine, at a clock or an analog clock in at least one of the SiP or the SoC, whether the range for the set of signals is within the threshold range for signals.

[0157] Aspect 6 is the apparatus of any of aspects 1 to 5, wherein to determine whether the range for the set of signals is within the threshold range for signals, the at least one processor, individually or in any combination, is configured to: determine, at an input of a power supply, an output of the power supply, or a reference power signal in at least one of the SiP or the SoC, whether the range for the set of signals is within the threshold range for signals.

[0158] Aspect 7 is the apparatus of any of aspects 1 to 5, wherein at least one of the SoC or the PMIC includes a set of error pins, wherein to monitor the set of signals associated with the regulation of the device, the at least one processor, individually or in any combination, is configured to: monitor the set of error pins for a change in state of the device; and monitor the set of signals associated with the regulation of the device.

[0159] Aspect 8 is the apparatus of any of aspects 1 to 7, wherein the set of signals is a set of analog signals, wherein the at least one processor, individually or in any combination, is further configured to: convert or translate the set of analog signals to a set of digital signals prior to the determination; and measure the range of the set of analog signals based on conversion or translation of the set of analog signals to the set of digital signals.

[0160] Aspect 9 is the apparatus of aspect 8, wherein to convert or translate the set of analog signals to the set of digital signals, the at least one processor, individually or in any combination, is configured to: convert or translate, via a set of analog-to-digital converters, the set of analog signals to the set of digital signals.

[0161] Aspect 10 is the apparatus of any of aspects 1 to 9, wherein the range includes at least one of a level, the range, or an input, and wherein the threshold range comprises a minimum target value or a maximum target value for the signals, and wherein to129025-2381WO01Qualcomm Ref. No. 2404558WO 62 determine whether the range for the set of signals is within the threshold range for signals, the at least one processor, individually or in any combination, is configured to: compare at least one of the level, the range, or the input for the set of signals to a reference level, a reference range, or a reference input for signals.

[0162] Aspect 11 is the apparatus of any of aspects 1 to 10, wherein to output the indication to configure the source, the at least one processor, individually or in any combination, is configured to: output, based on the range for the set of signals being outside of the threshold range, an indication to adjust the source for the set of signals.

[0163] Aspect 12 is the apparatus of aspect 11, wherein to output the indication to adjust the source for the set of signals, the at least one processor, individually or in any combination, is configured to: adjust the source for the set of signals; or output an indication to power down the device, stop the device, or restart the device.

[0164] Aspect 13 is the apparatus of aspect 12, wherein the indication includes a set of interrupt signals, and wherein to output the indication to power down the device, stop the device, or restart the device, the at least one processor, individually or in any combination, is configured to: output a set of interrupt signals to power down the SoC of the device or the PMIC of the device, stop the SoC or the PMIC, or restart the SoC or the PMIC.

[0165] Aspect 14 is the apparatus of any of aspects 11 to 13, wherein the at least one processor, individually or in any combination, is further configured to: measure, within a time window prior to outputting the indication to adjust the source, the set of signals for determining that the range for the set of signals is outside of the threshold range; and monitor, within the time window and subsequent to the measurement, the set of signals.

[0166] Aspect 15 is the apparatus of any of aspects 1 to 14, wherein to output the indication to configure the source, the at least one processor, individually or in any combination, is configured to: output, based on the range for the set of signals being within the threshold range, an indication to maintain the source for the set of signals; or maintain the source for the set of signals.

[0167] Aspect 16 is the apparatus of any of aspects 1 to 15, wherein to monitor the set of signals, the at least one processor, individually or in any combination, is configured to monitor a translation or a modulation of the set of signals associated with the regulation of the device, and wherein the regulation of the device comprises a regulation of a temperature or power at the device.129025-2381WO01Qualcomm Ref. No. 2404558WO 63

[0168] Aspect 17 is the apparatus of any of aspects 1 to 15, wherein the set of signals includes a set of signals for at least one of a power level at the device, a temperature sensor at the device, or an analog clock at the device, wherein the temperature sensor corresponds to a resistance at the device, and wherein the analog clock is at the PMIC of the device.

[0169] Aspect 18 is the apparatus of any of aspects 1 to 16, wherein the at least one processor, individually or in any combination, is configured to: obtain an indication of the threshold range for signals prior to monitoring the set of signals, wherein at least one of a power level at the device, a temperature sensor at the device, or an analog clock at the device is less than or equal to a threshold level.

[0170] Aspect 19 is the apparatus of any of aspects 1 to 18, wherein to output the indication to configure the source for the set of signals, the at least one processor, individually or in any combination, is configured to: transmit the indication to configure the source for the set of signals; or store the indication to configure the source for the set of signals.

[0171] Aspect 20 is the apparatus of aspect 19, further comprising at least one of an antenna or a transceiver coupled to the at least one processor, wherein to transmit the indication to configure the source for the set of signals, the at least one processor, individually or in any combination, is configured to: transmit, via at least one of the antenna or the transceiver, the indication to configure the source for the set of signals.

[0172] Aspect 21 is a method of wireless communication for implementing any of aspects 1 to 20.

[0173] Aspect 22 is an apparatus for wireless communication including means for implementing any of aspects 1 to 20.

[0174] Aspect 23 is a computer-readable medium (e.g., a non-transitory computer-readable medium) storing computer executable code, the code when executed by at least one processor causes the at least one processor to implement any of aspects 1 to 20.129025-2381WO01

Claims

Qualcomm Ref. No. 2404558WO 64CLAIMSWHAT IS CLAIMED IS:

1. An apparatus for communication at a device, comprising: at least one memory; and at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor, individually or in any combination, is configured to: monitor a set of signals associated with a regulation of the device; determine, in at least one of a system-in-package (SiP) of the device, a system on-chip (SoC) of the device, or a power management integrated circuit (PMIC) of the device, whether a range for the set of signals is within a threshold range for signals; and output, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals.

2. The apparatus of claim 1, wherein to determine whether the range for the set of signals is within the threshold range for signals, the at least one processor, individually or in any combination, is configured to: determine, at a microcontroller in at least one of the SiP, the SoC, or the PMIC, whether the range for the set of signals is within the threshold range for signals.

3. The apparatus of claim 2, wherein the microcontroller is a safety controller, and wherein to determine whether the range for the set of signals is within the threshold range for signals, the at least one processor, individually or in any combination, is configured to: determine, at the safety controller in at least one of the SiP, the SoC, or the PMIC, whether the range for the set of signals is within the threshold range for signals.

4. The apparatus of claim 1, wherein to determine whether the range for the set of signals is within the threshold range for signals, the at least one processor, individually or in any combination, is configured to: determine, at a sensor or a temperature sensor in at least one of the SoC or the PMIC, whether the range for the set of signals is within the threshold range for signals.129025-2381WO01Qualcomm Ref. No. 2404558WO 655. The apparatus of claim 1, wherein to determine whether the range for the set of signals is within the threshold range for signals, the at least one processor, individually or in any combination, is configured to: determine, at a clock or an analog clock in at least one of the SiP or the SoC, whether the range for the set of signals is within the threshold range for signals.

6. The apparatus of claim 1, wherein to determine whether the range for the set of signals is within the threshold range for signals, the at least one processor, individually or in any combination, is configured to: determine, at an input of a power supply, an output of the power supply, or a reference power signal in at least one of the SiP or the SoC, whether the range for the set of signals is within the threshold range for signals.

7. The apparatus of claim 1, wherein at least one of the SoC or the PMIC includes a set of error pins, wherein to monitor the set of signals associated with the regulation of the device, the at least one processor, individually or in any combination, is configured to: monitor the set of error pins for a change in state of the device; and monitor the set of signals associated with the regulation of the device.

8. The apparatus of claim 1, wherein the set of signals is a set of analog signals, wherein the at least one processor, individually or in any combination, is further configured to: convert or translate the set of analog signals to a set of digital signals prior to the determination; and measure the range of the set of analog signals based on conversion or translation of the set of analog signals to the set of digital signals.

9. The apparatus of claim 8, wherein to convert or translate the set of analog signals to the set of digital signals, the at least one processor, individually or in any combination, is configured to: convert or translate, via a set of analog-to-digital converters, the set of analog signals to the set of digital signals.129025-2381WO01Qualcomm Ref. No. 2404558WO 6610. The apparatus of claim 1, wherein the range includes at least one of a level, the range, or an input, and wherein the threshold range comprises a minimum target value or a maximum target value for the set of signals, and wherein to determine whether the range for the set of signals is within the threshold range for signals, the at least one processor, individually or in any combination, is configured to: compare at least one of the level, the range, or the input for the set of signals to a reference level, a reference range, or a reference input for signals.

11. The apparatus of claim 1, wherein to output the indication to configure the source, the at least one processor, individually or in any combination, is configured to: output, based on the range for the set of signals being outside of the threshold range, an indication to adjust the source for the set of signals.

12. The apparatus of claim 11, wherein to output the indication to adjust the source for the set of signals, the at least one processor, individually or in any combination, is configured to: adjust the source for the set of signals; or output an indication to power down the device, stop the device, or restart the device.

13. The apparatus of claim 12, wherein the indication includes a set of interrupt signals, and wherein to output the indication to power down the device, stop the device, or restart the device, the at least one processor, individually or in any combination, is configured to: output the set of interrupt signals to power down the SoC of the device or the PMIC of the device, stop the SoC or the PMIC, or restart the SoC or the PMIC.

14. The apparatus of claim 11, wherein the at least one processor, individually or in any combination, is further configured to: measure, within a time window prior to outputting the indication to adjust the source, the set of signals for determining that the range for the set of signals is outside of the threshold range; and monitor, within the time window and subsequent to the measurement, the set of signals.129025-2381WO01Qualcomm Ref. No. 2404558WO 6715. The apparatus of claim 1, wherein to output the indication to configure the source, the at least one processor, individually or in any combination, is configured to: output, based on the range for the set of signals being within the threshold range, an indication to maintain the source for the set of signals; or maintain the source for the set of signals.

16. The apparatus of claim 1, wherein to monitor the set of signals, the at least one processor, individually or in any combination, is configured to monitor a translation or a modulation of the set of signals associated with the regulation of the device, and wherein the regulation of the device comprises a regulation of a temperature or power at the device.

17. The apparatus of claim 1, wherein the set of signals includes a set of signals for at least one of a power level at the device, a temperature sensor at the device, or an analog clock at the device, wherein the temperature sensor corresponds to a resistance at the device, and wherein the analog clock is at the PMIC of the device.

18. The apparatus of claim 1, wherein the at least one processor, individually or in any combination, is configured to: obtain an indication of the threshold range for signals prior to monitoring the set of signals, wherein at least one of a power level at the device, a temperature sensor at the device, or an analog clock at the device is less than or equal to a threshold level.

19. A method of communication at a device, comprising: monitoring a set of signals associated with a regulation of the device; determining, in at least one of a system-in-package (SiP) of the device, a system on-chip (SoC) of the device, or a power management integrated circuit (PMIC) of the device, whether a range for the set of signals is within a threshold range for signals; and outputting, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals.

20. A computer-readable medium storing computer executable code, the code when executed by at least one processor causes the at least one processor to:129025-2381WO01Qualcomm Ref. No. 2404558WO 68 monitor a set of signals associated with a regulation of a device; determine, in at least one of a system-in-package (SiP) of the device, a system on- chip (SoC) of the device, or a power management integrated circuit (PMIC) of the device, whether a range for the set of signals is within a threshold range for signals; and output, based on the range for the set of signals being within or outside of the threshold range, an indication to configure a source for the set of signals.129025-2381WO01

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