Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a base, and a first voltage line, a second voltage line and a drive module which are arranged on the base. The drive module comprises a multi-stage drive circuit, which comprises an inverter. At least part of the orthographic projection of the inverter on the base is arranged between the orthographic projection of a first side edge of the first voltage line on the base and the orthographic projection of a second side edge of the second voltage line on the base; the first side edge of the first voltage line is the side edge of the first voltage line away from a display area, and the second side edge of the second voltage line is the side edge of the second voltage line close to the display area. In the display substrate, at least part of the inverter being arranged between the orthographic projection of the first side edge of the first voltage line on the base and the orthographic projection of the second side edge of the second voltage line on the base facilitates the implementation of a narrow bezel.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] In the related art, a scan driving circuit is directly integrated in a non-display area of an array substrate, which can replace a driving chip connected to the array substrate, has advantages of low cost, few processes, high production capacity, etc., and is referred to as a GOA (Gate Driver On Array, gate driving circuit arranged on the array substrate) design. In an OLED (Organic Light Emitting Diode) pixel driving circuit, a Gate signal is controlled by a GOA circuit of each row, wherein an inverter is an indispensable module in the GOA circuit, can implement a reverse pressure function on a first node and a second node in the GOA circuit, and a Darlington inverter can implement TFT (Thin Film Transistor) alternate work, reduce stress of the TFT, can be compatible with a threshold voltage negative drift of the TFT, and is commonly used in an oxide GOA circuit. However, the Darlington inverter needs to use multiple TFTs, occupies a larger space than other types of inverters, and usually each row of pixel driving circuits needs multiple GOA modules to provide a gate driving signal, which occupies a superimposed space, and is not conducive to a narrow frame display.

[0003] SUMMARY

[0004] In one aspect, the present disclosure provides a display substrate, comprising a substrate, a first voltage line, a second voltage line and a driving module arranged on the substrate, the driving module comprising a plurality of driving circuits, and the driving circuit comprising an inverter.

[0005] At least part of a projection of the inverter on the substrate is arranged between a projection of a first side of the first voltage line on the substrate and a projection of a second side of the second voltage line on the substrate.

[0006] The first side of the first voltage line is a side of the first voltage line away from a display area, and the second side of the second voltage line is a side of the first voltage line close to the display area.

[0007] Optionally, a projection of an electrode of a transistor of the inverter on the substrate, which is electrically connected to the first voltage line, at least partially overlaps with the projection of the first voltage line on the substrate.

[0008] A projection of an electrode of a transistor of the inverter on the substrate, which is electrically connected to the second voltage line, at least partially overlaps with the projection of the second voltage line on the substrate.

[0009] Optionally, a projection of at least part of the inverter on the substrate is located between a projection of the first voltage line on the substrate and a projection of the second voltage line on the substrate.

[0010] Optionally, at least part of the driving circuit, except the inverter, is disposed between the second voltage line and the display area.

[0011] At least one electrode of part of the transistors included in the inverter is electrically connected to a conductive pattern included in the at least part of the driving circuit through a connection line.

[0012] The second voltage line includes a first part and a second part, a projection of the first part on the substrate at least partially overlaps a projection of the connection line on the substrate, and a projection of the second part on the substrate does not overlap a projection of the connection line on the substrate.

[0013] In a direction perpendicular to an extension direction of the second voltage line, a width of the first part is less than a maximum width of the second part.

[0014] Optionally, the inverter includes a plurality of transistors.

[0015] Projections of the gates of the plurality of transistors on the substrate are disposed between a projection of the first voltage line on the substrate and a projection of the second voltage line on the substrate.

[0016] Optionally, the second voltage line has a first avoiding space, and a gate of part of the transistors included in the inverter is disposed in the first avoiding space.

[0017] Optionally, a minimum distance between a projection of the gate of part of the transistors included in the inverter on the substrate and a projection of the second voltage line on the substrate is greater than 2 μm.

[0018] Optionally, the second voltage line includes a hollow region, and at least part of the connection line is disposed in the hollow region.

[0019] Optionally, the inverter comprises a first transistor, a second transistor, a third transistor and a fourth transistor; a gate of the first transistor is electrically connected with the first voltage line, a first electrode of the first transistor is electrically connected with the first voltage line, and a second electrode of the first transistor is electrically connected with a first electrode of the second transistor; a gate of the second transistor is electrically connected with a gate of the fourth transistor, and a second electrode of the second transistor is electrically connected with the first voltage line; a gate of the third transistor is electrically connected with the second electrode of the first transistor, a first electrode of the third transistor is electrically connected with the first voltage line, and a second electrode of the third transistor is electrically connected with a first electrode of the fourth transistor; and a second electrode of the fourth transistor is electrically connected with the second voltage line.

[0020] The second electrode of the third transistor is electrically connected with the first conductive pattern included in the at least partial device through a first connecting line.

[0021] The gate of the second transistor is electrically connected with the second conductive pattern included in the at least partial device through a second connecting line.

[0022] The second voltage line comprises at least one hollow region.

[0023] At least part of the first connecting line is arranged in a corresponding first hollow region; and / or at least part of the second connecting line is arranged in a corresponding second hollow region.

[0024] Optionally, a normal projection of at least part of the inverter on the substrate is surrounded by a normal projection of the first voltage line on the substrate; and / or a normal projection of at least part of the inverter on the substrate is surrounded by a normal projection of the second voltage line on the substrate.

[0025] Optionally, the inverter comprises a plurality of transistors.

[0026] The first voltage line comprises a third hollow region, and the second voltage line comprises a fourth hollow region.

[0027] Gates of part of the transistors included in the inverter are arranged in the third hollow region, and gates of another part of the transistors included in the inverter are arranged in the fourth hollow region.

[0028] Optionally, the inverter comprises a first transistor, a second transistor, a third transistor and a fourth transistor; a gate of the first transistor is electrically connected with the first voltage line, a first electrode of the first transistor is electrically connected with the first voltage line, and a second electrode of the first transistor is electrically connected with a first electrode of the second transistor; a gate of the second transistor is electrically connected with a gate of the fourth transistor, and a second electrode of the second transistor is electrically connected with the first voltage line; a gate of the third transistor is electrically connected with the second electrode of the first transistor, a first electrode of the third transistor is electrically connected with the first voltage line, and a second electrode of the third transistor is electrically connected with a first electrode of the fourth transistor; and a second electrode of the fourth transistor is electrically connected with the second voltage line.

[0029] The gate of the first transistor, the gate of the third transistor, the second electrode of the first transistor and the second electrode of the third transistor are arranged in the third hollow region, and the gate of the second transistor, the gate of the fourth transistor, the first electrode of the second transistor and the first electrode of the fourth transistor are arranged in the fourth hollow region.

[0030] Optionally, a normal projection of the first electrode of the first transistor on the substrate at least partially overlaps a normal projection of the first voltage line on the substrate; and a normal projection of the first electrode of the third transistor on the substrate at least partially overlaps a normal projection of the first voltage line on the substrate.

[0031] A normal projection of the second electrode of the second transistor on the substrate at least partially overlaps a normal projection of the second voltage line on the substrate; and a normal projection of the second electrode of the fourth transistor on the substrate at least partially overlaps a normal projection of the second voltage line on the substrate.

[0032] Optionally, the driving circuit further comprises a second node reset circuit; the second node reset circuit is electrically connected with a reset end, the second node and the first voltage line respectively, and is configured to control the second node to communicate with the first voltage line under control of a reset signal provided by the reset end.

[0033] At least part of a normal projection of the second node reset circuit on the substrate is arranged between a normal projection of the first voltage line on the substrate and a normal projection of the second voltage line on the substrate.

[0034] Optionally, the second node reset circuit comprises a fifth transistor; a first electrode of the fifth transistor is electrically connected with the first voltage line, and a second electrode of the fifth transistor is electrically connected with the second node.

[0035] The gate of the fifth transistor is electrically connected with the reset end through a third connection line; a projection of the third connection line on the substrate at least partially overlaps a projection of the third connection line on the substrate;

[0036] The first voltage line has a fifth hollow region, and a portion of the third connection line is arranged in the fifth hollow region.

[0037] Optionally, the first voltage line, the second voltage line, and the drive module are arranged in the peripheral region.

[0038] The peripheral region includes a first bezel region and a second bezel region, the first bezel region is arranged at a first side of the display region, and the second bezel region is arranged at a second side of the display region, the first side and the second side being opposite sides.

[0039] The first voltage line, the second voltage line, and the drive module are arranged in the first bezel region; or the first voltage line, the second voltage line, and the drive module are arranged in the second bezel region; or the display substrate includes two first voltage lines, two second voltage lines, and two drive modules; a first first voltage line, a first second voltage line, and a first drive module are arranged in the first bezel region, and a second second voltage line, a second second voltage line, and a second drive module are arranged in the second bezel region.

[0040] In a second aspect, the display device includes the display substrate. BRIEF DESCRIPTION OF DRAWINGS

[0041] FIG. 1 is a circuit diagram of at least one embodiment of an inverter;

[0042] FIGS. 2A, 2B, and 2C are structural diagrams of an inverter and a high-voltage line VDD and a low-voltage line VSS in at least one embodiment of the present disclosure;

[0043] FIG. 3 is a layout diagram of a gate metal layer in FIG. 2A;

[0044] FIG. 4 is a layout diagram of a semiconductor layer in FIG. 2A;

[0045] FIG. 5 is a layout diagram of a source / drain metal layer in FIG. 2A;

[0046] FIG. 6 is a layout diagram of a light-shielding metal layer in FIG. 2A;

[0047] FIG. 7 is a cross-sectional view of A-A’ in FIG. 2A;

[0048] FIGS. 8A and 8B are structural diagrams of an inverter and a high-voltage line VDD and a low-voltage line VSS in at least one embodiment of the present disclosure;

[0049] FIG. 9 is a layout diagram of the gate metal layer in FIG. 8A;

[0050] FIG. 10 is a layout diagram of the semiconductor layer in FIG. 8A;

[0051] FIG. 11 is a layout diagram of the source-drain metal layer in FIG. 8A;

[0052] FIG. 12A is a layout diagram of the light-shielding metal layer in FIG. 8A.

[0053] FIG. 12B is a cross-sectional view of A-A' in FIG. 8A;

[0054] FIGS. 13A and 13B are structural schematic diagrams of an inverter and high-voltage line VDD, low-voltage line VSS in at least one embodiment of the present disclosure;

[0055] FIG. 14 is a layout diagram of the gate metal layer in FIG. 13A;

[0056] FIG. 15 is a layout diagram of the semiconductor layer in FIG. 13A;

[0057] FIG. 16 is a layout diagram of the source-drain metal layer in FIG. 13A;

[0058] FIG. 17A is a layout diagram of the light-shielding metal layer in FIG. 13A.

[0059] FIG. 17B is a cross-sectional view of A-A' in FIG. 13A;

[0060] FIGS. 18A and 18B are structural schematic diagrams of an inverter and high-voltage line VDD, low-voltage line VSS in at least one embodiment of the present disclosure;

[0061] FIGS. 19A and 19B are structural schematic diagrams of an inverter and high-voltage line VDD, low-voltage line VSS in at least one embodiment of the present disclosure;

[0062] FIGS. 20A and 20B are structural schematic diagrams of an inverter and high-voltage line VDD, low-voltage line VSS in at least one embodiment of the present disclosure;

[0063] FIG. 21 is a structural diagram of at least one embodiment of a driving circuit;

[0064] FIG. 22 is a circuit diagram of at least one embodiment of the driving circuit;

[0065] FIG. 23 is a working timing diagram of at least one embodiment of the driving circuit shown in FIG. 22;

[0066] FIG. 24 is a working timing diagram of a driving module in at least one embodiment of the present disclosure;

[0067] FIG. 25 is a schematic diagram of the positional relationship among a first side region, a display region, and a second side region;

[0068] FIG. 26 is a schematic diagram of the positional relationship of a signal line, a driving module and a display area. DETAILED DESCRIPTION

[0069] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work are within the scope of protection of the present disclosure.

[0070] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is referred to as the first pole and the other is referred to as the second pole.

[0071] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0072] In the related art, the scan driving circuit is directly integrated in the non-display area of the array substrate, which can replace the driving chip connected to the array substrate, has the advantages of low cost, fewer processes, high production capacity, etc., and is referred to as GOA (Gate Driver On Array, gate driving circuit arranged on the array substrate) design. In the OLED (organic light emitting diode) pixel driving circuit, the Gate signal is controlled by the GOA circuit of each row, and the inverter is an indispensable module in the GOA circuit, which can realize the function of reverse pressure of the first node and the second node in the GOA circuit. The Darlington inverter can realize the alternating work of the TFT (thin film transistor), reduce the stress of the TFT, and can be compatible with the negative drift of the threshold voltage of the TFT, and is mostly used in oxide GOA circuits. However, since the Darlington inverter needs to use multiple TFTs, it occupies a larger space compared to other types of inverters, and usually each row of pixel driving circuit needs multiple groups of GOA modules to provide gate driving signals, which occupies a large space, which is not conducive to narrow frame display.

[0073] In the related art, the Darlington inverter is arranged together with other modules included in the driving circuit on the side of the voltage line close to the display area, which cannot utilize the space between the voltage lines to arrange the inverter, is not conducive to narrow frame display, and can cause the breakdown short circuit probability of high voltage difference cross-line.

[0074] The display substrate provided by the embodiments of the present disclosure comprises a substrate, a first voltage line, a second voltage line and a driving module arranged on the substrate, the driving module comprises a plurality of driving circuits, and the driving circuit comprises an inverter.

[0075] At least part of the orthographic projection of the inverter on the substrate is arranged between the orthographic projection of the first side edge of the first voltage line on the substrate and the orthographic projection of the second side edge of the second voltage line on the substrate.

[0076] The first side edge of the first voltage line is the side edge of the first voltage line away from the display area, and the second side edge of the second voltage line is the side edge of the first voltage line close to the display area.

[0077] In the display substrate provided by the embodiments of the present disclosure, at least part of the orthographic projection of the inverter included in the driving circuit on the substrate is arranged between the orthographic projection of the first side edge of the first voltage line on the substrate and the orthographic projection of the second side edge of the second voltage line on the substrate, so that at least part of the inverter can be arranged by using the space between the first voltage line and the second voltage line, and narrow frame can be realized.

[0078] In at least one embodiment of the present disclosure, the first voltage line can be a high-voltage line, and the second voltage line can be a low-voltage line.

[0079] In specific implementation, the first voltage line, the second voltage line and the driving module can be arranged in the peripheral area.

[0080] The peripheral area comprises a first frame area and a second frame area, the first frame area is arranged on the first side of the display area, the second frame area is arranged on the second side of the display area, and the first side and the second side are opposite sides.

[0081] The first voltage line, the second voltage line and the driving module are all arranged in the first frame area, or the first voltage line, the second voltage line and the driving module are all arranged in the second frame area, or the display substrate comprises two first voltage lines, two second voltage lines and two driving modules, the first first voltage line, the first second voltage line and the first driving module are arranged in the first frame area, and the second second voltage line, the second second voltage line and the second driving module are arranged in the second frame area.

[0082] In at least one embodiment of the present disclosure, at least part of the orthographic projection of the inverter on the substrate can be arranged between the orthographic projection of the first side edge of the first voltage line on the substrate and the orthographic projection of the second side edge of the second voltage line on the substrate; or,

[0083] The part of the normal projection of the inverter on the substrate is arranged between the normal projection of the first side edge of the first voltage line on the substrate and the normal projection of the second side edge of the second voltage line on the substrate, and the other part of the normal projection of the inverter on the substrate can be arranged on the side of the normal projection of the first voltage line on the substrate away from the normal projection of the first voltage line on the substrate.

[0084] In at least one embodiment of the present disclosure, the inverter can be electrically connected with the first node and the second node respectively, and used for inverting the electric potential of the first node to obtain the electric potential of the second node.

[0085] As shown in FIG. 1, at least one embodiment of the inverter includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4.

[0086] The gate of the first transistor T1 is electrically connected with a high voltage line VDD, the first electrode of the first transistor T1 is electrically connected with the high voltage line VDD, and the second electrode of the first transistor T1 is electrically connected with the first electrode of the second transistor T2.

[0087] The gate of the second transistor T2 is electrically connected with the gate of the fourth transistor T4, and the second electrode of the second transistor T2 is electrically connected with the high voltage line VDD.

[0088] The gate of the third transistor T3 is electrically connected with the second electrode of the first transistor T1, the first electrode of the third transistor T3 is electrically connected with the high voltage line VDD, and the second electrode of the third transistor T3 is electrically connected with the first electrode of the fourth transistor T4.

[0089] The second electrode of the fourth transistor T4 is electrically connected with a low voltage line VSS.

[0090] T1, T2, T3 and T4 are all n-type transistors.

[0091] The gate of T2 is electrically connected with the gate of T4, and the second electrode of T3 is electrically connected with the second node QB.

[0092] In at least one embodiment of the inverter shown in FIG. 1, the gate of T4 is electrically connected with the first node Q, and the second electrode of T3 is electrically connected with the second node QB.

[0093] In at least one embodiment of the present disclosure, the driving circuit further includes a second node reset circuit; the second node reset circuit is electrically connected with a reset end, the second node and the first voltage line respectively, and used for controlling the communication between the second node and the first voltage line under the control of a reset signal provided by the reset end.

[0094] At least part of the second node reset circuit in the orthographic projection on the substrate is arranged between the orthographic projection of the first voltage line on the substrate and the orthographic projection of the second voltage line on the substrate.

[0095] In a specific implementation, the driving circuit further comprises a second node reset circuit, at least part of the orthographic projection of the second node reset circuit on the substrate is arranged between the orthographic projection of the first voltage line on the substrate and the orthographic projection of the second voltage line on the substrate, so that the connection line electrically connected with the first voltage line does not need to cross the second voltage line to be electrically connected with the transistor arranged in the TFT area, thereby reducing the probability of breakdown short circuit caused by high-voltage-difference cross-line.

[0096] Optionally, the second node reset circuit can comprise a fifth transistor, a gate of the fifth transistor is electrically connected with the reset end, a first electrode of the fifth transistor is electrically connected with the first voltage line, and a second electrode of the fifth transistor is electrically connected with the second node.

[0097] In at least one embodiment of the present disclosure, the electrode of the transistor of the inverter, which is electrically connected with the first voltage line, in the orthographic projection on the substrate, at least partially overlaps with the orthographic projection of the first voltage line on the substrate.

[0098] The electrode of the transistor of the inverter, which is electrically connected with the second voltage line, in the orthographic projection on the substrate, at least partially overlaps with the orthographic projection of the second voltage line on the substrate.

[0099] In a specific implementation, the electrode of the transistor of the inverter, which is electrically connected with the first voltage line, in the orthographic projection on the substrate, at least partially overlaps with the orthographic projection of the first voltage line on the substrate, so as to facilitate the electrode of the transistor of the inverter to be electrically connected with the first voltage line; the electrode of the transistor of the inverter, which is electrically connected with the second voltage line, in the orthographic projection on the substrate, at least partially overlaps with the orthographic projection of the second voltage line on the substrate, so as to facilitate the electrode of the transistor of the inverter to be electrically connected with the second voltage line, so that the connection line electrically connected with the first voltage line does not need to cross the second voltage line to be electrically connected with the transistor arranged in the TFT area, thereby reducing the probability of breakdown short circuit caused by high-voltage-difference cross-line.

[0100] In at least one embodiment of the present disclosure, the first electrode of the first transistor in the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first voltage line on the substrate; the first electrode of the third transistor in the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first voltage line on the substrate.

[0101] A second electrode of the second transistor has a projection on the substrate that at least partially overlaps a projection of the second voltage line on the substrate; and a second electrode of the fourth transistor has a projection on the substrate that at least partially overlaps a projection of the second voltage line on the substrate.

[0102] In at least one embodiment of the present disclosure, at least a portion of the inverter has a projection on the substrate that is located between a projection of the first voltage line on the substrate and a projection of the second voltage line on the substrate, so that at least a portion of the inverter is arranged in a space between the first voltage line and the second voltage line, facilitating the realization of a narrow frame.

[0103] In at least one embodiment of the present disclosure, at least a portion of the driving circuit, except for the inverter, is arranged between the second voltage line and the display area.

[0104] At least one electrode of a portion of the transistors included in the inverter is electrically connected to a conductive pattern included in the at least a portion of the driving circuit through a connection line.

[0105] The second voltage line includes a first portion and a second portion, a projection of the first portion on the substrate at least partially overlaps a projection of the connection line on the substrate, and a projection of the second portion on the substrate does not overlap a projection of the connection line on the substrate.

[0106] In a direction perpendicular to an extension direction of the second voltage line, a width of the first portion is less than a maximum width of the second portion.

[0107] In a specific implementation, at least a portion of the driving circuit, except for the inverter, is arranged between the second voltage line and the display area, and in a direction perpendicular to an extension direction of the second voltage line, a width of the first portion is arranged to be less than a maximum width of the second portion, that is, in an overlapping region of the connection line and the second voltage line, the width of the second voltage line is arranged to be smaller, so that the RC loading of the second voltage line can be reduced by means of a hole dug in the second voltage line.

[0108] Optionally, the inverter includes a plurality of transistors.

[0109] Projections of the gates of the plurality of transistors on the substrate are arranged between a projection of the first voltage line on the substrate and a projection of the second voltage line on the substrate.

[0110] In a specific implementation, projections of the gates of the transistors included in the inverter on the substrate can be arranged between a projection of the first voltage line on the substrate and a projection of the second voltage line on the substrate, so as to save horizontal space and facilitate the realization of a narrow frame.

[0111] In at least one embodiment of the present disclosure, the second voltage line has a first avoiding space, and a gate of a part of transistors included in the inverter is arranged in the first avoiding space.

[0112] In implementation, in order to arrange the gate of the part of transistors included in the inverter, the second voltage line can have the first avoiding space, and the gate of the part of transistors is arranged in the first avoiding space.

[0113] Optionally, the minimum distance between the orthogonal projection of the gate of the part of transistors included in the inverter on the substrate and the orthogonal projection of the second voltage line on the substrate is greater than 2 μm.

[0114] In implementation, the minimum distance between the orthogonal projection of the gate of the part of transistors included in the inverter on the substrate and the orthogonal projection of the second voltage line on the substrate is arranged to be greater than 2 μm, so as to prevent overlapping due to misalignment when manufacturing the display substrate.

[0115] Further, the minimum distance between the orthogonal projection of the gate of the part of transistors included in the inverter on the substrate and the orthogonal projection of the second voltage line on the substrate can be greater than or equal to 4 μm.

[0116] In at least one embodiment of the present disclosure, the second voltage line includes a hollow region, and at least part of the connection line is arranged in the hollow region.

[0117] In implementation, a hole can be dug in the second voltage line, and at least part of the connection line is arranged in the hollow region included in the second voltage line, so as to reduce the RC loading of the second voltage line.

[0118] Optionally, the second electrode of the third transistor is electrically connected with the first conductive pattern included in the at least part of devices through the first connection line.

[0119] The gate of the second transistor is electrically connected with the second conductive pattern included in the at least part of devices through the second connection line.

[0120] The second voltage line includes at least one hollow region.

[0121] At least part of the first connection line is arranged in the corresponding first hollow region, and / or at least part of the second connection line is arranged in the corresponding second hollow region.

[0122] In a specific implementation, the second electrode of the third transistor is electrically connected to the first conductive pattern included in the at least partial device through a first connection line, and the gate of the second transistor is electrically connected to the second conductive pattern included in the at least partial device through a second connection line; the second voltage line can include two hollow regions: a first hollow region and a second hollow region; at least part of the first connection line can be arranged in the first hollow region, and at least part of the second connection line can be arranged in the second hollow region, so as to reduce the RC loading of the second voltage line.

[0123] FIGS. 2A, 2B and 2C are schematic structural diagrams of inverters and high-voltage lines VDD and low-voltage lines VSS in at least one embodiment of the present disclosure;

[0124] FIG. 3 is a layout diagram of a gate metal layer in FIG. 2A, FIG. 4 is a layout diagram of a semiconductor layer in FIG. 2A, FIG. 5 is a layout diagram of a source-drain metal layer in FIG. 2A, and FIG. 6 is a layout diagram of a light-shielding metal layer in FIG. 2A.

[0125] In at least one embodiment of FIGS. 2A-6, the gate of each transistor is formed in a gate metal layer, the active pattern of each transistor is formed in a semiconductor layer, the first electrode of each transistor and the second electrode of each transistor are formed in a source-drain metal layer; the high-voltage line VDD and the low-voltage line VSS are formed in a light-shielding metal layer.

[0126] As shown in FIGS. 2A-6, the high-voltage line VDD and the low-voltage line VSS are arranged along a direction close to the display area A0; the inverter includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4;

[0127] The orthogonal projection of the gate of T1 on the substrate and the orthogonal projection of the gate of T3 on the substrate are arranged between the orthogonal projection of VDD on the substrate and the orthogonal projection of VSS on the substrate;

[0128] As shown in FIG. 2B, the low-voltage line VSS includes a first second part VL12, a first first part VL11, a second second part VL22, a second first part VL21 and a third second part VL32;

[0129] The VSS extends along the vertical direction;

[0130] The width of VL11 along the horizontal direction is less than the maximum width of VL12 along the horizontal direction;

[0131] The width of VL11 along the horizontal direction is less than the maximum width of VL22 along the horizontal direction;

[0132] The width of VL11 along the horizontal direction is less than the maximum width of VL32 along the horizontal direction;

[0133] The width of VL21 along the horizontal direction is less than the maximum width of VL12 along the horizontal direction;

[0134] The width of VL21 along the horizontal direction is less than the maximum width of VL22 along the horizontal direction;

[0135] The width of VL21 along the horizontal direction is less than the maximum width of VL32 along the horizontal direction.

[0136] In FIG. 2A and FIG. 2B, L1 is the first connection line, and L2 is the second connection line;

[0137] The second electrode of T3 is electrically connected to the first connection line L1, L1 crosses VSS and leads to the TFT area AT;

[0138] VDD and VSS are arranged in the signal line area, and the TFT area AT is arranged between the signal line area and the display area.

[0139] As shown in FIG. 2A and FIG. 2B, the low-voltage line VSS includes a first hollow area LA1 and a second hollow area LA2;

[0140] Part of the first connection line L1 is arranged in the first hollow area LA1, and part of the second connection line L2 is arranged in the second hollow area LA2;

[0141] As shown in FIG. 2A-FIG. 6, the low-voltage line VSS has a first avoiding space B1;

[0142] The gate G2 of T2 and the gate G4 of T4 are arranged in the first avoiding space B1.

[0143] In FIG. 2A, the first hollow area LA1 and the second hollow area LA2 do not belong to the part of VSS.

[0144] As shown in FIG. 2A-FIG. 6, the orthographic projection of the first electrode S1 of the first transistor T1 on the substrate at least partially overlaps the orthographic projection of the high-voltage line VDD on the substrate; the orthographic projection of the first electrode S3 of the third transistor T3 on the substrate at least partially overlaps the orthographic projection of the high-voltage line VDD on the substrate; so as to facilitate the electrical connection between S1 and S3 and VDD;

[0145] The orthographic projection of the second electrode D2 of the second transistor T2 on the substrate at least partially overlaps the orthographic projection of the low-voltage line VSS on the substrate; the orthographic projection of the second electrode D4 of the fourth transistor T4 on the substrate at least partially overlaps the orthographic projection of the low-voltage line VSS on the substrate; so as to facilitate the electrical connection between D2 and D4 and VSS.

[0146] As shown in FIGS. 2A-6, the front projection of T1 on the substrate, the front projection of T2 on the substrate, the front projection of T3 on the substrate, and the front projection of T4 on the substrate are arranged between the front projection of VDD on the substrate away from the left side of the display area A0 and the front projection of VSS on the substrate close to the right side of the display area A0.

[0147] The front projection of the gate G1 of T1 on the substrate and the front projection of the gate G3 of T3 on the substrate are arranged between the front projection of VDD on the substrate and the front projection of VSS on the substrate.

[0148] In at least one embodiment shown in FIGS. 2A-6, the first voltage line is the high voltage line VDD, and the second voltage line is the low voltage line VSS.

[0149] In FIG. 4, A1 is the active pattern of T1, A2 is the active pattern of T2, A3 is the active pattern of T3, and A4 is the active pattern of T4.

[0150] In at least one embodiment shown in FIGS. 2A-6, VDD and VSS extend in the vertical direction.

[0151] The horizontal width of VDD and the horizontal width of VSS are greater than or equal to 70 μm and less than or equal to 150 μm to ensure that the IR drop is within the allowable range of panel uniformity, and the spacing between VDD and VSS is greater than or equal to 25 μm and less than or equal to 50 μm to ensure that the spacing between the high voltage line and the low voltage line is large enough to prevent the breakdown current caused by the electric field between the PINs.

[0152] The inverter includes T1, T2, T3, and T4 arranged in the signal line area, which saves the space of the TFT area originally occupied, narrows the overall frame, or reserves more design space for other TFTs.

[0153] The second electrode of T3 and the first electrode of T4 are both electrically connected to the second node, and the second node crosses VSS through the first connecting line L1 and leads to the TFT area AT.

[0154] The gate G2 of T2 and the gate G4 of T4 are both electrically connected to the first node, and the first node crosses VSS through the second connecting line L2 and leads to the TFT area AT.

[0155] In at least one embodiment of the present disclosure, the long-term high-voltage cross-line between VDD and VSS in the related art is replaced by the short-term high-voltage cross-line between the first node or the second node and VSS, which can prevent the short circuit phenomenon caused by the breakdown of the inorganic layer between the metal layers under high voltage.

[0156] As shown in FIGS. 2A-6, the minimum distance between the orthogonal projection of the gate G2 of the second transistor T2 on the substrate and the orthogonal projection of the low-voltage line VSS on the substrate is greater than 2 μm, and the minimum distance between the orthogonal projection of the gate G4 of the fourth transistor T4 on the substrate and the orthogonal projection of the low-voltage line VSS on the substrate is greater than 2 μm, to prevent overlapping due to misalignment when manufacturing the display substrate.

[0157] In FIG. 2B, F1 is an inverter, and the inverter F1 can include a first transistor, a second transistor, a third transistor, and a fourth transistor.

[0158] In at least one embodiment of the present disclosure, the hollowed-out region excavated on the voltage line is not part of the voltage line.

[0159] FIG. 7 is a cross-sectional view of A-A' in FIG. 2A.

[0160] In FIG. 7, 10 is a substrate, 11 is a light-blocking metal layer, 12 is a buffer layer, 13 is a semiconductor layer, 14 is a gate insulating layer, 15 is a gate metal layer, 16 is a first passivation layer, 17 is a source-drain metal layer, and 18 is a second passivation layer.

[0161] In at least one embodiment of the present disclosure, the orthogonal projection of at least part of the inverter on the substrate is surrounded by the orthogonal projection of the first voltage line on the substrate; and / or, the orthogonal projection of at least part of the inverter on the substrate is surrounded by the orthogonal projection of the second voltage line on the substrate.

[0162] In a specific implementation, the orthogonal projection of at least part of the inverter on the substrate can be surrounded by the orthogonal projection of the first voltage line on the substrate; and / or, the orthogonal projection of at least part of the inverter on the substrate is surrounded by the orthogonal projection of the second voltage line on the substrate, that is, at least part of the inverter can be disposed in the hollowed-out region of the first voltage line, and / or at least part of the inverter can be disposed in the hollowed-out region of the second voltage line, to facilitate narrow frame. Moreover, at least one embodiment of the present disclosure reduces RC loading by excavating holes on the first voltage line and / or the second voltage line, prevents strong electric fields from being generated between the first voltage line, the second voltage line, and the connection pattern overlapping therewith, and prevents short circuit from occurring after the film layer is broken down.

[0163] In at least one embodiment of the present disclosure, the inverter includes a plurality of transistors;

[0164] The first voltage line includes a third hollowed-out region, and the second voltage line includes a fourth hollowed-out region;

[0165] The gate of a part of the transistor included in the inverter is arranged in the third hollow region, and the gate of another part of the transistor included in the inverter is arranged in the fourth hollow region.

[0166] Optionally, the gate of the first transistor, the gate of the third transistor, the second electrode of the first transistor and the second electrode of the third transistor are arranged in the third hollow region, and the gate of the second transistor, the gate of the fourth transistor, the first electrode of the second transistor and the first electrode of the fourth transistor are arranged in the fourth hollow region.

[0167] In at least one embodiment of the present disclosure, the first electrode of the first transistor has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the first voltage line on the substrate, facilitating the electrical connection between the first electrode of the first transistor and the first voltage line and facilitating the realization of a narrow frame.

[0168] The first electrode of the third transistor has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the first voltage line on the substrate, facilitating the electrical connection between the first electrode of the third transistor and the first voltage line and facilitating the realization of a narrow frame.

[0169] The second electrode of the second transistor has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the second voltage line on the substrate, facilitating the electrical connection between the second electrode of the second transistor and the second voltage line and facilitating the realization of a narrow frame.

[0170] The second electrode of the fourth transistor has an orthogonal projection on the substrate that at least partially overlaps with the orthogonal projection of the second voltage line on the substrate, facilitating the electrical connection between the second electrode of the fourth transistor and the second voltage line and facilitating the realization of a narrow frame.

[0171] FIGS. 8A and 8B are structural schematic diagrams of an inverter and a high-voltage line VDD and a low-voltage line VSS in at least one embodiment of the present disclosure.

[0172] FIG. 9 is a layout diagram of a gate metal layer in FIG. 8A, FIG. 10 is a layout diagram of a semiconductor layer in FIG. 8A, FIG. 11 is a layout diagram of a source-drain metal layer in FIG. 8A, and FIG. 12A is a layout diagram of a light-shielding metal layer in FIG. 8A.

[0173] FIG. 12B is a cross-sectional view of A-A’ in FIG. 8A.

[0174] In FIG. 8A, the third hollow region LA3 does not belong to the part of VDD, and the fourth hollow region LA4 does not belong to the part of VSS.

[0175] As shown in FIGS. 8A-12A, the inverter F1 (F1 is shown in FIG. 8B) includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4;

[0176] The high-voltage line VDD includes a third hollow region LA3, and the low-voltage line VSS includes a fourth hollow region LA4;

[0177] The gate G1 of the first transistor T1, the gate G3 of the third transistor T3, the second electrode D1 of the first transistor T1, and the second electrode D3 of the third transistor T3 are disposed in the third hollow region LA3, and the gate G2 of the second transistor T2, the gate G4 of the fourth transistor T4, the first electrode S2 of the second transistor T2, and the first electrode S4 of the fourth transistor T4 are disposed in the fourth hollow region LA4.

[0178] The first electrode S1 of the first transistor T1 has a projection on the substrate that at least partially overlaps a projection of the high-voltage line VDD on the substrate, facilitating electrical connection between the first electrode S1 of the first transistor T1 and the high-voltage line VDD, and facilitating narrow frame implementation.

[0179] The first electrode S3 of the third transistor T3 has a projection on the substrate that at least partially overlaps a projection of the high-voltage line VDD on the substrate, facilitating electrical connection between the first electrode S3 of the third transistor T3 and the high-voltage line VDD, and facilitating narrow frame implementation.

[0180] The second electrode D2 of the second transistor T2 has a projection on the substrate that at least partially overlaps a projection of the low-voltage line VSS on the substrate, facilitating electrical connection between the second electrode S2 of the second transistor T2 and the low-voltage line VSS, and facilitating narrow frame implementation.

[0181] The second electrode D4 of the fourth transistor T4 has a projection on the substrate that at least partially overlaps a projection of the low-voltage line VSS on the substrate, facilitating electrical connection between the second electrode D4 of the fourth transistor T4 and the low-voltage line VSS, and facilitating narrow frame implementation.

[0182] In FIG. 12B, 10 is a substrate, 11 is a light-blocking metal layer, 12 is a buffer layer, 13 is a semiconductor layer, 14 is a gate insulating layer, 15 is a gate metal layer, 16 is a first passivation layer, 17 is a source-drain metal layer, and 18 is a second passivation layer.

[0183] At least one embodiment of the display substrate shown in FIG. 13A differs from at least one embodiment of the display substrate shown in FIG. 2A as follows:

[0184] T4, T3, T2 and T1 are arranged in sequence along the extension direction of the high-voltage line VDD, the inverter occupies less space in the lateral direction, and the gate of all the transistors included in the inverter, the second electrode D1 of T1, the first electrode S2 of T2, the second electrode D3 of T3 and the first electrode S4 of T4 are all located between VDD and VSS; by means of the hole digging manner on VSS, the RC loading is reduced.

[0185] In at least one embodiment of the display substrate shown in FIG. 13A, the long-term high-voltage cross-line between VDD and VSS in the related art is replaced by a short-term high-voltage cross-line between the first node or the second node and VSS, which can prevent the short circuit caused by the high-voltage breakdown of the inorganic layer between the metal layers.

[0186] In FIG. 13B, F1 is an inverter;

[0187] As shown in FIGS. 13A and 13B, the inverter F1 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4.

[0188] In FIG. 13A, the first hollow area LA1 does not belong to the part of VSS.

[0189] FIG. 14 is a layout diagram of the gate metal layer in FIG. 13A, FIG. 15 is a layout diagram of the semiconductor layer in FIG. 13A, FIG. 16 is a layout diagram of the source-drain metal layer in FIG. 13A, and FIG. 17A is a layout diagram of the light-shielding metal layer in FIG. 13A.

[0190] FIG. 17B is an A-A' cross-sectional view in FIG. 13A.

[0191] In FIG. 13A, LA1 is a first hollow area, L1 is a first connection line, and L2 is a second connection line.

[0192] The orthogonal projection of the first connection line L1 on the substrate at least partially overlaps the orthogonal projection of the low-voltage line VSS on the substrate; and part of the first connection line L1 is arranged in the first hollow area LA1.

[0193] The orthogonal projection of the second connection line L2 on the substrate at least partially overlaps the orthogonal projection of the low-voltage line VSS on the substrate.

[0194] In the overlapping part of the second connection line L2 and SS, the left and right sides of the low-voltage line VSS are hollowed out, so that the lateral width of the low-voltage line VSS is reduced, and the RC loading is reduced.

[0195] As shown in FIG. 13A, the orthogonal projection of the first electrode S1 of T1 on the substrate at least partially overlaps with the orthogonal projection of the high-voltage line VDD on the substrate, which facilitates the electrical connection between S1 and VDD and helps to achieve a narrow frame;

[0196] The orthogonal projection of the second electrode D2 of T2 on the substrate at least partially overlaps with the orthogonal projection of the low-voltage line VSS on the substrate, which facilitates the electrical connection between D2 and VSS and helps to achieve a narrow frame;

[0197] The orthogonal projection of the first electrode S3 of T3 on the substrate at least partially overlaps with the orthogonal projection of VDD on the substrate, which facilitates the electrical connection between S3 and VDD and helps to achieve a narrow frame;

[0198] The orthogonal projection of the second electrode D4 of T4 on the substrate at least partially overlaps with the orthogonal projection of the low-voltage line VSS on the substrate, which facilitates the electrical connection between D4 and VSS and helps to achieve a narrow frame.

[0199] In FIG. 14, G1 is the gate of T1, G2 is the gate of T2, G3 is the gate of T3, G4 is the gate of T4, and L2 is the second connection pattern; the second connection pattern L3 is integrally formed between G2 and G4.

[0200] In FIG. 15, A1 is the active pattern of T1, A2 is the active pattern of T2, A3 is the active pattern of T3, and A4 is the active pattern of T4.

[0201] In FIG. 16, L1 is the first connection pattern, and the first electrode S4 of T4 is integrally formed with L1.

[0202] As shown in FIG. 17A, the low-voltage line VSS includes a first second portion VL12, a first first portion VL11, a second second portion VL22, a second first portion VL21, and a third second portion VL32.

[0203] VSS extends along the vertical direction;

[0204] The width of VL11 along the horizontal direction is less than the maximum width of VL12 along the horizontal direction;

[0205] The width of VL11 along the horizontal direction is less than the maximum width of VL22 along the horizontal direction;

[0206] The width of VL11 along the horizontal direction is less than the maximum width of VL32 along the horizontal direction;

[0207] The width of VL21 along the horizontal direction is less than the maximum width of VL12 along the horizontal direction;

[0208] The width of VL21 along the horizontal direction is less than the maximum width of VL22 along the horizontal direction.

[0209] The width of VL21 along the horizontal direction is less than the maximum width of VL32 along the horizontal direction.

[0210] As shown in FIGS. 13A-17A, the orthographic projection of VL11 on the substrate at least partially overlaps the orthographic projection of L1 on the substrate, and the orthographic projection of VL21 on the substrate at least partially overlaps the orthographic projection of L2 on the substrate. By reducing the width of VL11 along the horizontal direction and the width of VL21 along the horizontal direction, the RC loading can be reduced.

[0211] In FIG. 17B, 10 is a substrate, 11 is a light-shielding metal layer, 12 is a buffer layer, 13 is a semiconductor layer, 14 is a gate insulating layer, 15 is a gate metal layer, 16 is a first passivation layer, 17 is a source-drain metal layer, and 18 is a second passivation layer.

[0212] Optionally, the driving circuit further comprises a second node reset circuit; the second node reset circuit is electrically connected with the reset end, the second node and the first voltage line respectively, and is configured to control the second node to communicate with the first voltage line under the control of a reset signal provided by the reset end;

[0213] At least part of the orthographic projection of the second node reset circuit on the substrate is arranged between the orthographic projection of the first voltage line on the substrate and the orthographic projection of the second voltage line on the substrate.

[0214] In a specific implementation, the driving circuit can further comprise a second node reset circuit. At least part of the orthographic projection of the second node reset circuit on the substrate can be arranged between the orthographic projection of the first voltage line on the substrate and the orthographic projection of the second voltage line on the substrate. The second node reset circuit is arranged in the space between the first voltage line and the second voltage line, which is conducive to achieving a narrow frame, facilitating the electrical connection of the first electrode of the transistor included in the second node reset circuit, and changing the long-term high-voltage cross-line between VDD and VSS into a short-term high-voltage cross-line between the second node (the second electrode of the second node reset circuit is electrically connected with the second node) and VDD, which can prevent short circuit caused by high-voltage breakdown of the inorganic layer between the metal layers.

[0215] In at least one embodiment of the present disclosure, the second node reset circuit comprises a fifth transistor; the first electrode of the fifth transistor is electrically connected with the first voltage line, and the second electrode of the fifth transistor is electrically connected with the second node.

[0216] The gate of the fifth transistor is electrically connected with the reset end through a third connection line; a projection of the third connection line on the substrate at least partially overlaps with a projection of the third connection line on the substrate;

[0217] The first voltage line has a fifth hollow region, and a portion of the third connection line is arranged in the fifth hollow region.

[0218] At least one embodiment of the display substrate shown in FIG. 18A is different from at least one embodiment of the display substrate shown in FIG. 2A as follows: a fifth transistor T5 is further included; the high voltage line VDD has a fifth hollow region LA5;

[0219] A portion of the projection of T5 on the substrate is arranged between the projection of the high voltage line VDD on the substrate and the projection of the low voltage line VSS on the substrate;

[0220] The fifth transistor T5 is electrically connected with the reset end through a third connection line L3, the first electrode of the fifth transistor T5 is electrically connected with the high voltage line VDD, and the second electrode of the fifth transistor T5 is electrically connected with the first connection line L1;

[0221] The third connection line L3 is formed in the gate metal layer, and the third connection line L3 is integrally formed with the gate of T5;

[0222] A portion of the third connection line L3 is located in the third hollow region LA3.

[0223] In FIG. 18B, the label F1 is an inverter;

[0224] As shown in FIGS. 18A and 18B, the inverter F1 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. In FIG. 18A, the fifth hollow region LA5 is not part of VDD, and the first hollow region LA1 and the second hollow region LA2 are not part of VSS.

[0225] At least one embodiment of the display substrate shown in FIG. 19A is different from at least one embodiment of the display substrate shown in FIG. 8A as follows: a fifth transistor T5 is further included; the high voltage line VDD has a fifth hollow region LA5;

[0226] A portion of the projection of T5 on the substrate is arranged between the projection of the high voltage line VDD on the substrate and the projection of the low voltage line VSS on the substrate;

[0227] The fifth transistor T5 is electrically connected with the reset end through a third connection line L3, the first electrode of the fifth transistor T5 is electrically connected with the high voltage line VDD, and the second electrode of the fifth transistor T5 is electrically connected with the first connection line L1;

[0228] The third connection line L3 is formed in the gate metal layer, and the third connection line L3 is integrally formed with the gate of T5.

[0229] Part of the third connection line L3 is located in the third hollow region LA3.

[0230] In FIG. 19B, F1 is an inverter;

[0231] As shown in FIGS. 19A and 19B, the inverter F1 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0232] At least one embodiment of the display substrate shown in FIG. 20A is different from at least one embodiment of the display substrate shown in FIG. 13A as follows: a fifth transistor T5 is further included; the high-voltage line VDD has a fifth hollow region LA5;

[0233] Part of the orthogonal projection of T5 on the base is arranged between the orthogonal projection of the high-voltage line VDD on the base and the orthogonal projection of the low-voltage line VSS on the base;

[0234] The first electrode of the fifth transistor T5 is electrically connected to the high-voltage line VDD through the third connection line L3, and the second electrode of the fifth transistor T5 is electrically connected to the first connection line L1.

[0235] The third connection line L3 is formed in the gate metal layer, and the third connection line L3 is integrally formed with the gate of T5.

[0236] Part of the third connection line L3 is located in the third hollow region LA3.

[0237] As shown in FIG. 20A, T5, T4, T3, T2, and T1 are arranged in sequence along the vertical direction, and the extension direction of VDD and the extension direction of VSS are the vertical direction.

[0238] In FIG. 20B, F1 is an inverter;

[0239] As shown in FIGS. 20A and 20B, the inverter F1 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0240] As shown in FIG. 21, at least one embodiment of the driving circuit includes an inverter 21, a second node reset circuit 22, a third node control circuit 23, an input circuit 24, a first energy storage circuit 251, a second energy storage circuit 252, an output circuit 26, and an output reset circuit 27.

[0241] The inverter 21 is electrically connected to the first node Q and the second node QB respectively, and is used for inverting the potential of the first node Q to obtain the potential of the second node QB.

[0242] The second node reset circuit 22 is electrically connected with the reset terminal RST, the second node QB and the first voltage line V1 respectively, and is configured to control the second node QB to be in communication with the first voltage line V1 under the control of a reset signal provided by the reset terminal RST;

[0243] The third node control circuit 23 is electrically connected with the first voltage line V1, the first node Q and the third node Q3 respectively, and is configured to control the first node Q to be in communication with the third node Q3 under the control of a first voltage signal provided by the first voltage line V1;

[0244] The input circuit 24 is electrically connected with the clock signal terminal CLK, the input terminal STV and the first node Q respectively, and is configured to control the input terminal STV to be in communication with the first node Q under the control of a clock signal provided by the clock signal terminal CLK;

[0245] The first energy storage circuit 251 is electrically connected with the third node Q3 and the drive output terminal OT respectively, and is configured to store energy;

[0246] The second energy storage circuit 252 is electrically connected with the second node QB, and is configured to maintain the potential of the second node QB;

[0247] The output circuit 26 is electrically connected with the third node Q3, the first voltage line V1 and the drive output terminal OT respectively, and is configured to control the drive output terminal OT to be in communication with the first voltage line V1 under the control of the potential of the third node Q3;

[0248] The output reset circuit 27 is electrically connected with the second node QB, the drive output terminal OT and the second voltage line V2 respectively, and is configured to control the drive output terminal OT to be in communication with the second voltage line V2 under the control of the potential of the second node QB.

[0249] Optionally, the first voltage line can be a high voltage line, and the second voltage line can be a low voltage line.

[0250] As shown in FIG. 22, on the basis of at least one embodiment of the driving circuit shown in FIG. 21, the inverter comprises a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4;

[0251] The gate of the first transistor T1 is electrically connected with the high voltage line VDD, the first electrode of the first transistor T1 is electrically connected with the high voltage line VDD, and the second electrode of the first transistor T1 is electrically connected with the first electrode of the second transistor T2;

[0252] The gate of the second transistor T2 is electrically connected with the gate of the fourth transistor T4, and the second electrode of the second transistor T2 is electrically connected with the high voltage line VDD;

[0253] The gate of the third transistor T3 is electrically connected with the second electrode of the first transistor T1, the first electrode of the third transistor T3 is electrically connected with the high voltage line VDD, and the second electrode of the third transistor T3 is electrically connected with the first electrode of the fourth transistor T4;

[0254] The second electrode of the fourth transistor T4 is electrically connected with the low voltage line VSS;

[0255] The gate of T2 is electrically connected with the gate of T4, and the second electrode of T3 is electrically connected with the second node QB;

[0256] The second node reset circuit comprises a fifth transistor T5;

[0257] The gate of T5 is electrically connected with the reset end RST, the first electrode of T5 is electrically connected with the high voltage line VDD, and the second electrode of T5 is electrically connected with the second node QB;

[0258] The input circuit comprises a seventh transistor T7, the third node control circuit comprises a sixth transistor T6, the output circuit comprises an eighth transistor T8, the output reset circuit comprises a ninth transistor T9, the first energy storage circuit comprises a first capacitor C1, and the second energy storage circuit comprises a second capacitor C2;

[0259] The gate of T6 is electrically connected with the high voltage line VDD, the first electrode of T6 is electrically connected with the first node Q, and the second electrode of T6 is electrically connected with the third node Q3;

[0260] The gate of T7 is electrically connected with the clock signal end CLK, the first electrode of T7 is electrically connected with the input end STV, and the second electrode of T7 is electrically connected with the first node Q;

[0261] The gate of T8 is electrically connected with the third node Q3, the first electrode of T8 is electrically connected with the high voltage line VDD, and the second electrode of T8 is electrically connected with the driving output end OT;

[0262] The gate of T9 is electrically connected with the second node QB, the first electrode of T9 is electrically connected with the driving output end OT, and the second electrode of T9 is electrically connected with the low voltage line VSS;

[0263] The first end of C1 is electrically connected with the third node Q3, and the second end of C1 is electrically connected with the driving output end OT;

[0264] The first end of C2 is electrically connected with the second node QB, and the second end of C2 is electrically connected with the low voltage line VSS.

[0265] In at least one embodiment of the driving circuit shown in FIG. 22, all transistors are n-type transistors.

[0266] In at least one embodiment of the driving circuit shown in FIG. 22, the channel width-length ratio of T7 is 10 / 12, the channel width-length ratio of T1 is 10 / 8, the channel width-length ratio of T2 is 20 / 8, the channel width-length ratio of T3 is 10 / 8, the channel width-length ratio of T4 is 20 / 8, the channel width-length ratio of T6 is 10 / 12, the channel width-length ratio of T8 is 250 / 7, the channel width-length ratio of T9 is 150 / 7, and the channel width-length ratio of T5 is 15 / 10; the capacitance value of C1 is 800fF, and the capacitance value of C2 is 350fF.

[0267] In at least one embodiment of the driving circuit shown in FIG. 22, the high voltage value of the clock signal provided by CLK is 20V, and the low voltage value of the clock signal provided by CLK is -6V.

[0268] The high voltage value of the input signal provided by STV is 20V, and the low voltage value of the input signal is -6V.

[0269] The high voltage value of the reset signal provided by RST is 20V, and the low voltage value of the reset signal is -6V.

[0270] The voltage value of the high voltage signal provided by VDD is 20V, and the voltage value of the low voltage signal provided by VSS is -6V.

[0271] FIG. 23 is a working timing diagram of at least one embodiment of the driving circuit shown in FIG. 22.

[0272] In at least one embodiment of the present disclosure, the driving module can include multiple stages of at least one embodiment of the driving circuit shown in FIG. 22 of the present disclosure.

[0273] In at least one embodiment of the driving module, the driving module can further be provided with a first virtual driving circuit and a second virtual driving circuit before the first-stage driving circuit.

[0274] In at least one embodiment of the driving module, the clock signal end of the odd-stage driving circuit can be electrically connected with the first clock signal line CK, and the clock signal end of the even-stage driving circuit can be electrically connected with the second clock signal line CB.

[0275] FIG. 24 is a working timing diagram of the driving module in at least one embodiment of the present disclosure.

[0276] In FIG. 24, STV0 is a start voltage terminal, OT-dm1 is a driving output terminal of a first virtual driving circuit, OT-dm2 is a driving output terminal of a second virtual driving circuit, OT1 is a driving output terminal of a first stage driving circuit, and Q10 is a first node in a tenth stage driving circuit.

[0277] In at least one embodiment of the present disclosure, the first voltage line, the second voltage line, and the driving module are all arranged in a peripheral region;

[0278] The peripheral region includes a first bezel region and a second bezel region, the first bezel region is arranged at a first side of the display region, and the second bezel region is arranged at a second side of the display region, the first side and the second side being opposite sides;

[0279] The first voltage line, the second voltage line, and the driving module are all arranged in the first bezel region, or the first voltage line, the second voltage line, and the driving module are all arranged in the second bezel region, or the display substrate includes two first voltage lines, two second voltage lines, and two driving modules, a first first voltage line, a first second voltage line, and a first driving module are arranged in the first bezel region, and a second second voltage line, a second second voltage line, and a second driving module are arranged in the second bezel region.

[0280] For example, the first bezel region can be arranged at the left side of the display region, and the second bezel region can be arranged at the right side of the display region.

[0281] As shown in FIG. 25, B1 is a first bezel region, B2 is a second bezel region, and A0 is a display region;

[0282] The first bezel region B1 is arranged at the left side of A0, and the second bezel region B2 is arranged at the right side of A0.

[0283] The first voltage line, the second voltage line, and the driving module can be arranged in the first bezel region B1, or the first voltage line, the second voltage line, and the driving module can be arranged in the second bezel region B2, or a first first voltage line, a first second voltage line, and a first driving module can be arranged in the first bezel region B1, and a second second voltage line, a second second voltage line, and a second driving module are arranged in the second bezel region B2.

[0284] As shown in FIG. 26, the first bezel region B1 can be provided with a first clock signal line CLKA, a second clock signal line CLKB, a start voltage line STV, a reset control line RST, a high voltage line VDD, and a low voltage line VSS.

[0285] The inverter F1 can be disposed between the left side of the VDD and the right side of the VSS.

[0286] The other part Q0 included in the driving circuit in the driving module can be disposed between the VSS and the display area A0.

[0287] The display device described in the embodiments of the present disclosure includes the display substrate described above.

[0288] The above is the preferred embodiment of the present disclosure, it should be pointed out that, for those skilled in the art, without departing from the principles of the present disclosure, can make a number of improvements and refinements, these improvements and refinements should also be considered as the protection scope of the present disclosure.

Claims

1. A display substrate, comprising a substrate, a first voltage line, a second voltage line and a driving module disposed on the substrate, the driving module comprising a multi-stage driving circuit, the driving circuit comprising an inverter; at least part of the in-plane projection of the inverter on the substrate is disposed between the in-plane projection of a first side edge of the first voltage line on the substrate and the in-plane projection of a second side edge of the second voltage line on the substrate; the first side edge of the first voltage line is a side edge of the first voltage line away from a display area, and the second side edge of the second voltage line is a side edge of the first voltage line close to the display area. 2.The display substrate of claim 1, wherein, an electrode of a transistor included in the inverter and electrically connected to the first voltage line has an in-plane projection on the substrate that at least partially overlaps with the in-plane projection of the first voltage line on the substrate; an electrode of a transistor included in the inverter and electrically connected to the second voltage line has an in-plane projection on the substrate that at least partially overlaps with the in-plane projection of the second voltage line on the substrate. 3.The display substrate of claim 1, wherein, at least part of the in-plane projection of the inverter on the substrate is between the in-plane projection of the first voltage line on the substrate and the in-plane projection of the second voltage line on the substrate. 4.The display substrate of claim 1, wherein, at least part of a device included in the driving circuit other than the inverter is disposed between the second voltage line and the display area; at least one electrode of part of the transistors included in the inverter is electrically connected to a conductive pattern included in the at least part of the device through a connection line; the second voltage line comprises a first part and a second part, the in-plane projection of the first part on the substrate at least partially overlaps with the in-plane projection of the connection line on the substrate, and the in-plane projection of the second part on the substrate does not overlap with the in-plane projection of the connection line on the substrate; in a direction perpendicular to the extension direction of the second voltage line, the width of the first part is less than the maximum width of the second part. 5.The display substrate of claim 4, wherein, the inverter comprises a plurality of transistors; the in-plane projection of the gate of the plurality of transistors on the substrate is disposed between the in-plane projection of the first voltage line on the substrate and the in-plane projection of the second voltage line on the substrate. 6.The display substrate of claim 5, wherein, the second voltage line has a first avoiding space, and the gate of part of the transistors included in the inverter is disposed in the first avoiding space. 7.The display substrate of claim 6, wherein, the minimum distance between the in-plane projection of the gate of part of the transistors included in the inverter on the substrate and the in-plane projection of the second voltage line on the substrate is greater than 2 μm. 8.The display substrate of claim 4, wherein, the second voltage line comprises a hollow region, and at least part of the connection line is disposed in the hollow region. 9.The display substrate of claim 4, wherein, The inverter comprises a first transistor, a second transistor, a third transistor and a fourth transistor; a gate of the first transistor is electrically connected with the first voltage line, a first electrode of the first transistor is electrically connected with the first voltage line, and a second electrode of the first transistor is electrically connected with a first electrode of the second transistor; a gate of the second transistor is electrically connected with a gate of the fourth transistor, and a second electrode of the second transistor is electrically connected with the first voltage line; a gate of the third transistor is electrically connected with the second electrode of the first transistor, a first electrode of the third transistor is electrically connected with the first voltage line, and a second electrode of the third transistor is electrically connected with a first electrode of the fourth transistor; and a second electrode of the fourth transistor is electrically connected with the second voltage line. The second electrode of the third transistor is electrically connected with the first conductive pattern included in the at least partial device through a first connecting line. The gate of the second transistor is electrically connected with the second conductive pattern included in the at least partial device through a second connecting line. The second voltage line comprises at least one hollow region. At least part of the first connecting line is arranged in a corresponding first hollow region. And / or, at least part of the second connecting line is arranged in a corresponding second hollow region. 10.The display substrate of claim 1, wherein, At least part of the inverter on the substrate is surrounded by the orthogonal projection of the first voltage line on the substrate. And / or, at least part of the inverter on the substrate is surrounded by the orthogonal projection of the second voltage line on the substrate. 11.The display substrate of claim 10, wherein, The inverter comprises a plurality of transistors. The first voltage line comprises a third hollow region, and the second voltage line comprises a fourth hollow region. The gates of part of the transistors included in the inverter are arranged in the third hollow region, and the gates of another part of the transistors included in the inverter are arranged in the fourth hollow region. 12.The display substrate of claim 11, wherein, The inverter comprises a first transistor, a second transistor, a third transistor and a fourth transistor; a gate of the first transistor is electrically connected with the first voltage line, a first electrode of the first transistor is electrically connected with the first voltage line, and a second electrode of the first transistor is electrically connected with a first electrode of the second transistor; a gate of the second transistor is electrically connected with a gate of the fourth transistor, and a second electrode of the second transistor is electrically connected with the first voltage line; a gate of the third transistor is electrically connected with the second electrode of the first transistor, a first electrode of the third transistor is electrically connected with the first voltage line, and a second electrode of the third transistor is electrically connected with a first electrode of the fourth transistor; and a second electrode of the fourth transistor is electrically connected with the second voltage line. The gate of the first transistor, the gate of the third transistor, the second electrode of the first transistor and the second electrode of the third transistor are arranged in the third hollow region, and the gate of the second transistor, the gate of the fourth transistor, the first electrode of the second transistor and the first electrode of the fourth transistor are arranged in the fourth hollow region. 13.The display substrate of claim 9 or 12, wherein, A positive projection of the first electrode of the first transistor on the substrate at least partially overlaps a positive projection of the first voltage line on the substrate; A positive projection of the first electrode of the third transistor on the substrate at least partially overlaps a positive projection of the first voltage line on the substrate; A positive projection of the second electrode of the second transistor on the substrate at least partially overlaps a positive projection of the second voltage line on the substrate; A positive projection of the second electrode of the fourth transistor on the substrate at least partially overlaps a positive projection of the second voltage line on the substrate.

14. The display substrate of any one of claims 1 to 12, wherein, The driving circuit further comprises a second node reset circuit; the second node reset circuit is electrically connected with a reset end, the second node and the first voltage line respectively, and is configured to control communication between the second node and the first voltage line under control of a reset signal provided by the reset end; At least part of a positive projection of the second node reset circuit on the substrate is arranged between a positive projection of the first voltage line on the substrate and a positive projection of the second voltage line on the substrate. 15.The display substrate of claim 14, wherein, The second node reset circuit comprises a fifth transistor; a first electrode of the fifth transistor is electrically connected with the first voltage line, and a second electrode of the fifth transistor is electrically connected with the second node; A gate of the fifth transistor is electrically connected with the reset end through a third connection line; a positive projection of the third connection line on the substrate at least partially overlaps a positive projection of the third connection line on the substrate; The first voltage line has a fifth hollow region, and part of the third connection line is arranged in the fifth hollow region.

16. The display substrate of any one of claims 1 to 12, wherein, The first voltage line, the second voltage line and the driving module are arranged in a peripheral region; The peripheral region comprises a first bezel region and a second bezel region; the first bezel region is arranged at a first side of the display region, and the second bezel region is arranged at a second side of the display region; the first side and the second side are opposite sides; The first voltage line, the second voltage line and the driving module are arranged in the first bezel region; or, the first voltage line, the second voltage line and the driving module are arranged in the second bezel region; or, the display substrate comprises two first voltage lines, two second voltage lines and two driving modules; a first first voltage line, a first second voltage line and a first driving module are arranged in the first bezel region, and a second second voltage line, a second second voltage line and a second driving module are arranged in the second bezel region.

17. A display device comprising the display substrate according to any one of claims 1 to 15.

Images