Array substrate, display panel and display apparatus

Abstract

Disclosed are an array substrate, a display panel and a display apparatus. The array substrate comprises: a base substrate, which comprises a first region and a fan-out region located on one side of the first region in a first direction; and at least one conductive layer, which is located on one side of the base substrate. In the fan-out region, the at least one conductive layer comprises a plurality of fan-out lines, a first dummy fan-out line located on one side of the fan-out lines, and at least one etching stop portion, wherein the first dummy fan-out line comprises a plurality of dummy fan-out sub-lines arranged in the extension direction thereof, and break regions located between the dummy fan-out sub-lines; and the etching stop portion is at least located on the side of the fan-out lines facing the first dummy fan-out line and is arranged opposite the break regions.

Description

Array substrate, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly relates to an array substrate, a display panel and a display device. BACKGROUND

[0002] In the prior art, dummy signal lines are arranged on one side of the fan-out lines of the array substrate, and each dummy signal line is arranged in sections, i.e., one dummy signal line includes a plurality of sub-sections that are disconnected from each other.

[0003] However, the fan-out line closest to the dummy signal line arranged in sections is prone to over-etching and being cut off, which leads to disconnection of the fan-out line and failure of signal transmission, thereby affecting the yield of the array substrate.

[0004] SUMMARY

[0005] An array substrate provided by an embodiment of the present disclosure includes:

[0006] A substrate includes a first region and a fan-out region located on one side of the first region in a first direction;

[0007] At least one conductive layer is located on one side of the substrate; in the fan-out region, the at least one conductive layer includes a plurality of fan-out lines, a first dummy fan-out line located on one side of the fan-out lines, and at least one etching stopper; the dummy fan-out line includes a plurality of sub-dummy fan-out lines arranged in an extension direction thereof and a disconnection region located between the sub-dummy fan-out lines; and the etching stopper is arranged opposite to the disconnection region on the side of the fan-out line facing the first dummy fan-out line.

[0008] In some embodiments, the etching stopper is connected to the fan-out line in the region arranged opposite to the disconnection region.

[0009] In some embodiments, in the extension direction of the fan-out line, the length of the etching stopper is greater than the length of the disconnection region.

[0010] In some embodiments, in a direction perpendicular to the extension direction of the fan-out line, the width of the etching stopper is greater than or equal to 0.75 microns.

[0011] In some embodiments, the etching stopper includes a second dummy fan-out line continuously extending between the first dummy fan-out line and the fan-out line.

[0012] In some embodiments, the line width of the second dummy fan-out line is the same in different regions, and the line width of the first dummy fan-out line is less than the line width of the second dummy fan-out line.

[0013] In some embodiments, the second dummy fan-out line includes a first portion and a second portion alternately connected; the first portion is arranged opposite to the disconnection region

[0014] The line width of the first portion is greater than the line width of the second portion, and the line width of the first portion is greater than the line width of the first dummy fan-out line.

[0015] In some embodiments, a difference between the maximum line width of the second dummy fan-out line and the line width of the first dummy fan-out line is greater than or equal to 0.75 microns.

[0016] In some embodiments, the first dummy fan-out line farthest from the second dummy fan-out line further comprises:

[0017] a first protrusion located on a side of the sub-dummy fan-out line away from the second dummy fan-out line;

[0018] The etching blocking portion further comprises:

[0019] at least one third dummy fan-out line, one end of the third dummy fan-out line being electrically connected to the second dummy fan-out line, and the other end of the third dummy fan-out line comprising a first end, the first end being located on a side of the first protrusion away from the second dummy fan-out line, and the first end being oppositely arranged to the first protrusion, a distance between the first end and the first protrusion being greater than 0.

[0020] In some embodiments, the two ends of the second dummy fan-out line are respectively electrically connected to different third dummy fan-out lines.

[0021] In some embodiments, the etching blocking portion comprises 2n third dummy fan-out lines, n being an integer greater than 1.

[0022] Some of the third dummy fan-out lines are further electrically connected to a region other than the two ends of the second dummy fan-out line.

[0023] In some embodiments, the third dummy fan-out line further comprises: a first sub-segment, a second sub-segment, and a third sub-segment electrically connected in sequence, the first sub-segment being electrically connected to the second dummy fan-out line, and the third sub-segment being electrically connected to the first end.

[0024] The extension directions of the first sub-segment and the third sub-segment cross the extension direction of the second dummy fan-out line, and the extension direction of the second sub-segment is parallel to the extension direction of the second dummy fan-out line; the first sub-segment and the third sub-segment are located on a side of the second sub-segment facing the first protrusion.

[0025] In some embodiments, the 2n third dummy fan-out lines of the etching blocking portion are divided into: n groups of dummy fan-out line groups arranged in sequence.

[0026] The third sub-segments of the two third dummy fan-out lines in one dummy fan-out line group are adjacent.

[0027] The first sub-segments of the two third dummy fan-out lines respectively located in two adjacent dummy fan-out line groups are adjacent.

[0028] In some embodiments, at least two adjacent third dummy fan-out lines share the first sub-section.

[0029] In some embodiments, the first protrusion and the first end each have a sharp corner in the orthographic projection on the substrate substrate, and the sharp corner of the first protrusion is opposite to the sharp corner of the first end.

[0030] In some embodiments, the first protrusion and the first end each have a triangular shape in the orthographic projection on the substrate substrate.

[0031] In some embodiments, the array substrate further comprises:

[0032] a connecting portion on the side of the conductive layer away from the substrate substrate; the connecting portion is electrically connected to the first protrusion and the first end.

[0033] In some embodiments, the array substrate further comprises:

[0034] at least one transparent conductive layer on the side of the conductive layer away from the substrate substrate; the at least one transparent conductive layer comprises the connecting portion.

[0035] In some embodiments, the at least one conductive layer comprises: a first conductive layer, and a second conductive layer on the side of the first conductive layer away from the substrate substrate.

[0036] The first conductive layer and the second conductive layer each comprise a plurality of fan-out lines; the fan-out lines on the first conductive layer are first fan-out lines, and the fan-out lines on the second conductive layer are second fan-out lines.

[0037] The first conductive layer further comprises: an etching blocking portion on the side of the first fan-out lines and a first dummy fan-out line.

[0038] In some embodiments, the orthographic projection of the second fan-out lines on the substrate substrate overlaps with the orthographic projection of the first fan-out lines on the substrate substrate.

[0039] Alternatively, the orthographic projection of the second fan-out lines on the substrate substrate overlaps with the region between the orthographic projections of two adjacent first fan-out lines on the substrate substrate.

[0040] In some embodiments, the second conductive layer does not comprise the etching blocking portion and the first dummy fan-out line.

[0041] In some embodiments, the second conductive layer further comprises: a first dummy fan-out line on the side of the second fan-out lines.

[0042] In some embodiments, the orthographic projection of the first dummy fan-out lines of the second conductive layer on the substrate substrate overlaps with the orthographic projection of the first dummy fan-out lines of the first conductive layer on the substrate substrate.

[0043] Or, the second conductive layer further includes a third dummy fan-out line; the third dummy fan-out line of the second conductive layer is not overlapped with the third dummy fan-out line of the first conductive layer in the orthographic projection of the substrate.

[0044] In some embodiments, the second conductive layer further includes an etching blocking part; the etching blocking part of the second conductive layer is overlapped with the etching blocking part of the first conductive layer in the orthographic projection of the substrate.

[0045] In some embodiments, the second conductive layer further includes an etching blocking part;

[0046] The etching blocking part includes a second dummy fan-out line; the second dummy fan-out line of the second conductive layer is not overlapped with the second dummy fan-out line of the first conductive layer in the orthographic projection of the substrate.

[0047] In some embodiments, the etching blocking part further includes a third dummy fan-out line;

[0048] The third dummy fan-out line of the second conductive layer is not overlapped with the third dummy fan-out line of the first conductive layer in the orthographic projection of the substrate.

[0049] Or, the third dummy fan-out line of the second conductive layer is only partially overlapped with the third dummy fan-out line of the first conductive layer in the orthographic projection of the substrate.

[0050] In some embodiments, the array substrate further includes a connecting part;

[0051] The connecting part is electrically connected with the first conductive layer through a first via, and is electrically connected with the second conductive layer through a second via; the first via is not overlapped with the second via in the orthographic projection of the substrate.

[0052] In some embodiments, the at least one conductive layer includes a first conductive layer and a second conductive layer; the array substrate further includes a plurality of thin film transistors located in the first area; the first conductive layer further includes a gate electrode of the thin film transistor, and the second conductive layer further includes a source electrode and a drain electrode of the thin film transistor.

[0053] The at least one transparent conductive layer includes:

[0054] A first transparent conductive layer is located on a side of the conductive layer away from the substrate.

[0055] A second transparent conductive layer is located on a side of the first transparent conductive layer away from the substrate; the second transparent conductive layer includes a connecting part.

[0056] In some embodiments, the array substrate further includes a second conductive layer and a first transparent conductive layer.

[0057] The second conductive layer includes a plurality of second fan-out lines and a plurality of first bonding electrodes, and each of the second fan-out lines is electrically connected to one of the first bonding electrodes;

[0058] The first transparent conductive layer further includes a plurality of first protection structures, each of the first protection structures is electrically connected to one of the second fan-out lines and one of the first bonding electrodes, and each of the first protection structures covers one of the second fan-out lines and one of the first bonding electrodes.

[0059] The display panel provided by the embodiment of the present disclosure includes:

[0060] The array substrate provided by the embodiment of the present disclosure includes:

[0061] The opposite substrate is arranged opposite to the array substrate.

[0062] The liquid crystal layer is located between the array substrate and the opposite substrate.

[0063] The display device provided by the embodiment of the present disclosure includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0065] FIG. 1 is a structural schematic diagram of an array substrate provided by the related art;

[0066] FIG. 2 is a structural schematic diagram of an array substrate provided by the embodiment of the present disclosure;

[0067] FIG. 3 is an enlarged structural schematic diagram of the E region in FIG. 2 provided by the embodiment of the present disclosure;

[0068] FIG. 4 is a structural schematic diagram of another array substrate provided by the embodiment of the present disclosure;

[0069] FIG. 5 is a structural schematic diagram of still another array substrate provided by the embodiment of the present disclosure;

[0070] FIG. 6 is a structural schematic diagram of still another array substrate provided by the embodiment of the present disclosure;

[0071] FIG. 7 is a structural schematic diagram of still another array substrate provided by the embodiment of the present disclosure;

[0072] FIG. 8 is a structural schematic diagram of still another array substrate provided by the embodiment of the present disclosure;

[0073] FIG. 9 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0074] FIG. 10 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0075] FIG. 11 is a structural schematic diagram of a cross section along FF' in FIG. 8 or FIG. 9 according to an embodiment of the present disclosure;

[0076] FIG. 12 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0077] FIG. 13 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0078] FIG. 14 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0079] FIG. 15 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0080] FIG. 16 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0081] FIG. 17 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0082] FIG. 18 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0083] FIG. 19 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0084] FIG. 20 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0085] FIG. 21 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0086] FIG. 22 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0087] FIG. 23 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0088] FIG. 24 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0089] FIG. 25 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0090] FIG. 26 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0091] FIG. 27 is a structural schematic diagram of another array substrate according to an embodiment of the present disclosure;

[0092] FIG. 28 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0093] FIG. 29 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0094] FIG. 30 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0095] FIG. 31 is a structural schematic diagram of a cross section along PP' in FIG. 30 provided by an embodiment of the present disclosure;

[0096] FIG. 32 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0097] FIG. 33 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0098] FIG. 34 is a structural schematic diagram of a cross section along MM' in FIG. 32 or FIG. 33 provided by an embodiment of the present disclosure;

[0099] FIG. 35 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0100] FIG. 36 is a structural schematic diagram of a cross section along LL' in FIG. 35 provided by an embodiment of the present disclosure;

[0101] FIG. 37 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0102] FIG. 38 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0103] FIG. 39 is a structural schematic diagram of a cross section along HH' in FIG. 38 provided by an embodiment of the present disclosure;

[0104] FIG. 40 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0105] FIG. 41 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0106] FIG. 42 is a structural schematic diagram of a cross section along JJ' in FIG. 41 provided by an embodiment of the present disclosure;

[0107] FIG. 43 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0108] FIG. 44 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0109] FIG. 45 is a structural schematic diagram of another array substrate provided by the related art;

[0110] FIG. 46 is a structural schematic diagram of a display panel according to an embodiment of the present disclosure;

[0111] FIG. 47 is a structural schematic diagram of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0112] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Moreover, the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict, if possible. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0113] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by those skilled in the art to which the present disclosure pertains. The terms “first”, “second”, and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms “include”, “contain”, and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0114] It should be noted that the sizes and shapes of the figures in the drawings do not reflect the true proportions, but only serve to illustrate the present disclosure. Moreover, the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout the drawings.

[0115] In the related art, users have higher and higher requirements for display products, and the peripheral area of the display product needs to be compressed to achieve narrow-frame display. Due to the need to compress the peripheral area, the size of the fan-out area located in the peripheral area also needs to be reduced accordingly. The fan-out area includes a plurality of fan-out lines, and due to the large number of fan-out lines, the reduction of the size of the fan-out area will increase the difficulty of the patterning process of the fan-out lines. Generally, the fan-out lines are metal, and processes such as coating photoresist, exposure, development, and etching are needed to form the pattern of the fan-out lines. As shown in FIG. 1, the B' side blank area is large, this area is not covered with photoresist, and is easy to accumulate a large amount of etching liquid. When the B' side metal pattern is completely etched, the etching liquid will flow to the dummy signal line 1 and accumulate in the break area C of the dummy signal line 1. Due to the high concentration of the etching liquid and the isotropy of the etching liquid etching, the fan-out line 2 adjacent to the break area C of the innermost dummy signal line 1 will be over-etched. If the fan-out line 2 is etched off, it will cause the fan-out line to be disconnected, the display product to display abnormally, and affect the yield of the display product.

[0116] The array substrate provided by the embodiments of the present disclosure is shown in FIGS. 2 and 3, and includes:

[0117] The substrate 3 includes a first area AA and a fan-out area NA-1 located on one side of the first area AA in the first direction Y;

[0118] The at least one conductive layer 4 is located on one side of the substrate 3. In the fan-out area NA-1, the at least one conductive layer 4 includes a plurality of fan-out lines 401, a first dummy fan-out line 402 located on one side of the fan-out line 401, and at least one etching blocking part 403. The first dummy fan-out line 402 includes a plurality of sub-dummy fan-out lines 4021 arranged in the extension direction thereof and a break area C located between the sub-dummy fan-out lines 4021. The etching blocking part 403 is at least located on the side of the fan-out line 401 facing the first dummy fan-out line 402 and is arranged opposite to the break area C.

[0119] It should be noted that if there is a large area of blank area on one side of the fan-out line, the high concentration of the etching liquid will cause the fan-out line close to the blank area to be etched through and affect the signal transmission. The array substrate provided by the embodiments of the present disclosure has a plurality of first dummy fan-out lines arranged on one side of the fan-out line, thereby avoiding a large area of non-patterned area on one side of the plurality of fan-out lines and reducing the risk of the fan-out line being etched through. In addition, the first dummy fan-out line includes a break area, which can also avoid the first dummy fan-out line from accumulating static electricity to damage the fan-out line.

[0120] Also, the array substrate provided by the embodiments of the present disclosure is provided with an etching blocking part between the fan-out line and the first dummy fan-out line with the fracture zone, and the etching blocking part is arranged opposite to the fracture zone. Even if high-concentration etching liquid is enriched in the fracture zone of the first dummy fan-out line, the etching blocking part can play a buffering role and can protect the fan-out line from being over-etched, thereby avoiding the risk of line breakage of the fan-out line and improving the yield of the array substrate.

[0121] It should be noted that FIG. 3 is an enlarged schematic view of the E area in FIG. 2.

[0122] It should be noted that the array substrate provided by the embodiments of the present disclosure can be applied to a display panel. The first area corresponds to a display area of the display panel, that is, the first area coincides with the display area.

[0123] In some embodiments, at least two first dummy fan-out lines are arranged on one side of the fan-out line of the edge; and the fracture zones of adjacent first dummy fan-out lines are arranged in a staggered manner, that is, the fracture zone of one of the adjacent first dummy fan-out lines is opposite to the other first dummy fan-out line.

[0124] In some embodiments, the length of the first dummy fan-out line is about 45 microns, and the length of the fracture zone, that is, the distance between adjacent first dummy fan-out lines, is about 3.3 microns.

[0125] In some embodiments, as shown in FIG. 3, the etching blocking part 403 is connected to the fan-out line 401 in the area opposite to the fracture zone C. That is, the etching blocking part 403 is integrally connected to the fan-out line 401.

[0126] The array substrate provided by the embodiments of the present disclosure is provided with an etching blocking part in the area opposite to the fracture zone and connected to the fan-out line, which is equivalent to widening the fan-out line in the area opposite to the fracture zone and widening the fan-out line on the side of the fan-out line toward the fracture zone. The etching blocking part can effectively prevent the etching liquid enriched in the fracture zone from etching the fan-out line, reduce the concentration of the etching liquid, play a buffering protection role, avoid the risk of line breakage of the fan-out line, and improve the yield of the array substrate.

[0127] In some embodiments, as shown in FIG. 2, the first dummy fan-out line 402 closest to the fan-out line 401 includes a plurality of fracture zones C, and a plurality of etching blocking parts 403 are arranged on one side of the fan-out line 401.

[0128] An etching blocking part 403 needs to be arranged in the area opposite to each fracture zone C of the first dummy fan-out line 402 closest to the fan-out line 401.

[0129] In some embodiments, as shown in FIG. 3, in a direction parallel to the substrate substrate 1 and perpendicular to the extension direction of the fan-out line 401 (i.e. in the X' direction in FIG. 3), the orthographic projection of the fracture zone C falls within the orthographic projection of the etching blocking part 403. Thus, the relative position of the fracture zone C and the fan-out line 401 in the direction parallel to the substrate substrate 1 and perpendicular to the extension direction of the fan-out line 401 can be completely avoided, the buffering protection effect of the etching blocking part 403 can be further improved, and the risk of disconnection of the fan-out line 401 can be further avoided, thereby improving the yield of the array substrate.

[0130] In some embodiments, as shown in FIG. 3, in the extension direction of the fan-out line 401, the length h1 of the etching blocking part 403 is greater than the length h2 of the fracture zone C.

[0131] The array substrate provided by the embodiments of the present disclosure can ensure that the orthographic projection of the fracture zone falls within the orthographic projection of the etching blocking part while the length of the etching blocking part is greater than the length of the fracture zone, that is, even if there is a process deviation, the orthographic projection of the fracture zone in the direction parallel to the substrate substrate and perpendicular to the extension direction of the fan-out line can fall within the orthographic projection of the etching blocking part, the protection effect of the etching blocking part can be further improved, the risk of disconnection of the fan-out line can be further avoided, and the yield of the array substrate can be improved.

[0132] In some embodiments, as shown in FIG. 3, in the direction perpendicular to the extension direction of the fan-out line 401, the width h3 of the etching blocking part 403 is greater than or equal to 0.75 microns.

[0133] The width of the etching blocking part provided by the embodiments of the present disclosure is greater than or equal to 0.75 microns, so that the buffering effect of the etching blocking part on the etching liquid concentration can be improved, the protection effect of the etching blocking part can be further improved, the risk of disconnection of the fan-out line can be further avoided, and the yield of the array substrate can be improved.

[0134] In some embodiments, the line width of the fan-out line is equal to the line width of the sub-virtual fan-out line.

[0135] In some embodiments, the line width of the fan-out line and the line width of the sub-virtual fan-out line are greater than or equal to 0.75 microns.

[0136] Alternatively, in some embodiments, the etching blocking part and the fan-out line are disconnected from each other and not connected to each other.

[0137] In some embodiments, as shown in FIG. 4, the etching blocking part 403 includes a second virtual fan-out line 4031 continuously extending between the first virtual fan-out line 402 and the fan-out line 401.

[0138] It should be noted that the continuous extension of the second virtual fan-out line means that the second virtual fan-out line is a complete line and does not include a fracture zone.

[0139] The array substrate provided by the embodiments of the present disclosure, the etching blocking part comprises a second dummy fan-out line extending continuously, that is, the wire adjacent to the fan-out line is a wire continuously arranged without a break area, so that the risk of etching the fan-out line due to high concentration of etching liquid can be avoided, and the setting of the second dummy fan-out line extending continuously can also reduce the concentration of the etching liquid, achieve the buffering protection effect, avoid the risk of breakage of the fan-out line, and improve the yield of the array substrate. Although the second dummy fan-out line is opposite to the break area of the first dummy fan-out line, since the second dummy fan-out line does not need to transmit a signal line, even if the second dummy fan-out line is over-etched, and since the second dummy fan-out line and the fan-out line are mutually broken, the signal transmission will not be affected.

[0140] In some embodiments, as shown in FIG. 4, the line width h4 of the second dummy fan-out line 4031 in different areas is the same, and the line width h5 of the first dummy fan-out line 402 is smaller than the line width h4 of the second dummy fan-out line 4031.

[0141] The array substrate provided by the embodiments of the present disclosure, the etching blocking part comprises a second dummy fan-out line extending continuously, that is, the wire adjacent to the fan-out line is a wire continuously arranged without a break area, so that the risk of etching the fan-out line due to high concentration of etching liquid can be avoided, and the setting of the second dummy fan-out line extending continuously can also reduce the concentration of the etching liquid, achieve the buffering protection effect, avoid the risk of breakage of the fan-out line, and improve the yield of the array substrate. Although the second dummy fan-out line is opposite to the break area of the first dummy fan-out line, since the second dummy fan-out line does not need to transmit a signal line, even if the second dummy fan-out line is over-etched, and since the second dummy fan-out line and the fan-out line are mutually broken, the signal transmission will not be affected.

[0142] Alternatively, in some embodiments, as shown in FIG. 5, the line width h4 of the second dummy fan-out line 4031 in different areas is not completely the same; at least in the area opposite to the break area C, the line width h4 of the second dummy fan-out line 4031 is greater than the line width h5 of the first dummy fan-out line 402.

[0143] In some embodiments, as shown in FIG. 5, the second dummy fan-out line 4031 comprises: a first part 40311 and a second part 40312 connected alternately; the first part 40311 is arranged opposite to the break area C;

[0144] The line width h41 of the first part 40311 is greater than the line width h42 of the second part 40312, and the line width h41 of the first part 40311 is greater than the line width h5 of the first dummy fan-out line 402.

[0145] That is, the array substrate provided by the embodiments of the present disclosure, the second dummy fan-out line is widened in the area opposite to the break area, which can effectively prevent the etching liquid enriched in the break area from etching the fan-out line, reduce the concentration of the etching liquid, achieve the buffering protection effect, avoid the risk of breakage of the fan-out line, and improve the yield of the array substrate.

[0146] In some embodiments, the line width of the fan-out line is equal to the line width of the first dummy fan-out line and the line width of the second part.

[0147] In some embodiments, as shown in FIG. 5, the edge of the first portion 40311 towards one side of the fan-out line 401 is on the same line as the edge of the second portion 40312 towards one side of the fan-out line 401, and the edge of the first portion 40311 away from one side of the fan-out line 401 is not on the same line as the edge of the second portion 40312 away from one side of the fan-out line 401. That is, the second dummy fan-out line 4031 has a protrusion towards one side of the first dummy fan-out line 402, and the protrusion corresponds to the first portion 40311.

[0148] In some embodiments, as shown in FIG. 5, the first dummy fan-out line 402 closest to the fan-out line 401 includes a plurality of cutaway regions C, and the second dummy fan-out line 4031 includes a plurality of first portions 40311.

[0149] Each cutaway region C of the first dummy fan-out line 402 closest to the fan-out line 401 needs to be provided with a first portion 40311.

[0150] In some embodiments, as shown in FIG. 5, in a direction parallel to the substrate 1 and perpendicular to the extension direction of the fan-out line 401 (i.e., the X' direction in the figure), the orthographic projection of the cutaway region C falls within the orthographic projection of the first portion 40311. Thus, the cutaway region can be completely avoided from being opposite to the region with a relatively narrow line width, the risk of over-etching of the fan-out line due to the second dummy fan-out line being cut off and having a cutaway can be avoided, the buffering protection effect of the etching blocking portion can be further improved, the risk of the fan-out line being broken can be further avoided, and the yield of the array substrate can be improved.

[0151] In some embodiments, as shown in FIG. 5, in the extension direction of the fan-out line 401, the length h6 of the first portion 40311 is greater than the length h2 of the cutaway region C.

[0152] The array substrate provided by the embodiments of the present disclosure can make the length of the first portion greater than the length of the cutaway region while the orthographic projection of the cutaway region falls within the orthographic projection of the first portion, avoid the region where the cutaway region is opposite to the second portion due to process deviation, avoid the risk of over-etching of the fan-out line due to the second dummy fan-out line being cut off and having a cutaway, further improve the protection effect of the etching blocking portion, further avoid the risk of the fan-out line being broken, and improve the yield of the array substrate.

[0153] In some embodiments, the maximum line width of the second dummy fan-out line 4031 is greater than or equal to 0.75 microns larger than the line width of the first dummy fan-out line. It should be noted that when the etching blocking part includes the second dummy fan-out line with the same line width in different regions, the line width of any part of the second dummy fan-out line is the maximum line width. When the line width of the second dummy fan-out line is not completely the same in different regions, the line width of the second dummy fan-out line 4031 in the region opposite to the fracture zone C is the maximum line width. For example, when the second dummy fan-out line includes a first part and a second part, the line width of the first part is the maximum line width.

[0154] The array substrate provided by the embodiments of the present disclosure has a difference between the maximum line width of the second dummy fan-out line and the line width of the first dummy fan-out line greater than or equal to 0.75 microns, so that the buffering effect of the etching blocking part on the etching liquid concentration can be improved, and the protection effect of the etching blocking part can be improved, thereby further avoiding the risk of line breakage of the fan-out line and improving the yield of the array substrate.

[0155] In some embodiments, as shown in FIGS. 6-9, the first dummy fan-out line 402 farthest from the second dummy fan-out line 4031 further includes:

[0156] The first protruding part 4022 is located on the side of the sub-dummy fan-out line 4021 away from the second dummy fan-out line 4031.

[0157] The etching blocking part 403 further includes:

[0158] At least one third dummy fan-out line 4032; one end of the third dummy fan-out line 4032 is electrically connected to the second dummy fan-out line 4031, and the other end of the third dummy fan-out line 4032 includes a first end 40321, the first end 40321 is located on the side of the first protruding part 4022 away from the second dummy fan-out line 4031, and the first end 40321 is opposite to the first protruding part 4022, and the distance between the first end 40321 and the first protruding part 4022 is greater than 0.

[0159] It should be noted that since the second dummy fan-out line is continuously extended, the second dummy fan-out line is prone to static electricity accumulation, and the static electricity accumulation cannot be released and is prone to damage the adjacent fan-out line.

[0160] The array substrate provided by the embodiments of the present disclosure further comprises a first protruding portion in the first dummy fan-out line, and the etching blocking portion further comprises a first end arranged opposite to the first protruding portion, so that when static electricity accumulates in the second dummy fan-out line, the static electricity can be released through the first end and the first protruding portion, thereby avoiding the static electricity from damaging the fan-out line adjacent to the second dummy fan-out line and affecting the signal transmission of the fan-out line, and the yield and working stability of the array substrate can be improved. In addition, the first protruding portion is located on the side of the sub-dummy fan-out line away from the second dummy fan-out line, that is, the first protruding portion and the first end are arranged opposite to each other on the outside of the first dummy fan-out line, so that the first protruding portion is arranged on the side of the sub-dummy fan-out line facing the second dummy fan-out line, thereby avoiding the risk of etching liquid accumulation caused by the increase in the distance between the first protruding portion and the second dummy fan-out line and the etching of the fan-out line.

[0161] In some embodiments, as shown in FIGS. 6-9, in the extension direction of the sub-dummy fan-out line 4021, the maximum width of the first end 40321 is greater than the line width of the remaining regions of the third dummy fan-out line 4032 except the first end 40321.

[0162] In some embodiments, as shown in FIGS. 6-9, in the extension direction of the sub-dummy fan-out line 4021, the maximum width of the first end 40321 is equal to the maximum width of the first protruding portion 4022.

[0163] In some embodiments, as shown in FIGS. 6-9, the first protruding portion 4022 corresponds to the first end 40321 one by one.

[0164] In some embodiments, as shown in FIGS. 6-9, the first dummy fan-out line 402 farthest away from the second dummy fan-out line 4031 comprises a plurality of first protruding portions 4022, and the etching blocking portion 403 comprises a plurality of first ends 40321.

[0165] In some embodiments, as shown in FIGS. 6-9, when the first dummy fan-out line 402 farthest away from the second dummy fan-out line 4031 comprises a plurality of first protruding portions 4022, the plurality of first protruding portions 4022 are respectively located on one side of different sub-dummy fan-out lines 4021. In this way, static electricity can be released through different sub-dummy fan-out lines, which is equivalent to increasing the static electricity release position and improving the efficiency of static electricity release, thereby avoiding the static electricity from damaging the fan-out line adjacent to the second dummy fan-out line and affecting the signal transmission of the fan-out line, and the yield and working stability of the array substrate can be improved.

[0166] Alternatively, in some embodiments, when the first dummy fan-out line farthest away from the second dummy fan-out line comprises a plurality of first protruding portions, in the case that a plurality of first protruding portions can be arranged on the length of the sub-dummy fan-out line, in order to save space, a plurality of first protruding portions can also be arranged on at least part of the side of the sub-dummy fan-out line away from the second dummy fan-out line.

[0167] In some embodiments, as shown in FIG. 10, the first dummy fan-out line 402 with the first protruding part 4022 arranged on one side has a first symmetry axis 21 perpendicular to the extending direction of the first dummy fan-out line 402, and the first symmetry axis 21 passes through the first protruding part 4022.

[0168] That is, the first protruding part is arranged in the middle region of the sub-dummy fan-out line.

[0169] In some embodiments, the first symmetry axis also passes through the first end.

[0170] In some embodiments, as shown in FIG. 10, the first symmetry axis 21 bisects the first protruding part 4022, that is, the first symmetry axis 21 is also a symmetry axis of the first protruding part 4022.

[0171] In some embodiments, the first symmetry axis also bisects the first end.

[0172] Alternatively, in some embodiments, the first symmetry axis can also not pass through the first protruding part.

[0173] Alternatively, in some embodiments, the first protruding part is arranged on the side of the end of the sub-dummy fan-out line.

[0174] In some embodiments, as shown in FIGS. 6 and 7, the first protruding part 4022 and the first end 40321 have sharp corners 9 in the orthographic projection of the substrate 3, and the sharp corner 9 of the first protruding part 4022 is arranged opposite to the sharp corner 9 of the first end 40321.

[0175] The array substrate provided by the embodiments of the present disclosure has the following advantages: the first protruding part included in the first dummy fan-out line and the first end included in the etching stop part both have sharp corners, and the sharp corner of the first protruding part is arranged opposite to the sharp corner of the first end, so that the sharp end discharge can be realized at the sharp corner of the first protruding part and the sharp corner of the first end. Specifically, when the second dummy fan-out line has static electricity accumulation, there is a potential difference between the first end and the first protruding part, so that the charge on the second dummy fan-out line can be induced to be released through the first end, the fan-out line adjacent to the second dummy fan-out line is prevented from being electrostatically shocked, the signal transmission of the fan-out line is prevented from being affected, the yield and the working stability of the array substrate can be improved.

[0176] In some embodiments, as shown in FIGS. 6 and 7, the distance between the sharp corner 9 of the first protruding part 4022 and the sharp corner 9 of the first end 40321 is greater than 0.

[0177] In some embodiments, as shown in FIGS. 6 and 7, the first protruding part 4022 and the first end 40321 have the same shape in the orthographic projection of the substrate 3.

[0178] In some embodiments, as shown in FIGS. 6 and 7, the first protruding part 4022 and the first end 40321 both have a triangular shape in the orthographic projection of the substrate 3.

[0179] The apex of the triangle of the first protruding portion 4022 is opposite to the apex of the triangle of the first end 40321.

[0180] Alternatively, in some embodiments, as shown in FIG. 8, FIG. 9, and FIG. 11, the array substrate further comprises:

[0181] The connecting portion 10 is located on the side of the conductive layer 4 away from the substrate 3; the connecting portion 10 is electrically connected with the first protruding portion 4022 and the first end 40321.

[0182] It should be noted that FIG. 11 is a cross-sectional view along FF' in FIG. 8 or FIG. 9.

[0183] The array substrate provided by the embodiments of the present disclosure, the first dummy fan-out line comprises a first protruding portion, the etching blocking portion comprises a first end, the first protruding portion and the first end are electrically connected with a connecting portion located at the upper layer of the two to form an electrostatic discharge loop, the connecting portion and the first conductive layer are located in different layers, and there is a difference in resistance between the two. When there is static electricity accumulation, the charge on the second dummy fan-out line can be induced to reach the connecting portion for discharge, the fan-out line adjacent to the second dummy fan-out line is prevented from being electrocuted, the signal transmission of the fan-out line is prevented from being affected, the yield and working stability of the array substrate can be improved.

[0184] In some embodiments, as shown in FIG. 11, the array substrate further comprises:

[0185] The at least one transparent conductive layer 12 is located on the side of the conductive layer 4 away from the substrate 3; the at least one transparent conductive layer 12 comprises the connecting portion 10.

[0186] The array substrate provided by the embodiments of the present disclosure, the transparent conductive layer comprises a transparent conductive material, and the conductive layer is usually a metal material. The resistance of the transparent conductive layer is greatly different from the resistance of the conductive layer. When the connecting portion is located in the transparent conductive layer, when there is static electricity accumulation, the charge on the second dummy fan-out line can be induced to reach the connecting portion. Since the resistance of the conductive layer is greatly different from the resistance of the transparent conductive layer, the connecting portion is burned out when the static electricity reaches the connecting portion, so as to achieve electrostatic discharge, prevent the fan-out line adjacent to the second dummy fan-out line from being electrocuted, prevent the signal transmission of the fan-out line from being affected, and improve the yield and working stability of the array substrate.

[0187] In some embodiments, as shown in FIG. 8 and FIG. 9, the distance between the first protruding portion 4022 and the first end 40321 is greater than 0.

[0188] In some embodiments, as shown in FIG. 8 and FIG. 9, the first protruding portion 4022 and the first end 40321 have the same shape in the orthographic projection of the substrate 3.

[0189] In some embodiments, as shown in FIG. 8 and FIG. 9, the first protruding portion 4022 and the first end 40321 have a rectangular shape in the orthographic projection of the substrate 3.

[0190] In some embodiments, as shown in FIG. 8 and FIG. 9, the connecting portion 10 has a rectangular shape in the orthographic projection of the substrate 3.

[0191] In some embodiments, as shown in FIG. 8 and FIG. 9, the orthographic projection of the connecting portion 10 covers the orthographic projection of the first protruding portion 4022 and the first end 40321 in the orthographic projection of the substrate 3.

[0192] In some embodiments, as shown in FIG. 8, FIG. 9 and FIG. 11, the connecting portion 10 is electrically connected to the first protruding portion 4022 and the first end 40321 through different vias 11 respectively.

[0193] In some embodiments, as shown in FIG. 8 and FIG. 9, in the direction perpendicular to the arrangement direction of the first protruding portion 4022 and the first end 40321, the width h7 of the connecting portion 10 is greater than the width h8 of the first protruding portion 4022, and the width h7 of the connecting portion 10 is greater than the width h9 of the first end 40321.

[0194] In some embodiments, as shown in FIG. 8 and FIG. 9, in the arrangement direction of the first protruding portion 4022 and the first end 40321, the length of the connecting portion 10 is equal to the sum of the length of the first protruding portion 4022, the length of the first end 40321 and the distance between the first protruding portion 4022 and the first end 40321.

[0195] In some embodiments, as shown in FIG. 12, the array substrate further comprises: a plurality of thin film transistors TFT located in the first area (not shown); the thin film transistor TFT comprises: a gate G, an active layer 13, a source S and a drain D; the source S and the drain D are located on the side of the gate G away from the substrate 3.

[0196] In some embodiments, as shown in FIG. 12, the at least one conductive layer 4 comprises: a first conductive layer 4-1, and a second conductive layer 4-2 located on the side of the first conductive layer 4-1 away from the substrate 3.

[0197] The first conductive layer 4-1 comprises the gate G of the thin film transistor TFT;

[0198] The source S and the drain D are arranged in the same layer, and the second conductive layer 4-2 comprises the source S and the drain D.

[0199] It should be noted that FIG. 12 takes the bottom gate structure of the thin film transistor TFT as an example for illustration, i.e., the active layer 13 is located on the side of the gate G away from the substrate 3, and the source S and the drain D are in contact with the active layer 13 on the side of the active layer 13 away from the substrate 3;

[0200] The array substrate further comprises a gate insulating layer 14 between the first conductive layer 4 and the active layer 13, and a buffer layer 15 between the first conductive layer 4 and the substrate 3.

[0201] Alternatively, in some embodiments, the thin film transistor can also be a top gate structure, i.e., the gate electrode is located on the side of the active layer away from the substrate, and the source electrode and the drain electrode are located on the side of the gate electrode away from the substrate; the array substrate further comprises a gate insulating layer between the gate electrode and the active layer, and an interlayer insulating layer between the source electrode, the drain electrode and the gate electrode.

[0202] In some embodiments, as shown in FIG. 2, the first conductive layer 4-1 further comprises a plurality of scan lines 404, and the second conductive layer 4-2 further comprises a plurality of data lines 405; the plurality of scan lines 404 and the plurality of data lines 405 are arranged in a cross manner.

[0203] The data lines 405 extend along a first direction Y, and the scan lines 404 extend along a second direction X.

[0204] In some embodiments, the scan lines are electrically connected to the gate electrodes, and the data lines are electrically connected to the source electrodes.

[0205] In some embodiments, as shown in FIG. 2, the array substrate further comprises a peripheral area NA surrounding the first area AA; the peripheral area NA comprises a fan-out area NA-1; the peripheral area NA further comprises a binding area NA-2 located on the side of the fan-out area NA-1 away from the first area AA.

[0206] The array substrate further comprises a plurality of binding pins 17 located in the binding area NA-2; the binding pins 17 are electrically connected to the fan-out lines 401; the scan lines 404 and the data lines 405 are electrically connected to the fan-out lines 401.

[0207] When the array substrate is applied to a display product, the plurality of binding pins are bound to a driving chip, so that the driving chip can provide signals to the scan lines and the data lines through the binding pins and the fan-out lines, respectively. In some embodiments, the array substrate further comprises a touch electrode, and the plurality of fan-out lines further comprise a fan-out line electrically connected to the touch electrode, so that the driving chip can perform signal transmission between the binding pins and the touch electrode through the fan-out lines.

[0208] In some embodiments, as shown in FIG. 2, the scan lines 404 are electrically connected to the fan-out lines 401 through a peripheral connection line 18 arranged in the peripheral area NA.

[0209] Alternatively, the array substrate can further comprise a gate driving circuit located on at least one side of the first area AA in the second direction X; the gate driving circuit is electrically connected to the plurality of scan lines, and part of the fan-out lines are electrically connected to the gate driving circuit.

[0210] That is, in a specific implementation, on at least one side of the extension direction of the scan lines, the plurality of scan lines are electrically connected to the partial fan-out lines through the plurality of peripheral connection leads or the gate driving circuit.

[0211] It should be noted that only the plurality of fan-out lines 401, the etching blocking part 403 and the first dummy fan-out line 402 of one conductive layer 4 are shown in FIG. 2.

[0212] In some embodiments, as shown in FIG. 2, on both sides of the arrangement direction of the plurality of fan-out lines 401 in the same conductive layer 4, there are large-area blank areas, i.e., the K2 and K3 areas in FIG. 2. The area between the plurality of fan-out lines 401 can also include a blank area without a fan-out line pattern, i.e., the K1 area in FIG. 2.

[0213] In some embodiments, as shown in FIG. 2, at least in the blank area without a fan-out line pattern between the plurality of fan-out lines 401, i.e., the K1 area in FIG. 2, the etching blocking part 403 and the first dummy fan-out line 402 are arranged.

[0214] Of course, in some embodiments, the blank areas on both sides of the arrangement direction of the plurality of fan-out lines 401, i.e., the K2 and K3 areas in FIG. 2, can also be provided with the etching blocking part and the first dummy fan-out line.

[0215] In some embodiments, as shown in FIG. 2, the fan-out lines 401 included in the same conductive layer 4 are divided into two groups (Z1 and Z2 in FIG. 2), each group including a plurality of fan-out lines 401, and the two groups of fan-out lines 401 have a K1 blank area; and each group of fan-out lines 401 needs to be provided with a dummy fan-out line 402 having a break area C on the side facing the K1 blank area. Therefore, the etching blocking part 403 is arranged between each group of fan-out lines 401 and the first dummy fan-out line 402.

[0216] In some embodiments, as shown in FIG. 2, the peripheral area NA only includes one binding area NA-2, i.e., the array substrate only needs to be bound with one driving chip.

[0217] Alternatively, in some embodiments, as shown in FIG. 23, the peripheral area NA includes a plurality of binding areas NA-2 arranged along the second direction X. That is, the array substrate needs to be bound with a plurality of driving chips.

[0218] In some embodiments, as shown in FIG. 23, in the same conductive layer 4, there are large-area blank areas, i.e., K2 and K3 areas in FIG. 23, on both sides of the arrangement direction of the plurality of fan-out lines 401. The area between the plurality of fan-out lines 401 corresponding to one binding area NA-2 can also include a blank area without a fan-out line pattern, i.e., K1 area in FIG. 23. The area between the fan-out lines 401 corresponding to adjacent binding areas NA-2 can also include a blank area without a fan-out line pattern, i.e., K4 area in FIG. 23. At least one of the K1 area, the K2 area, the K3 area, and the K4 area is provided with an etching stop portion 403 and a first dummy fan-out line 402 on one side of the fan-out line 401.

[0219] In some embodiments, the array substrate is applied to a liquid crystal display. As shown in FIG. 12, at least one transparent conductive layer 12 includes:

[0220] A first transparent conductive layer 6 is located on the side of the conductive layer 4, i.e., the second conductive layer 4-2, away from the substrate 3.

[0221] A second transparent conductive layer 7 is located on the side of the first transparent conductive layer 6 away from the substrate 3.

[0222] In specific implementation, one of the first transparent conductive layer and the second transparent conductive layer includes a pixel electrode, and the other of the first transparent conductive layer and the second transparent conductive layer includes a common electrode. In FIG. 12, the first transparent conductive layer 6 includes a pixel electrode 602, and the second transparent conductive layer 7 includes a common electrode 701.

[0223] The pixel electrode 602 is electrically connected to the drain D. Specifically, in FIG. 12, the pixel electrode 602 is directly overlapped with the drain D.

[0224] The array substrate further includes an insulating layer 16 located between the first transparent conductive layer 6 and the second transparent conductive layer 7. The insulating layer 16 includes a planarization layer 1602.

[0225] In some embodiments, as shown in FIG. 12, the insulating layer 16 further includes a passivation layer 1601 located between the planarization layer 1602 and the first transparent conductive layer 6.

[0226] In some embodiments, the pixel electrode is electrically connected to the thin film transistor in one-to-one correspondence, and the common electrode is provided in an entire area.

[0227] One of the pixel electrode and the common electrode includes a plurality of slits.

[0228] In some embodiments, the substrate is a glass substrate.

[0229] In some embodiments, the first conductive layer and the second conductive layer are metal layers.

[0230] In some embodiments, the first transparent conductive layer and the second transparent conductive layer comprise a transparent conductive material, such as indium tin oxide, indium zinc oxide, etc.

[0231] In some embodiments, the planarization layer is an organic insulating layer.

[0232] The passivation layer, the buffer layer, and the gate insulating layer are inorganic insulating layers.

[0233] In some embodiments, the first transparent conductive layer or the second transparent conductive layer comprises a connecting portion.

[0234] In some embodiments, as shown in FIG. 11, the second transparent conductive layer 7 comprises a connecting portion 10. That is, the static electricity is led out through the conductive layer farthest from the first fan-out line, which is more conducive to avoiding the first fan-out line from being struck by static electricity.

[0235] In some embodiments, the first conductive layer comprises a fan-out line, a first dummy fan-out line, and an etching stop portion; as shown in FIG. 11, the connecting portion 10 is electrically connected to the first protruding portion 4022 and the first end 40321 through different vias 11 penetrating the planarization layer 1602, the passivation layer 1601, and the gate insulating layer 14, respectively.

[0236] Alternatively, in some embodiments, the first transparent conductive layer comprises a connecting portion. When the first conductive layer comprises a fan-out line, a first dummy fan-out line, and an etching stop portion, the connecting portion is electrically connected to the first protruding portion and the first end through different vias penetrating the gate insulating layer, respectively.

[0237] In some embodiments, as shown in FIGS. 6-8, the two ends of the second dummy fan-out line 4031 are electrically connected to different third dummy fan-out lines 4032, respectively. That is, the two ends of the second dummy fan-out line 4031 are electrically connected to the first end 40321.

[0238] The array substrate provided by the embodiments of the present disclosure has the following advantages: the two ends of the second dummy fan-out line in the extension direction thereof are electrically connected to the third dummy fan-out line, and since the third dummy fan-out line comprises a first end oppositely arranged relative to the first protruding portion, when static electricity accumulates on the second dummy fan-out line, a potential difference exists between the first end and the first protruding portion, thereby inducing the charges on the second dummy fan-out line to be released through the first end of the third dummy fan-out line electrically connected to the two ends of the second dummy fan-out line, improving the efficiency of static electricity release, further avoiding the fan-out line adjacent to the second dummy fan-out line from being struck by static electricity, avoiding affecting the signal transmission of the fan-out line, and improving the yield and working stability of the array substrate.

[0239] In some embodiments, as shown in FIGS. 6-8, the etching stop portion 403 comprises two third dummy fan-out lines 4032. That is, the second dummy fan-out line 4031 is electrically connected to the third dummy fan-out line 4032 at only the two ends in the extension direction thereof.

[0240] In some embodiments, as shown in FIGS. 6-8, the two first protrusions 4022 opposite to the first ends 40321 of the two third dummy fan-out lines 4032 are respectively located at different sub dummy fan-out lines 4021.

[0241] In some embodiments, when the etching blocking part includes two third dummy fan-out lines electrically connected to the two ends of the second dummy fan-out line respectively, the first protrusion opposite to the first end of the third dummy fan-out line is close to the middle part of the first dummy fan-out line.

[0242] Alternatively, in some embodiments, as shown in FIGS. 13-16, the etching blocking part 403 includes more than two first ends 40321, the etching blocking part 403 includes more than two third dummy fan-out lines 4032, and part of the third dummy fan-out lines 4032 are also electrically connected to the regions other than the two ends of the second dummy fan-out line 4031.

[0243] The array substrate provided by the embodiments of the present disclosure can induce the charges on the second dummy fan-out line to be released through the first ends of the third dummy fan-out lines electrically connected to the two ends of the second dummy fan-out line when the second dummy fan-out line has static electricity accumulation, because the third dummy fan-out line includes the first end opposite to the first protrusion. In addition to arranging the third dummy fan-out lines electrically connected to the two ends of the second dummy fan-out line in the extension direction of the second dummy fan-out line, the third dummy fan-out lines electrically connected to the regions other than the two ends of the second dummy fan-out line are also arranged, which is equivalent to increasing the positions of static electricity release, and further improves the efficiency of static electricity release. Local static electricity release can be realized, the local static electricity accumulation of the second dummy fan-out line is avoided, the fan-out lines adjacent to the second dummy fan-out line are further prevented from being electrostatically shocked, the signal transmission of the fan-out lines is avoided from being affected, and the yield and working stability of the array substrate can be improved.

[0244] In some embodiments, as shown in FIGS. 13-16, the etching blocking part 403 includes 2n third dummy fan-out lines 4032, and n is an integer greater than 1.

[0245] In some embodiments, as shown in FIGS. 13-16, the 2n third dummy fan-out lines 4032 included in the etching blocking part 403 are divided into n groups of dummy fan-out line groups 8 arranged in sequence.

[0246] In some embodiments, as shown in FIGS. 13-16, the dummy fan-out line group 8 and the second dummy fan-out line 4031 between the dummy fan-out line groups 8 are partially projected on the substrate 3 in a shape similar to a ring.

[0247] In some embodiments, as shown in FIGS. 13-16, two third dummy fan-out lines 4032 in the dummy fan-out line group 8 are symmetrically arranged.

[0248] In some embodiments, the n groups of dummy fan-out line groups are periodically arranged. Thus, the distribution of the third dummy fan-out lines is more uniform, and the distribution of the corresponding first ends and first protrusions is more uniform, which is more conducive to achieving local electrostatic discharge, avoiding local electrostatic accumulation of the second dummy fan-out lines, further avoiding electrostatic shock of the fan-out lines adjacent to the second dummy fan-out lines, avoiding affecting the signal transmission of the fan-out lines, and can improve the yield and working stability of the array substrate.

[0249] In some embodiments, as shown in FIGS. 13-16, the maximum distance between the two third dummy fan-out lines 4032 in the dummy fan-out line group 8 is a first distance h10, the distance between the first ends 40321 of the two third dummy fan-out lines 4032 in the dummy fan-out line group 8 is a second distance h11, and the minimum distance between the two third dummy fan-out lines 4032 adjacent to each other and located in different dummy fan-out line groups 8 is a third distance h12.

[0250] The first distance h10 of different dummy fan-out line groups 8 is equal, the second distance h11 is equal, and the third distance h12 of any two adjacent dummy fan-out line groups 8 is equal.

[0251] In some embodiments, as shown in FIGS. 6-8 and 13-16, the third dummy fan-out line 4032 further includes a first sub-section 40322, a second sub-section 40323, and a third sub-section 40324 connected in sequence; the first sub-section 40322 is electrically connected with the second dummy fan-out line 4031, and the third sub-section 40324 is electrically connected with the first end 40321.

[0252] The extension direction of the first sub-section 40322 and the third sub-section 40324 is crossed with the extension direction of the second dummy fan-out line 4031, and the extension direction of the second sub-section 40323 is parallel to the extension direction of the second dummy fan-out line 4031; the first sub-section 40322 and the third sub-section 40324 are located on one side of the second sub-section 40323 facing the first protrusion 4022.

[0253] In some embodiments, as shown in FIGS. 6-8 and 13-16, the first sub-section 40322, the second sub-section 40323, and the third sub-section 40324 can include a straight line section or an arc line section.

[0254] In some embodiments, as shown in FIGS. 13-16, the third sub-sections 40324 of the two third dummy fan-out lines 4032 in one dummy fan-out line group 8 are adjacent.

[0255] The first sub-segments 40322 of the two third dummy fan-out lines 4032 located at two adjacent dummy fan-out line groups 8 are adjacent.

[0256] Specifically, the distance between the first sub-segments 40322 of the two third dummy fan-out lines 4032 in one dummy fan-out line group 8 is a first distance h10, and the distance between the first sub-segments 40322 of the two third dummy fan-out lines 4032 in adjacent dummy fan-out line groups 8 is a third distance h12.

[0257] In some embodiments, as shown in FIGS. 13-16, part of the third dummy fan-out line 4032 passes through the break area C.

[0258] In some embodiments, as shown in FIGS. 17-20, at least part of the two adjacent third dummy fan-out lines 4032 share the first sub-segment 40322. Thus, the periodic arrangement of the dummy fan-out line group can be achieved while saving wiring space and cost.

[0259] In some embodiments, as shown in FIGS. 13-20, in each dummy fan-out line group 8, four sub-dummy fan-out lines 4021 are arranged between the two first sub-segments 40322. Thus, the number of dummy fan-out line groups can be as large as possible while reasonably utilizing the wiring space, further improving the effect of local electrostatic discharge, avoiding local electrostatic accumulation of the second dummy fan-out line, further avoiding the fan-out line adjacent to the second dummy fan-out line from being electrostatically shocked, avoiding affecting the signal transmission of the fan-out line, and improving the yield and working stability of the array substrate.

[0260] In some embodiments, as shown in FIGS. 6, 8, 13, 15, 17, 19, the line width of the second dummy fan-out line 4031 is equal in different areas, and the line width of the third dummy fan-out line 4032 in the area other than the first end 40321 is equal to the line width of the second dummy fan-out line 4031.

[0261] Alternatively, in some embodiments, as shown in FIGS. 7, 9, 14, 16, 18, 20, the second dummy fan-out line 4031 includes a first part 40311 and a second part 40312, and the line width of the third dummy fan-out line 4032 in the area other than the first end 40321 is equal to the line width of the second part 40312. Alternatively, the line width of the third dummy fan-out line 4032 in the area other than the first end 40321 can also be equal to the line width of the first part 40311.

[0262] In some embodiments, as shown in FIGS. 6-8 and 13-20, the lengths of the second sub-segments 40323 of the third dummy fan-out lines 4032 are equal.

[0263] It should be noted that only one etching blocking part 403 is included between the fan-out line 401 and the first dummy fan-out line 402 in Figs. 2-8 and 13-20. In actual implementation, as shown in Figs. 21 and 22, two etching blocking parts 403 can be included between the fan-out line 401 and the first dummy fan-out line 402. In order to distinguish the two etching blocking parts 403, the two etching blocking parts 403 are respectively referred to as a first etching blocking part 403-1 and a second etching blocking part 403-2. The first etching blocking part 403-1 is an etching blocking part 403 integrally connected with the fan-out line 401, and the second etching blocking part 403-2 is an etching blocking part 403 including a second dummy fan-out line 4031 located between the fan-out line 401 and the first dummy fan-out line 402. In the case of sufficient wiring space, the first etching blocking part 403-1 and the second etching blocking part 403-2 are arranged between the fan-out line 401 and the first dummy fan-out line 402, so as to further improve the protection effect of the fan-out line 401 and avoid the fan-out line 401 from being disconnected and affecting the yield of the array substrate. The specific arrangement mode of the first etching blocking part 403-1 and the second etching blocking part 403-2 is described in the foregoing embodiments, which will not be described here.

[0264] It should be noted that Figs. 4-9 and 13-22 are projection views of at least one of the partial regions of the K1 region, the K2 region and the K3 region in Fig. 2 or the projection views of at least one of the partial regions of the K1 region, the K2 region, the K3 region and the K4 region in Fig. 23. Figs. 4-9 and 13-22 only show the positional relationship of the fan-out line 401, the first dummy fan-out line 402 and the etching blocking part 403, and the extension direction of the fan-out line 401, the first dummy fan-out line 402 and the etching blocking part 403 does not necessarily represent the actual extension direction.

[0265] In actual implementation, the conductive layer can be any conductive layer in which the fan-out line and the dummy fan-out line with the disconnection region adjacent to the fan-out line need to be arranged. For any conductive layer included in the array substrate, when the fan-out line and the dummy fan-out line with the disconnection region adjacent to the fan-out line need to be arranged in the fan-out region, the etching blocking part can be arranged between the fan-out line and the dummy fan-out line with the disconnection region. That is, when the array substrate includes two conductive layers, the first conductive layer includes the fan-out line and the first dummy fan-out line with the disconnection region on one side of the fan-out line, and the first conductive layer includes the etching blocking part located between the fan-out line and the first dummy fan-out line; and / or, the second conductive layer includes the fan-out line and the first dummy fan-out line with the disconnection region on one side of the fan-out line, and the second conductive layer includes the etching blocking part located between the fan-out line and the first dummy fan-out line.

[0266] In some embodiments, as shown in FIGS. 24-27, the first conductive layer 4-1 and the second conductive layer 4-2 each include a plurality of fan-out lines 401; the fan-out lines on the first conductive layer 4-1 are first fan-out lines 4011, and the fan-out lines on the second conductive layer 4-2 are second fan-out lines 4012.

[0267] In some embodiments, as shown in FIGS. 24 and 25, the second fan-out lines 4012 overlap the first fan-out lines 4011 in the projection of the substrate 3.

[0268] For example, in at least some regions, the bisector of the second fan-out lines in the direction parallel to the plane of the substrate overlaps the bisector of the first fan-out lines in the projection of the substrate.

[0269] In some embodiments, as shown in FIGS. 24 and 25, two adjacent second fan-out lines 4012 are separated by at least one first fan-out line 4011 in the projection of the substrate 3 in at least some regions.

[0270] Alternatively, in some embodiments, as shown in FIGS. 26 and 27, the second fan-out lines 4012 overlap the region between two adjacent first fan-out lines 4011 in the projection of the substrate 3.

[0271] For example, in at least some regions, the bisector of the second fan-out lines in the direction parallel to the plane of the substrate falls into the region between two adjacent first fan-out lines in the projection of the substrate.

[0272] In some embodiments, the scan lines, the data lines, and the first fan-out lines are electrically connected, and the touch electrodes are electrically connected to the second fan-out lines.

[0273] In some embodiments, as shown in FIGS. 24-27, the first conductive layer 4-1 further includes an etching blocking portion 403 on one side of the first fan-out lines 4011 and a first dummy fan-out line 402.

[0274] In some embodiments, the line width of the first fan-out lines is smaller than the line width of the second fan-out lines.

[0275] In some embodiments, the line width of the first fan-out lines is less than 3 microns. Further, the line width of the first fan-out lines is less than 2 microns.

[0276] It should be noted that when the fan-out line width is less than 3 microns or even 2 microns, if there is a region without a pattern of the conductive layer on one side of the fan-out line, the fan-out line is more likely to be etched through and broken. Therefore, when the line width of the first fan-out line is less than 3 microns or even 2 microns, the array substrate provided by the embodiments of the present disclosure is provided with the first dummy fan-out line and the etching blocking part to protect the first fan-out line, avoid the first fan-out line from being etched through, and improve the yield of the array substrate.

[0277] In some embodiments, the line width of the second fan-out line is greater than or equal to 4 microns. In some embodiments, the second conductive layer does not include the etching blocking part and the first dummy fan-out line.

[0278] It should be noted that when the line width of the fan-out line is greater than or equal to 4 microns, if there is a region without a pattern of the conductive layer on one side of the fan-out line, the fan-out line is not easy to be etched through and broken. Therefore, when the line width of the second fan-out line is greater than or equal to 4 microns, the second conductive layer can not be provided with the etching blocking part and the first dummy fan-out line with the breakage area, which can save the wiring space while ensuring the yield of the array substrate.

[0279] In some embodiments, when the line width of the second fan-out line is less than 3 microns or even less than 2 microns, the first dummy fan-out line can also be provided on the second conductive layer. Further, the etching blocking part can also be provided on the side of the second fan-out line towards the first dummy fan-out line. Thus, the second fan-out line can be protected to avoid being etched through, and the yield of the array substrate can be improved.

[0280] In some embodiments, as shown in FIGS. 28-43, the second conductive layer 4-2 further includes: a first dummy fan-out line 402 located on one side of the second fan-out line 4012.

[0281] The array substrate provided by the embodiments of the present disclosure can avoid a large-area blank area on one side of the second fan-out line, and alleviate the problem that the fan-out line close to the blank area is etched through and affects signal transmission due to a high concentration of etching liquid, because the first dummy fan-out line includes the sub-dummy fan-out line and the breakage area.

[0282] In some embodiments, as shown in FIGS. 28, 29, 30-36, the first dummy fan-out line 402 of the second conductive layer 4-2 overlaps the first dummy fan-out line 402 of the first conductive layer 4-1 in the orthographic projection of the substrate 3.

[0283] It should be noted that in FIGS. 30, 32, 33, 35, the first dummy fan-out line 402 of the second conductive layer 4-2 is represented by a dashed line. For example, FIG. 31 is a cross-sectional view along PP' in FIG. 30, FIG. 34 is a cross-sectional view along MM' in FIG. 32 or FIG. 33, and FIG. 36 is a cross-sectional view along LL' in FIG. 5.

[0284] In some embodiments, as shown in FIGS. 28-36, the sub-fanout line 4021 of the second conductive layer 4-2 is overlapped by the sub-fanout line 4021 of the first conductive layer 4-1 in the orthographic projection of the substrate 3.

[0285] In some embodiments, as shown in FIGS. 29, 30, 31, the second conductive layer 4-2 further comprises a first protruding portion 4022 located on the side of the sub-fanout line 4021 away from the fanout line 401;

[0286] The orthographic projection of the first protruding portion 4022 of the second conductive layer 4-2 on the substrate 3 is overlapped by the orthographic projection of the first protruding portion 4022 of the first conductive layer 4-1 on the substrate 3.

[0287] In some embodiments, as shown in FIG. 29, the orthographic projection of the first protruding portion 4022 of the second conductive layer 4-2 on the substrate 3 is overlapped by the orthographic projection of the first protruding portion 4022 of the first conductive layer 4-1 on the substrate 3.

[0288] Alternatively, in some embodiments, as shown in FIGS. 30, 31, the orthographic projection of the first protruding portion 4022 of the second conductive layer 4-2 on the substrate 3 falls within the orthographic projection of the first protruding portion 4022 of the first conductive layer 4-1 on the substrate 3.

[0289] Alternatively, in some embodiments, as shown in FIGS. 32, 33, 34, 35, 36, the second conductive layer 4-2 further comprises a first protruding portion 4022 located on the side of the sub-fanout line 4021 away from the fanout line 401;

[0290] The orthographic projection of the first protruding portion 4022 of the second conductive layer 4-2 on the substrate 3 is not overlapped by the orthographic projection of the first protruding portion 4022 of the first conductive layer 4-1 on the substrate 3.

[0291] When the orthographic projection of the first protruding portion 4022 of the second conductive layer 4-2 on the substrate 3 is not overlapped by the orthographic projection of the first protruding portion 4022 of the first conductive layer 4-1 on the substrate 3, in some embodiments, as shown in FIGS. 32, 35, the orthographic projection of the first protruding portion 4022 of the second conductive layer 4-2 on the substrate 3 and the orthographic projection of the first protruding portion 4022 of the first conductive layer 4-1 on the substrate 3 are located on the same side of the orthographic projection of a sub-fanout line 4021 on the substrate 3; or, as shown in FIG. 33, the orthographic projection of the first protruding portion 4022 of the second conductive layer 4-2 on the substrate 3 and the orthographic projection of the first protruding portion 4022 of the first conductive layer 4-1 on the substrate 3 correspond to the orthographic projection of different sub-fanout lines 4021 on the substrate 3 in the extension direction of the first fanout line 402, respectively.

[0292] Alternatively, in some embodiments, as shown in FIGS. 37-43, the sub- dummy fanout lines 4021 of the second conductive layer 4-2 do not overlap with the sub-dummy fanout lines 4021 of the first conductive layer 4-1 in the projection of the substrate 3.

[0293] It should be noted that in FIGS. 38, 40, 41, and 43, the first dummy fanout lines 402 of the second conductive layer 4-2 are represented by dashed lines, and in order to clearly show different sub-dummy fanout lines 4021, two adjacent sub-dummy fanout lines 4021 in one first dummy fanout line 402 are represented by different dashed line patterns, and the broken areas of the dashed line segments are not the broken areas of the first dummy fanout lines. For example, FIG. 39 is a cross-sectional view along HH’ in FIG. 38, and FIG. 42 is a cross-sectional view along JJ’ in FIG. 41.

[0294] In some embodiments, as shown in FIGS. 28-34 and 37-43, the second conductive layer 4-2 further comprises an etching blocking portion 403.

[0295] In some embodiments, as shown in FIGS. 28-34, the etching blocking portion 403 of the second conductive layer 4-2 overlaps with the etching blocking portion 403 of the first conductive layer 4-1 in the projection of the substrate 3.

[0296] In some embodiments, as shown in FIGS. 29-34, the etching blocking portion 403 comprises second dummy fanout lines 4031;

[0297] The second dummy fanout lines 4031 of the second conductive layer 4-2 overlap with the second dummy fanout lines 4031 of the first conductive layer 4-1 in the projection of the substrate 3. For example, the second dummy fanout lines 4031 of the second conductive layer 4-2 overlap with the second dummy fanout lines 4031 of the first conductive layer 4-1 in the projection of the substrate 3.

[0298] In some embodiments, as shown in FIGS. 29, 30, and 31, the third dummy fanout lines 4032 of the second conductive layer 4-2 overlap with the third dummy fanout lines 4032 of the first conductive layer 4-1 in the projection of the substrate 3.

[0299] In some embodiments, as shown in FIG. 29, the third dummy fanout lines 4032 of the second conductive layer 4-2 overlap with the third dummy fanout lines 4032 of the first conductive layer 4-1 in the projection of the substrate 3.

[0300] In some embodiments, the third dummy fan-out line of the second conductive layer has a projection on the substrate that overlaps with a projection on the substrate of the third dummy fan-out line of the first conductive layer, and the first protrusion and the first end each include a sharp corner, and the first protrusion of the first and second conductive layers has a projection on the substrate that overlaps with a projection on the substrate of the first protrusion of the first conductive layer. For example, the first and second conductive layers can be any of the overlaps in FIGS. 6, 7, 13, 14, 17, and 18.

[0301] Alternatively, in some embodiments, as shown in FIG. 30, the third dummy fan-out line 4032 of the second conductive layer 4-2 has a projection on the substrate 3 that overlaps with a projection on the substrate 3 of the third dummy fan-out line 4032 of the first conductive layer 4-1. For example, outside the first end 40321, the third dummy fan-out line 4032 of the second conductive layer 4-2 has a projection on the substrate 3 that overlaps with a projection on the substrate 3 of the third dummy fan-out line 4032 of the first conductive layer 4-1.

[0302] Alternatively, in some embodiments, as shown in FIGS. 32-34, the third dummy fan-out line 4032 of the second conductive layer 4-2 has a projection on the substrate 3 that overlaps with a projection on the substrate 3 of the third dummy fan-out line 4032 of the first conductive layer 4-1 in some areas;

[0303] The third dummy fan-out line 4032 of the second conductive layer 4-2 has a projection on the substrate 3 that does not overlap with a projection on the substrate 3 of the third dummy fan-out line 4032 of the first conductive layer 4-1 in the remaining areas.

[0304] In some embodiments, as shown in FIGS. 32-33, the first sub-section 40322 of the second conductive layer 4-2 has a projection on the substrate 3 that overlaps with a projection on the substrate 3 of the first sub-section 40322 of the first conductive layer 4-1. For example, the first sub-section 40322 of the second conductive layer 4-2 has a projection on the substrate 3 that overlaps with a projection on the substrate 3 of the first sub-section 40322 of the first conductive layer 4-1.

[0305] In some embodiments, as shown in FIGS. 32-33, the second sub-section 40323 of the second conductive layer 4-2 has a projection on the substrate 3 that overlaps with a projection on the substrate 3 of the second sub-section 40323 of the first conductive layer 4-1 in some areas;

[0306] The second sub-section 40323 of the second conductive layer 4-2 has a projection on the substrate 3 that does not overlap with a projection on the substrate 3 of the second sub-section 40323 of the first conductive layer 4-1 in the remaining areas.

[0307] In some embodiments, as shown in FIGS. 32-33, the third sub-section 40324 of the second conductive layer 4-2 and the first end 40321 are not overlapped with the third sub-section 40324 of the first conductive layer 4-1 and the first end 40321 in the projection of the substrate 3. Correspondingly, the remaining area of the first protruding part 4022 of the second conductive layer 4-2 and the first protruding part 4022 of the first conductive layer 4-1 in the projection of the substrate 3 are not overlapped.

[0308] Alternatively, in some embodiments, as shown in FIGS. 38-43, the etching blocking part 403 includes a second dummy fan-out line 4031, and the second dummy fan-out line 4031 of the second conductive layer 4-2 and the second dummy fan-out line 4031 of the first conductive layer 4-1 are not overlapped in the projection of the substrate 3.

[0309] In some embodiments, as shown in FIGS. 38-43, the etching blocking part 403 further includes a third dummy fan-out line 4032.

[0310] In some embodiments, as shown in FIGS. 40, 43, the third dummy fan-out line 4032 of the second conductive layer 4-2 and the third dummy fan-out line 4032 of the first conductive layer 4-1 are not overlapped in the projection of the substrate 3.

[0311] In some embodiments, as shown in FIGS. 40, 43, the first protruding part 4022 of the second conductive layer 4-2 and the first protruding part 4022 of the first conductive layer 4-1 are not overlapped in the projection of the substrate 3.

[0312] In some embodiments, as shown in FIGS. 40, 43, the third dummy fan-out line 4032 of the second conductive layer 4-2 is located inside the third dummy fan-out line 4032 of the first conductive layer 4-1 in the projection of the substrate 3.

[0313] Alternatively, in some embodiments, as shown in FIGS. 38, 41, the third dummy fan-out line 4032 of the second conductive layer 4-2 and the third dummy fan-out line 4032 of the first conductive layer 4-1 are only partially overlapped in the projection of the substrate 3.

[0314] In some embodiments, as shown in FIGS. 38, 41, the second sub-section 40323 of the second conductive layer 4-2 and the second sub-section 40323 of the first conductive layer 4-1 are not overlapped in the projection of the substrate 3.

[0315] The first sub-section 40322 and the third sub-section 40324 of the second conductive layer 4-2 have an overlapping area with the first sub-section 40322 and the third sub-section 40324 of the first conductive layer 4-1 in the orthographic projection of the substrate 3.

[0316] In some embodiments, as shown in FIG. 38, FIG. 41, the second sub-section 40323 of the second conductive layer 4-2 is located on the side away from the fan-out line 4 in the orthographic projection of the substrate 3 relative to the second sub-section 40323 of the first conductive layer 4-1 in the orthographic projection of the substrate 3.

[0317] Alternatively, in some embodiments, the second sub-section of the second conductive layer can also be located on the side toward the fan-out line in the orthographic projection of the substrate relative to the second sub-section of the first conductive layer in the orthographic projection of the substrate.

[0318] In some embodiments, as shown in FIG. 38, FIG. 41, the first end 40321 of the second conductive layer 4-2 has an overlapping area with the third sub-section 40324 of the first conductive layer 4-1 in the orthographic projection of the substrate 3.

[0319] The first protruding portion 4022 of the second conductive layer 4-2 and the first protruding portion 4022 of the first conductive layer 4-1 do not overlap in the orthographic projection of the substrate 3.

[0320] In some embodiments, as shown in FIG. 30-FIG. 36, FIG. 41-FIG. 43, the connection portion 10 is electrically connected to the first conductive layer 4-1 through the first via 1101, and the connection portion 10 is electrically connected to the second conductive layer 4-2 through the second via 1102, and the first via 1101 and the second via 1102 do not overlap in the orthographic projection of the substrate 3.

[0321] In some embodiments, as shown in FIG. 30-FIG. 36, FIG. 41-FIG. 43, the second transparent conductive layer 7 includes the connection portion 10.

[0322] The first via 1101 penetrates the planarization layer 1602, the passivation layer 1601, and the gate insulating layer 14, and the second via 1102 penetrates the planarization layer 1602 and the passivation layer 1601.

[0323] In some embodiments, as shown in FIG. 30-FIG. 34, FIG. 41-FIG. 43, the second conductive layer 4-2 and the first conductive layer 4-1 each include the first protruding portion 4022 and the first end 40321.

[0324] The connection portions 10 are respectively electrically connected to the first protruding portions 4022 and the first ends 40321 of the first conductive layer 4-1 through different first vias 1101, and the connection portions 10 are respectively electrically connected to the first protruding portions 4022 and the first ends 40321 of the second conductive layer 4-2 through different second vias 1102.

[0325] In some embodiments, as shown in FIGS. 35 and 36, the first conductive layer 4-1 includes the etching blocking portion 403, and the second conductive layer 4-2 does not include the etching blocking portion 403; but the first protruding portion 4022 can be arranged on the side of the dotted fan-out line 4021 of the second conductive layer 4-2, so that the first protruding portion 4022 is electrically connected to the connection portion 10 to realize electrostatic discharge.

[0326] Specifically, the connection portions 10 are respectively electrically connected to the first protruding portions 4022 and the first ends 40321 of the first conductive layer 4-1 through different first vias 1101, and the connection portions 10 are respectively electrically connected to the first protruding portions 4022 of the second conductive layer 4-2 through different second vias 1102.

[0327] In some embodiments, as shown in FIGS. 30-36 and 41-43, when the second conductive layer 4-2 and the first conductive layer 4-1 are both electrically connected to the connection portion 10,

[0328] The connection portion 10 electrically connected to the second conductive layer 4-2 and the connection portion 10 electrically connected to the first conductive layer 4-1 are integrally connected.

[0329] Alternatively, when the first conductive layer and the second conductive layer both realize electrostatic discharge through the etching blocking portion and the connection portion, the connection portion electrically connected to the second conductive layer and the connection portion electrically connected to the first conductive layer can be disconnected from each other.

[0330] It should be noted that only two third dotted fan-out lines 4032 are shown in FIGS. 30, 32, 33, 35, 38, 40, 41 and 43. When the etching blocking portion 403 includes a plurality of virtual fan-out line groups, the patterns of the two conductive layers can be, for example, the patterns of FIGS. 30, 32, 33, 35, 38, 40, 41 and 43 translated along the extension direction of the fan-out line. The specific arrangement of the fan-out line groups of each conductive layer can be referred to the foregoing embodiments, which will not be described herein.

[0331] In some embodiments, the array substrate further includes a touch electrode, for example, a common electrode multiplexed as a touch electrode; and the second fan-out line is further electrically connected to the touch electrode. That is, in the array substrate provided by the embodiments of the present disclosure, the second fan-out line is used to transmit a touch signal.

[0332] In a specific implementation, the binding pins electrically connected with the fan-out wires include at least one layer of binding electrodes, and the binding electrodes located at the uppermost layer and partially exposed are bound with the driving chip.

[0333] In some embodiments, as shown in FIG. 44, the second conductive layer 4-2 further includes a plurality of first binding electrodes 406, and the second fan-out wire 4012 is electrically connected with the first binding electrode 406 in a one-to-one correspondence.

[0334] In the related art, as shown in FIG. 45, the first binding electrode 406 is electrically connected with the driving chip 24 through the conductive adhesive 23. However, for the product with this structure, there are vertical line and square malfunctions when performing reliability evaluation. The malfunctions are concentrated in the binding area and occur in the area where the organic insulating layer, i.e., the planarization layer, is removed. After removing the organic layer to troubleshoot the problem, it is found that the second conductive layer in this area has the problems of black spots and disconnection, which affect signal transmission and lead to vertical line and square malfunctions. In the binding area and the nearby fan-out area, the first transparent conductive layer above the second conductive layer needs to be removed through an etching process. The reason why the second conductive layer has disconnection is that the second conductive layer is damaged in the process of removing the first transparent conductive layer above the second conductive layer. Under the condition of high temperature and high humidity, the second conductive layer in the area not covered by the organic insulating layer is prone to corrosion.

[0335] In some embodiments, as shown in FIG. 44, the array substrate further includes a plurality of first protection structures 601, and the first protection structure 601 covers the second fan-out wire 4012 and the first binding electrode 406.

[0336] The array substrate provided by the embodiments of the present disclosure sets the first protection structure on one side of the second fan-out wire and the first binding electrode, and the first protection structure covers the second fan-out wire and the first binding electrode, thereby avoiding damage to the second conductive layer. In turn, the second conductive layer that is prone to corrosion under the condition of high temperature and high humidity can be avoided from disconnection, and vertical line and square display malfunctions caused by abnormal signal transmission can be avoided, which can improve the yield of the array substrate.

[0337] In some embodiments, as shown in FIG. 44, the first transparent conductive layer 6 includes a plurality of first protection structures 601.

[0338] That is, the array substrate provided by the embodiments of the present disclosure retains the first transparent conductive layer of the second fan-out wire and the first binding electrode as the first protection structure. Only the pattern of the first transparent conductive layer photomask needs to be changed without adding a photomasking step and a mask. While avoiding damage to the second conductive layer caused by the removal of the first transparent conductive layer and avoiding vertical line and square display malfunctions caused by abnormal signal transmission, costs can also be saved.

[0339] In actual implementation, the product provided by the embodiment of the present disclosure is tested, and no vertical line and square display defects occur. After removing the second fan-out line and the film layer above the first bonding electrode, no problem of black point and broken line of the second fan-out line and the first bonding electrode is found. The setting of the first protection structure of the present disclosure can effectively avoid the corrosion and broken line of the second conductive layer.

[0340] In some embodiments, as shown in FIG. 44, the passivation layer 1601 includes a third via 16011 located in the bonding area NA-1 and exposing the first protection structure 601. In the bonding area NA-1, the planarization layer 1602 has a removal area;

[0341] The driving chip 24 is electrically connected with the first protection structure 601 through the conductive adhesive 23 through the third via 16011. That is, the exposed part of the first protection structure 601 serves as a part of the bonding pin (not shown) bonded with the driving chip 24;

[0342] The second transparent conductive layer 7 includes a second bonding electrode 702, which extends to the bonding area NA-1, and the second bonding electrode 702 extends to the removal area of the planarization layer 1602, that is, a part of the second bonding electrode 702 is located above the passivation layer 1601;

[0343] The conductive adhesive 23 also covers a part of the second bonding electrode 702, so that the driving chip 24 is electrically connected with the second bonding electrode 702 through the conductive adhesive 23.

[0344] The array substrate provided by the embodiment of the present disclosure retains the first transparent conductive layer of the second fan-out line and the first bonding electrode as the first protection structure. In this way, in the patterning process of the first transparent conductive layer, the second fan-out line and the first bonding electrode covered by the first protection structure will not be damaged. Even if the organic insulating layer, i.e., the planarization layer, is removed in the bonding area, under the condition of high temperature and high humidity, the area not covered by the organic insulating layer, i.e., the planarization layer, will not be corroded. The second fan-out line and the first bonding electrode covered by the first protection structure will not be damaged. The process of removing the first transparent conductive layer avoids the corrosion of the second conductive layer, avoids the vertical line and square display defects caused by abnormal signal transmission, and improves the yield of the array substrate.

[0345] In some embodiments, as shown in FIG. 44, when the driving chip 24 is bonded with the array substrate through the conductive adhesive 23, a protective adhesive 25 covering at least part of the second bonding electrode 702 and part of the conductive adhesive 23 is also needed, and the protective adhesive 25 does not cover the driving chip 24.

[0346] Based on the same inventive concept, the present disclosure also provides a display panel, as shown in FIG. 46, which includes:

[0347] The array substrate 1901 provided by the embodiments of the present disclosure;

[0348] The opposite substrate 1902 is arranged opposite to the array substrate 1901;

[0349] The liquid crystal layer 1903 is located between the array substrate 1901 and the opposite substrate 1902.

[0350] In some embodiments, the opposite substrate also includes a substrate substrate, for the convenience of distinction, the substrate substrate of the opposite substrate is referred to as a second substrate substrate; the opposite substrate further includes: a black matrix and a plurality of color resist located on the side of the second substrate substrate facing the liquid crystal layer; the black matrix includes a plurality of opening regions, and the color resist is located at least in the opening region; the plurality of color resist includes, for example: a plurality of red color resist, a plurality of blue color resist and a plurality of green color resist.

[0351] In some embodiments, the display panel further includes: a first alignment layer located between the array substrate and the liquid crystal layer, and a second alignment layer located between the opposite substrate and the liquid crystal layer.

[0352] Based on the same inventive concept, the embodiments of the present disclosure also provide a display device, as shown in FIG. 47, the display device includes: the display panel 19 provided by the embodiments of the present disclosure.

[0353] In some embodiments, as shown in FIG. 47, the display device can further include: a backlight module 20 located on the light side of the display panel 19.

[0354] In some embodiments, the backlight module can be a direct type backlight module, or the backlight module can also be a side type backlight module.

[0355] In a specific implementation, the side-in backlight module can include a light bar, a reflector sheet, a light guide plate, a diffusion sheet, a prism group, etc., which are arranged in a stack, and the light bar is located at one side of the light guide plate in the thickness direction. The direct backlight module can include a matrix light source, a reflector sheet, a diffusion plate, and a brightness enhancement film, etc., which are arranged in a stack on the light exit side of the matrix light source, and the reflector sheet includes openings arranged opposite to the positions of the lamp beads in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.). The micro light-emitting diode of sub-millimeter level or even micron level is the same as the organic light-emitting diode (OLED) and belongs to a self-luminous device. Like the organic light-emitting diode, it has a series of advantages such as high brightness, ultra-low delay, and ultra-large viewing angle. Moreover, because the inorganic light-emitting diode emits light based on a metal semiconductor with more stable properties and lower resistance, it has the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life compared with the organic light-emitting diode based on organic matter. When the micro light-emitting diode is used as a backlight source, it can achieve more precise dynamic backlight effect, effectively improve the screen brightness and contrast, and solve the glare phenomenon caused by the traditional dynamic backlight between the light and dark areas of the screen, thereby optimizing the visual experience.

[0356] In some embodiments, the light-in side of the display panel is the side of the array substrate, i.e., the backlight module is arranged opposite to the array substrate, and the opposite substrate is located on the side of the array substrate away from the backlight module.

[0357] The display device provided by the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by those skilled in the art, and are not described herein in detail, nor should they be considered as a limitation on the present disclosure. The implementation of the display device can refer to the embodiments of the display panel and the array substrate described above, and repeated descriptions are omitted.

[0358] In summary, the array substrate, the display panel, and the display device provided by the embodiments of the present disclosure have the etching blocking part connected to the fan-out line in the region opposite to the fracture zone, which is equivalent to widening the fan-out line in the region opposite to the fracture zone and on the side of the fan-out line facing the fracture zone. The etching blocking part can effectively prevent the etching liquid enriched in the fracture zone from etching the fan-out line, reduce the concentration of the etching liquid, achieve the buffering protection effect, avoid the risk of line breakage of the fan-out line, and improve the yield of the array substrate.

[0359] While the preferred embodiments of the application have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the present disclosure. Therefore, the appended claims are intended to encompass all such variations and modifications as falling within the scope of the present application. What is claimed is:

[0360] It is apparent that many modifications and variations of this disclosure can be effected although only a few have been chosen for illustration here. No portion thereof is intended to be dedicated to the public regardless of whether these modifications and variations fall within the scope of the application. It is intended that all per cent amounts, parts, and percentages are based on weight unless otherwise indicated. It is intended that all measurements, values, ratings, and other specifications are to be understood as modified in all instances by the term "about" unless otherwise indicated.

Claims

1. An array substrate, wherein, The array substrate comprises: a substrate, comprising a first area and a fan-out area located on one side of the first area in a first direction; at least one conductive layer located on one side of the substrate; in the fan-out area, at least one of the conductive layers comprises a plurality of fan-out lines, a first dummy fan-out line located on one side of the fan-out lines, and at least one etching stopper; the first dummy fan-out line comprises a plurality of sub-dummy fan-out lines arranged in an extending direction thereof, and a break area located between the sub-dummy fan-out lines; the etching stopper is located on one side of the fan-out lines facing the first dummy fan-out line and is arranged opposite to the break area.

2. The array substrate according to claim 1, wherein, The etching stopper is connected to the fan-out line in the region arranged opposite to the break area.

3. The array substrate according to claim 2, wherein, In the extending direction of the fan-out line, the length of the etching stopper is greater than the length of the break area.

4. The array substrate according to claim 2 or 3, wherein, In a direction perpendicular to the extending direction of the fan-out line, the width of the etching stopper is greater than or equal to 0.75 microns.

5. The array substrate of claim 1, wherein, The etching stopper comprises a second dummy fan-out line continuously extending between the first dummy fan-out line and the fan-out line.

6. The array substrate of claim 5, wherein, The line width of the second dummy fan-out line is the same in different regions, and the line width of the first dummy fan-out line is smaller than the line width of the second dummy fan-out line.

7. The array substrate according to claim 5, wherein, The second dummy fan-out line comprises a first part and a second part alternately connected; the first part is arranged opposite to the break area The line width of the first part is greater than the line width of the second part, and the line width of the first part is greater than the line width of the first dummy fan-out line.

8. The array substrate according to any one of claims 5 to 7, wherein, The difference between the maximum line width of the second dummy fan-out line and the line width of the first dummy fan-out line is greater than or equal to 0.75 microns.

9. The array substrate according to any one of claims 5 to 8, wherein, The first dummy fan-out line farthest from the second dummy fan-out line further comprises: a first protruding part located on one side of the sub-dummy fan-out line away from the second dummy fan-out line; The etching stopper further comprises: at least one third dummy fan-out line; one end of the third dummy fan-out line is electrically connected to the second dummy fan-out line, and the other end of the third dummy fan-out line comprises a first end located on one side of the first protruding part away from the second dummy fan-out line, and the first end is arranged opposite to the first protruding part, and the distance between the first end and the first protruding part is greater than 0.

10. The array substrate of claim 9, wherein, The two ends of the second dummy fan-out line are respectively electrically connected to different third dummy fan-out lines.

11. The array substrate of claim 10, wherein, The etching stopper comprises 2n third dummy fan-out lines, and n is an integer greater than 1; Part of the third dummy fan-out lines are also electrically connected to regions other than the two ends of the second dummy fan-out line.

12. The array substrate according to claim 10 or 11, wherein, The third dummy fan-out line further comprises a first sub-section, a second sub-section, and a third sub-section electrically connected in sequence; the first sub-section is electrically connected to the second dummy fan-out line, and the third sub-section is electrically connected to the first end; The extending direction of the first sub-section and the third sub-section is perpendicular to the extending direction of the second dummy fan-out line, and the extending direction of the second sub-section is parallel to the extending direction of the second dummy fan-out line; the first sub-section and the third sub-section are located on one side of the second sub-section facing the first protruding part.

13. The array substrate of claim 9, wherein, The 2n third dummy fan-out lines included in the etching blocking part are divided into n groups of dummy fan-out line groups arranged in sequence; The third sub-segments of two third dummy fan-out lines in one of the dummy fan-out line groups are adjacent; The first sub-segments of the two third dummy fan-out lines respectively located in two adjacent dummy fan-out line groups are adjacent. The first sub-segments of the two third dummy fan-out lines respectively located in two adjacent dummy fan-out line groups are adjacent.

14. The array substrate of claim 13, wherein, At least two adjacent third dummy fan-out lines share the first sub-segment.

15. The array substrate according to any one of claims 9 to 14, wherein, The first protruding part and the first end have sharp corners in the orthographic projection of the substrate, and the sharp corner of the first protruding part is opposite to the sharp corner of the first end.

16. The array substrate of claim 15, wherein, The first protruding part and the first end have a triangular shape in the orthographic projection of the substrate.

17. The array substrate according to any one of claims 9 to 14, wherein, The array substrate further comprises: A connecting part located on the side of the conductive layer away from the substrate; the connecting part is electrically connected with the first protruding part and the first end.

18. The array substrate of claim 17, wherein, The array substrate further comprises: At least one transparent conductive layer located on the side of the conductive layer away from the substrate; at least one transparent conductive layer includes the connecting part.

19. The array substrate according to any one of claims 1 to 18, wherein, At least one conductive layer includes a first conductive layer and a second conductive layer located on the side of the first conductive layer away from the substrate; The first conductive layer and the second conductive layer each include a plurality of fan-out lines; the fan-out lines located in the first conductive layer are first fan-out lines, and the fan-out lines located in the second conductive layer are second fan-out lines; The first conductive layer further includes the etching blocking part and the first dummy fan-out line located on the side of the first fan-out line.

20. The array substrate of claim 19, wherein, The orthographic projection of the second fan-out line on the substrate overlaps with the orthographic projection of the first fan-out line on the substrate. Alternatively, the orthographic projection of the second fan-out line on the substrate overlaps with the region between the orthographic projections of two adjacent first fan-out lines on the substrate.

21. The array substrate according to claim 19 or 20, wherein, The second conductive layer does not include the etching blocking part and the first dummy fan-out line.

22. The array substrate of claim 19 or 20, wherein, The second conductive layer further includes the first dummy fan-out line located on the side of the second fan-out line.

23. The array substrate of claim 22, wherein, The orthographic projection of the first dummy fan-out line of the second conductive layer on the substrate overlaps with the orthographic projection of the first dummy fan-out line of the first conductive layer on the substrate. Alternatively, the orthographic projection of the first dummy fan-out line of the second conductive layer on the substrate does not overlap with the orthographic projection of the first dummy fan-out line of the first conductive layer on the substrate.

24. The array substrate of claim 22 or 23, wherein, The second conductive layer further includes the etching blocking part. The orthographic projection of the etching blocking part of the second conductive layer on the substrate overlaps with the orthographic projection of the etching blocking part of the first conductive layer on the substrate.

25. The array substrate of claim 22 or 23, wherein, The second conductive layer further includes the etching blocking part. The etching blocking part includes a second dummy fan-out line, and the orthographic projection of the second dummy fan-out line of the second conductive layer on the substrate does not overlap with the orthographic projection of the second dummy fan-out line of the first conductive layer on the substrate.

26. The array substrate of claim 25, wherein, The etching blocking part further includes a third dummy fan-out line. The third dummy fan-out line of the second conductive layer does not overlap with the third dummy fan-out line of the first conductive layer in the orthographic projection of the substrate. Alternatively, the third dummy fan-out line of the second conductive layer only partially overlaps with the third dummy fan-out line of the first conductive layer in the orthographic projection of the substrate.

27. The array substrate according to any one of claims 22 to 26, wherein, The array substrate further comprises a connecting portion; The connecting portion is electrically connected with the first conductive layer through a first via hole, and is electrically connected with the second conductive layer through a second via hole, and the orthographic projection of the first via hole does not overlap with the orthographic projection of the second via hole in the substrate.

28. The array substrate according to any one of claims 17 to 18, 27, wherein, The at least one conductive layer comprises a first conductive layer and a second conductive layer; the array substrate further comprises a plurality of thin film transistors in the first area; the first conductive layer further comprises a gate of the thin film transistor, and the second conductive layer further comprises a source and a drain of the thin film transistor. The at least one transparent conductive layer comprises: A first transparent conductive layer located on a side of the second conductive layer away from the substrate; A second transparent conductive layer located on a side of the first transparent conductive layer away from the substrate; the second transparent conductive layer comprises the connecting portion.

29. The array substrate according to any one of claims 1 to 28, wherein, The array substrate further comprises a second conductive layer and a first transparent conductive layer; The second conductive layer comprises a plurality of second fan-out lines and a plurality of first binding electrodes, and the second fan-out lines are electrically connected with the first binding electrodes one by one; The first transparent conductive layer further comprises a plurality of first protection structures; the first protection structures correspond to the second fan-out lines and the first binding electrodes, and the first protection structures cover the second fan-out lines and the first binding electrodes.

30. A display panel, wherein, The display panel comprises: The array substrate according to any one of claims 1-29; A counter substrate arranged opposite to the array substrate; A liquid crystal layer located between the array substrate and the counter substrate.

31. A display device, wherein, The display device comprises the display panel according to claim 30.

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