Brain-like computing compilation method and apparatus for software-hardware decoupling, and compilation framework

Abstract

The present disclosure relates to the technical field of brain-like computing compilation, and in particular to a brain-like computing compilation method and apparatus for software-hardware decoupling, and a compilation framework. The method comprises: converting a brain-like computing application to be compiled into a first intermediate representation, the first intermediate representation being used for being identified by the compilation framework; converting the first intermediate representation into a second intermediate representation, a level of abstraction of the second intermediate representation being lower than that of the first intermediate representation; and converting the second intermediate representation into a low-level hardware representation, the low-level hardware representation being used for generating a parameter file running on target hardware. In the method provided in embodiments of the present disclosure, on the basis of the design idea of software-hardware decoupling, a multi-level intermediate representation is used to hierarchically descend a brain-like computing application into an low-level hardware representation, thereby achieving efficient support for different types of applications.

Description

Brain-inspired computing compilation method and device with decoupling of software and hardware and compilation framework

[0001] The present application claims priority to the Chinese patent application No. 202411346376.8, filed on September 25, 2024, and entitled "Brain-inspired computing compilation method and device with decoupling of software and hardware and compilation framework", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of brain-inspired computing compilation, and in particular to a brain-inspired computing compilation method and device with decoupling of software and hardware and a compilation framework. BACKGROUND

[0003] With the rapid development of artificial intelligence technology, brain-inspired computing, as an important research direction of the next generation of artificial intelligence, has shown great potential and application prospects. Brain-inspired computing hardware, as one of the major development directions of post-moore architecture, has significant advantages in processing specific domain problems. In particular, spiking neural network (SNN), as the core computing paradigm of brain-inspired computing, is considered as one of the key technologies to promote the development of artificial intelligence.

[0004] However, how to efficiently run various brain-inspired computing applications on the developed architecture or chip is still a technical problem. Currently, teams developing brain-inspired computing models and algorithms are facing the challenge of efficient computation on different brain-inspired chips. The provision and convenient use of efficient computing are crucial for the development of algorithms, which has been proven in the development process of deep learning.

[0005] Currently, there is a blank state for general compilation frameworks for various brain-inspired computing chips. Most of the current compilation software is designed for specific hardware, although it can achieve good performance on the target architecture, but such design limits the reusability, interoperability and composability between tool chains, and increases the cost of developing new chip compilers. For different types of brain-inspired computing applications, their computing characteristics differ greatly, making it difficult to efficiently support diversified application requirements. These problems limit the wide application and rapid development of brain-inspired computing technology. SUMMARY

[0006] Therefore, the present disclosure proposes a brain-inspired computing compilation method and device with decoupling of software and hardware and a compilation framework, which can improve the running efficiency and compatibility of brain-inspired computing applications on different hardware platforms.

[0007] In an aspect of the present disclosure, a brain-inspired computing compilation method with software and hardware decoupling is provided, and the method comprises:

[0008] Converting a brain-inspired computing application to be compiled into a first intermediate expression, the first intermediate expression being used for being recognized by a compilation framework;

[0009] Converting the first intermediate expression into a second intermediate expression, the second intermediate expression having a lower level of abstraction than the first intermediate expression;

[0010] Converting the second intermediate expression into a bottom-layer hardware expression, the bottom-layer hardware expression being used for generating a parameter file running on target hardware.

[0011] In a possible implementation, the converting the first intermediate expression into a second intermediate expression comprises:

[0012] Converting the first intermediate expression into the second intermediate expression according to an operator attribute of the brain-inspired computing application provided by the first intermediate expression, the operator attribute being used for indicating a storage format of a spike of a neuron and / or a storage format of a synapse of the neuron.

[0013] In another possible implementation, the storage format of the spike comprises: a dense storage format or a sparse storage format; and / or,

[0014] The storage format of the synapse comprises one of a dense storage format, a Compressed Sparse Row (CSR) storage format, and an Expanded Compressed Sparse Row (ECSR) storage format, the ECSR format being used for indicating that synapses with different delays are stored in a same CSR matrix.

[0015] In another possible implementation, the brain-inspired computing application comprises an operator and an operator attribute, the operator comprising at least one of a neuron update operator, a synapse propagation operator, a neuron definition operator, and a synapse definition operator, the operator attribute comprising a format attribute and / or a delay attribute, the format attribute being used for indicating whether the operator is sparse, and the delay attribute being used for indicating whether the operator has a delay.

[0016] In another possible implementation, the synapse propagation operator is converted into a bottom-layer operator in the process of converting the second intermediate expression into the bottom-layer hardware expression.

[0017] In another possible implementation, the method further comprises:

[0018] merge the plurality of operators when the plurality of operators in the brain-like computing application satisfy a preset merging condition.

[0019] The preset merging condition comprises that the plurality of operators are of the same type.

[0020] In another possible implementation, the method further comprises:

[0021] In the intermediate expression conversion process, for each input operator, a corresponding output operator is determined according to a preset conversion model, and an abstraction level of the output operator is lower than an abstraction level of the input operator.

[0022] The preset conversion model is used to indicate a preset mapping relationship between the input operator and the output operator.

[0023] According to another aspect of the present disclosure, a brain-like computing compiling device for software and hardware decoupling is provided, and the device comprises:

[0024] A first conversion module is configured to convert a brain-like computing application to be compiled into a first intermediate expression, and the first intermediate expression is used for being recognized by a compiling framework.

[0025] A second conversion module is configured to convert the first intermediate expression into a second intermediate expression, and an abstraction level of the second intermediate expression is lower than an abstraction level of the first intermediate expression.

[0026] A third conversion module is configured to convert the second intermediate expression into a bottom-layer hardware expression, and the bottom-layer hardware expression is used for generating a parameter file running on a target hardware.

[0027] In a possible implementation, the second conversion module is further configured to:

[0028] The first intermediate expression is converted into the second intermediate expression according to an operator attribute of the brain-like computing application provided by the first intermediate expression, and the operator attribute is used for indicating a storage format of a pulse of a neuron and / or a storage format of a synapse of the neuron.

[0029] In another possible implementation, the storage format of the pulse comprises a dense storage format or a sparse storage format; and / or,

[0030] The storage format of the synapse comprises one of a dense storage format, a CSR storage format and an ECSR storage format, and the ECSR format is used for indicating that synapses with different time delays are stored in a same CSR matrix.

[0031] In a possible implementation, the brain-like computing application comprises operators and operator attributes, the operators comprise at least one of a neuron update operator, a synapse propagation operator, a neuron definition operator, and a synapse definition operator, and the operator attributes comprise a format attribute and / or a delay attribute, the format attribute is used to indicate whether the operator is sparse, and the delay attribute is used to indicate whether the operator has a delay.

[0032] In a possible implementation, the synapse propagation operator is converted into a bottom-layer operator in the process of converting the second intermediate expression into the bottom-layer hardware expression.

[0033] In a possible implementation, the apparatus further comprises a merging module configured to:

[0034] merge a plurality of operators in the brain-like computing application when the plurality of operators satisfy a preset merging condition.

[0035] The preset merging condition comprises that the plurality of operators are of the same type.

[0036] In a possible implementation, the apparatus further comprises a determining module configured to:

[0037] In the process of converting the intermediate expression, for each input operator, a corresponding output operator is determined according to a preset conversion model, and an abstraction level of the output operator is lower than an abstraction level of the input operator.

[0038] The preset conversion model is used to indicate a preset mapping relationship between the input operator and the output operator.

[0039] According to another aspect of the present disclosure, there is provided a brain-like computing compiling apparatus for decoupling software and hardware, the apparatus comprising:

[0040] a processor;

[0041] a memory for storing processor-executable instructions;

[0042] The processor is configured to implement the above method when executing the instructions stored in the memory.

[0043] According to another aspect of the present disclosure, there is provided a brain-like computing compiling framework for decoupling software and hardware, the compiling framework being used to implement the above method.

[0044] According to another aspect of the present disclosure, there is provided a non-volatile computer-readable storage medium having computer program instructions stored thereon, the computer program instructions being executed by a processor to implement the above method.

[0045] According to another aspect of the present disclosure, a computer program product is provided, comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which, when run in a processor of an electronic device, causes the processor in the electronic device to perform the method described above.

[0046] The embodiment of the present disclosure provides a brain-computer computing compiling method for decoupling software and hardware. The brain-computer computing application to be compiled is converted into a first intermediate expression, the first intermediate expression is used for being recognized by a compiling framework, the first intermediate expression is converted into a second intermediate expression, an abstract level of the second intermediate expression is lower than an abstract level of the first intermediate expression, the second intermediate expression is converted into a bottom-layer hardware expression, and the bottom-layer hardware expression is used for generating a parameter file running on target hardware. That is, the method is based on a design idea of decoupling software and hardware, uses multi-level intermediate representation (MLIR), and lowers the brain-computer computing application to a hardware bottom-layer primitive in a hierarchical manner, so as to realize efficient support for different types of applications, effectively solve the problem of low running efficiency of the brain-computer computing application on different hardware platforms in the related art, improve reusability, interoperability and compositability of the compiler, reduce the cost of developing a new chip compiler, and accelerate the development and application of brain-computer computing technology.

[0047] Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0048] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present disclosure and serve to explain the principles of the present disclosure.

[0049] FIG. 1 shows a schematic diagram of an application scenario according to an exemplary embodiment of the present disclosure.

[0050] FIG. 2 shows a flowchart of a brain-computer computing compiling method for decoupling software and hardware according to an exemplary embodiment of the present disclosure.

[0051] FIG. 3 shows a schematic diagram of a compiling framework according to an exemplary embodiment of the present disclosure.

[0052] FIG. 4 shows a schematic diagram of user-defined data according to an exemplary embodiment of the present disclosure.

[0053] FIG. 5 shows a structural schematic diagram of a brain-computer computing compiling apparatus for decoupling software and hardware according to an exemplary embodiment of the present disclosure.

[0054] FIG. 6 is a block diagram of an apparatus for performing a brain-inspired computing compilation method according to an exemplary embodiment. DETAILED DESCRIPTION

[0055] Various exemplary embodiments, features, and aspects of the present disclosure will be described below in detail with reference to accompanying drawings. The same reference numbers in different drawings denote the same or similar elements / functionally similar elements. Although various aspects of embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0056] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0057] In addition, for the purpose of convenience and brevity, detailed descriptions of well-known functions and structures incorporated in the present disclosure can be omitted. It will be appreciated by those skilled in the art that the present disclosure can be practiced without these specific details. In some instances, well-known methods, procedures, components, and circuits have not been described in detail since it can obscure the pertinent aspects of the subject matter.

[0058] Brain-inspired computing compilation software is used to convert various brain-inspired computing applications into executable forms that can efficiently drive brain-inspired computing chips with different architectures. This also helps to combine research forces in various fields to form a good research ecosystem, such as applying new findings in the field of neurology to the field of AI, or widely and efficiently applying the latest (brain-inspired) computing chips to help new algorithms evolve and apply quickly.

[0059] Currently, there is still a blank in the general compilation framework for various brain-inspired computing chips. The brain-inspired computing compilation framework is a compiler infrastructure that is not specific to a particular hardware. Through a flexible multi-level internal architecture, intermediate representation, and interface, it can support a variety of brain-inspired computing applications and brain-inspired computing chips. This is different from the current various compilation software for specific brain-inspired chips, which can achieve good performance on the target architecture, but the interface between the software modules and levels is specific to the target chip, which limits the reusability of the software modules, the interoperability and composability between tool chains, and the cost of developing new chip compilers is high.

[0060] Currently, for various types of running brain-like computing applications, there are compilers or SNN simulation frameworks for brain-like chips. Among them, the compiler of the brain-like chip mainly depends on the target chip. For example, the chip based on emerging neuromorphic devices completes synaptic processing and / or neuron calculation in the form of analog circuits. The above-mentioned many brain-like chips generally have their own tool chain software, and the core part is the compiler. The compiler is one of the key components of the brain-like computing basic software, but it is currently mainly designed for the target chip. This limits the reusability of software modules, the interoperability and composability between tool chains, and the cost of developing new chip compilers is relatively high.

[0061] And the SNN simulation framework is usually developed for CPU and general GPU, such as Spikingjelly and Nest. Spikingjelly is a simulator based on Pytorch, and on this basis, automatic differentiation, gradient replacement, parallelization acceleration, etc. are realized; at present, it also supports the deployment of spiking neural network applications on different brain-like chips. Nest is a pulse neural network simulator developed in python, and NEST mainly supports the simulation of nervous system and supports Spike-Timing Dependent Plasticity (STDP) training.

[0062] For brain-like computing applications, different application computing characteristics differ greatly, and it is difficult to efficiently support different types of applications. For the current pulse neural network simulation tools, different applications are usually optimized, for example, NEST focuses more on supporting examples of computational neuroscience, and SpikingJelly focuses more on supporting Deep Spiking Neural Network (DSNN) applications, which leads to the inconvenience of using simulation frameworks and low efficiency.

[0063] That is, in the related art, there are the following technical problems: first, the application computing feature has a large span. From the computing and data access features, it has a large span and is complex - from the DSNN which is computationally intensive and has regular data access, to applications characterized by sparse event-triggered computing and irregular data access (such as simulation of biological neural networks derived from neuroscience), and the latter's rich spatiotemporal neural dynamics make this computing model have more optimization space. Second, the chip architecture has a large span. Since the class brain computing chip has not yet been widely accepted, the microarchitecture also has a large span, from the mature traditional von Neumann architecture to the data flow architecture based on emerging neuromorphic devices, and there are various hybrid architectures between the two ends, such as Tianji chips, Loihi, GaBAN, etc. Moreover, the granularity of hardware primitives provided by the chip is different, such as the SpiNNaker chip based on the traditional von Neumann architecture, which takes ARM soft core as the computing core and provides traditional general-purpose instruction sets as the fine-grained software and hardware interface, while many class brain chips (such as TrueNorth, BrainScaleS, etc.) expose hardware functions with neuron model granularity as coarse-grained interfaces, and the memory and computing integrated chip based on emerging non-volatile devices takes the crossbar structure as the operation main body, that is, it directly takes the dot product calculation of a certain scale as a hardware primitive. Therefore, it is necessary to implement a unified compilation framework with high resource reuse degree on these different architecture chips to improve the development efficiency (productivity), and it is also necessary to flexibly combine different levels of compilation optimization methods to achieve high performance (performance portability) on different backends for different applications.

[0064] Therefore, the embodiments of the present disclosure design a class brain computing compilation method decoupled from software and hardware, which can make class brain computing applications (such as spiking neural network applications) pass through multiple intermediate layers of expression and descend to the hardware bottom layer primitives in layers. In this way, different types of applications can be supported, and when new class brain computing hardware is proposed, the class brain computing compilation method can start from the intermediate layer to develop and reuse general optimizations in class brain computing compilation.

[0065] It should be noted that the compiling framework provided by the embodiments of the present disclosure is mainly for the researchers of brain-like chip and brain-like application development tools, while the compiler or simulator is mainly for the application developers. That is, the compiling framework of the embodiments of the present disclosure aims to provide efficient tools for the researchers of brain-like chip and brain-like application development tools, and these researchers are responsible for generating new compilers for target hardware more efficiently by using the compiling framework. This framework helps them to convert the brain-like computing application described in a high-level language into a parameter file that can be executed by the target hardware. In contrast, the compiler or simulator focuses more on the needs of application developers, who use these compilers or simulators to run and test specific application programs. Unlike traditional SNN simulators or compilers, the compiling framework using multi-layer intermediate representation used by the embodiments of the present disclosure provides convenience for developing new compiler backends, supports describing the characteristics of brain-like computing applications using operator attributes, supports the partial descent of brain-like computing applications at compile time, and reuses the optimization of the compiler. That is, the compiling framework allows the compiling process from the first intermediate representation to the second intermediate representation to be reused to some extent between different hardware backends, which reduces the workload of developing optimization for each hardware separately, enables different hardware backends to reuse the same intermediate optimization steps, improves the efficiency of the compiler, and may improve the cross-platform performance.

[0066] FIG. 1 shows a schematic diagram of an application scenario provided by an example embodiment of the present disclosure. The application scenario includes a brain-like computing application 11, a compiler 12, and target hardware 13.

[0067] The brain-like computing application 11 refers to a computing application that simulates the structure and function of human brain neuron networks. Such an application usually involves a large number of neurons and synaptic connections, as well as complex dynamic behavior. In order to implement such an application, a specific programming language and tool are needed to describe the structure and function of the neural network. The brain-like computing application is a neural network application, and the neural network can be an SNN, a DSNN, or a biological spiking neural network. The SNN is an artificial neural network that models the pulse behavior of neurons, which can simulate the mechanism of information exchange and transmission between neurons through discrete action potentials in the human brain. The DSNN is an extension of the SNN, which simulates more complex neural activity through a multi-layer network structure. The DSNN is mainly used to complete artificial intelligence (AI) tasks. The biological spiking neural network focuses more on simulating the physiological structure and function of the human brain from a biological perspective, and the biological spiking neural network simulation is used for biological simulation computing.

[0068] The compiler 12 is a tool that converts high-level language code into machine language code. In brain-inspired computing compilation, the compiler 12 is a bridge connecting the brain-inspired computing application 11 and the target hardware 13. The core function of the compiler 12 is to convert the brain-inspired computing application 11 written in a high-level language into a format that the target hardware 13 can understand and execute.

[0069] The target hardware 13 refers to the actual physical device that runs the brain-inspired computing application 11. In brain-inspired computing compilation, the target hardware 13 is usually a specialized hardware platform with a large number of parallel processing units and a high-speed interconnection network. These hardware platforms can efficiently simulate the dynamic behavior of neural networks and provide sufficient computing power and storage space to support the running of large-scale neural networks. The target hardware 13 can be a brain-inspired computing chip. For example, the target hardware is a general-purpose graphics processing unit (GPGPU).

[0070] The functions involved in this application scenario include but are not limited to the following: 1. Receiving brain-inspired computing applications 11: The compiler 12 receives brain-inspired computing application code written in a high-level language such as Python, C++, etc. These codes usually contain information such as neural network models, algorithm descriptions, and parameter configurations. 2. Generating intermediate representations: The compiler 12 converts the application code written in a high-level language into various intermediate representations, and through multiple layers of intermediate representations, the brain-inspired computing application is hierarchically lowered to hardware bottom primitives. These intermediate representations are closer to machine language, but still maintain a certain degree of abstraction, facilitating subsequent optimization and conversion. 3. Optimization and conversion: At the intermediate representation level, the compiler 12 implements various optimization strategies to improve the efficiency and performance of the final execution. 4. Mapping to brain-inspired computing chips: The compiler 12 further converts the optimized intermediate representation into the bottom hardware representation of the target hardware. 5. Generating executable files: Finally, the compiler 12 generates parameter files that can run on the target hardware, i.e. executable files. These files contain all the necessary information required to configure and control the target hardware. 6. Loading and execution: The generated parameter files are loaded onto the target hardware and executed by the target hardware to complete specific computing tasks.

[0071] The compiler 12 is used to perform the brain-inspired computing compilation method decoupled from software and hardware provided by the embodiments of the present disclosure, i.e. the compiler 12 is used to convert the brain-inspired computing application to be compiled into a first intermediate representation, the first intermediate representation is used to be recognized by a compiled framework; convert the first intermediate representation into a second intermediate representation, the abstraction level of the second intermediate representation is lower than that of the first intermediate representation; convert the second intermediate representation into a bottom hardware representation, and the bottom hardware representation is used to generate a parameter file running on the target hardware.

[0072] In the following, several illustrative embodiments are used to further introduce the soft and hardware decoupled brain-inspired computing compiling method provided by the embodiments of the present disclosure.

[0073] Please refer to FIG. 2, which shows a flowchart of the soft and hardware decoupled brain-inspired computing compiling method provided by an example embodiment of the present disclosure, and the present embodiment takes the method used in the compiler shown in FIG. 1 as an example. The method includes the following steps.

[0074] Step 201, convert the brain-inspired computing application to be compiled into a first intermediate representation, and the first intermediate representation is used for being recognized by a compiling framework.

[0075] The brain-inspired computing application written in a high-level language (including operators and operator attributes) is converted into a first intermediate representation. The purpose of this step is to enable the compiling framework to recognize and process this information. Optionally, this step can include the following: analyzing the operators and operator attributes in the brain-inspired computing application; generating the first intermediate representation according to the operators and operator attributes. In the compiling process, intermediate representation (IR) is a representation form of one or more abstract levels in the process of converting source code into target code. They are usually used in different stages of the compiler to facilitate optimization and code generation. The following is a glossary of the first intermediate representation: the first intermediate representation is also called high-level intermediate representation, and the first intermediate representation has a higher abstract level, retains the high-level structure and semantics of the source code, and at the same time begins to approach the instruction set of the target machine. In the brain-inspired computing application, the first intermediate representation is a high-level instruction under the SNN dialect, such as snn.new_lif, which is used for initializing, assigning values to, and calculating neuron groups and synapses. They are abstract instructions, input and return operands, but have not been specifically mapped to the underlying hardware level.

[0076] Optionally, the brain-inspired computing application includes operators and operator attributes, the operators include at least one of a neuron update operator, a synapse propagation operator, a neuron definition operator, and a synapse definition operator, and the operator attributes include a format attribute and / or a delay attribute, the format attribute is used to indicate whether the operator is sparse, and the delay attribute is used to indicate whether the operator has a delay. The following is a glossary of these operators and operator attributes:

[0077] 1. Neuron update operator: The neuron update operator is responsible for simulating the activity of biological neurons, including the processing and transmission of their electrical signals. This type of operator is usually included in SNNs to describe how neurons modify their state based on input signals and generate output pulses.

[0078] 2. Synapse propagation operator: Synapse propagation operators model the function of the synapse, i.e., the connection between neurons. They define how signals are transmitted between neurons and how this transmission affects the activity of the receiving neuron. Synapse propagation operators are particularly important in implementing learning rules such as STDP. Optionally, the synapse propagation operator is not converted in the process of converting the first intermediate representation to the second intermediate representation, but is converted to a lower-level operator in the process of converting the second intermediate representation to the underlying hardware representation.

[0079] 3. Neuron definition operator: These operators are used to define and initialize the state and parameters of a neuron. For example, setting the threshold value of a neuron, resetting characteristics, etc., which are crucial for simulating the dynamic behavior of a neuron.

[0080] 4. Synapse definition operator: Synapse definition operators describe the characteristics of a synapse, such as weight, delay, and synapse type (excitatory or inhibitory). These parameters determine the effect and manner of transmission of neural signals.

[0081] 5. Format attribute: The format attribute is used to indicate whether the operator is sparse or not. In brain-like computing, many connections may not exist or be invalid, and sparse operators can effectively take advantage of this feature, processing only existing connections, thereby reducing computational resource consumption and improving computational efficiency. The format attribute includes a first format value or a second format value, the first format value is used to indicate that the operator is sparse, and the second format value is used to indicate that the operator is dense.

[0082] 6. Delay attribute: The delay attribute is used to indicate whether the operator has a delay or not. In biological neural systems, signal transmission inevitably has a delay, and simulating this feature helps improve the biological plausibility and accuracy of the model. The delay attribute includes a first delay value or a second delay value, the first delay value is used to indicate that the operator has no delay, and the second delay value is used to indicate that the operator has a delay.

[0083] In the application of brain-like computing, operator merging is an important optimization method, aiming to improve the computing efficiency and reduce resource consumption. When multiple operators in the brain-like computing application meet the preset merging condition, the multiple operators can be merged, and they can be merged into a composite operator, thereby reducing the storage and transmission requirements of intermediate data. The preset merging condition can include that the operator types of multiple operators are the same, or the merging can be based on the data dependency between operators, the parallelism of operator execution, and the resource demand of the operator, and the embodiments of the present disclosure are not limited thereto. It should be noted that operator merging can be performed at multiple links in the brain-like computing compilation process, that is, it can be performed when there is a need to merge operators in steps 201 to 203. Taking the case where operator merging is performed in step 201, that is, the process of converting the brain-like computing application into the first intermediate expression, when multiple operators in the brain-like computing application meet the preset merging condition, the operators can be merged first, and then the conversion is performed.

[0084] In order to describe a brain-like computing application, it is necessary to define the neuron model, the connection mode between neurons, the storage format of neuron pulses, and the storage format of neuron synapses. The following are the explanations of these data:

[0085] 1. Neuron model: defines the biological or mathematical behavior of neurons, used to simulate the dynamic characteristics of neurons. The neuron model describes how neurons respond to input signals, and different models have different mathematical expressions and parameters.

[0086] 2. Connection mode between neurons: describes how neurons are connected through synapses, including the topological structure and functional characteristics of the connection. The connection mode between neurons defines the architecture of the network, such as feedforward network, convolutional network, recurrent network, etc.

[0087] 3. Storage format of pulses: determines the recording method of pulse information, such as frequency coding, time coding, etc. Different storage formats will affect the processing method and access efficiency of data. The storage format of pulses includes: dense storage format or sparse storage format.

[0088] Dense storage format: each neuron's pulse is stored separately, even if many values are zero (inactive), the same space is occupied.

[0089] Sparse storage format: only stores non-zero elements (i.e. actual pulses), saving storage space and improving processing efficiency.

[0090] 4. Storage format of synapses: describes the information of connection strength between neurons, which usually exists in the form of weight matrix. The storage format of synapses includes: one of dense storage format, CSR storage format, and ECSR storage format.

[0091] Dense storage format: A dense format similar to a pulse, all synaptic weights are stored, regardless of whether their values are zero or not.

[0092] CSR storage format: An optimized sparse matrix storage method that only stores non-zero elements, reducing memory usage and increasing data access speed.

[0093] ECSR storage format: Further optimization on this basis, synapses with different delays can be stored in the same CSR matrix, more efficiently managing synapse data with delay differences. The delay attribute corresponding to CSR is the first delay value, and the delay attribute corresponding to ECSR is the second delay value. The first delay value is used to indicate the absence of delay, and the second delay value is used to indicate the presence of delay. Optionally, for the GPGPU backend, a new data format called ECSR is implemented. This data structure is used to show that synapses with different delays are placed in the same CSR matrix, which can greatly reduce the sparsity of synapses with each delay, increasing the computational efficiency.

[0094] Step 202, converting the first intermediate expression into a second intermediate expression, the second intermediate expression has a lower level of abstraction than the first intermediate expression.

[0095] The abstraction level of the first intermediate expression is lowered to the second intermediate expression, which is to further refine the representation of the brain-like computing application, so as to be more easily mapped to the underlying hardware.

[0096] The first intermediate expression usually maintains an abstraction level close to the high-level source code, facilitating program analysis and optimization by the compiler. In brain-like computing, the first intermediate expression may contain high-level descriptions of neuron models, connection methods, etc. The second intermediate expression is a form of expression closer to the target machine, and its abstraction level is lower than that of the first intermediate expression. This may involve directly mapping the specific implementation details of neurons and synapses to the instruction set or data structure executable by the target hardware. The second intermediate expression is also called a low-level intermediate expression, which is further optimized and converted on the basis of the first intermediate expression. The second intermediate expression has a lower level of abstraction than the first intermediate expression and is closer to the instruction set and specific hardware operations of the target machine. The second intermediate expression usually includes specific instructions and data structures, such as specific instructions including loop instructions, control instructions, and some computing instructions, etc., and data structures including arrays, etc. In brain-like computing applications, the second intermediate expression refines the abstract instructions of the first intermediate expression, for example, converting snn.new_lif to memref.alloc in the memref dialect, which is a memory allocation instruction closer to the hardware level, preparing for the final conversion to the underlying hardware expression.

[0097] Optionally, the first intermediate expression is converted into a second intermediate expression according to an operator attribute of the brain-like computing application provided by the first intermediate expression, including: when the operator attribute is a first attribute value, converting the first intermediate expression into the second intermediate expression in a first manner; and when the operator attribute is a second attribute value, converting the first intermediate expression into the second intermediate expression in a second manner different from the first manner to generate a different second-level intermediate expression and increase computing efficiency. The operator attribute is used to indicate a storage format of a pulse of a neuron and / or a storage format of a synapse of the neuron. That is, the storage format of the synapse and / or the storage format of the pulse can be determined according to the operator attribute; the synapse and / or the pulse are stored in a memory, and different algorithms are used to calculate synapse propagation and neuron update processes according to different storage formats. Illustratively, the operator attribute includes a format attribute and a delay attribute. When the format attribute of the synapse indicates that the operator is dense and the delay attribute indicates that the operator has no delay, code in a dense synapse case is generated, and in this case, weights are stored in a two-dimensional array. When the format attribute of the synapse indicates that the operator is sparse and the delay attribute indicates that the operator has no delay, a CSR array is generated to store the weights, and the original weights are compressed to be stored in the CSR array. The present disclosure does not limit this.

[0098] In step 203, the second intermediate expression is converted into a bottom-layer hardware expression, and the bottom-layer hardware expression is used to generate a parameter file running on a target hardware.

[0099] The second intermediate expression is converted into a bottom-layer hardware expression, and the bottom-layer hardware expression has a lower level of abstraction than the second intermediate expression, so as to generate a parameter file running on a target hardware. In the conversion in this step, the bottom-layer code is generated and optimized according to hardware characteristics. The synapse propagation process is also lowered to a bottom-layer operator at this time, and this is designed because different hardware has great differences and the algorithms used for synapse propagation are also different. The purpose of this step is to map the brain-like computing application to specific hardware resources, so as to achieve efficient running. The bottom-layer hardware expression can be a data structure related to the target hardware, such as an instruction set or a configuration file. That is, for a CPU, a GPU, and other instruction set architectures, corresponding instruction set assembly is generated, and for some hybrid stream coarse-grained description architectures, a corresponding configuration file is generated. The bottom-layer hardware expression is used to describe the execution manner of the brain-like computing application on the target hardware. The parameter file can be an executable file of the target hardware, and the parameter file can be a text file containing hardware configuration information, which is used to guide the running of the brain-like computing application on the target hardware.

[0100] Optionally, the intermediate expression includes multiple operators, that is, the first intermediate expression, the second intermediate expression and the underlying hardware expression each include multiple operators. In the intermediate expression conversion process, for each input operator, a corresponding output operator is determined according to a preset conversion model, the abstraction level of the output operator is lower than that of the input operator, and the preset conversion model is used to indicate a preset mapping relationship between the input operator and the output operator. The intermediate expression conversion process can be any one of the above three steps. In the process of converting the brain-like computing application to be compiled into the first intermediate expression, the input operator is an operator in the brain-like computing application, and the output operator is an operator in the first intermediate expression. In the process of converting the first intermediate expression into the second intermediate expression, the input operator is an operator in the first intermediate expression, and the output operator is an operator in the second intermediate expression. In the process of converting the second intermediate expression into the underlying hardware expression, the input operator is an operator in the second intermediate expression, and the output operator is an operator in the underlying hardware expression.

[0101] After the second intermediate expression is converted into the underlying hardware expression, the compiler converts the underlying hardware expression into assembly language (assembly language is a description method that can be directly recognized by hardware), and finally converts the assembly language into an executable file, that is, a parameter file running on the target hardware. The parameter file can be executed on the corresponding target hardware backend.

[0102] In summary, the embodiment of the present disclosure proposes a brain-like computing compilation method decoupled from software and hardware. The brain-like computing application to be compiled is converted into a first intermediate expression, the first intermediate expression is used for recognition by a compiled framework, the first intermediate expression is converted into a second intermediate expression, the abstraction level of the second intermediate expression is lower than that of the first intermediate expression, the second intermediate expression is converted into an underlying hardware expression, and the underlying hardware expression is used to generate a parameter file running on target hardware. That is, the method is based on the design idea of decoupling software and hardware, uses multiple intermediate expressions, and hierarchically reduces the brain-like computing application to hardware bottom primitives, thereby achieving efficient support for different types of applications, effectively solving the problem of low running efficiency of brain-like computing applications on different hardware platforms in related technologies, improving the reusability, interoperability and composability of the compiler, reducing the development difficulty and workload of the brain-like chip compiler, and improving the running efficiency of the brain-like application (through brain-like compilation optimization).

[0103] The compiling framework provided by the embodiments of the present disclosure is based on the design idea of decoupling software and hardware, uses multi-layer intermediate expression, and divides the compiling framework of brain-like computing into three layers: a description layer, an intermediate layer, and a hardware layer, so as to better achieve the effect of decoupling software and hardware. The multi-layer intermediate expression is a sub-project of the Low-Level Virtual Machine (LLVM) compiling infrastructure, which provides multiple dialects (English: Dialect), each of which is a collection of operators and data structures in a specific field, and the multi-layer intermediate expression is easy to extend new dialects and convert to original dialects, so the multi-layer intermediate expression is often used as a development tool for specific field compilers.

[0104] As shown in FIG. 3, the compiling framework includes a description layer, an intermediate layer, and a hardware layer, which correspond to a first intermediate expression, a second intermediate expression, and a bottom hardware expression respectively. The conversion between the three is through a compiling pass conversion, that is, the compiler converts the description layer expression (that is, the first intermediate expression) to the intermediate layer expression (that is, the second intermediate expression), and then to the hardware layer expression (that is, the bottom hardware expression) by executing a compiling method, and finally converts it into an executable file (that is, a parameter file) of a target hardware backend. Among them, “%v” is a variable name, “snn.new_lif” is an operator, which belongs to the SNN dialect and is used to create or define a Leaky Integrate-and-Fire (LIF) neuron group, and the meaning of the entire expression “%v=snn.new_lif” is to define the LIF neuron group in the SNN dialect and assign the reference of this neuron group to the variable “%v”. In other expressions, “%p” is another variable name; “%s” is another variable name; “memref.alloc” is another operator, which belongs to the memref dialect in MLIR and is used to allocate space for variables in memory; “llvm.alloc” is another operator, which is an instruction in LLVM IR and is used to allocate memory space for local variables on the stack frame of a function. The meanings of other expressions are similar and will not be described here. In the following, the compiling framework will be further introduced.

[0105] 1. The compiler converts the brain-like computing application described by the user in a high-level language into a form that can be recognized by the compiling framework. In order to make this step as simple as possible, the design of the description layer should be as close as possible to the expression of the common brain-like computing simulation framework, for example, close to the syntax of PyNN, which is a widely used SNN description language.

[0106] To describe a spiking neural network application, some target data need to be defined, including neuron model, connection between neurons, storage format of spike and storage format of synapse. Some neuron models are built-in in the simulation framework, which can be used directly by users (e.g. LIF, Izhikevich, IAF, etc.). Users need to specify a specific neuron in the built-in neuron models and provide the hyper-parameters of the neuron model (e.g. threshold voltage, resting voltage, etc.).

[0107] The connection between neurons supports static synapses. The framework supports multiple methods to initialize static synapses, such as reading from a file, or using one-to-one, many-to-many, probabilistic connection, etc. in NEST.

[0108] Users can also specify the storage format of spike and / or the storage format of synapse. Since spiking neural network applications are quite different, their computational characteristics are quite different, and the sparsity of spike and synapse varies greatly between different applications. The framework supports users to specify the storage format of spike and synapse according to the computational characteristics of the problem, so as to improve the overall computational efficiency. The storage format of spike and synapse can be user-defined, and the computational characteristics refer to the sparsity of synapse and spike. Since the sparsity of synapse and spike varies greatly in different spiking neural network applications, dense or sparse storage format may be used in the calculation process. Here, the compilation framework will determine the data structure of synapse and spike according to the operator properties provided by the user. Storage refers to storing spike and synapse in memory and using different algorithms to calculate synapse propagation and neuron update process according to different storage formats.

[0109] Overall, the spiking neural network application described in high-level language is converted into the input of the compilation framework. Therefore, the description layer has the following two characteristics: (1) flexibility for upper-layer application conversion; (2) high efficiency for subsequent optimization.

[0110] Optionally, the user-defined data schematic diagram is shown in FIG. 4, which includes operators, data structures, operator properties and compilation flows. The spiking neural network application is an application described using operators. Some operators (neuron update operator, synapse propagation operator, neuron definition operator, synapse definition operator) use operator properties in their definitions. Operator properties are some information used to additionally specify operators for subsequent optimization. Format property is used to indicate whether the operator is sparse, and delay property is used to indicate whether the operator has delay. Some synapses of the spiking neural network application have delay, and the synapses with delay need to highlight the post-neuron after a period of time after the pre-neuron fires. Some synapses of the spiking neural network application do not have delay (or the delay is 1 time step). Therefore, the delay property is used to describe whether the synapses of the spiking neural network application have delay.

[0111] 2. The intermediate layer needs to take the description layer on one hand, and convert the abstract operators of the description layer into specific algorithm implementation. On the other hand, it needs to take the hardware layer down, so the primitives of this layer need to be supported by the bottom hardware, so as to run on the corresponding hardware platform.

[0112] At compile time, the compiler converts the first intermediate expression of the description layer into a second intermediate expression (IR) at a slightly lower level. At the same time, the intermediate layer also describes the actual calculation process of the spiking neural network application. In the process of converting the abstract operators of the description layer into the intermediate layer, some operator properties of the description layer will guide the specific intermediate code generation, for example, the synaptic sparsity of different applications may be different, so it is necessary to use dense / sparse matrix for storage. This requires the description layer to provide the characteristics of the application. In addition, since the synapse propagation operator is usually the hotspot of the whole brain computing application, the conversion of the synapse propagation operator is usually performed when the intermediate layer is converted to the hardware layer.

[0113] Some operator properties of the description layer will guide the specific intermediate code generation, including: checking the operator properties corresponding to the input operator, for example, for the synapse propagation definition operator, by obtaining the format attribute and the delay attribute, when the format attribute indicates that the operator is dense, and the delay attribute indicates that the operator does not exist delay, the code for the case of dense synapse is generated, and the weight is stored in a two-dimensional array. When the format attribute indicates that the operator is sparse, and the delay attribute indicates that the operator does not exist delay, a CSR array is generated to store the weight, and the original weight is compressed to store in the CSR array. In addition, in the process of neuron update, the storage form of the generated pulse is also determined according to the format attribute of the pulse, such as, when the format attribute of the pulse indicates that the operator is dense, the pulse is directly stored in the dense array in the form of 0 / 1, and when the format attribute of the pulse indicates that the operator is sparse, only the identifier (id) of the neuron with value 1 is stored.

[0114] Overall, most of the operators of the description layer are converted to specific second intermediate expressions, leaving a small number of hot operators waiting for subsequent conversion. In the conversion process from the description layer to the intermediate layer, the compiler will optimize according to the properties of the description layer. The hot operator is the operator with the longest time consumption in the application, and in the brain computing application, the hot operator is usually the synapse propagation operator. In the process of converting the first intermediate expression to the second intermediate expression, the synapse propagation operator does not descend, but waits to be converted when the second intermediate expression is converted to the bottom hardware expression.

[0115] 3. The hardware layer takes the intermediate layer and converts the second intermediate representation of the intermediate layer into a bottom hardware representation of the hardware layer. In this step of conversion, the bottom code will be generated and optimized according to the hardware characteristics. The synapse propagation process will also be lowered to the bottom operator at this time. This is designed because different hardware is very different, and the algorithm used for synapse propagation is also different. After all the operators are converted into the bottom hardware representation, the compiler converts them into assembly language and finally into an executable file for execution on the corresponding hardware backend.

[0116] The intermediate representations of different layers are converted through a compilation flow. Optionally, the embodiment of the present disclosure implements two compilation flows, the first being a merge pass of automatic neuron groups, and the other being a lower pass. The lower pass is a compilation phase that converts the intermediate representations of the three different layers, and the merge pass can be an optimization phase in the process of converting the brain-inspired computing application into the first intermediate representation. After the merge pass, the neuron groups are merged to increase the computing efficiency, and the brain-inspired computing application still uses the first intermediate representation.

[0117] The merge pass is an optimization flow that traverses all the operators of the brain-inspired computing application, finds all the neuron definition operators, and determines whether the neuron definition operators can be merged (for example, the preset merging conditions include whether the types of neurons are the same). If the neuron definition operators can be merged, all operators using the neuron groups need to be merged along the use chain of the neuron definition operators. It should be noted that the operators that need to be merged can also be neuron update operators, synapse propagation operators, and operators and functions on the use chain of these operators.

[0118] The lower pass involves the conversion of intermediate representations of different levels, and needs to define what conversion needs to be performed in this compilation flow, define the input and output operator sets of this flow, and the input and output operators can be dialects. The conversion rules of all possible input operators of this flow are also defined. For each input operator, a lowering method needs to be designed to map it to the output operator set. Then when this compilation flow is executed, the compiler will replace the original input operator according to the conversion rule, match the input operator, and execute the conversion rule to replace it with the output operator set. Therefore, the most critical is to implement the replacement rule of each operator, and use a more bottom-level operator combination to realize the function of a high-level and abstract operator.

[0119] The application of the compiling framework provided by the embodiments of the present disclosure on various hardware platforms achieves significant improvement in running efficiency. In an illustrative example, for target hardware including CPUs, general-purpose GPUs, and data flow-based brain chips based on ReRAM, vector processing-based brain chips GaBAN II, and brain-like Tianji chips, the compiling framework provided by the embodiments of the present disclosure exhibits excellent performance. Among them, the code generated by the compiling framework on the data flow-based brain chips based on ReRAM, GaBAN II, and brain-like Tianji chips has a running efficiency not lower than that of the code generated by using the original tool chain. This shows that the compiling framework can effectively adapt to these specific hardware architectures and optimize the code execution performance. For more general hardware platforms, such as CPUs and general-purpose GPUs, the compiling framework also performs well. Compared with the simulation framework NEST for SNN applications, the compiling framework achieves an average speedup of 6.7 times on CPUs and an average speedup of 5.1 times on GPUs. In addition, compared with the simulation framework SpikingJelly for DSNN applications, the compiling framework achieves an average speedup of 7.6 times on CPUs and an average speedup of 4.8 times on GPUs. These results show that whether on traditional CPUs and GPUs or on specially designed brain-like chips, the compiling framework provided by the embodiments of the present disclosure can significantly improve the running efficiency of the code. This cross-platform performance improvement demonstrates the wide applicability and optimization capability of the compiling framework, providing strong support for brain-like computing applications on different hardware platforms.

[0120] In summary, unlike traditional SNN simulators or compilers, the embodiments of the present disclosure use a multi-layer intermediate expression compiling framework, support the use of operator attributes to describe the characteristics of brain-like computing applications, and support the partial descent of brain-like computing applications at compile time, so that different hardware backends can reuse the same intermediate optimization. Reusing the same intermediate optimization mainly refers to the above-mentioned optimization of merging streams and descending streams. Different hardware backends can reuse the optimization of merging streams and can partially reuse the optimization in descending streams, depending on the characteristics of the hardware backend. The descending stream has different optimizations for traditional instruction set architectures, data flow architectures, and hybrid stream architectures. New hardware backends can select different descending processes according to hardware characteristics, thereby reusing different optimizations. The optimization of merging streams combines neurons to increase the parallelism and memory continuity of neuron groups. The descending stream performs multi-thread optimization, vectorization optimization, ECSR optimization, and the like. Moreover, the embodiments of the present disclosure provide a synaptic propagation algorithm for GPGPU, implement a new data format, i.e., ECSR, for the GPGPU backend, and use the data structure in the synaptic propagation process. The data structure is used to show that different delay synapses are stored in the same CSR matrix, which can greatly reduce the sparsity of each delay synapse and increase the computing efficiency.

[0121] The following is a device embodiment of the embodiments of the present disclosure. For parts not elaborated in the device embodiment, please refer to the technical details disclosed in the above method embodiments.

[0122] Please refer to FIG. 5, which shows a structural schematic diagram of a brain-computer computing device decoupled by software and hardware according to an example embodiment of the present disclosure. The device can realize all or part of a computing device through software, hardware, and a combination of the two. The device includes a first conversion module 51, a second conversion module 52, and a third conversion module 53.

[0123] The first conversion module 51 is configured to convert a brain-computer computing application to be compiled into a first intermediate expression, the first intermediate expression being used for identification by a compiled framework.

[0124] The second conversion module 52 is configured to convert the first intermediate expression into a second intermediate expression, the second intermediate expression having a lower level of abstraction than the first intermediate expression.

[0125] The third conversion module 53 is configured to convert the second intermediate expression into a bottom-layer hardware expression, the bottom-layer hardware expression being used to generate a parameter file running on a target hardware.

[0126] In a possible implementation, the second conversion module 52 is further configured to:

[0127] convert the first intermediate expression into the second intermediate expression according to an operator attribute of the brain-computer computing application provided by the first intermediate expression, the operator attribute being used to indicate a storage format of a pulse of a neuron and / or a storage format of a synapse of the neuron.

[0128] In another possible implementation, the storage format of the pulse includes a dense storage format or a sparse storage format; and / or,

[0129] The storage format of the synapse includes one of a dense storage format, a CSR storage format, and an ECSR storage format, the ECSR format being used to indicate that synapses with different time delays are stored in the same CSR matrix.

[0130] In another possible implementation, the brain-computer computing application includes an operator and an operator attribute, the operator including at least one of a neuron update operator, a synapse propagation operator, a neuron definition operator, and a synapse definition operator, the operator attribute including a format attribute and / or a delay attribute, the format attribute being used to indicate whether the operator is sparse, and the delay attribute being used to indicate whether the operator has a delay.

[0131] In another possible implementation, the synapse propagation operator is converted into a bottom-layer operator in the process of converting the second intermediate expression into the bottom-layer hardware expression.

[0132] In another possible implementation manner, the apparatus further includes a merging module configured to:

[0133] The plurality of operators are merged when the plurality of operators in the brain-like computing application satisfy a preset merging condition.

[0134] The preset merging condition includes that the plurality of operators are of the same type.

[0135] In another possible implementation manner, the apparatus further includes a determining module configured to:

[0136] In the intermediate representation conversion process, for each input operator, a corresponding output operator is determined according to a preset conversion model, and an abstraction level of the output operator is lower than an abstraction level of the input operator.

[0137] The preset conversion model is used to indicate a mapping relationship between the preset input operator and the output operator.

[0138] It should be noted that the apparatus provided in the above embodiments is used to implement the functions thereof, and the above-described functions are completed by different functional modules according to actual needs in actual application, that is, the content structure of the apparatus is divided into different functional modules to complete all or part of the above-described functions.

[0139] As to the apparatus in the above embodiments, the specific manners in which the modules perform operations have been described in detail in the embodiments of the method, and will not be described in detail here.

[0140] The disclosure embodiments further provide a brain-like computing compiling framework decoupled from hardware and software, and the compiling framework is used to implement the above method.

[0141] The disclosure embodiments further provide a brain-like computing compiling apparatus decoupled from hardware and software, and the apparatus includes a processor, and a memory configured to store processor-executable instructions, wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0142] The disclosure embodiments further provide a non-volatile computer-readable storage medium having computer program instructions stored thereon, and the computer program instructions are executed by a processor to implement the above method.

[0143] The disclosure embodiments further provide a computer program product including computer-readable code or a non-volatile computer-readable storage medium carrying the computer-readable code, and when the computer-readable code is run in a processor of a computing device, the processor in the computing device executes the above method.

[0144] FIG. 6 is a block diagram illustrating an apparatus 1900 for performing a brain-inspired computing compilation method for software and hardware decoupling, according to an example embodiment. For example, the apparatus 1900 can be provided as a server or a terminal device. Referring to FIG. 6, the apparatus 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions, such as an application program, executable by the processing component 1922. The application program stored in the memory 1932 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above method.

[0145] The apparatus 1900 can further include a power supply component 1926 configured to perform power management of the apparatus 1900, a wired or wireless network interface 1950 configured to connect the apparatus 1900 to a network, and an input / output interface 1958 (I / O interface). The apparatus 1900 can operate based on an operating system stored in the memory 1932, such as Windows Server TM , Mac OS X TM , Unix TM , Linux TM , FreeBSD TM or the like.

[0146] In an example embodiment, a non-transitory computer readable storage medium, such as the memory 1932 including computer program instructions, is also provided, which can be executed by the processing component 1922 of the apparatus 1900 to complete the above method.

[0147] The present disclosure can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0148] Computer readable storage media can be tangible storage media which can retain and store instructions for use by an instruction execution device. Computer readable storage media can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer readable storage media include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0149] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0150] Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0151] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0152] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0153] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0154] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0155] Embodiments of the present disclosure have been described above, and the description is intended to be illustrative, and not restrictive, of the disclosed embodiments. Many modifications and variations of the described embodiments are possible, and all such modifications and variations are intended to be within the scope of the described embodiments. The description used herein is intended to best explain the principles of the various embodiments, the practical application, and the best mode of using the present disclosure, and to enable others skilled in the art to understand the disclosure, various embodiments, and the application, devices, and apparatuses.

Claims

1. A method for compiling a brain-like computing system decoupled from hardware, characterized in that, The method comprises: converting a brain-like computing application to be compiled into a first intermediate expression, the first intermediate expression being used for being recognized by a compiled framework; converting the first intermediate expression into a second intermediate expression, the second intermediate expression having a lower level of abstraction than the first intermediate expression; converting the second intermediate expression into a bottom-layer hardware expression, the bottom-layer hardware expression being used for generating a parameter file running on a target hardware.

2. The method of claim 1, wherein, The converting the first intermediate expression into a second intermediate expression comprises: converting the first intermediate expression into the second intermediate expression according to an operator attribute of the brain-like computing application provided by the first intermediate expression, the operator attribute being used for indicating a storage format of a pulse of a neuron and / or a storage format of a synapse of the neuron.

3. The method of claim 2, wherein: the storage format of the pulse comprises a dense storage format or a sparse storage format; and / or the storage format of the synapse comprises one of a dense storage format, a compressed sparse row (CSR) storage format, and an extended compressed sparse row (ECSR) storage format, the ECSR format being used for indicating that synapses with different delays are stored in a same CSR matrix.

4. The method of claim 1, wherein, The brain-like computing application comprises operators and operator attributes, the operators comprising at least one of a neuron update operator, a synapse propagation operator, a neuron definition operator, and a synapse definition operator, the operator attributes comprising a format attribute and / or a delay attribute, the format attribute being used for indicating whether the operator is sparse, and the delay attribute being used for indicating whether the operator has a delay.

5. The method of claim 4, wherein, The synapse propagation operator is converted into a bottom-layer operator in the process of converting the second intermediate expression into the bottom-layer hardware expression.

6. The method according to any one of claims 1 to 5, characterized in that, The method further comprises: merging a plurality of operators in the brain-like computing application when the plurality of operators satisfy a preset merging condition; wherein the preset merging condition comprises that the plurality of operators have a same operator type.

7. The method according to any one of claims 1 to 5, characterized in that, The method further comprises: in the process of converting the intermediate expression, for each input operator, determining a corresponding output operator according to a preset conversion model, the output operator having a lower level of abstraction than the input operator; wherein the preset conversion model is used for indicating a preset mapping relationship between the input operator and the output operator.

8. A brain-inspired computing compiling device for decoupling software and hardware, characterized in that, The apparatus comprises: a first conversion module configured to convert a brain-like computing application to be compiled into a first intermediate expression, the first intermediate expression being used for being recognized by a compiled framework; a second conversion module configured to convert the first intermediate expression into a second intermediate expression, the second intermediate expression having a lower level of abstraction than the first intermediate expression; a third conversion module configured to convert the second intermediate expression into a bottom-layer hardware expression, the bottom-layer hardware expression being used for generating a parameter file running on a target hardware.

9. A brain-inspired computing compiling device for decoupling software and hardware, characterized in that, The apparatus comprises: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the method of any one of claims 1 to 7 when executing the instructions stored in the memory.

10. A brain-inspired computing compilation framework decoupled from hardware, characterized in that, The compiled framework is used for implementing the method of any one of claims 1 to 7.

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