Semiconductor device and operating method therefor, system, and computer-readable storage medium

Abstract

Provided in the present disclosure are a semiconductor device and an operating method therefor, a system, and a computer-readable storage medium. The semiconductor device comprises: a memory array, wherein the memory array comprises a first memory string and a second memory string, and the first memory string comprises at least one first dummy memory cell; and a peripheral circuit, coupled to the memory array, and configured to perform a programming operation on the at least one first dummy memory cell, so that a threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold to a first target threshold, wherein when the threshold voltage of the at least one first dummy memory cell reaches the first target threshold, the difference between a current of the first memory string and a current of the second memory string is less than or equal to a preset threshold.

Description

Semiconductor device and method of operating same, system, and computer-readable storage medium

[0001] Cross-reference to Related Applications

[0002] The present disclosure is based on and claims priority to Chinese Patent Publication No. 202411346247.9, filed on September 25, 2024, the entire contents of which are hereby incorporated by reference into the present disclosure. TECHNICAL FIELD

[0003] The present disclosure relates to, but is not limited to, a semiconductor device and method of operating same, system, and computer-readable storage medium. BACKGROUND

[0004] In the classical von Neumann computing architecture, the memory and the processor are separated, and data transmission is performed between the two through a data bus. When executing a command, the processor first reads data from the memory, and after processing, the updated data is written back to the memory. Frequent data movement brings huge power consumption and time overhead. In addition, due to the limited memory bandwidth, the processing speed of the processor is limited by the access speed of the memory, greatly affecting the computing performance. With the rise of big data and artificial intelligence applications, the processing of massive data makes the von Neumann computing architecture bottleneck more and more prominent. SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor device and method of operating same, system, and computer-readable storage medium.

[0006] In a first aspect, embodiments of the present disclosure provide a semiconductor device, comprising: a memory array; the memory array comprising a first memory string and a second memory string; the first memory string comprising at least one first dummy memory cell; a peripheral circuit coupled to the memory array and configured to: perform a programming operation on the at least one first dummy memory cell, so that a threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold to a first target threshold; wherein, in a case where the threshold voltage of the at least one first dummy memory cell reaches the first target threshold, a difference between a current of the first memory string and a current of the second memory string is less than or equal to a preset threshold.

[0007] In an optional implementation, the second memory string comprises at least one second dummy memory cell; the threshold voltage of the at least one second dummy memory cell remains at the initial threshold; wherein, before performing the programming operation on the at least one first dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and the difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold.

[0008] In an optional implementation, the second memory string includes at least one second dummy memory cell; the peripheral circuit is configured to perform a programming operation on the at least one second dummy memory cell, so that the threshold voltage of the at least one second dummy memory cell is adjusted from the initial threshold value to a second target threshold value; wherein, in the case that the threshold voltage of the at least one first dummy memory cell reaches the first target threshold value and the threshold voltage of the at least one second dummy memory cell reaches the second target threshold value, the difference between the current of the first memory string and the current of the second memory string is less than or equal to the preset threshold value.

[0009] In an optional implementation, the first target threshold value is equal to the second target threshold value.

[0010] In an optional implementation, the first target threshold value is greater than the second target threshold value; wherein, before performing the programming operation on the at least one first dummy memory cell and the at least one second dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and the difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold value.

[0011] In an optional implementation, the peripheral circuit is further configured to: apply a read voltage to a target word line in a target memory block; apply a first turn-on voltage to a non-target word line in the target memory block; apply a corresponding input voltage to each of a plurality of first selection lines in the target memory block; apply a second turn-on voltage to each of a plurality of second selection lines in the target memory block; and sense a current on a bit line coupled to the target memory block to obtain a current of a memory string in the target memory block; wherein the target memory block includes the first memory string and the second memory string.

[0012] In an optional implementation, the peripheral circuit is specifically configured to: apply a corresponding input voltage to a first selection line coupled to one memory string in the target memory block to turn on the memory string; and apply a corresponding input voltage to a first selection line coupled to another memory string on the same bit line as the memory string to turn off the another memory string.

[0013] In an optional implementation, the target memory block includes a plurality of memory cells; the memory cells are configured to store N-bit weight data, and the plurality of memory cells in the target memory block are configured to have 2 N memory states, the read voltage is located between threshold voltage distributions corresponding to two adjacent memory states; N is an integer greater than or equal to 1.

[0014] In an alternative embodiment, the first select line is one of a top select line and a bottom select line, and the second select line is the other of the top select line and the bottom select line.

[0015] In an alternative embodiment, the peripheral circuit includes an analog-to-digital conversion circuit, a digital-to-analog conversion circuit, a voltage generator, a column decoder, and control logic; the analog-to-digital conversion circuit is coupled to the column decoder and the control logic; and the digital-to-analog conversion circuit is coupled to the voltage generator and the control logic.

[0016] In an alternative embodiment, the semiconductor device includes a three-dimensional NAND-type memory.

[0017] In an alternative embodiment, the semiconductor device includes a first semiconductor structure, a hybrid bonding layer, and a second semiconductor structure stacked along a thickness direction of the semiconductor device, the hybrid bonding layer being located between the first semiconductor structure and the second semiconductor structure; the memory array is located in the first semiconductor structure, the peripheral circuit is located in the second semiconductor structure, and the memory array and the peripheral circuit are coupled through bonding structures in the hybrid bonding layer.

[0018] In a second aspect, the embodiments of the present disclosure provide a system, including: at least one semiconductor device according to any one of the above embodiments; and a controller coupled to the at least one semiconductor device and configured to send input data to the semiconductor device and receive an operation result of the semiconductor device.

[0019] In a third aspect, the embodiments of the present disclosure provide an operation method of a semiconductor device, including: performing a programming operation on at least one first dummy memory cell included in a first memory string included in the semiconductor device, so that a threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold value to a first target threshold value; and wherein, in a case where the threshold voltage of the at least one first dummy memory cell reaches the first target threshold value, a difference between a current of the first memory string and a current of a second memory string included in the semiconductor device is less than or equal to a preset threshold value.

[0020] In an alternative embodiment, the operation method further includes: causing a threshold voltage of at least one second dummy memory cell included in a second memory string included in the semiconductor device to remain at the initial threshold value; and wherein, before performing the programming operation on the at least one first dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and a difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold value.

[0021] In an optional implementation, the method further includes: performing a programming operation on at least one second dummy memory cell included in the second memory string, so that a threshold voltage of the at least one second dummy memory cell is adjusted from the initial threshold to a second target threshold; and wherein, when the threshold voltage of the at least one first dummy memory cell reaches the first target threshold and the threshold voltage of the at least one second dummy memory cell reaches the second target threshold, a difference between the current of the first memory string and the current of the second memory string is less than or equal to the preset threshold.

[0022] In an optional implementation, the first target threshold is equal to the second target threshold.

[0023] In an optional implementation, the first target threshold is greater than the second target threshold; and wherein, before the programming operation is performed on the at least one first dummy memory cell and the at least one second dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and a difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold.

[0024] In an optional implementation, the method further includes: applying a read voltage to a target word line in a target memory block included in the semiconductor device; applying a first turn-on voltage to non-target word lines in the target memory block; applying a corresponding input voltage to each of a plurality of first selection lines in the target memory block; applying a second turn-on voltage to each of a plurality of second selection lines in the target memory block; and sensing a current on a bit line coupled to the target memory block to obtain a current of a memory string in the target memory block; wherein the target memory block includes the first memory string and the second memory string.

[0025] In an optional implementation, the applying of the corresponding input voltage to each of the plurality of first selection lines in the target memory block includes: applying a corresponding input voltage to a first selection line coupled to a memory string in the target memory block to turn on the memory string; and applying a corresponding input voltage to first selection lines coupled to other memory strings on the same bit line as the memory string to turn off the other memory strings.

[0026] In an optional implementation, the target memory block includes a plurality of memory cells; the memory cells are configured to store N-bit weight data, the plurality of memory cells are configured to have 2 N memory states, the read voltage is located between threshold voltage distributions corresponding to two adjacent memory states; and N is an integer greater than or equal to 1.

[0027] In a fourth aspect, the present disclosure provides a computer readable storage medium, having stored thereon a computer program, which, when executed by a processor, performs the operation method of any of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0028] FIG. 1 is a schematic diagram of a system according to an embodiment of the present disclosure;

[0029] FIG. 2 is a schematic diagram of a system according to an embodiment of the present disclosure;

[0030] FIG. 3 is a schematic diagram of a memory card according to an embodiment of the present disclosure;

[0031] FIG. 4 is a schematic diagram of a solid state disk according to an embodiment of the present disclosure;

[0032] FIG. 5 is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure;

[0033] FIG. 6 is a schematic diagram of a semiconductor device according to an embodiment of the present disclosure;

[0034] FIG. 7 is a schematic diagram of inputting a voltage from a word line to a memory block according to an embodiment of the present disclosure;

[0035] FIG. 8 is a schematic diagram of inputting a voltage from a top select line to a memory block according to an embodiment of the present disclosure;

[0036] FIG. 9 is a schematic diagram of threshold voltage distribution of a memory cell coupled to a target word line according to an embodiment of the present disclosure;

[0037] FIG. 10 is a schematic diagram of a plurality of memory cell strings coupled to one bit line according to an embodiment of the present disclosure;

[0038] FIG. 11 is a schematic diagram of measuring a current of a memory string according to an embodiment of the present disclosure;

[0039] FIG. 12 is a current-voltage curve according to an embodiment of the present disclosure;

[0040] FIG. 13 is a schematic diagram after performing a program operation on a first dummy memory cell according to an embodiment of the present disclosure;

[0041] FIG. 14 is a schematic diagram after performing a program operation on a first dummy memory cell and a second dummy memory cell according to an embodiment of the present disclosure;

[0042] FIG. 15 is a current-voltage curve according to an embodiment of the present disclosure;

[0043] FIG. 16 is a schematic diagram after performing a program operation on a first dummy memory cell and a second dummy memory cell according to an embodiment of the present disclosure;

[0044] FIG. 17 is a schematic diagram of a computer readable storage medium according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. While example embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure can be embodied in various forms without being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0046] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily complicate the present disclosure. In addition, it is to be understood that the terminology used herein is for the purpose of describing the particular embodiments only and is not intended to be limiting.

[0047] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals designate like elements throughout the specification.

[0048] It will be understood that when an element or layer is referred to as being "on" or "adjacent" another element or layer, it can be directly on the other element or layer or intervening elements or layers can also be present. In contrast, when an element is referred to as being "directly on" or "directly adjacent" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0049] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, then a dependent element or feature described as "below" or "beneath" another element or feature would then be oriented "above" and / or "over" the other element or feature. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] In order to enable a person skilled in the art to more fully understand the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present disclosure.

[0052] In a classical von Neumann computing architecture, the memory for storing data and the processor for processing data are separated, and data transmission is performed between the two through a data bus. When a data processing command is executed, the processor needs to read data from the memory first, and after processing, the updated data is written back to the memory, which requires frequent data transmission between the memory and the processor, resulting in huge power consumption and time overhead. In addition, due to the limited bandwidth of the memory, the processing speed of the processor is limited by the access speed of the memory, thereby limiting the improvement of computing performance. With the rise of application fields such as big data and artificial intelligence, the bottleneck of the von Neumann computing architecture is becoming more and more prominent due to the increasing demand for processing massive data.

[0053] In order to solve the bottleneck of the classical von Neumann computing architecture, a memory-compute integrated chip architecture emerges as the times require, and its basic idea is to directly use the memory for logical computing, thereby reducing the overhead caused by frequent data transmission between the memory and the processor, reducing power consumption while improving computing performance.

[0054] The storage-computing integrated chip has both storage capability and computing capability due to its physical characteristics. The storage capability refers to the capability of storing values by changing the conductance values of the storage units according to the physical characteristics of different types of storage units, and the computing capability refers to the capability of implementing multiply-accumulate (MAC) operations according to Ohm's law and Kirchhoff's law by constructing an array of storage units.

[0055] In some specific examples, for the storage-computing integrated chip, a weight matrix can be stored in a storage array according to a certain mapping rule by changing the conductance values of the storage units, specifically, the conductance value of each storage unit can represent a weight in the weight matrix. After the weight matrix is written into the storage array, the elements in the input vector can be mapped to the voltage values at the input ends of the storage array, for example, the input voltage of multiple elements in the input vector is mapped to multiple rows, based on Ohm's law, the current output by each storage unit in the storage array represents the result of the multiplication operation of an element in the input vector and a weight, based on Kirchhoff's law, the current output by a column of storage units is accumulated to obtain the calculation result after the multiple product results are summed, and the calculation result output by a column of storage units can correspond to an element in the output vector, and then the calculation result of the weight matrix and the input vector can be output through the storage array including multiple columns of storage units. Thus, the storage array in the storage-computing integrated chip not only stores the weight matrix to realize the storage function, but also realizes the computing function.

[0056] In some embodiments, the storage-computing integrated chip can include one of a static random access memory (SRAM), a dynamic random access memory (DRAM), a phase-change memory (PCM), a NAND flash memory, and the like. The NAND flash memory is a type of non-volatile memory, which has a large storage capacity, especially a three-dimensional NAND type memory with a three-dimensional structure, which has a high storage density and has the potential to be developed into a storage-computing integrated chip. In the following, the related content of the three-dimensional NAND type memory will be introduced.

[0057] In some embodiments, a system including a three-dimensional NAND type memory includes a semiconductor device and a controller coupled to the semiconductor device. The controller is configured to send an input vector or an input matrix to the semiconductor device and receive the operation result of the semiconductor device.

[0058] In some embodiments, the system in the above embodiments can be a system 102 as shown in FIG. 1, which includes a controller 103 and a semiconductor device 104 coupled with the controller 103.

[0059] According to some embodiments, as shown in FIG. 1, the controller 103 is coupled to the semiconductor device 104 and the host 101, and is configured to control the operation of the semiconductor device 104, such as reading, erasing, programming, computing operation.

[0060] In some other embodiments, the system in the above embodiments can be a system 100 as shown in FIG. 2, which includes a host 101 and a semiconductor device 104 that can directly communicate with the host 101, and the controller in the above embodiments can be a Central Processing Unit (CPU) in the host 101.

[0061] In one example as shown in FIG. 3, the system can be integrated into a memory card 200, and the semiconductor device in the system can be a memory device 203 in the memory card 200, and the controller in the system can be a memory controller 202 in the memory card 200. The memory card 200 can be one of a compact flash card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as Mini SD card, Micro SD card, SDHC card, etc., a universal flash storage card. The memory card 200 can further include a memory card connector 201 that couples the memory card 200 with a host. In another example as shown in FIG. 4, the system can be integrated into a solid state disk (SSD) 210, and the semiconductor device in the system can be a memory device 213 in the SSD 210, and the controller in the system can be a memory controller 212 in the SSD 210. The SSD 210 can further include a SSD connector 211 that couples the SSD 210 with a host device. In some embodiments, the storage capacity and / or operating speed of the SSD 210 is greater than that of the memory card 200.

[0062] In some embodiments, the system can be integrated in a terminal device, and the controller can be a CPU of the terminal device. Here, the terminal device can include, but is not limited to, any terminal device or portable terminal device, such as a mobile phone, a smart television, a smart speaker, a wearable device, a tablet computer, a desktop computer, an all-in-one computer, a handheld computer, a notebook computer, a server, an Ultra-Mobile Personal Computer (UMPC), a netbook, a Personal Digital Assistant (PDA), a Laptop, a mobile computer, an Augmented Reality (AR) device, a Virtual Reality (VR) device, an Artificial Intelligence (AI) device, and the like.

[0063] FIG. 5 is a schematic diagram of a semiconductor device 300, according to an embodiment of the present disclosure. The semiconductor device 300 can include a memory array 301 and a periphery circuit 302 coupled to the memory array 301. The memory array 301 is a three-dimensional NAND type memory array in which memory cells 306 are NAND memory cells provided in an array of memory strings 308, each of which extends vertically. In some implementations, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or a charge, that depends on the number of electrons captured by the memory cell 306. Each memory cell 306 can be a charge-trapping type memory cell that includes a charge-trapping transistor.

[0064] In some implementations, each memory cell 306 is a Single Level Cell (SLC) that has two possible memory states and thus can store one bit of data. For example, a first memory state “0” can correspond to a first voltage range, and a second memory state “1” can correspond to a second voltage range. In some implementations, each memory cell 306 is a Multi-Level Cell (MLC) that can store more than a single bit of data in four or more memory states, such as a two-bit-per-cell MLC, a three-bit-per-cell Triple Level Cell (TLC), or a four-bit-per-cell Quad-Level Cell (QLC).

[0065] As shown in FIG. 5, each memory string 308 can include a bottom select transistor 310 at its source end and a top select transistor 312 at its drain end. The bottom select transistor 310 and the top select transistor 312 can be configured to activate a selected memory string 308 during read and program operations. For example, during a program operation, the top select transistor 312 in a selected memory string 308 can be turned on and the top select transistor 310 in an unselected memory string 308 can be turned off, such that only the selected memory string 308 can be coupled to a bit line (BL) 316, i.e., the selected memory string 308 is activated.

[0066] In some embodiments, the sources of the memory strings 308 in the same memory block 304 can be coupled by a common source line (CSL) 314. In other words, all memory strings 308 in the same memory block 304 have a common source (ACS). According to some embodiments, the top select transistor 312 of each memory string 308 is coupled to a respective bit line 316 from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., a voltage higher than a threshold voltage of the top select transistor 312) or a deselect voltage (e.g., 0V) to the respective top select transistor 312 through one or more top select lines (TSL) 313 and / or by applying a select voltage (e.g., a voltage higher than a threshold voltage of the bottom select transistor 310) or a deselect voltage (e.g., 0V) to the respective bottom select transistor 310 through one or more bottom select lines (BSL) 315.

[0067] As shown in FIG. 5, the memory strings 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314. In some embodiments, each memory block 304 is a basic unit of data for erase operations, i.e., all memory cells 306 in the same memory block 304 are erased at the same time. To erase the memory cells 306 in a selected memory block, the common source line 314 coupled to the selected memory block and to unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage. It should be appreciated that in some examples, erase operations can be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by a read or program operation.

[0068] In some embodiments, the peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for effectuating operations on the memory array 301 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell 306 through the bit lines 316, the word lines 318, the common source lines 314, the bottom select lines 315, and the top select lines 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor technology.

[0069] FIG. 6 is a schematic diagram of a second example of a semiconductor device, according to embodiments of the disclosure. As shown in FIG. 6, the peripheral circuitry can include a page buffer / sense amplifier 321, a column decoder / bit line driver 322, a row decoder / word line driver 323, a voltage generator 324, control logic 325, registers 326, a flash interface 327, and a data bus 328.

[0070] The page buffer / sense amplifier 321 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic 325. In one example, the page buffer / sense amplifier 321 can store a page of program data (write data) to be programmed to the memory array 301. In another example, the page buffer / sense amplifier 321 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells coupled to a selected word line. In yet another example, the page buffer / sense amplifier 321 can also sense a low-power signal from a bit line representing a data bit stored in a memory cell and amplify a small voltage swing to an identifiable logic level in a read operation. The column decoder / bit line driver 322 can be configured to be controlled by the control logic 325 and select one or more memory strings by applying a bit line voltage generated from the voltage generator 324.

[0071] Row decoders / word line drivers 323 can be configured to be controlled by control logic 325 and select / deselect memory blocks of memory array 301 and select / deselect word lines of the memory blocks. Row decoders / word line drivers 323 can also be configured to drive the word lines using word line voltages generated from voltage generator 324. In some embodiments, row decoders / word line drivers 323 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, row decoders / word line drivers 323 are configured to perform program operations on memory cells coupled to selected word line(s). Voltage generator 324 can be configured to be controlled by control logic 325 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0072] Control logic 325 can be coupled to each of the circuits described above and configured to control the operation of each of the circuits. Registers 326 can be coupled to control logic 325 and include status registers, command registers, and address registers to store status information, command operation codes (OP codes), and command addresses for controlling the operation of each of the peripheral circuits. Flash interface 327 can be coupled to control logic 325 and act as a control buffer to buffer control commands received from a host device (not shown) and relay them to control logic 325, as well as buffer status information received from control logic 325 and relay them to the memory controller. Flash interface 327 can also be coupled to column decoders / bit line drivers 322 via data bus 328 and act as a data I / O interface and data buffer to buffer data and relay them to or from memory array 301.

[0073] In some embodiments, continuing to refer to FIG. 6, when a semiconductor device including a three-dimensional NAND type memory is used as an integrated chip of storage and calculation, in addition to the above-described various circuits, the peripheral circuit can further include a digital-to-analog conversion circuit 331 and an analog-to-digital conversion circuit 332. The digital-to-analog conversion circuit 331 is connected to the control logic 325 and the voltage generator 324, and the analog-to-digital conversion circuit 332 is connected to the control logic 325 and the column decoder / BL driver 322. In the calculation stage using the three-dimensional NAND type memory, the control logic 325 can receive input data transmitted by the controller, the digital-to-analog conversion circuit 331 can convert the input data into a voltage signal, and the voltage generator 324 can generate a corresponding input voltage based on the voltage signal; the analog calculation result obtained after the calculation can be transmitted to the analog-to-digital conversion circuit 332, and the analog-to-digital conversion circuit 332 can convert the analog calculation result into a digital calculation result.

[0074] In some embodiments, for an in-memory computing chip, it is required to implement the operation of input data and weight matrix, the input data can be an input vector or an input matrix composed of multiple elements, and the weight matrix is composed of multiple weights, each element in the input data needs to be multiplied and accumulated with multiple weights in the weight matrix to obtain the corresponding element in the output data.

[0075] To implement the above operation function, the memory array in the semiconductor device can be configured to store the weight matrix, specifically, the weights in the weight matrix can be written into the memory array according to a certain mapping rule, and each memory cell in the memory array can be configured to store a weight. In the inference operation phase, the semiconductor device can receive input data from the controller, the input data can be an input vector or an input matrix composed of multiple elements, and each element in the input data can be converted into an input voltage by the digital-to-analog conversion circuit and input into the memory array by the bit line or the word line.

[0076] In some specific examples, FIG. 7 is a schematic diagram of inputting the input voltage into the memory block by the word line. As shown in FIG. 7, the memory cells coupled with the target word line WLn can be configured to store the weight data in the weight matrix, specifically, the threshold voltage corresponding to the memory state of the memory cell can correspond to a weight data. The input voltage V in can be applied to the target word line WLn, and the on voltage V pass can be applied to the non-target word line coupled with the same memory block, so that the memory cells coupled with the non-target word line are all in the on state, in which case whether each memory string produces obvious current only depends on whether the threshold voltage of the memory cell coupled with the target word line WLn is greater than the input voltage V in . When the input voltage V in is greater than the threshold voltage of the memory cell, the memory string to which the memory cell belongs is turned on and produces obvious current, and when the input voltage V in is less than the threshold voltage of the memory cell, the memory string to which the memory cell belongs is turned off and does not produce obvious current, in which case the current on each bit line can be detected at the end coupled with the sensing circuit, for example, the current I0 on the bit line BL0 corresponds to the multiplication of the corresponding input data and the weights w in , w 00 , w 10 , and w 20 , and the result of the multiplication and accumulation.

[0077] In the above example, only one element in the input data and the weight matrix can be operated at a time, and the flexibility of the operation is low. When the input data is an input vector or an input matrix including multiple elements, the input voltage corresponding to the multiple elements needs to be input from the target word line WLn one by one, resulting in a long operation period and low operation efficiency. Therefore, it is necessary to further optimize the operation scheme of the semiconductor device including the three-dimensional NAND type memory.

[0078] In the embodiments of the present disclosure, the input voltage corresponding to the element in the input data can be input from the first selection line, and the first selection line can be one of the top selection line and the bottom selection line. FIG. 8 is a schematic diagram of inputting the input voltage from the top selection line to the storage block according to an embodiment of the present disclosure. FIG. 9 is a schematic diagram of the threshold voltage distribution of the storage unit coupled with the target word line according to an embodiment of the present disclosure. FIG. 10 is a schematic diagram of a plurality of storage strings coupled with one bit line according to an embodiment of the present disclosure.

[0079] In some specific examples, as shown in FIG. 8, the input voltage corresponding to the element in the input data can be input from a plurality of top selection lines. During the operation stage using the semiconductor device, a read voltage V rd The plurality of top selection lines coupled with the target storage block are respectively applied with corresponding input voltages, for example, the top selection lines TSL0, TSL1, TSL2 coupled with the target storage block are respectively applied with input voltages V in0 , V in1 , V in2 The non-target word line coupled with the target storage block is applied with a first conduction voltage, for example, the word line WLn+1 is applied with a first conduction voltage V pass1 The bottom selection line coupled with the target storage block is applied with a second conduction voltage, for example, the bottom selection line BSL is applied with a second conduction voltage V pass2 The operation result can be obtained by sensing the current on the bit line coupled with the target storage block and converting the current on the bit line, for example, by sensing the current I0 on the bit line BL0 and converting the current I0, the sum of the product of the element corresponding to the input voltage V in0 , the weight w 00 , the product of the element corresponding to the input voltage V in1 , the weight w 10 , and the product of the element corresponding to the input voltage V in2 , the weight w 20 .

[0080] In some embodiments, the target storage block includes a plurality of storage units, and the storage units can be configured to store N-bit weight data. The plurality of storage units in the target storage block are configured to have 2N a memory state, the read voltage V rd is located between threshold voltage distributions corresponding to two adjacent memory states. Here, N is an integer greater than or equal to 1.

[0081] In some specific examples, as shown in FIG. 9, taking the example that a storage cell is configured to store 1-bit weight data, a plurality of storage cells in a target storage block have a first memory state and a second memory state, the threshold voltage of a storage cell having the first memory state is less than the threshold voltage of a storage cell having the second memory state, the read voltage V rd is greater than the threshold voltage of a storage cell having the first memory state and less than the threshold voltage of a storage cell having the second memory state. Here, the storage cells in the target storage block can be single-level cells SLCs storing 1-bit data, the first memory state can be an erased state E, and the second memory state can be a programmed state P. The peripheral circuit can be configured to, before performing the operation, perform a programming operation on the storage cells coupled to the target word line, and write the weight into the storage cells according to a certain mapping rule. For a single-level cell, the process of writing the weight includes applying a corresponding programming voltage to adjust the threshold voltage of part of the storage cells coupled to the target word line to a range of the threshold voltage distribution corresponding to the second memory state.

[0082] In some embodiments, referring to FIG. 10, taking the example that a target storage block includes eight storage strings coupled to a bit line BL0, four of the storage cells coupled to the target word line WLn are in a first memory state (erased state E), and the other four storage cells are in a second memory state (programmed state P), the input data can be input from eight top selection lines TSL0 to TSL7. Specifically, the input data can be an input vector including eight elements, which can include five “1”s and three “0”s. An analog-to-digital conversion circuit can convert each element of the input vector into a corresponding voltage signal, and a voltage generator can convert the voltage signal into an input voltage needed to be applied to the top selection line, and transmit the input voltage to the top selection line through a driver coupled to the top selection line. Specifically, the eight input voltages can be applied to the eight top selection lines simultaneously. The input voltage corresponding to “1” can make the top selection transistors TSG0, TSG1, TSG4, TSG5, and TSG6 respectively coupled to the top selection lines TSL0, TSL1, TSL4, TSL5, and TSL6 conductive, and the input voltage corresponding to “0” can make the top selection transistors TSG2, TSG3, and TSG7 respectively coupled to the top selection lines TSL2, TSL3, and TSL7 non-conductive. In addition, a first conductive voltage V pass1to turn on all the memory cells coupled with the non-target word lines; and applying a second turn-on voltage V pass2 to turn on all the bottom select transistors coupled with the bottom select line BSL. In this case, the current I0 on the bit line BL0 is the sum of the output currents of the eight memory strings coupled with the bit line BL0, wherein the input voltages on the top select lines coupled with the memory strings Str0, Str4 and Str5 make the top select transistors TSG0, TSG4 and TSG5 in the turn-on state, and the memory cells coupled with the target word line WLn in the memory strings Str0, Str4 and Str5 have the first memory state (the erase state E), so that the memory strings Str0, Str4 and Str5 are turned on, and a current greater than or equal to the preset current can be generated, the current I0 on the bit line BL0 is substantially equal to the sum of the output currents of the memory strings Str0, Str4 and Str5, and the multiple of the current I0 relative to the current generated by any of the memory strings Str0, Str4 and Str5 is about 3. If the weight value stored in the memory cell in the first memory state is equivalent to "1", and the weight value stored in the memory cell in the second memory state is equivalent to "0", then the operation performed by the eight memory strings coupled with the bit line BL0 can be equivalent to: 1*1+1*0+0*1+0*0+1*1+1*1+1*0+0*0=3.

[0083] In the operation scheme provided in the above embodiment, when the memory strings coupled with the bit line BLx in the target memory block are Y+1, the Y+1 elements corresponding to the input voltages input by the Y+1 top select lines are α0, α1……α Y The weights stored in the Y+1 memory cells coupled with the target word line WLn are w0, w1……w Y The operation result equivalent to the multiple of the current on the bit line BLx relative to the output current greater than or equal to the preset current can be α 0* w0+α 1* w1+……+α Y* w Y In the multiplication accumulation operation, Y+1 multiplication operations are included, and the multipliers α0, α1……α Y are different, and for the entire target memory block, the multipliers of the multiplication operations performed by the memory strings coupled with different top select lines can be different, so that the flexibility of the operation can be improved, and a more complex operation can be realized by the semiconductor device.

[0084] In the operation scheme provided in the above embodiments, the operation result is obtained based on the current on the bit line relative to the multiple of the output current of a single memory string. When the threshold voltage of the memory cell coupled with the target word line is less than the read voltage, for example, the memory cells coupled with the target word line are all in the erased state, and the input voltage applied to the top selection line makes the top selection transistor in the on state, the difference between the output currents of different memory strings should be less than a preset threshold value, so that the operation result of the multiplication accumulation operation based on the current on the bit line is reliable. However, due to process errors in the manufacturing process, there may be certain differences in the performance of different memory strings, for example, there may be a large difference between the resistances of different memory strings, which may cause a large difference in the output current of different memory strings when they are turned on, which may reduce the reliability of the operation result.

[0085] To further improve the reliability of the semiconductor device as a memory-computing integrated chip, the present disclosure proposes the following embodiments.

[0086] The present disclosure provides a semiconductor device, comprising: a memory array; the memory array comprises a first memory string and a second memory string; the first memory string comprises at least one first dummy memory cell; a peripheral circuit coupled with the memory array and configured to: perform a programming operation on the at least one first dummy memory cell, so that the threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold value to a first target threshold value; wherein, in the case that the threshold voltage of the at least one first dummy memory cell reaches the first target threshold value, the difference between the current of the first memory string and the current of the second memory string is less than or equal to a preset threshold value.

[0087] In the embodiments of the present disclosure, in order to improve the reliability of the semiconductor device as a memory-computing integrated chip, before the semiconductor device is used for operation, the difference in current of different memory strings can be reduced by adjusting the threshold voltage of the dummy memory cell in the memory string. Here, the current of the memory string can be the current on the bit line sensed when only the memory string connected with the bit line is turned on among a plurality of memory strings connected with the bit line.

[0088] In some specific examples, as shown in FIG. 11, the memory array comprises a first memory string STR1 and a second memory string STR2, the first memory string STR1 is coupled with a bit line BL1, and the second memory string STR2 is coupled with a bit line BL2. The first memory string STR1 comprises at least one first dummy memory cell coupled with a dummy word line WLd, and the second memory string STR2 comprises at least one second dummy memory cell coupled with the dummy word line WLd.

[0089] It should be noted that in the embodiments of the present disclosure, the first storage string and the second storage string can represent two types of storage strings in the target storage block, wherein the first storage string can represent a storage string with a lower resistance and a higher corresponding current, and the second storage string can represent a storage string with a higher resistance and a lower corresponding current. Here, for ease of illustration, a first storage string STR1 and a second storage string STR2 are taken as examples, and the first storage string STR1 and the second storage string STR2 are respectively coupled to different bit lines. It can be understood that the operation performed by the peripheral circuit on the first storage string STR1 can be an operation performed on all storage strings with a lower resistance in the target storage block, and the operation performed on the second storage string STR2 can be an operation performed on all storage strings with a higher resistance in the target storage block. The first storage string STR1 and the second storage string STR2 can also be storage strings coupled to the same bit line.

[0090] In addition, in the embodiments of the present disclosure, the dummy storage unit refers to a storage unit in a storage string that is not used for storing weights. In FIG. 11, it is taken as an example that the first storage string STR1 and the second storage string STR2 each include a dummy storage unit coupled to a dummy word line WLd, and the dummy storage unit is coupled between the bit line and other storage units in the storage string, but the present disclosure is not limited thereto. In other embodiments, the dummy storage unit can be coupled between the common source and other storage units in the storage string, or the dummy storage unit can be coupled between storage units in the storage string. The present disclosure does not make specific limitations on the setting position of the dummy storage unit in the storage string and the number of dummy storage units.

[0091] In some embodiments, the current of the storage string can be measured before the programming operation is performed on the first dummy storage unit. Specifically, as shown in FIG. 11, the peripheral circuit can be configured to: apply a read voltage V rd to a target word line WLn in the target storage block; apply a first conduction voltage V pass1 to non-target word lines in the target storage block; apply a corresponding input voltage to each of a plurality of first selection lines in the target storage block; apply a second conduction voltage V pass2 to each of a plurality of second selection lines in the target storage block; and sense the current on the bit line coupled to the target storage block to obtain the current of the storage string in the target storage block. Here, the first selection line can be one of the top selection line and the bottom selection line, and the second selection line can be the other of the top selection line and the bottom selection line. The embodiments of the present disclosure take the first selection line as the top selection line and the second selection line as the bottom selection line as an example.

[0092] In the embodiments of the present disclosure, the current of the memory string can be measured by using a scheme similar to the operation phase. In this case, the memory cells coupled with the target word line WLn can all be in the first memory state (erased state), and the peripheral circuit is specifically configured to: apply a corresponding input voltage to the first selection line coupled with one memory string in the target memory block to turn on the memory string; and apply a corresponding input voltage to the first selection line coupled with other memory strings on the same bit line to turn off the other memory strings. For example, when measuring the current of the first memory string STR1, the input voltage applied to the first selection line coupled with the first memory string STR1 can turn on the top selection transistor in the first memory string STR1, and then the read voltage V rd is applied to the target word line WLn, the first turn-on voltage V pass1 is applied to the non-target word line, and the second turn-on voltage V pass2 is applied to the second selection line, the first memory string STR1 can be turned on, and only the first memory string STR1 among the plurality of memory strings coupled with the bit line BL1 is turned on. In this case, the current of the first memory string STR1 can be obtained by sensing the current on the bit line BL1.

[0093] In some embodiments, the current of each memory string in the target memory block can be measured by the above method. Taking the first memory string STR1 as a memory string with a smaller resistance and the second memory string STR2 as a memory string with a larger resistance as an example, as shown in FIG. 12, before the programming operation is performed on the at least one first dummy memory cell, the current of the first memory string STR1 is Ia, the current of the second memory string STR2 is Ib, Ia is greater than Ib, and the difference between Ia and Ib is greater than a preset threshold It, that is, the difference between the current Ia of the first memory string STR1 and the current Ib of the second memory string STR2 is large, which can affect the reliability of the operation.

[0094] In the embodiments of the present disclosure, the peripheral circuit can be configured to perform a programming operation on at least one dummy memory cell in the first memory string STR1, so that the threshold voltage of the at least one dummy memory cell is adjusted from an initial threshold value to a first target threshold value Vt1, and in the case where the threshold voltage of the at least one first dummy memory cell reaches the first target threshold value Vt1, the difference between the current of the first memory string STR1 and the current of the second memory string STR2 is less than or equal to the preset threshold It.

[0095] In a specific example, the preset threshold It should be less than Ib / 2.

[0096] In some specific examples, performing the programming operation on the at least one first dummy storage unit includes performing the programming operation on the first dummy storage unit by an increment step pulse program (ISPP) method. In the process of the increment step pulse program, a bit line voltage (for example, a ground voltage Vss) is applied to a bit line BL1 coupled with the first storage string STR1, and an increasing programming voltage is applied to a dummy word line WLd coupled with the at least one first dummy storage unit to perform the programming operation on the at least one first dummy storage unit. A difference between two adjacent programming voltages is a step length of a step pulse. Between the two adjacent programming pulses, a program verify operation is performed, a verify voltage is applied to the dummy word line WLd to confirm whether the threshold voltage of the first dummy storage unit reaches the first target threshold Vt1, and if the first dummy storage unit fails the program verify operation, the program-verify operation is continued until the threshold voltage of the first dummy storage unit reaches the first target threshold Vt1.

[0097] In some embodiments, referring to FIG. 13, in the case where the threshold voltage of the at least one first dummy storage unit in the first storage string STR1 is adjusted to the first target threshold Vt1, the threshold voltage of the at least one second dummy storage unit in the second storage string STR2 remains at the initial threshold Vt0. Here, the initial threshold Vt0 is less than the first target threshold Vt1.

[0098] In the embodiments of the present disclosure, by performing the programming operation on the at least one first dummy storage unit in the first storage string, the threshold voltage of the first dummy storage unit can be increased, the resistance of the first storage string in the on state can be increased, the current of the first storage string can be reduced, and the difference between the current of the first storage string and the current of the second storage string can be reduced, thereby the reliability of the operation result can be improved.

[0099] In some embodiments, the peripheral circuit is configured to perform a programming operation on the at least one second dummy storage unit, so that the threshold voltage of the at least one second dummy storage unit is adjusted from the initial threshold to a second target threshold Vt2; and in the case where the threshold voltage of the at least one first dummy storage unit reaches the first target threshold Vt1 and the threshold voltage of the at least one second dummy storage unit reaches the second target threshold Vt2, the difference between the current of the first storage string STR1 and the current of the second storage string STR2 is less than or equal to a preset threshold It.

[0100] In some embodiments, referring to FIG. 14, the first target threshold Vt1 is equal to the second target threshold Vt2; and the peripheral circuit is configured to perform the programming operation on the first dummy memory cell in the first memory string STR1 and the second dummy memory cell in the second memory string STR2 to adjust the threshold voltage of the first dummy memory cell and the threshold voltage of the second dummy memory cell to the first target threshold Vt1, so that the resistance of the first memory string STR1 and the second memory string STR2 can be increased simultaneously. Here, the first dummy memory cell in the first memory string STR1 and the second dummy memory cell in the second memory string STR2 can be coupled to the same dummy word line WLd, and the programming operation can be performed on the first dummy memory cell and the second dummy memory cell simultaneously.

[0101] In some specific examples, referring to FIG. 12 and FIG. 15, by increasing the threshold voltage of the dummy memory cell in the memory string to the first target threshold Vt1, the resistance of the memory string can be increased, and the current of the memory string when the read voltage V rd is applied to the target word line can be reduced. For example, the current of the first memory string STR1 is reduced from Ia to Ia', the current of the second memory string STR2 is reduced from Ib to Ib', and the difference between the current of the first memory string and the current of the second memory string can also be compressed, so that the reliability of the operation result can be improved.

[0102] In some embodiments, referring to FIG. 16, the peripheral circuit is further configured to perform the programming operation on the at least one second dummy memory cell so that the threshold voltage of the at least one second dummy memory cell reaches the second target threshold Vt2, and the first target threshold Vt1 is greater than the second target threshold Vt2.

[0103] In some specific examples, the first target threshold Vt1 and the second target threshold Vt2 are both higher than the target threshold Vt0, and the first target threshold Vt1 is within the range of the threshold voltage distribution corresponding to the programming state, and the second target threshold Vt2 can still be within the range of the threshold voltage distribution corresponding to the erasing state.

[0104] In the embodiments of the present disclosure, the programming operation can be performed on the first dummy memory cell in the first memory string and the second dummy memory cell in the second memory string to adjust the threshold voltage of the first dummy memory cell to the first target threshold and the threshold voltage of the second dummy memory cell to the second target threshold, and the first target threshold is greater than the second target threshold, so that on the basis of increasing the resistance of the first memory string and the resistance of the second memory string, the increase degree of the resistance of the first memory string which has a smaller resistance before the programming operation is performed on the first dummy memory cell and the second dummy memory cell can be greater than the increase degree of the resistance of the second memory string which has a larger resistance, so as to further reduce the difference between the current of the first memory string and the current of the second memory string and improve the reliability of the operation result.

[0105] In the embodiments of the present disclosure, before the semiconductor device is used for operation, the resistance of the storage string in the target storage block can be adjusted by the method provided in any of the above embodiments, so that the difference between the currents of different storage strings is less than the preset threshold value. Therefore, during the operation stage of the semiconductor device, the output currents of different storage strings in the on state can be substantially equal, thereby improving the reliability of the operation result of the multiplication accumulation operation based on the current on the bit line relative to the output current of a single storage string.

[0106] In some embodiments, the semiconductor device in the above embodiments includes a three-dimensional NAND type memory.

[0107] In the embodiments of the present disclosure, without making major changes to the three-dimensional NAND type memory as an integrated storage and computing chip, the semiconductor device in any of the above embodiments can be obtained, that is, without increasing the area of the circuit and chip, the effect of improving the operation precision can be achieved.

[0108] In some embodiments, the semiconductor device in the above embodiments includes a first semiconductor structure and a second semiconductor structure, the storage array is located in the first semiconductor structure, and the peripheral circuit is located in the second semiconductor structure. The first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device.

[0109] In some embodiments, the semiconductor device includes a first semiconductor structure, a hybrid bonding layer, and a second semiconductor structure stacked along the thickness direction of the semiconductor device. The storage array is located in the first semiconductor structure, and the peripheral circuit is located in the second semiconductor structure. The peripheral circuit and the storage array are coupled through the bonding structure in the hybrid bonding layer.

[0110] In the embodiments of the present disclosure, the first semiconductor structure and the second semiconductor structure of the semiconductor device can be formed by bonding two wafers, for example, the first semiconductor structure can be formed on one wafer, the second semiconductor structure can be formed on another wafer, and then the two wafers are bonded to form the hybrid bonding layer between the first semiconductor structure and the second semiconductor structure. In other embodiments, the first semiconductor structure and the second semiconductor structure of the semiconductor device can also be formed on the same wafer, but the first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device. The architecture of stacking the first semiconductor structure and the second semiconductor structure along the thickness direction of the semiconductor device can save the area of the semiconductor device.

[0111] Based on a similar concept as the foregoing semiconductor device, the present disclosure further provides a system, comprising: at least one semiconductor device as described in any of the foregoing embodiments; and a controller coupled to the at least one semiconductor device and configured to send input data to the semiconductor device and receive an operation result of the semiconductor device.

[0112] In some embodiments, the operation result of the semiconductor device can be the operation result based on the current on the bit line in the foregoing embodiments.

[0113] In some other embodiments, the peripheral circuit in the semiconductor device can be further configured to perform a logical operation on the operation result based on the current on the bit line, and the operation result of the semiconductor device can be the operation result obtained by performing a logical operation again on the operation result based on the current on the bit line in the foregoing embodiments.

[0114] In some embodiments, the specific components and functional implementations of the system can refer to the descriptions of FIGS. 1-6 in the foregoing, which will not be repeated here for brevity.

[0115] Based on a similar concept as the foregoing semiconductor device, the present disclosure further provides a method for operating a semiconductor device, comprising: performing a programming operation on at least one first dummy memory cell included in a first memory string included in the semiconductor device, so that a threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold value to a first target threshold value; wherein, in a case where the threshold voltage of the at least one first dummy memory cell reaches the first target threshold value, a difference between a current of the first memory string and a current of a second memory string included in the semiconductor device is less than or equal to a preset threshold value.

[0116] In some embodiments, the method further comprises: causing a threshold voltage of at least one second dummy memory cell included in a second memory string included in the semiconductor device to remain at the initial threshold value; wherein, before performing the programming operation on the at least one first dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and a difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold value.

[0117] In some embodiments, the method further comprises: performing a programming operation on at least one second dummy memory cell included in the second memory string, so that a threshold voltage of the at least one second dummy memory cell is adjusted from the initial threshold value to a second target threshold value; wherein, in a case where the threshold voltage of the at least one first dummy memory cell reaches the first target threshold value and the threshold voltage of the at least one second dummy memory cell reaches the second target threshold value, a difference between the current of the first memory string and the current of the second memory string is less than or equal to the preset threshold value.

[0118] In some embodiments, the first target threshold is equal to the second target threshold.

[0119] In some embodiments, the first target threshold is greater than the second target threshold; wherein, before performing the programming operation on the at least one first dummy memory cell and the at least one second dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and the difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold.

[0120] In some embodiments, the operation method further comprises: applying a read voltage to a target word line in a target memory block included in the semiconductor device; applying a first turn-on voltage to a non-target word line in the target memory block; applying a respective input voltage to each of a plurality of first selection lines in the target memory block; applying a second turn-on voltage to each of a plurality of second selection lines in the target memory block; and sensing a current on a bit line coupled to the target memory block to obtain a current of a memory string in the target memory block; wherein the target memory block includes the first memory string and the second memory string.

[0121] In some embodiments, the applying a respective input voltage to each of the plurality of first selection lines in the target memory block comprises: applying a respective input voltage to a first selection line coupled to a memory string in the target memory block to turn on the memory string; and applying a respective input voltage to a first selection line coupled to another memory string on the same bit line as the memory string to turn off the another memory string.

[0122] In some embodiments, the target memory block includes a plurality of memory cells; each memory cell is configured to store N-bit weight data, and the plurality of memory cells are configured to have 2 N memory states, the read voltage is located between threshold voltage distributions corresponding to two adjacent memory states; N is an integer greater than or equal to 1.

[0123] Based on the similar concept as the operation method of the semiconductor device described above, the present disclosure also provides a computer readable storage medium, and FIG. 17 is a schematic diagram of the computer readable storage medium provided by an embodiment of the present disclosure. The computer readable storage medium 501 stores a computer program, and when the computer program is executed by a processor 502, the operation method of the semiconductor device in any of the above embodiments can be implemented.

[0124] In some embodiments, the computer readable storage medium 501 can be a ferromagnetic random access memory (FRAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), and the like. It can also be various devices including one or any combination of the above memory devices.

[0125] It should be understood that all the technical and structural features mentioned in the specification are meant to be included in at least one of the embodiments of the present disclosure. Therefore, the "in an embodiment" or "in one embodiment" appearing throughout the specification does not necessarily mean the same embodiment. In addition, these specific features, structures or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the size of the sequence number of each process in various embodiments of the present disclosure does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence number of the above embodiments of the present disclosure is only for description, not representing the advantages or disadvantages of the embodiments.

[0126] The features disclosed in several device embodiments provided by the present disclosure can be combined in any suitable manner without conflict, to obtain new device embodiments.

[0127] The methods disclosed in several method embodiments provided by the present disclosure can be combined in any suitable manner without conflict, to obtain new method embodiments.

[0128] The above is merely specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Industrial applicability

[0129] In the technical solutions provided in the present disclosure, the peripheral circuit is configured to adjust the resistance of the storage string by adjusting the threshold voltage of the dummy storage unit in the storage string, so that the difference between the currents of different storage strings is less than a preset threshold value, thereby the output currents of different storage strings in the on state can be substantially equal during the operation stage using the semiconductor device, and the reliability of the operation result of the multiplication accumulation operation based on the multiple of the current on the bit line relative to the output current of a single storage string can be improved.

Claims

1. A semiconductor device, comprising: a memory array; the memory array comprises a first memory string and a second memory string; the first memory string comprises at least one first dummy memory cell; a peripheral circuit coupled to the memory array and configured to perform a programming operation on the at least one first dummy memory cell so that a threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold to a first target threshold; wherein, in a case that the threshold voltage of the at least one first dummy memory cell reaches the first target threshold, a difference between a current of the first memory string and a current of the second memory string is less than or equal to a preset threshold.

2. The semiconductor device of claim 1, wherein, the second memory string comprises at least one second dummy memory cell; the threshold voltage of the at least one second dummy memory cell remains at the initial threshold; wherein, before the programming operation is performed on the at least one first dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and a difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold.

3. The semiconductor device of claim 1, wherein, the second memory string comprises at least one second dummy memory cell; the peripheral circuit is configured to: perform a programming operation on the at least one second dummy memory cell so that a threshold voltage of the at least one second dummy memory cell is adjusted from the initial threshold to a second target threshold; wherein, in a case that the threshold voltage of the at least one first dummy memory cell reaches the first target threshold and the threshold voltage of the at least one second dummy memory cell reaches the second target threshold, the difference between the current of the first memory string and the current of the second memory string is less than or equal to the preset threshold.

4. The semiconductor device of claim 3, wherein, the first target threshold is equal to the second target threshold.

5. The semiconductor device of claim 3, wherein, the first target threshold is greater than the second target threshold; wherein, before the programming operation is performed on the at least one first dummy memory cell and the at least one second dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and the difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold.

6. The semiconductor device of claim 1, wherein, the peripheral circuit is further configured to: apply a read voltage to a target word line in a target memory block; apply a first turn-on voltage to a non-target word line in the target memory block; apply a corresponding input voltage to each of a plurality of first select lines in the target memory block; apply a second turn-on voltage to each of a plurality of second select lines in the target memory block; sense a current on a bit line coupled to the target memory block to obtain a current of a memory string in the target memory block; wherein the target memory block comprises the first memory string and the second memory string.

7. The semiconductor device of claim 6, wherein, the peripheral circuit is specifically configured to: apply a corresponding input voltage to a first select line coupled to one memory string in the target memory block to turn on the memory string; apply a corresponding input voltage to a first select line coupled to other memory strings on the same bit line as the memory string to turn off the other memory strings.

8. The semiconductor device of claim 6, wherein, The target memory block includes a plurality of memory cells; the memory cells are configured to store N-bit weight data, a plurality of memory cells in the target memory block are configured to have 2 N memory states, the read voltage is located between threshold voltage distributions corresponding to two adjacent memory states; N is an integer greater than or equal to 1.

9. The semiconductor device of claim 6, wherein, The first selection line is one of a top selection line and a bottom selection line, and the second selection line is the other of the top selection line and the bottom selection line.

10. The semiconductor device of claim 1, wherein, The peripheral circuit includes an analog-to-digital conversion circuit, a digital-to-analog conversion circuit, a voltage generator, a column decoder, and control logic; the analog-to-digital conversion circuit is coupled to the column decoder and the control logic; and the digital-to-analog conversion circuit is coupled to the voltage generator and the control logic.

11. The semiconductor device of claim 1, wherein, The semiconductor device includes a three-dimensional NAND-type memory.

12. The semiconductor device of claim 1, wherein, The semiconductor device includes a first semiconductor structure, a hybrid bonding layer, and a second semiconductor structure stacked along a thickness direction of the semiconductor device, the hybrid bonding layer being located between the first semiconductor structure and the second semiconductor structure; the memory array is located in the first semiconductor structure, the peripheral circuit is located in the second semiconductor structure, and the memory array and the peripheral circuit are coupled through bonding structures in the hybrid bonding layer.

13. A system comprising: At least one semiconductor device as claimed in any one of claims 1 to 12; A controller coupled to the at least one semiconductor device and configured to send input data to the semiconductor device and receive an operation result of the semiconductor device.

14. An operating method of a semiconductor device, comprising: performing a programming operation on at least one first dummy memory cell included in a first memory string included in the semiconductor device, so that a threshold voltage of the at least one first dummy memory cell is adjusted from an initial threshold value to a first target threshold value; wherein, in a case where the threshold voltage of the at least one first dummy memory cell reaches the first target threshold value, a difference between a current of the first memory string and a current of a second memory string included in the semiconductor device is less than or equal to a preset threshold value.

15. The method of operation of claim 14, wherein, The operating method further comprises: so that a threshold voltage of at least one second dummy memory cell included in a second memory string included in the semiconductor device remains at the initial threshold value; wherein, before the programming operation is performed on the at least one first dummy memory cell, the current of the first memory string is greater than the current of the second memory string, and a difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold value.

16. The method of operation of claim 14, wherein, The operating method further comprises: performing a programming operation on at least one second dummy memory cell included in the second memory string, so that a threshold voltage of the at least one second dummy memory cell is adjusted from the initial threshold value to a second target threshold value; wherein, in a case where the threshold voltage of the at least one first dummy memory cell reaches the first target threshold value and the threshold voltage of the at least one second dummy memory cell reaches the second target threshold value, the difference between the current of the first memory string and the current of the second memory string is less than or equal to the preset threshold value.

17. The method of operation of claim 16, wherein, The first target threshold value is equal to the second target threshold value.

18. The method of operation of claim 16, wherein, The first target threshold is greater than the second target threshold; wherein, before performing the programming operation on the at least one first dummy memory cell and the at least one second dummy memory cell, a current of the first memory string is greater than a current of the second memory string, and a difference between the current of the first memory string and the current of the second memory string is greater than the preset threshold.

19. The method of operation of claim 14, wherein, The operation method further comprises: applying a read voltage to a target word line in a target memory block included in the semiconductor device; applying a first turn-on voltage to a non-target word line in the target memory block; applying a corresponding input voltage to each of a plurality of first selection lines in the target memory block; applying a second turn-on voltage to each of a plurality of second selection lines in the target memory block; sensing a current on a bit line coupled to the target memory block to obtain a current of a memory string in the target memory block; wherein the target memory block includes the first memory string and the second memory string.

20. The method of operating according to claim 19, wherein, The applying a corresponding input voltage to each of the plurality of first selection lines in the target memory block comprises: applying a corresponding input voltage to a first selection line coupled to one memory string in the target memory block to turn on the memory string; and applying a corresponding input voltage to a first selection line coupled to other memory strings on a same bit line as the memory string to turn off the other memory strings.

21. The method of operating of claim 19, wherein, The target memory block includes a plurality of memory cells; the memory cells are configured to store N-bit weight data, the plurality of memory cells are configured to have 2 N memory states, the read voltage is located between threshold voltage distributions corresponding to two adjacent memory states; N is an integer greater than or equal to 1. 22.A computer readable storage medium having stored thereon a computer program, the computer program being executed by a processor to perform the operation method of any one of claims 14 to 21.

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