Photoelectric conversion apparatus and electronic device

Abstract

The present invention relates to the technical field of photoelectric sensors. Disclosed are a photoelectric conversion apparatus and an electronic device. The photoelectric conversion apparatus comprises an SPAD device, a quenching module, a counting module, a time-to-analog conversion module, and a data processing module. The data processing module is configured to, when a count value is not greater than a preset value, use the count value to characterize the ambient light intensity; and when the count value is greater than the preset value, calculate, on the basis of an accumulated value of an analog voltage, an average voltage corresponding to an average value of pulse widths of electrical signal pulses within an entire exposure period, and use the average voltage to characterize the ambient light intensity. The present invention employs a scheme in which the counting module is first used to count the number of photons received by the SPAD device, and when the count value reaches the preset value, the time-to-analog conversion module is switched to characterize the ambient light intensity, thereby expanding the dynamic range of photon detection without increasing power consumption. As a result, photons can be accurately detected under both low and high light intensity conditions, and inaccurate counting caused by counter saturation due to an increase in light intensity is avoided.

Description

Photoelectric conversion device and electronic device TECHNICAL FIELD

[0001] The present application relates to the technical field of photoelectric imaging sensors, and particularly relates to a photoelectric conversion device and an electronic device. BACKGROUND

[0002] The SPAD device (Single Photon Avalanche Diode) in the photoelectric imaging sensor usually adopts a passive quenching mode, as shown in FIG. 1. When the SPAD device 201 detects a photon, avalanche multiplication occurs. Since the resistance of the quenching device 202 is much greater than the resistance of the SPAD device 201 in the avalanche state, the VC point starts to discharge, causing the VC voltage to drop. When the VC voltage is lower than the judgment threshold, the VO voltage starts to rise.

[0003] As shown in FIGS. 2 and 3, from time t0 to time t1, the voltage difference "VH-VL" is applied to the SPAD device 201 in FIG. 1. At time t1, when a photon is incident on the SPAD device 201, avalanche multiplication occurs in the SPAD device 201 to cause avalanche multiplication current to flow in the quenching element 202, causing the voltage of the VC to drop. If the voltage drop further increases, and the voltage difference applied to the SPAD device 201 becomes smaller, the avalanche multiplication of the SPAD device 201 stops at time t2, and the voltage level of the VC point does not drop below a predetermined value. Then, between time t2 and time t3, current flows from voltage VL to VC to constitute a voltage drop, and at time t3, the potential level of the VC point is statically stabilized to the original potential level. At this time, in the case that the output waveform of the VC point exceeds the threshold value, the output waveform is shaped by the waveform shaping unit 210, and is output as a signal to VO. At this time, the VO point is finally output in the form of a pulse voltage (as shown in FIG. 3), and if the VO point is connected to a counter, photon counting can be performed, that is, the number of pulse voltages is recorded.

[0004] As shown in FIG. 5, under low light intensity, only 3 photons are present, when the SPAD device 201 receives 3 photons, the counter counts three pulses accordingly. But as shown in FIG. 6, under high light intensity, although about 20 photons are incident, only 3 pulses are counted, the count value is small, although the photon irradiation continues, the VC point voltage continues to be lower than the threshold voltage, VO does not generate a pulse signal, it can be seen that during the high level of each clock cycle of the clock signal, only the first triggered photon can be responded, so the count value is less than the actual number of photons. Therefore, as shown in FIG. 4, after the light intensity reaches a certain value, the value represented by the count value actually decreases, the count value and the light intensity value cannot be one-to-one corresponding, in this case, the SPAD device cannot obtain the correct count value, and the count value of the counter is easily saturated, and the subsequent photons cannot be counted.

[0005] At present, in a strong light environment, the dynamic range of the SPAD is usually increased by increasing the number of bits of the counter and the clock frequency, but this way will significantly increase the power consumption of the photoelectric sensor chip, which is not conducive to the development of the SPAD image sensor. SUMMARY

[0006] In view of the above deficiencies of the prior art, the purpose of the present application is to provide a photoelectric conversion device and electronic equipment to solve the problem that the count value of the existing photoelectric sensor is inaccurate in a strong light environment.

[0007] To solve the above technical problems, the present application adopts the following technical solutions:

[0008] A photoelectric conversion device, comprising a SPAD device, a quenching module, a counting module, a time analog conversion module and a data processing module;

[0009] The quenching module is used for switching the working state according to the clock signal, when the quenching module is in the on state, the SPAD device is charged to the power supply voltage, and when the quenching module is in the off state, the SPAD device waits to receive photon trigger;

[0010] The SPAD device is used for generating an electrical signal pulse according to the first received photon signal in each clock cycle during the exposure period;

[0011] The counting module is used for counting the number of electrical signal pulses output by the SPAD device to obtain a count value;

[0012] The time analog conversion module is used for converting the pulse width value of the electrical signal pulse in all clock cycles to an accumulated value of an analog voltage;

[0013] The data processing module is configured to use the count value to represent the ambient light intensity when the count value is not greater than a preset value, and to calculate an average voltage corresponding to an average value of the pulse width of the electrical signal pulse during the entire exposure period according to the cumulative value of the analog voltage, and use the average voltage to represent the ambient light intensity when the count value is greater than the preset value.

[0014] In the photoelectric conversion device, the preset value is less than a maximum value of the counter.

[0015] In the photoelectric conversion device, when the SPAD device receives a photon signal during a high level of the clock signal, the electrical signal pulse is at a high level.

[0016] The pulse width value of the electrical signal pulse is a time length between a first time point at which the SPAD device is triggered by a photon for the first time in each clock cycle and a second time point at which the clock signal falls.

[0017] In the photoelectric conversion device, a proportion of the high level of the clock signal in a clock cycle is at least 80%.

[0018] In the photoelectric conversion device, the time-to-analog conversion module includes a first PMOS transistor, a first NMOS transistor, a second NMOS transistor and a first capacitor, a gate of the first PMOS transistor is connected to an external bias power supply, a source of the first PMOS transistor is connected to a power supply end, a drain of the first PMOS transistor is connected to a drain of the first NMOS transistor, a gate of the first NMOS transistor is connected to an output end of the SPAD device, a source of the first NMOS transistor is connected to one end of the first capacitor, an input end of the data processing module and a drain of the second NMOS transistor, a source of the second NMOS transistor and the other end of the first capacitor are grounded, and a gate of the second NMOS transistor is connected to a first external control end.

[0019] The external bias power supply controls the first PMOS transistor to be continuously turned on to provide a charging current for the first capacitor; when the SPAD device receives a photon at the beginning of exposure, the output of the SPAD device controls the first NMOS transistor to be turned on to charge the first capacitor, and the second NMOS transistor is disconnected at this time; at the end of exposure, the output of the SPAD device controls the first NMOS transistor to be disconnected, and the second NMOS transistor is turned on at this time to release the charge of the first capacitor, and the next exposure is waited.

[0020] In the photoelectric conversion device, the average value of the pulse width of the electrical signal pulse during the entire exposure period is calculated according to the cumulative value of the analog voltage, and specifically includes:

[0021] The average voltage of the analog voltage corresponding to the pulse width of the electrical signal pulse is obtained by dividing the change value of the voltage of the first capacitor before and after exposure by the number of the electrical signal pulses.

[0022] In the photoelectric conversion device, the time analog conversion module comprises a D flip-flop, an inverter, a buffer, a second PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a second capacitor and a third capacitor, the input end of the D flip-flop is connected with the output end of the SPAD device, the clock pulse input end of the D flip-flop is connected with the trigger clock, the output end of the D flip-flop is connected with the gate of the third NMOS tube, the input end of the inverter and the input end of the buffer, the output end of the inverter is connected with the reset end of the D flip-flop, the output end of the buffer is connected with the gate of the fifth NMOS tube, the gate of the second PMOS tube is connected with the second external control end, the source of the second PMOS tube is connected with the power supply end, the drain of the second PMOS tube is connected with the drain of the third NMOS tube and one end of the second capacitor, the source of the third NMOS tube is connected with the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected with the third external control end, the source of the fourth NMOS tube is connected with the drain of the fifth NMOS tube and one end of the third capacitor, and the source of the fifth NMOS tube, the other end of the second capacitor and the other end of the third capacitor are all grounded.

[0023] The clock frequency of the trigger clock is n times of the clock signal, before the exposure starts, the second external control end controls the second PMOS tube to be turned on, and the power supply end charges the second capacitor.

[0024] After the exposure starts, the fourth NMOS tube is turned on, the second external control end controls the second PMOS tube to be turned off, when the electrical signal pulse is in the high level period, the D flip-flop outputs a high level signal to make the third NMOS tube be turned on at each rising edge of the trigger clock, at this time, the charge of the second capacitor is discharged to the third capacitor through the third NMOS tube and the fourth NMOS tube, and the fifth NMOS tube is turned off at this time; the high level signal output by the D flip-flop is inverted by the inverter and used as the reset signal of the D flip-flop, the output of the D flip-flop is reset to a low level signal to make the third NMOS tube be turned off, at this time, the fifth NMOS tube is turned on, and the charge of the third capacitor is discharged to the ground, and the charge on the second capacitor is continuously discharged according to the high level of the electrical signal pulse during the exposure.

[0025] In the photoelectric conversion device, the clock frequency of the trigger clock is 5 times of the clock signal, and the trigger clock has 1-4 rising edges to make the third NMOS tube be turned on 1-4 times when the electrical signal pulse is in the high level period.

[0026] In the photoelectric conversion device, the capacitance of the second capacitor is M times of the capacitance of the third capacitor, and M is greater than the number of the electrical signal pulses during the exposure.

[0027] In the photoelectric conversion device, the average value of the pulse width of the electric signal during the whole exposure period is calculated according to the cumulative value of the analog voltage, and specifically comprises:

[0028] The average value of the pulse width of the electric signal is obtained by dividing the change value of the second capacitor voltage before and after exposure by a coefficient, and the coefficient is related to the number of the electric signal pulses and the clock frequency of the trigger clock which is a multiple of the clock signal.

[0029] The application also provides an electronic device, characterized by comprising the photoelectric conversion device as described above.

[0030] Compared with the prior art, the photoelectric conversion device and the electronic device provided by the application use a counting module to count the number of photons received by the SPAD device first, and when the counting value reaches a set value, the time analog conversion module is switched to represent the ambient light intensity, which realizes the expansion of the dynamic range of photon detection without increasing the power consumption, so that photons can be detected at low and high light intensities, and the situation of inaccurate counting caused by the saturation of the counter due to the increase of light intensity is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0031] FIG. 1 is a circuit diagram of a photoelectric sensor of the prior art.

[0032] FIG. 2 is a voltage waveform diagram of the VC point when the SPAD device avalanches in the photoelectric sensor of the prior art.

[0033] FIG. 3 is a voltage waveform diagram of the VO point when the SPAD device avalanches in the photoelectric sensor of the prior art.

[0034] FIG. 4 is a light intensity diagram.

[0035] FIG. 5 is a counting diagram of the photons received by the SPAD device under low light intensity in the photoelectric sensor of the prior art.

[0036] FIG. 6 is a counting diagram of the photons received by the SPAD device under high light intensity in the photoelectric sensor of the prior art.

[0037] FIG. 7 is a structural block diagram of the photoelectric conversion device provided by the application.

[0038] FIG. 8 is a waveform correspondence diagram of the clock signal, the electric signal pulse, the counting value and the output pulse width value of the time analog conversion module in the photoelectric conversion device provided by the application.

[0039] FIG. 9 is a waveform diagram of the photoelectric conversion device provided by the application using the counting module and the time analog conversion module to represent the light intensity, respectively.

[0040] FIG. 10 is a circuit diagram of one embodiment of the time analog conversion module in the photoelectric conversion device provided by the application.

[0041] Fig. 11 is a schematic diagram of voltage waveforms of VO and VC1 in Fig. 10.

[0042] Fig. 12 is a circuit diagram of another embodiment of the time-to-analog conversion module in the photoelectric conversion device provided by the present application.

[0043] Fig. 13 is a schematic diagram of voltage waveforms of VO, V TRG , V Dis , and VC2 in Fig. 12.

[0044] Legend SPAD device 11, quenching module 12, counting module 13, time-to-analog conversion module 14, data processing module 15, first PMOS transistor Q1, first NMOS transistor Q2, second NMOS transistor Q3, first capacitor C1, D flip-flop U1, inverter INVT, buffer A1, second PMOS transistor Q4, third NMOS transistor Q5, fourth NMOS transistor Q6, fifth NMOS transistor Q7, second capacitor C2, third capacitor C3 Best Mode for Carrying Out the Invention

[0045] The application provides a photoelectric conversion device, comprising a SPAD device, a quenching module, a counting module, a time analog conversion module and a data processing module; the quenching module is used for switching the working state according to a clock signal, when the quenching module is in a conduction state, the SPAD device is charged to a power supply voltage, and when the quenching module is in a non-conduction state, the SPAD device waits for receiving a photon trigger. The SPAD device is used for generating an electrical signal pulse according to a first received photon signal in each clock cycle during an exposure period. The logic module is an input reverse AND gate, the cathode voltage of the SPAD is denoted as VC, and the clock signal clk_R and VC are input into the AND gate. When a photon is incident on the SPAD, the value of VC is converted from a high level to a low level. The counting module is used for counting the number of the electrical signal pulses VO output by the SPAD device, to obtain a counting value. The time analog conversion module is used for converting the pulse width value Ti of the electrical signal pulse VO in all clock cycles into an accumulated value Vn of an analog voltage. The data processing module is used for representing the ambient light intensity by the counting value when the counting value is not greater than a preset value, and is used for calculating the average value of the electrical signal pulse VO pulse width in the entire exposure period according to the accumulated value Vn of the analog voltage when the counting value is greater than the preset value, converting the average value of the pulse width into an average voltage Vi, and representing the ambient light intensity by the average voltage Vi. The application adopts the mode that the counting module is used for counting the number of the photons received by the SPAD device first, and the time analog conversion module is switched to represent the ambient light intensity when the counting value reaches a set value, so that the dynamic range of the photon detection is expanded without increasing the power consumption, the photons can be detected when the light intensity is low or high, and the situation that the counter is saturated due to the increase of the light intensity and the inaccuracy of the counting are avoided. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical scheme and advantages of the application clearer, the application is further described in detail below with reference to the drawings and examples. It should be understood that the specific examples described herein are only used to explain the application, and are not used to limit the application.

[0047] Referring to Fig. 7, the photoelectric conversion device provided by the application mainly comprises a SPAD device 11, a quenching module 12, a counting module 13, a time-to-analog conversion module 14 and a data processing module 15. The cathode of the SPAD device 11 is connected to a power supply end (such as a VDD power supply) through the quenching module 12 and is also connected to an input end of a logic module, and the anode of the SPAD device 11 is grounded. An external clock source is connected to another input end of the logic module and is connected to a clock pulse input end STOP of the time-to-analog conversion module 14. The output end of the logic module is connected to an input end of the counting module 13 and a control input end START of the time-to-analog conversion module 14. The output end of the counting module 13 and the output end of the time-to-analog conversion module 14 are connected to an input end of the data processing module 15.

[0048] The quenching module 12 is used to switch the working state according to the clock signal. When the quenching module 12 is in a conduction state, the SPAD device 11 is charged to the power supply voltage (i.e. the voltage VDD of the power supply end). When the quenching module 12 is in a non-conduction state, the SPAD device 11 waits to receive a photon trigger. In an embodiment, the quenching module is a PMOS tube.

[0049] The SPAD device 11 is used to generate an electrical signal pulse VO according to the first received photon signal in each clock cycle during the exposure period.

[0050] In an embodiment, the logic module is an input-reversed AND gate as shown in Fig. 7. The cathode voltage of the SPAD is denoted as VC, and the clock signal clk_R and VC are input into the AND gate. When a photon is incident on the SPAD, the value of VC changes from high to low. In this case, when the clock signal clk_R is at a high level, the output VO of the logic module becomes high. Then, in the case where the clock signal clk_R changes from high to low, the output VO of the logic module changes to low, thereby generating an output signal, i.e. the electrical signal pulse VO.

[0051] The counting module 13 is used to count the number of the electrical signal pulses VO output by the SPAD device 11 to obtain a count value. The counting module 13 is a counter used in the existing SPAD image sensor, which is a prior art and will not be described in detail here.

[0052] The time-to-analog conversion module 14 is used to convert the pulse width values Ti (such as T1 and T2 in Fig. 8) of the electrical signal pulses VO in all clock cycles into an accumulated value Vn of an analog voltage. Referring to Fig. 8, in the photoelectric conversion device provided by the application, the pulse width value of the electrical signal pulse VO is represented as a time signal, i.e. the length of time during which the high level lasts in one cycle of the electrical signal pulse VO.

[0053] The data processing module 15 is configured to represent the ambient light intensity by the count value when the count value is not greater than a preset value, and to calculate an average value of the pulse width of the electrical signal pulse VO during the entire exposure period according to the cumulative value Vn of the analog voltage, convert the average value of the pulse width into an average voltage Vi, and represent the ambient light intensity by the average voltage Vi when the count value is greater than the preset value.

[0054] The application adopts the mode of counting the number of photons received by the SPAD device 11 by the counting module 13 first, and switching to the time-analog conversion module 14 to represent the ambient light intensity when the count value reaches the set value, so as to expand the dynamic range of the ambient light intensity detection without increasing the power consumption, i.e. the photoelectric conversion device can represent the light intensity value under weak light and strong light. That is, the count value is counted by the counting module 13 when the count value is not greater than the preset value (i.e. under low light intensity), and the ambient light intensity is represented by the average value of the electrical signal pulse during the entire exposure period by the time-analog conversion module 14 when the count value is greater than the preset value. The combination of the two modes can obtain a larger dynamic range with low power consumption.

[0055] As shown in FIG. 9, the dynamic range DR1 is represented by the count value (counter) provided by the counting module 13, but the counting module 13 is saturated, i.e. full, when the light intensity reaches a certain value. The application switches to the time-analog conversion module 14 to work before the counting module is saturated. The dynamic range DR2 in FIG. 9 is represented according to the analog voltage value output by the time-analog conversion module 14. As can be seen from FIG. 9, the dynamic range of the SPAD detection photon can be increased by the combination of the counting module 13 and the time-analog conversion module 14. The light intensity is represented by the count value of the counting module under weak light to ensure accuracy, and the light intensity is represented by the analog voltage output by the time-analog conversion module under strong light to expand the detection range.

[0056] In an optional embodiment, the preset value is less than the maximum value of the counter. For example, the maximum count value of the counting module 13 can be 1024, and the preset value can be 1000. When the count value of the counter reaches 1000, the data processing module calculates the voltage value Vi corresponding to the average value of the pulse width of the electrical signal pulse VO during the entire exposure period according to the cumulative value Vn of the analog voltage output by the time-analog conversion module 14, and outputs Vi to represent the ambient light intensity, so as to expand the dynamic range of the photon detection without increasing the power consumption, i.e. the ambient light intensity can be detected under strong light and weak light.

[0057] As shown in FIG. 8, in the time-to-analog conversion module 14, during the period when the clock signal is at high level, the electric signal pulse VO outputted by the time-to-analog conversion module 14 is converted from low level to high level when the SPAD device 11 receives the first photon signal; the pulse width value Ti of the electric signal pulse VO is the time length between the first time point when the SPAD device 11 is triggered by the photon for the first time and the second time point when the clock signal falls within each clock cycle.

[0058] However, the light intensity is not accurately represented by the electric signal pulse VO within one clock cycle, and the pulse width values T1-Tn corresponding to the high level periods of the electric signal pulse VO_1-VO_n within the entire clock cycle during the exposure are obtained when the exposure is completed, and the pulse width average value is obtained by averaging, and the stronger the light is, the greater the pulse width average value is. The pulse width average value reflects the light intensity, and thus the voltage corresponding to the pulse width average value has a linear relationship with the light intensity, and the light intensity value can be obtained by calculating the voltage corresponding to the pulse width average value.

[0059] In an optional embodiment, the proportion of the high level of the clock signal provided by the clock source in the clock cycle is at least 80%, for example, the high level accounts for 90% and the low level accounts for only 10% in one clock cycle, so as to make the high level time as long as possible to receive more photons and improve the accuracy of counting.

[0060] Please refer to FIG. 10 and FIG. 11, in an optional embodiment of the photoelectric conversion device, the time-to-analog conversion module 14 includes a first PMOS tube Q1, a first NMOS tube Q2, a second NMOS tube Q3 and a first capacitor C1, the MOS tube is turned on when the gate of the first PMOS tube Q1 is at low level, and the MOS tube is turned on when the gates of the first NMOS tube Q2 and the second NMOS tube Q3 are at high level.

[0061] The gate of the first PMOS tube Q1 is connected to an external bias power supply Vbias, the source of the first PMOS tube Q1 is connected to a power supply end VDD, the drain of the first PMOS tube Q1 is connected to the drain of the first NMOS tube Q2, the gate of the first NMOS tube Q2 is connected to the output end of the SPAD device 11, the source of the first NMOS tube Q2 is connected to one end of the first capacitor C1, the input end of the data processing module 15 and the drain of the second NMOS tube Q3, the source of the second NMOS tube Q3 and the other end of the first capacitor C1 are grounded, and the gate of the second NMOS tube Q3 is connected to a first external control end VR. The external bias power supply Vbias and the first external control end VR can be provided by a chip or a switch, and the provision mode is not the protection point of the present application, which is not described in detail here.

[0062] If a photon reaches the SPAD device 11 during the high level of clk_R, when the SPAD device 11 receives the photon, the first NMOS tube Q2 is turned on and the second NMOS tube Q3 is turned off to charge the first capacitor C1, when the exposure ends, the second NMOS tube Q3 is turned on and the first NMOS tube Q2 is turned off to release the charge of the first capacitor C1, and the next exposure is waited.

[0063] In the embodiment, the first PMOS tube Q1 is used to provide a charging current for the first capacitor C1, during the exposure period, the first PMOS tube Q1 is continuously turned on to provide a charging current for the first capacitor C1, the first PMOS tube is controlled to be continuously turned on by an external bias power supply Vbias, and the size of the charging current can be controlled, and is denoted as I, the first NMOS tube Q2 and the second NMOS tube Q3 both act as switches, whether the first NMOS tube Q2 is turned on is controlled by the high and low level states of the electrical signal pulse VO, when the electrical signal pulse VO is at a high level, the first NMOS tube Q2 is turned on, and the current I during each turn-on is used to charge the first capacitor C1. The second NMOS tube Q3 is turned off during normal exposure of the SPAD, and is turned on after the exposure ends to release the charge on the first capacitor C1, and the next exposure is waited, and the first capacitor C1 is charged and discharged multiple times, so that more photons can be counted.

[0064] When the exposure starts, when the SPAD device receives a photon, the output of the SPAD device controls the first NMOS tube Q2 to be turned on to charge the first capacitor C1, and the second NMOS tube Q3 is turned off at this time; when the SPAD device does not receive a photon, the output of the SPAD device controls the first NMOS tube Q2 to be turned off, and at this time the second NMOS tube Q3 is turned on to release the charge of the first capacitor C1, and the next exposure is waited.

[0065] In the embodiment, according to the cumulative value Vn of the analog voltage, the average value of the pulse width of the electrical signal pulse VO during the entire exposure period is calculated, specifically including: dividing the change value of the voltage of the first capacitor C1 before and after exposure by the number of electrical signal pulses VO to obtain the average voltage of the analog voltage corresponding to the pulse width of the electrical signal pulse VO, and the average voltage is used to represent the intensity of the ambient light, wherein the pulse width and the analog voltage are in a linear relationship, and the analog voltage and the light intensity are in a linear relationship.

[0066] But the capacitance of the first capacitor C1 needs to be very large, and the charging current needs to be very small, to meet the charge amount is small each time charging, that is, Q1 = C1V = It, so that the entire exposure period, the output pulse of the electrical signal pulse VO, the first capacitor C1 can be charged, and will not be filled very soon, otherwise affect the stability of the ambient light intensity measurement, but the larger the capacitance, the larger the volume of the capacitor, so that the capacitor occupies a large space, does not meet the requirements of the photoelectric conversion device miniaturization development, but also increases the cost.

[0067] As can be seen from Figure 11, with the increase of the number of photons received by each clock, the voltage of VC1 gradually increases, but the maximum VC1 is increased to VDD, if VDD is 1.1v / 3.3v / 2.5v, in order to not let VC1 increase very quickly, it is necessary to increase the capacitance of the first capacitor C1, the increase of the capacitance will increase the chip area, and increase the cost of the photoelectric sensor.

[0068] In another optional embodiment of the photoelectric conversion device of the present application, please refer to Figures 12 and 13, the time analog conversion module 14 comprises: D flip-flop U1, inverter INVT, buffer A1, second PMOS tube Q4, third NMOS tube Q5, fourth NMOS tube Q6, fifth NMOS tube Q7, second capacitor C2 and third capacitor C3, the gate of the second PMOS tube Q4 is low level conduction, the gate of the third NMOS tube Q5, the fourth NMOS tube Q6 and the fifth NMOS tube Q7 is high level, the MOS tube is turned on.

[0069] The input end of the D flip-flop U1 is connected with the output end of the SPAD device 11, the clock input end (the clock input end STOP of the time analog conversion module 14) of the D flip-flop U1 is connected with a trigger clock, the output end of the D flip-flop U1 is connected with the gate of the third NMOS tube Q5, the input end of the inverter INVT and the input end of the buffer A1, the output end of the inverter INVT is connected with the reset end of the D flip-flop U1, the output end of the buffer A1 is connected with the gate of the fifth NMOS tube Q7, the gate of the second PMOS tube Q4 is connected with the second external control end RSTB1, the source of the second PMOS tube Q4 is connected with the power supply end VDD, the drain of the second PMOS tube Q4 is connected with the drain of the third NMOS tube Q5 and one end of the second capacitor C2, the source of the third NMOS tube Q5 is connected with the drain of the fourth NMOS tube Q6, the gate of the fourth NMOS tube Q6 is connected with the third external control end Vb, the source of the fourth NMOS tube Q6 is connected with the drain of the fifth NMOS tube Q7 and one end of the third capacitor C3, and the source of the fifth NMOS tube Q7, the other end of the second capacitor C2 and the other end of the third capacitor C3 are all connected with the ground. The second external control end RSTB1 and the third external control end Vb can be provided by a chip or a switch, and the providing mode is not the protection point of the present application, and thus is not described in detail here.

[0070] The clock frequency of the trigger clock is n times of the clock signal, before the exposure starts, the second external control end RSTB1 controls the second PMOS tube Q4 to be turned on, the power supply end VDD charges the second capacitor C2 to wait for exposure. After the exposure starts, the fourth NMOS tube Q6 is turned on, the second external control end RSTB1 controls the second PMOS tube Q4 to be turned off, when the electrical signal pulse is in the high level period, the trigger clock rises every time, the flip-flop outputs a high level signal to make the third NMOS tube Q5 be turned on, at this time, the charge of the second capacitor C2 is discharged to the third capacitor C3 through the third NMOS tube Q5 and the fourth NMOS tube Q6, and the fifth NMOS tube Q7 is turned off at this time; the high level signal output by the D flip-flop is inverted by the inverter INVT to be used as the reset signal of the D flip-flop U1, so that the output of the D flip-flop is reset to be a low level signal to make the third NMOS tube Q5 be turned off, due to the function of the delay, the fifth NMOS tube Q7 is turned on at this time, and the charge of the third capacitor C3 is discharged to the ground, during the exposure, the charge on the second capacitor C2 is continuously discharged according to the high level of the electrical signal pulse.

[0071] In the embodiment, according to the cumulative value Vn of the analog voltage, the average value of the electrical signal pulse VO pulse width during the whole exposure is calculated, specifically including: the average value of the electrical signal pulse VO pulse width is obtained by dividing the change value of the second capacitor C2 voltage before and after exposure by a coefficient; the coefficient is related to the number of the electrical signal pulse and the clock frequency of the trigger clock which is the multiple of the clock signal.

[0072] In the embodiment, the clock frequency of the trigger clock ck2 is n times of the clock signal. The clock frequency can be n times of the clock signal by using frequency multiplier, phase-locked loop, resonator, etc. under the premise of the same clock source. In the embodiment, ck2 is the clock of the D flip-flop U1, the electrical signal pulse VO is the input signal of the D flip-flop U1, and the output VTRG of the D flip-flop U1 is the control signal for determining whether the third NMOS tube Q5 is on or off. Before the exposure starts, the signal RSTB1 controls the second PMOS tube Q4 to be on, and the VDD power supply charges the second capacitor C2. The exposure starts.

[0073] After the exposure starts, the RSTB1 is low to control the second PMOS tube Q4 to be off to stop charging the second capacitor C2. When the electrical signal pulse VO is at a high level and the ck2 rises at each time, the V TRG The signal at a high level makes the third NMOS tube Q5 on. After the inversion of the INVT, the signal is the reset signal of the D flip-flop U1, and the V TRG The signal at a low level makes the third NMOS tube Q5 off. Therefore, when the signal is at a high level, the third NMOS tube Q5 is on, and when the signal is at a low level, the third NMOS tube Q5 is off. TRG The signal at a high level makes the third NMOS tube Q5 on. After the inversion of the INVT, the signal is the reset signal of the D flip-flop U1, and the V

[0074] During the exposure period, the fourth NMOS tube Q6 is always on. When the third NMOS tube Q5 is on, the fifth NMOS tube Q7 is off, and the charge on the second capacitor C2 is discharged to the third capacitor C3 through the third NMOS tube Q5 and the fourth NMOS tube Q6. When the third NMOS tube Q5 is off, the fifth NMOS tube Q7 is on, and the charge on the third capacitor C3 is discharged to the ground through the fifth NMOS tube Q7.

[0075] During the exposure period, the charge on the second capacitor C2 is discharged according to the pulse of the electrical signal pulse VO, so the second capacitor C2 and the third capacitor C3 do not need to have a large capacitance.

[0076] In an optional embodiment, the clock frequency of the trigger clock is 5 times of the clock signal, that is, n is 5. During one period of the clock signal, the trigger clock has 1-4 rising edges when the electrical signal pulse is at a high level, so that the third NMOS tube Q5 is on 1-4 times. As shown in FIG. 13, during one period of the clock signal, the trigger clock has four clock rising edges when the electrical signal pulse is at a high level, so that the third NMOS tube Q5 and the fifth NMOS tube Q7 can be on 3 times.

[0077] Further, the capacitance of the second capacitor C2 is M times of the capacitance of the third capacitor C3, and M is greater than the number of the electrical signal pulse VO during the exposure period.

[0078] In another optional embodiment of the present application, as shown in Fig. 12, the voltage VC2 on the second capacitor C2 indirectly reflects the cumulative value of the pulse width of the electrical signal pulse VO; during one cycle of the clock signal, the electrical signal pulse VO is at a high level, and ck2 has 1-4 rising edges, so the third NMOS tube Q5 is turned on 1-4 times, and the second capacitor C2 discharges 1-4 times of charge, but each time the discharge time is very short, so during the exposure period, the second capacitor C2 can always discharge charge according to the high pulse of the electrical signal pulse VO, but it will not be discharged soon. The charge discharged each time is determined by the third capacitor C3 and the voltage on the third capacitor C3, which realizes more accurate control of the accuracy of the voltage VC2 drop, and the voltage VC2 gradually drops, and during the exposure period, the second capacitor C2 always has voltage and does not drop to 0 soon, so a more accurate ambient light intensity during the exposure period can be obtained.

[0079] According to Fig. 12 and Fig. 13, the charge Q2 on the second capacitor C2 is C2*VDD, and the voltage V3 on the third capacitor C3 is Vb-Vgs(Q6), so the charge Q3 of the third capacitor C3 each time is C3*V3, therefore, the third NMOS tube Q5 is turned on each time, and the charge discharged from the third NMOS tube Q5 is determined by the third capacitor C3, that is: Q2 / Q3=K*C2 / C3=the number of Vtrg pulses=M, the value of M represents how many times of VTRG pulse signals can be discharged from the second capacitor C2, so the value of M is concerned in this embodiment, and the absolute value of the second capacitor C2 is no longer concerned, so the area of the second capacitor C2 can be reduced.

[0080] The present application also provides an electronic device comprising the photoelectric conversion device described above, and the electronic device can be a scanner. Since the photoelectric conversion device has been described in detail above, no further description is given here.

[0081] In summary, the present application uses a counting module to count the number of photons received by the SPAD device first, and when the counting value reaches a set value, switches to a time analog conversion module to represent the ambient light intensity. In this way, the dynamic range of photon detection is expanded without increasing power consumption, so that photons can be detected at low and high light intensities, avoiding the situation that the counter is saturated due to the increase of light intensity, resulting in inaccurate counting.

[0082] At the same time, the present application does not need to increase the number of bits and the clock frequency of the counter, so that the photoelectric conversion device has small volume, low power consumption, and low product cost. Moreover, the counting module is used to count when the light intensity is low, and the time analog conversion module is used to represent the ambient light intensity when the counting module is close to saturation, which ensures the working efficiency of the photoelectric conversion device and makes it maintain good performance under different lighting conditions.

[0083] It can be understood that, for those skilled in the art, equivalent replacements or changes can be made according to the technical solutions and inventive concepts of the present application, and all such changes or replacements shall fall within the protection scope of the claims appended to the present application. Industrial applicability

[0084] The photoelectric conversion device and electronic equipment of the present application effectively solve the problem of counter saturation of SPAD devices under high light intensity in the prior art by using a counting module and a time analog conversion module, significantly expanding the dynamic range of photon detection, and achieving high-precision light intensity detection without increasing power consumption. The device adopts miniaturization design, suitable for the miniaturization demand of modern electronic equipment, and has high cost-effectiveness, suitable for various application scenarios such as scanners, cameras and optical communication equipment, etc. Its high performance, low power consumption and high precision characteristics make it have wide application prospect in the fields of industry, medical treatment and consumer electronics, etc., can meet the light intensity detection demand in different environments, promote the development and application of related technologies, and have industrial applicability.

Claims

1. A photoelectric conversion device, characterized by comprising: The SPAD device, the quenching module, the counting module, the time analog conversion module and the data processing module are included. The quenching module is used for switching the working state according to the clock signal, when the quenching module is in the conductive state, the SPAD device is charged to the power supply voltage, and when the quenching module is in the non-conductive state, the SPAD device waits for receiving the photon trigger; The SPAD device is used for generating an electrical signal pulse according to the first received photon signal in each clock cycle during the exposure period. The counting module is used for counting the number of the electrical signal pulses output by the SPAD device to obtain a counting value. The time analog conversion module is used for converting the pulse width value of the electrical signal pulse in all clock cycles into an accumulated value of an analog voltage. The data processing module is used for representing the ambient light intensity by the counting value when the counting value is not greater than a preset value, and is used for calculating an average voltage corresponding to the average value of the electrical signal pulse width during the entire exposure period according to the accumulated value of the analog voltage when the counting value is greater than the preset value, and representing the ambient light intensity by the average voltage. The preset value is less than the maximum value of the counter.

2. The photoelectric conversion device according to claim 1, wherein The electrical signal pulse is high when the SPAD device receives the photon signal during the high level of the clock signal.

3. The photoelectric conversion device according to claim 1, wherein The pulse width value of the electrical signal pulse is the time length between the first time point of the first photon trigger of the SPAD device in each clock cycle and the second time point of the falling edge of the clock signal. The proportion of the high level of the clock signal to the clock cycle is at least 80%.

4. The photoelectric conversion device according to claim 1, wherein The time analog conversion module includes a first PMOS tube, a first NMOS tube, a second NMOS tube and a first capacitor, the gate of the first PMOS tube is connected with an external bias power supply, the source of the first PMOS tube is connected with a power supply end, the drain of the first PMOS tube is connected with the drain of the first NMOS tube, the gate of the first NMOS tube is connected with the output end of the SPAD device, the source of the first NMOS tube is connected with one end of the first capacitor, the input end of the data processing module and the drain of the second NMOS tube, the source of the second NMOS tube and the other end of the first capacitor are grounded, and the gate of the second NMOS tube is connected with a first external control end.

5. The photoelectric conversion device according to claim 1, wherein The external bias power supply controls the first PMOS tube to be continuously conductive to provide a charging current for the first capacitor, when the SPAD device receives the photon, the output of the SPAD device controls the first NMOS tube to be conductive to charge the first capacitor, and at this time, the second NMOS tube is disconnected; when the exposure ends, the output of the SPAD device controls the first NMOS tube to be disconnected, at this time, the second NMOS tube is conductive to release the charge of the first capacitor, and waits for the next exposure. The average voltage corresponding to the average value of the electrical signal pulse width during the entire exposure period is calculated according to the accumulated value of the analog voltage, specifically including:

6. The photoelectric conversion device according to claim 5, wherein The average voltage corresponding to the average value of the electrical signal pulse width is obtained by dividing the change value of the voltage of the first capacitor before and after the exposure by the number of the electrical signal pulses. ​ 7. The photoelectric conversion device according to claim 1, wherein The time analog conversion module comprises a D flip-flop, an inverter, a buffer, a second PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a second capacitor and a third capacitor, the input end of the D flip-flop is connected to the output end of the SPAD device, the clock pulse input end of the D flip-flop is connected to the trigger clock, the output end of the D flip-flop is connected to the gate of the third NMOS tube, the input end of the inverter and the input end of the buffer, the output end of the inverter is connected to the reset end of the D flip-flop, the output end of the buffer is connected to the gate of the fifth NMOS tube, the gate of the second PMOS tube is connected to the second external control end, the source of the second PMOS tube is connected to the power supply end, the drain of the second PMOS tube is connected to the drain of the third NMOS tube and one end of the second capacitor, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the third external control end, the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube and one end of the third capacitor, and the source of the fifth NMOS tube, the other end of the second capacitor and the other end of the third capacitor are all connected to the ground; The clock frequency of the trigger clock is n times of the clock signal, before the exposure starts, the second external control end controls the second PMOS tube to be turned on, and the power supply end charges the second capacitor; After the exposure starts, the fourth NMOS tube is turned on, the second external control end controls the second PMOS tube to be turned off, when the electrical signal pulse is in the high level period, the D flip-flop outputs a high level signal to make the third NMOS tube be turned on every time the trigger clock rises, at this time, the charge of the second capacitor is discharged to the third capacitor through the third NMOS tube and the fourth NMOS tube, and the fifth NMOS tube is turned off at this time; the high level signal output by the D flip-flop is inverted to be used as the reset signal of the D flip-flop, the output of the D flip-flop is reset to be a low level signal to make the third NMOS tube be turned off, at this time, the fifth NMOS tube is turned on, and the charge of the third capacitor is discharged to the ground, and during the exposure, the charge on the second capacitor is continuously discharged according to the high level of the electrical signal pulse.

8. The photoelectric conversion device according to claim 7, wherein The clock frequency of the trigger clock is 5 times of the clock signal, and during the high level period of the electrical signal pulse in one period of the clock signal, the trigger clock has 1-4 rising edges to make the third NMOS tube be turned on 1-4 times.

9. The photoelectric conversion device according to claim 7, wherein The capacitance of the second capacitor is M times of the capacitance of the third capacitor, and M is greater than the number of the electrical signal pulses during the exposure.

10. The photoelectric conversion device according to claim 7, wherein According to the cumulative value of the analog voltage, the average value of the pulse width of the electrical signal pulse during the whole exposure is calculated, and the calculation specifically comprises: The average value of the pulse width of the electrical signal pulse is obtained by dividing the change value of the second capacitor voltage before and after exposure by a coefficient, and the coefficient is related to the number of the electrical signal pulses and the clock frequency of the trigger clock which is a multiple of the clock signal.

11. An electronic device, comprising: The photoelectric conversion device comprises the photoelectric conversion device according to any one of claims 1-10. The photoelectric conversion device comprises the photoelectric conversion device according to any one of claims 1-10.

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