Electronic device and method for accessing data

Abstract

Embodiments of the present application relate to the technical field of electronics. Disclosed are an electronic device and a method for accessing data. The electronic device comprises: a first processor, comprising an on-chip memory; and a system cache, comprising a first tag array, a second tag array, and a data array, wherein the first tag array is used for storing first tag information of the on-chip memory, and the second tag array is used for storing second tag information of the data array. The system cache is configured to: enable, by means of the first tag information, access to first system data stored in the on-chip memory; and enable, by means of the second tag information, access to second system data stored in the data array. According to the electronic device and the method for accessing data provided by the embodiments of the present application, the cache capacity of the electronic device can be improved.

Description

Electronic device and method for accessing data

[0001] The present application claims priority to the Chinese patent application No. 202411393128.9, filed on September 30, 2024, and entitled "Electronic device and method for accessing data", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the electronic technical field, and in particular to an electronic device and a method for accessing data. BACKGROUND

[0003] With the development of electronic technology, terminal devices can provide more functions for users to meet the diversified needs of users. In existing terminal devices, a plurality of intellectual property (IP) components, such as an application processor (AP) and a neural processing unit (NPU), are usually integrated on a system on chip (SOC) chip. Each IP component interacts with off-chip memory for programs and data through a system bus. However, the bandwidth of the IP component accessing the DRAM is low, the delay is large, and the power consumption is high, which greatly limits the performance and energy efficiency of each IP component.

[0004] Therefore, the industry proposes to build a large-capacity system cache (SC) inside the SOC to improve the memory performance of the IP component and reduce the off-chip access bandwidth. The larger the capacity of the system cache, the more effectively the access bandwidth of the off-chip memory can be reduced. However, a large-capacity system cache also significantly increases the chip cost. Therefore, how to improve the memory performance of the IP component while reducing the chip cost becomes a problem to be solved. SUMMARY

[0005] Embodiments of the present application provide an electronic device and a method for accessing data, which can improve the capacity of the system cache. To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides an electronic device, the electronic device comprising: a first processor comprising an on-chip memory; a system cache comprising a first tag array, a second tag array and a data array, the first tag array being configured to store first tag information of the on-chip memory, the second tag array being configured to store second tag information of the data array; the system cache being configured to enable access to first system data stored in the on-chip memory by the first tag information; and enable access to second system data stored in the data array by the second tag information.

[0007] The first tag information can comprise a first tag address, the first tag address being configured to index the first system data stored in the on-chip memory, the system cache can enable access to the first system data stored in the on-chip memory by the first tag address for one or more IP components, and the first tag information can further comprise other information such as a valid bit or the like, the valid bit being configured to indicate whether the first system data stored in the on-chip memory is valid. In addition, the system data described in the embodiment of the present application can be an instruction program or data read from a memory, or can be intermediate data generated during running of the electronic device.

[0008] The electronic device provided by the embodiment of the present application can release the on-chip memory in the first processor and uniformly arrange the on-chip memory with the system cache to form a larger-capacity system cache by setting the first tag array in the system cache and storing the first tag information of the on-chip memory by using the first tag array, and enabling access to the first system data stored in the on-chip memory by the first tag information, so as to effectively utilize the on-chip memory in the processor, which is equivalent to expanding the on-chip memory as the system cache. Thus, the electronic device increases the storage capacity of the system shared cache, can improve the hit rate of each IP component such as each processor accessing the system shared cache, improves the access efficiency of the electronic device, improves the performance of the electronic device, and reduces the power consumption of the chip system. In addition, the system cache improves the storage capacity by borrowing the on-chip memory of other processors as remote storage, and also improves the utilization rate of the on-chip memory in the entire electronic device.

[0009] In a possible implementation, the first processor comprises at least one of an image signal processor (ISP), a digital signal processor (DSP), a neural network processor (NPU), a graphics processor (GPU), a video processor, an audio processor, a modem or a display module. That is, the first processor can be various processors comprising an on-chip memory in the electronic device.

[0010] In a possible implementation, the first system data and the second system data are both allowed to be accessed by the plurality of processors. The system cache can be a shared cache of the electronic device or a last level cache in the electronic device, and the data stored in the system cache is allowed to be accessed by the plurality of processors. The first system data is also allowed to be accessed by the plurality of processors as remote storage data of the shared cache. In this way, each processor can access the data array (that is, local storage) of the system cache and the on-chip memory (that is, remote storage) in the first processor by accessing the first system data and the second system data in the system cache. Each processor is not aware of the local storage and the remote storage in service, and no additional delay cost is added when a cache miss occurs.

[0011] In a possible implementation, the plurality of processors includes a second processor, and the second processor is different from the first processor. That is, the other processors can access the on-chip memory in the first processor as a shared cache extension, thereby improving utilization.

[0012] In a possible implementation, the second processor includes at least one of a central processing unit (CPU), an image signal processor, a digital signal processor, a neural network processor, a graphics processor, a video processor, an audio processor, a modem, or a display module. That is, the second processor can be various types of processors or processing modules in the electronic device.

[0013] In a possible implementation, the system cache is specifically configured to: receive an access request from the second processor, the access request including a tag address to be accessed; compare the tag address with the first tag information to obtain a comparison result; and enable the second processor to access the first system data based on the comparison result. The enabling of the second processor to access the first system data can be that the second processor requests to access the system cache, and the system cache controls and enables the second processor to access the first system data in the on-chip memory as an extended cache, thereby realizing access of the second processor to the first system data, where the second processor is not aware of the local storage and the remote storage in service. The comparison of the tag address with the first tag information can be a comparison of the tag address with a plurality of tag addresses in the first tag information.

[0014] In a possible implementation, the system cache is further configured to: receive configuration information from the central processor; and configure first tag information in the first tag array based on the configuration information to enable the on-chip memory as an extension of the system cache. The first tag array can include at least one way, and the configuration information is used to configure enabling information and search information of the at least one way, the enabling information is used to indicate whether the corresponding way can be allocated or replaced, and the search information is used to indicate whether tag information in the corresponding way needs to be searched when a read or write request is received. Thus, the first tag information can further include enabling bits and search bits in the granularity of a way, and the system cache can configure the first tag information in the first tag array, for example, configure the enabling information and the search information of each way in the first tag array as valid, so as to establish a mapping relationship between the first tag array and the on-chip memory. Thus, the embodiment of the application enables the on-chip memory in the processor to be used as a remote cache by configuring the first tag information in the system cache, that is, the above large-capacity cache can be implemented by only increasing the extension capacity of the tag array in the system cache and a small amount of hardware circuit. Compared with increasing a storage space of the same capacity in the data array of the system cache, the embodiment of the application can also save costs.

[0015] In a possible implementation, the system cache is further configured to: receive indication information from the central processor; and clear the first tag information in the first tag array based on the indication information to recover the on-chip memory from the system cache. Thus, by recovering the on-chip memory, the on-chip memory can be used as the internal dedicated memory of the first processor again when the first processor is in a working state, without affecting the working performance of the first processor, so that dynamic extension of the cache capacity in the system cache can be implemented.

[0016] In a possible implementation, the on-chip memory and the data array have the same or different power supply configurations. The power supply configuration includes at least one of a power domain and a clock domain. When the on-chip memory and the data array have different power supply configurations, it is convenient to physically realize decoupling, that is, the working states of the data storage regions do not affect each other, and the normal working of the system cache can be ensured. When the on-chip memory and the data array have the same power supply configuration, the complexity of the power supply configuration can be reduced. Thus, flexible setting of the power supply configuration of each data storage region in the electronic device can be implemented.

[0017] In a possible implementation, the electronic device further includes a system bus and a dedicated signal transmission channel; the system bus is configured to connect the system cache and the first processor; and the dedicated signal transmission channel is configured to connect the system cache and the on-chip memory. By configuring the dedicated signal transmission channel, the system shared cache can locally perform distribution and convergence scheduling of read or write requests of the on-chip memory, and the related transmission can access the on-chip memory through the dedicated signal transmission channel, thereby improving transmission efficiency.

[0018] In a possible implementation, the first processor further includes at least one processor core, and when the at least one processor core is in a non-working state, the system cache is configured to enable access to the first system data stored in the on-chip memory by using the first tag information. The non-working state can include one of a sleep state or a power-off state. This implementation enables the system cache to fully utilize the on-chip memory as an extension when the first processor internal processor core does not need to use the on-chip memory, thereby improving system cache utilization.

[0019] Optionally, each operation performed by the system cache can be performed by the cache controller.

[0020] In a second aspect, an electronic device is provided, which includes a memory and the electronic device as in the first aspect; and the memory is configured to store software programs and data of the electronic device.

[0021] In a third aspect, a method for accessing data is provided, which is applied to an electronic device including a first processor and a system cache, the first processor including an on-chip memory, and the system cache including a first tag array, a second tag array and a data array, the first tag array being configured to store first tag information of the on-chip memory, and the second tag array being configured to store second tag information of the data array; the method includes: enabling access to first system data stored in the on-chip memory by using the first tag information; and enabling access to second system data stored in the data array by using the second tag information.

[0022] In a possible implementation, the above-mentioned enabling access to the first system data stored in the on-chip memory by using the first tag information includes: receiving an access request from a second processor, the access request including a tag address to be accessed; comparing the tag address with the first tag information to obtain a comparison result; and enabling the second processor to access the first system data based on the comparison result.

[0023] In a possible implementation, the method for accessing data further includes: receiving configuration information from a central processor; and configuring the first tag information in the first tag array based on the configuration information, to enable the on-chip memory to be extended as the system cache.

[0024] In a possible implementation, the method for accessing data further includes: receiving indication information from the central processor; and based on the indication information, emptying the first tag information in the first tag array to reclaim the in-memory storage from the system cache.

[0025] It should be understood that the second to third aspects of the present application are consistent with the technical solutions of the first aspect of the present application, and the beneficial effects obtained by the aspects and corresponding feasible implementations are similar, which will not be described again. BRIEF DESCRIPTION OF DRAWINGS

[0026] FIG. 1 is a structural schematic diagram of an electronic device according to an embodiment of the present application;

[0027] FIG. 2 is a structural schematic diagram of a cache system according to an embodiment of the present application;

[0028] FIG. 3 is another structural schematic diagram of a cache system according to an embodiment of the present application;

[0029] FIG. 4 is a flowchart of a method for configuring a remote cache according to an embodiment of the present application;

[0030] FIG. 5 is a flowchart of a method for reading data based on the cache system shown in FIG. 3 according to an embodiment of the present application;

[0031] FIG. 6 is a flowchart of a method for releasing a remote cache according to an embodiment of the present application;

[0032] FIG. 7 is a diagram of state information of an enable bit and a search bit in a tag array during a remote cache release process according to an embodiment of the present application;

[0033] FIG. 8 is a flowchart of a method for accessing data according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the embodiments of the present application.

[0035] The term “and / or” herein merely describes an association relationship of associated objects, and indicates that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone.

[0036] The terms "first", "second", and the like in the description of the present embodiments and in the claims of the present application are used for distinguishing between similar objects talking about the same object, and are not necessarily used to describe a specific order or sequence. Unless otherwise specified, the terms "comprises", "comprising", "includes", "including" and the like, used in the description and the claims of the present application, are used in the sense of "including but not limited to".

[0037] Furthermore, the terms "comprise", "comprising", "have", "having", "include", "including" and the like, used in the description of the present embodiments, are used in the sense of "including but not limited to".

[0038] It should be noted that, in the description of the present embodiments, the words "exemplary" and "for example" are used on the basis that at least one matter in accordance with at least one embodiment of the present embodiments is provided. Therefore, "exemplary" or "for example" in the present embodiments does not mean that the matter is preferred or advantageous over other embodiments. In fact, the words "exemplary" and "for example" are used to present the relevant concept in a specific manner.

[0039] In the description of the present embodiments, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0040] Referring to FIG. 1, FIG. 1 is a schematic diagram of a hardware architecture of an electronic apparatus 100 according to an embodiment of the present application. The electronic apparatus 100 can be located in an electronic device. The electronic device includes, but is not limited to, a mobile phone, a tablet computer, a personal computer, a palm computer, a mobile internet device (MID), a camera, a wearable device (for example, a smart watch, a smart bracelet, a pedometer, etc.), a sound equipment, an audio and video player, a set-top box, a game machine, a printer, a mouse, a keyboard, a vehicle-mounted device (for example, a device on a vehicle such as a car, an airplane, a ship, a train, and a high-speed rail), a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a smart home device (for example, a refrigerator, a television, an air conditioner, an electricity meter, etc.), a smart robot, a plant device, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, or a wireless terminal in a smart home, a flight device (for example, a smart robot, a hot air balloon, a drone, an airplane), etc. FIG. 1 is only an example of the electronic apparatus 100, and the electronic apparatus 100 can be any type of electronic component located in the electronic device or the electronic device itself, for example, the electronic apparatus 100 can be a chip, a chip set, a circuit board carrying a chip or a chip set, etc., and the present embodiment is not limited thereto. The chip, the chip set, or the circuit board carrying the chip or the chip set can work under a suitable software driver.

[0041] The electronic device 100 can include a plurality of IP components, which can include a plurality of processors, for example, can include the central processing unit (CPU) 11, the graphics processing unit (GPU) 12, the NPU 13, the image signal processor (ISP) 14, the modem 15, and the like shown in FIG. 1. It can be understood that the electronic device 100 provided by the embodiments of the present application can also include more or fewer processors or processing modules, for example, an audio processor, a video processor, a digital signal processor (DSP), a display module, and the like, and the embodiments of the present application do not make specific limitations. Optionally, the plurality of processors described above can be integrated in one or more chips, and the one or more chips can be connected to one chip set, and when the one or more processors are integrated in the same chip, the chip is also called a system on a chip (SOC), as shown in FIG. 1. In addition, the electronic device 100 can also be provided with a system bus 16 and a system cache (SC) 17, and the system bus 16 and the system cache 17 can be integrated in the SOC described above. The plurality of processors and the system cache 17 are coupled to the system bus 16, so that the plurality of processors communicate with the system cache 17 through the system bus 16. When the SOC includes multiple levels of cache (for example, three levels of cache or four levels of cache, etc.), the system cache 17 can also be the last level cache (LLC), or the system cache 17 is a shared cache of the plurality of processors on the SOC.

[0042] In the embodiments of the present application, the electronic device in which the electronic device 100 is arranged can also include one or more other components, for example, a memory 18, and the electronic device 100 also has a storage controller 19 for controlling the transmission channel between each processor and the memory 18. The storage controller 19 is usually integrated in the SOC described above. The memory 18 can exemplarily include a volatile memory, for example, a dynamic random access memory (DRAM) and the like for storing instructions and data. The memory 18 can also be referred to as the memory of the electronic device 100. In addition to the SOC described above, other IP components can also be included, for example, various multimedia components including but not limited to voice components, camera components, and display components, and the like. These multimedia components can be coupled to the system bus 16 through a media bus.

[0043] Based on the hardware architecture of the electronic device 100 shown in FIG. 1, in the embodiments of the present application, each of the plurality of processors can include a logic computing unit and a register and the like for loading programs and executing instruction contents, which can also be referred to as a core. The plurality of processors load programs and instructions, obtain data, and execute various function applications and data processing of the electronic device 100. The memory 18 can store software programs of the electronic device 100, for example, including but not limited to: an operating system program, an application program, instruction codes and data required for running, and the like. In at least some of the plurality of processors, in addition to including a core, a memory is also included, and the memory provided inside the processor can also be referred to as an on-chip memory (OCM). In FIG. 1, it is schematically shown that the CPU 11, the graphics processor 12, the neural network processor 13, the image processor 14, and the modem 15 include OCM, but this is not used to limit the solutions. The OCM located inside the processor can be a static random access memory (SRAM), including but not limited to a tightly coupled memory (TCM), a scratchpad memory (SPM), a buffer, a cache, and the like. That is, the processor including the OCM can use both the OCM inside the processor and the system cache 17 inside the SOC for data storage. In a possible implementation manner of the embodiments of the present application, as shown in the electronic device 100 in FIG. 1, the OCM inside each processor is further coupled to the system cache 17 through an electronic circuit to form a signal transmission channel. It should be noted that, in the embodiments of the present application, the central processor 11 can also manage and configure the processors such as the GPU 12, the NPU 13, and the ISP 14 through loading programs, to manage the running states (such as power-on state, power-off state, or hibernation state, and the like) of the processors, and in addition, the central processor 11 can also manage and configure the system cache 17, for example, configure the storage space size of the tag array in the system cache 17, or configure the mapping relationship between the tag array and the data array in the system cache 17.

[0044] Generally, the data required by the processor during the running of a process can be prefetched from the memory 18 to the OCM and the system cache 17. During the data reading process of the processor, the data can be first read from the OCM and the system cache 17, and if the OCM and the system cache 17 are not hit, the processor needs to access the memory 18 outside the chip through the system cache 17 and read from the memory 18. Since the system cache 17 and the OCM inside the processor are located in the chip, the larger the capacity of the system cache 17 and the OCM inside the processor, the higher the hit rate of the processor reading data from the OCM and the system cache 17, which can greatly reduce the data reading delay of the processor. In addition, accessing the memory 18 outside the chip usually has high power consumption, and each processor directly reading data from the OCM and the system cache 17 can also reduce the power consumption of the electronic device 100. However, due to factors such as layout area and cost of IP components, the capacity of the OCM inside the processor is limited; in addition, the larger the capacity of the system cache 17, the higher the chip cost.

[0045] In addition, as shown in the electronic device 100 of FIG. 1, the electronic device 100 usually needs multiple IP components to work together when processing a certain service, so the above-mentioned processor with OCM or some processors with OCM are usually applied to multiple scenarios, for example, using the neural network processor 13 for effect enhancement in the shooting and video recording scenarios, and for example, using the neural network processor 13 for inference in some intelligent recognition scenarios. That is to say, it is difficult to design part of the OCM as a time-sharing multiplexing resource of multiple IP components on the premise of scenario exclusion; in the prior art, the OCM is usually designed as a dedicated resource of the processor. However, a large number of IP components in the SoC do not work at the same time, for example, the image signal processor 14 only works in limited scenarios such as shooting, video recording, video call, and the neural network processor 13 only works in AI inference scenarios. The ISP 14 and the NPU 13 are in power-off or sleep state most of the time, but the OCM in IP components such as the graphic processor 12, the neural network processor 13, and the image signal processor 14 usually has a large capacity. When the OCM in these IP components is designed as a dedicated resource, the OCM resource in these IP components cannot be used by other processors when these IP components are in a power-off state or a sleep state, which causes a waste of on-chip memory resources and reduces the utilization rate of the overall OCM in the SOC.

[0046] The electronic device provided by the embodiment of the present application sets a first tag array in the system cache, and stores the first tag information of the on-chip memory by using the first tag array. The system cache can enable access to the first system data stored in the on-chip memory by using the first tag information, thereby releasing the on-chip memory in the first processor from the first processor, and uniformly arranging the on-chip memory with the system cache to form a larger-capacity system cache, so as to effectively utilize the on-chip memory in the processor, that is, to use the on-chip memory as an extension of the system cache. In this way, the electronic device increases the storage capacity of the system shared cache, can improve the hit rate of various IP components such as processors accessing the system shared cache, improves the access efficiency of the electronic device, improves the performance of the electronic device, and reduces the power consumption of the chip system. In addition, the system cache improves the storage capacity by borrowing the on-chip memory of other processors as remote storage, and also improves the utilization rate of the on-chip memory in the entire electronic device. The embodiments shown in FIGS. 2 to 7 are used to describe the embodiments of the present application in detail.

[0047] First, the structure of the system cache 17 provided by the embodiments of the present application is described. Referring to FIG. 2, FIG. 2 is a structural schematic diagram of the system cache 17 provided by the embodiments of the present application. As shown in FIG. 2, in the embodiments of the present application, the cache space of the system cache 17 can include a tag storage space and a data storage space, the tag storage space is used to store tag information, and the tag information is the information of a cache block in the data storage space. The positions for storing the tag information in the tag storage space are arranged in an array to form a tag array (Tag Array) T. Each column in the tag array T represents a way, and each row represents a set. The intersection area of the way and the set forms a storage unit, and the tag information is stored in the storage unit. One tag information can include but is not limited to a tag address, a valid bit, and a dirty bit, etc. Among them, the valid bit is used to indicate whether the data stored in the data array is valid. Only when the data is valid, the processor is allowed to read or write; the dirty bit is used to indicate whether the data stored in the data array is dirty data, i.e., the data rewritten by the processor. The data storage space is used to store data (including business data, program code or instructions), which can be data to be read by the processor or data to be written. The positions for storing the data in the data storage space can be arranged in an array to form a data array. The data array includes a plurality of cache blocks arranged in an array, and a cache block can also be referred to as a cache line; that is, the data is stored in the cache in units of cache blocks, and the data is written into or read from the cache in units of one or more cache blocks at a time. The tag array and the data array have a mapping relationship, and through the tag information in the tag array, the data stored in the cache block indicated by the tag information in the data array can be read or written. The tag information can be regarded as an index of the corresponding cache block. In addition, the system cache 17 can also be provided with a cache controller 171, which can be a hardware circuit, for example, including but not limited to a comparator, a decoder, and various logic gate circuits. The cache controller 171 is used to execute the processing logic of the system cache, for example, to cache and schedule access requests (which can also be referred to as read or write requests), to read the data of the tag array, to determine the hit / miss of the tag data, and to generate access requests for the data array or the DRAM. Therefore, various operations performed by the system cache can be specifically executed by the cache controller. For example, the cache controller 171 compares the tag address in the address access request with the tag address in the corresponding set based on the set in the address access request to determine whether the cache hits. When the two are the same, it is a hit; when the two are different, it is a miss.The cache controller 171 is further configured to enable a data access path between the processor and the data array when a cache hit occurs, so as to enable the processor to read / write the corresponding cache block in the data array; in addition, the cache controller 171 is further configured to read data from the external memory to the system cache when a cache miss occurs, and select one way from N ways for replacement, that is, the read data is written into the data block corresponding to the way, so that the processor can subsequently access the data block to obtain the cache data without accessing the external memory again. In addition, the system cache 17 is further provided with components such as configuration registers, and the CPU 11 can issue configuration information for configuring the system cache 17 to the configuration registers in the system cache 17, so that the system cache 17 is configured based on the information in the configuration registers.

[0048] As can be seen from FIG. 2, the tag array and the data array in the system cache 17 are located in different storage spaces in the system cache 17, and the storage space of the tag array is usually much smaller than that of the data array; and when data access is performed, it is first necessary to determine whether a Tag hit occurs based on the tag array, and only when a Tag hit occurs, data is further read from the data array. Therefore, based on the space storage mechanism of the system cache 17, in the embodiment of the present application, the CPU 11 configures corresponding tag information in the system cache 17 for the OCM in the processor in the non-working state, and establishes a mapping relationship between the tag array and the OCM, that is, the capacity of the system cache 17 can be expanded by using the OCM. It should be noted that in the embodiment of the present application, the processor in the non-working state can also mean that at least one processor core in the processor is in the non-working state, that is, when at least one processor core does not need to work, the corresponding OCM is not occupied by the at least one processor core, and then the OCM can be used as an extension of the system cache 17, so as to realize the system cache 17. The non-working state of the processor core here can include a sleep state or a power-off state. The processor core can include a logic processing circuit portion for processing tasks, which needs to read or write the OCM dedicated to the processor core, so as to complete the task. In some cases, the sleep state is also called a sleep state, a standby state or a low-power state. The processor core in the sleep state no longer processes tasks, that is, the OCM dedicated to it is no longer used.

[0049] In a possible implementation manner of the embodiment of the present application, the processor including the OCM can include but is not limited to an image signal processor (ISP), a digital signal processor (DSP), a neural network processor (NPU), a graphics processor (GPU), a video processor, an audio processor, a modem (Modem) or a display module. When one or more of the processors are in a non-working state, the OCMs in the processors can be released from the processors to serve as an extended cache of the system cache 17 for use by other processors. The OCMs serving as the extended cache of the system cache 17 can also be referred to as remote storage of the system cache 17. For example, when the DSP and the GPU are in a non-working state, the OCMs in the DSP and the GPU can be released. The storage space of the released OCMs can be allowed to be accessed by one or more of the ISP, the CPU, the NPU, the video processor and the audio processor as an extended part of the system cache.

[0050] The following describes the OCM 3 in the NPU 13 and the OCM 4 in the ISP 14 as an example of the extended cache, in combination with the system cache architecture shown in FIG. 3. When the ISP 14 and the NPU 13 are both in the non-working state, the OCM 3 and the OCM 4 are used as the two remote extended capacities of the system cache 17, and the new system cache architecture is shown in FIG. 3. As shown in FIG. 3, the tag array 02 corresponding to the OCM 3 and the tag array 03 corresponding to the OCM 4 are both arranged in the system cache 17, and the system cache 17 further includes a tag array 01 fixed in the system cache 17, so that the tag array 01, the tag array 02 and the tag array 03 jointly form a tag array T of the system cache 17. In addition, the system cache 17 further includes a data array fixed locally, and the OCM 3 and the OCM 4 are connected to the system cache 17 as the remote extended data array, or can be understood as the extended part of the system cache 17. The tag array 01 stores tag information 01 of the data array, the tag array 02 stores tag information 02 of the OCM 3, and the tag array 03 stores tag information 03 of the OCM 4. Thus, the system data required by each processor shown in FIG. 1 can be prefetched from the external memory to the data array, the OCM 3 and the OCM 4 shown in FIG. 3, the system cache 17 can enable the processor to access the system data 01 stored in the data array through the tag information 01, and can also enable the processor to access the system data 02 stored in the OCM 3 through the tag information 02, and can also enable the processor to access the system data 03 stored in the OCM 4 through the tag information 03. It can be understood that a tag information usually includes a tag address and a valid bit and the like. The enabling of the processor to access the system data stored in the OCM (or the data array) through the tag information can also be understood as enabling the access through the tag address in the tag information. Enabling a processor to access an OCM can be understood as that the system cache 17 is the management and control unit of the entire system cache, and allows the processor to perform the access, including but not limited to enabling the access by setting the required software or hardware resources, for example, enabling the processor to have the ability to access the OCM by starting or allowing the transmission channel required for the access. Alternatively, the process of enabling the processor to access the data array in the system cache 17 is similar, and is not described herein.

[0051] The system data stored in the OCM (or data array) can be accessed by an IP component, such as a processor, reading or writing the system data stored in the OCM (or data array). For example, the system cache receives an access request from any processor, parses the access request to obtain a tag address. If the tag address is the same as the tag address in the way of any tag array, it is determined to be a hit, and the reading or writing of the system data is performed on the corresponding data array or OCM3 or OCM4 according to the hit way. In addition, the system cache 17 shown in FIG. 3 can be a shared cache of the electronic device 100, and the system data 01, the system data 02 and the system data 03 can be accessed by multiple processors in the electronic device 100. For example, it can be allowed to be accessed by the ISP, the CPU, the NPU, the GPU, the video processor and the audio processor. It should be noted that the system data described in the embodiments of the present application can be instruction programs or data read from the memory, i.e., the memory 18, or intermediate data generated during the running of the electronic device 100. The embodiments do not limit the specific type of system data. It can be understood that the system data is shared by multiple IP components in the system, rather than being dedicated to a certain IP component.

[0052] In a possible implementation manner of the embodiments of the present application, the electronic device 100 can further be provided with a dedicated signal transmission channel, as shown in FIG. 3, which is used to connect the system cache 17 and any OCM. The dedicated signal transmission channel 201 is used to connect the system cache 17 and the OCM3, and the dedicated signal transmission channel 202 is used to connect the system cache 17 and the OCM4. The dedicated signal transmission channel can include an electronic circuit and a logic device provided on the electronic circuit, and the logic device includes but is not limited to a comparator, a logic gate and the like. When the OCM hits, the data stored in the OCM can be read or written through the dedicated signal transmission channel. That is to say, if an OCM is used as an extension of the system cache 17, when an IP component, such as a processor, accesses the OCM, the access channel is from the IP component to the system cache 17 and further connected to the OCM through the dedicated signal transmission channel, and the access does not need to pass through the processor where the OCM is located, thereby improving the access efficiency. Even if the processor is in a non-working state, the access is not affected.

[0053] Further, in the embodiments of the present application, the system cache 17 can enable the access of the OCM by the IP component by controlling the conduction of the above-mentioned dedicated signal transmission channel, i.e. the IP component can perform the access by using the above-mentioned dedicated signal transmission channel. For example, the system cache 17 can compare the tag address sent by the IP component with the tag address in the tag array, and when they are the same, trigger the conduction of the logic device in the dedicated signal transmission channel and can be used by the IP component, so that the data can be transmitted to the IP component through the dedicated signal transmission channel and the system bus, thereby realizing the access of the remote OCM by the IP component.

[0054] It should be noted that the access of each processor to the system cache 17 is aggregated and routed to the local node of the system cache 17 through the system bus, and at the system level, a single system cache 17 processing node is presented; wherein whether the system cache 17 uses remote expansion capacity and how much remote expansion capacity is used, each processor can not be aware of from the service, i.e. the routing strategy of the read or write command is not changed, and is uniformly scheduled by the system cache 17. Thus, when more OCMs can be used as the remote expansion data array of the system cache 17, the cache hit rate can be improved, and the power consumption and performance of the service can be more optimized. That is, the system cache 17 serves as the management and control center of the cache, and the management and control function can be selectively realized by the cache controller. When an IP component accesses the system cache 17, the system cache 17 can enable the IP component to access its original internal data array or remote expanded OCM by management action, and the enabled access channel will be controlled to be opened by the system cache 17, i.e. can be used by the corresponding processor, so that the processor can transmit data to the expanded OCM through the access channel, or the processor can transmit data to the expanded OCM through the access channel, so that the IP component initiating the access can realize the access under the control of the system cache 17, and the IP component itself does not perceive and distinguish the data array or the OCM.

[0055] In a possible implementation of the embodiment of the application, the OCMs as the extended cache and the storage array can have the same or different power supply configurations, including at least one of a power domain or a clock domain. In addition, the OCMs as the extended cache can also have the same or different power supply configurations. Having the same power domain can be understood as being powered by the same power terminal, and having different power domains can be understood as being powered by different power terminals. Similarly, having the same clock domain can be understood as being provided with a clock signal by the same clock signal source, and having different clock domains can be understood as being provided with a clock signal by different clock signal sources. It can be understood that when the OCMs and the storage array, or the OCMs, are powered by different power domains, the amplitudes of the power supply voltages of the power domains can be the same or different. For example, the OCM3, the OCM4, and the data array can be powered by different power domains and / or clock domains, facilitating physical decoupling, that is, the working states of the data storage areas do not affect each other, and the normal operation of the system cache can be ensured. For another example, the OCM3, the OCM4, and the data array can be powered by the same power domain and / or clock domain, to reduce the complexity of the power domain and / or clock domain.

[0056] In a possible implementation of the embodiment of the application, the physical distances between the different OCMs and the system cache 17 can be different. For example, the distance between the OCM3 and the system cache 17 is different from the distance between the OCM4 and the system cache 17, so that the lengths of the above-mentioned dedicated signal transmission channel 201 and the dedicated signal transmission channel 202 in the physical aspect can be different, which is not limited in the embodiment. In addition, the interfaces between the system cache 17 and the OCM3 and the interfaces between the system cache 17 and the OCM4 also have different performances, for example, at least one of signal transmission delay and data transmission bandwidth.

[0057] In a possible implementation of the embodiment of the application, the above-mentioned storage of the tag information of the OCM3 by the tag array 02 and the storage of the tag information of the OCM4 by the tag 03, so that the OCM3 and the OCM4 are used as the extended cache of the system cache 17, can be implemented based on the configuration information of the CPU 11. The following further describes the implementation by the interaction flow shown in FIG. 4 in combination with the system cache architecture shown in FIG. 3. The implementation is further described in combination with the flow shown in FIG. 4. Please refer to FIG. 4, which is a schematic diagram of an interaction flow 400 between the CPU 11 and the system cache 17 according to the embodiment of the application. FIG. 4 includes the following steps 401 to 402.

[0058] At step 401, the CPU 11 generates first configuration information corresponding to the OCM 3 in the NPU 13 and second configuration information corresponding to the OCM 4 in the ISP 14 when detecting that the NPU 13 and the ISP 14 are in a non-working state, i.e., the internal cores of the NPU 13 and the ISP 14 are not working. In this step, the CPU 11 can detect the working states of the NPU 13 and the ISP 14 in real time or periodically. When detecting that the NPU 13 is in the non-working state, the CPU 11 can release the OCM 3 in the NPU 13 as an extended cache of the system cache 17. Similarly, when detecting that the ISP 14 is in the non-working state, the CPU 11 can release the OCM 4 in the ISP 14 as an extended cache of the system cache 17. In the embodiments of the present application, it is assumed that the NPU 13 and the ISP 14 are in the non-working state, so that the CPU 11 can release the OCMs in the NPU 13 and the ISP 14 from the corresponding processing units as the extended cache of the system cache 17. The non-working state can include but is not limited to a power-off state or a hibernation state. The CPU 11 can assign a corresponding tag array 02 to the OCM 3 and a corresponding tag array 03 to the OCM 4 based on the capacity of each OCM, so as to establish a mapping relationship between the tag array 02 and the storage space of the OCM 3 and a mapping relationship between the tag array 03 and the storage space of the OCM 4. The assigned tag array 02 can include but is not limited to the number of ways of the tag array 02 and the position of the tag array 02 in the tag array T, and a dedicated signal transmission channel accessible between the tag array 02 and the OCM 3 is further set. The assigned tag array 03 can include but is not limited to the number of ways of the tag array 03 and the position of the tag array 03 in the tag array T, and a dedicated signal transmission channel accessible between the tag array 03 and the OCM 4 is further set.

[0059] It is assumed that the cache manager 171 assigns the number of ways of the OCM 3 to be 2 based on the capacity of the OCM 3, i.e., the tag array 02 corresponding to the OCM 3 is M*2. For example, the CPU 11 can assign the tag array formed by the two ways of way N and way (N+1) to the OCM 3. It is assumed that the cache manager 171 assigns the number of ways of the OCM 4 to be 1 based on the capacity of the OCM 4, i.e., the tag array 03 corresponding to the OCM 4 is M*1. For example, the processor 11 can assign the tag array formed by the one way of way (N+2) to the OCM 4. The above M is the number of sets in the tag array, and the set can be an integer greater than or equal to 1.

[0060] After the CPU 11 allocates the tag array 02 to the OMC 3, it can generate first configuration information, which can include enable information and search information of wayN and way(N+1). After the CPU 11 allocates the tag array 03 to the OMC 4, it can generate second configuration information, which can include enable information and search information of way(N+2). After the CPU 11 allocates the corresponding tag arrays to the OCM 2 and the OCM 3 respectively, it can also set enable information and search information for each way in each tag array. That is, the enable information and the search information are set in the granularity of a way. It can be considered that the way in the embodiment is a unit of operating and managing the tag array. The enable information and the search information can each be a bit. The enable information is used to indicate whether the way (i.e., the tag storage space corresponding to the OCM) can be allocated or replaced. When the enable information is set to "1", it means that the data read from the memory can be stored in the cache block corresponding to the way, or the data in the cache block corresponding to the way can be replaced. When the enable information is set to "0", it means that the data read from the memory is not allowed to be stored in the cache block corresponding to the way, or the data in the cache block corresponding to the way cannot be replaced. The search information is used to indicate whether the tag information in the corresponding way needs to be searched when a read or write request is received. When the search information is set to "1", it means that the data in the cache block corresponding to the way can be valid, and the tag information in the corresponding way needs to be searched after a read or write request is received. When the search information is set to "0", it means that the data in the cache block corresponding to the way is invalid, and the tag information in the corresponding way does not need to be searched after a read or write request is received. Thus, based on the value of the enable bit and the value of the search bit, each way can include three cases, which are described taking way(N+2) as an example. In case one, the enable bit and the search bit corresponding to way(N+2) are both "1", so the data read from the memory can be stored in the OCM 4 corresponding to way(N+2), the data stored in the OCM 4 can also be replaced, and the tag information of way(N+2) needs to be searched to determine whether it is hit after a read or write access request is received. In case two, the enable bit corresponding to way(N+2) is "0" and the search bit corresponding to way(N+2) is "1", so the data read from the memory is not allowed to be stored in the OCM 4, the data stored in the OCM 4 is also not allowed to be replaced, but the tag information of way(N+2) needs to be searched to determine whether it is hit after a read or write access request is received. In case three, the enable bit and the search bit corresponding to way(N+2) are both "0", so the data read from the memory is not allowed to be stored in the OCM 4, the data stored in the OCM 4 is also not allowed to be replaced, and the tag information of way(N+2) does not need to be searched after a read or write access request is received.

[0061] In the embodiment of the present application, after the CPU 11 generates the first configuration information and the second configuration information, the CPU 11 can store the first configuration information and the second configuration information into the configuration register in the system cache 17. For example, the configuration register can be located in the cache controller, and the embodiment is not limited in this regard.

[0062] In step 402, the system cache 17 configures the tag information 02 in the tag array 02 and the tag information 03 in the tag array 03 based on the first configuration information and the second configuration information. Here, configuring the tag information in the tag array 02 can mean configuring the values of the enable bits and the search bits corresponding to the respective ways. Specifically, the system cache 17 can set the values of the enable bits and the search bits corresponding to the way N and the way (N+1) in the tag array 02 to be valid, for example, both to “1”. In addition, the system cache 17 can set the values of the enable bits and the search bits corresponding to the way (N+2) in the tag array 03 to be valid, for example, both to “1”.

[0063] In one possible implementation of the embodiment of the present application, the first configuration information can further include information indicating power-on of the tag array 02 and initialization of the tag array 02, and the second configuration information can further include information indicating power-on of the tag array 03 and initialization of the tag array 03. Thus, the system cache 17 can further power on and initialize the tag array 02 and the tag array 03 based on the first configuration information and the second configuration information, thereby further expanding the operation of the OCM as part of the architecture of the system cache 17.

[0064] In the embodiment of the present application, through the interaction process shown in FIG. 4, the OCM 3 and the OCM 4 can be used as two remote extended capacities of the system cache 17 when the ISP 14 and the NPU 13 are in the non-working state, and the new system cache architecture formed is shown in FIG. 3. The following describes the working process of the system cache 17 when the CPU 11 initiates data access under the architecture shown in FIG. 3 through the interaction process 500 shown in FIG. 5. The working process of the system cache 17 shown in FIG. 5 includes steps 501 to 507. The following embodiment only takes data reading as an example, and it can be understood that the principle of data writing is similar to that of reading, which will not be described herein.

[0065] In step 501, a data reading request is received from the CPU 11, and the data reading request carries address information to be accessed, which includes a tag address Tag1 and group information Set3.

[0066] In step 502, it is queried that the search bits corresponding to each of the ways N to (N+2) are all valid (for example, all “1”).

[0067] Step 503, read the multiple tag information in way1-wayN+2 corresponding to Set3, compare the tag address in each of the multiple tag information with the tag address Tag1, and determine whether they are the same. Assuming that the Tag in (set3, wayN+1) is the same as Tag1, it means that the cache hits. The system cache 17 can continue to perform step 504. If it does not hit, steps 506-507 are performed.

[0068] Step 504, detect the valid bit of the tag information T3(N+1) in (set3, wayN+1). When the valid bit indicates that the data in the corresponding OCM3 is valid, step 505 can be continued.

[0069] Step 505, the CPU 11 reads the data from the cache block in the OCM3 corresponding to the tag information T3(N+1) through the dedicated signal transmission channel 201 between the OCM3 and the system cache 17, that is, the system cache can transmit the read data to the CPU 11.

[0070] Step 506, the CPU 11 reads data from the external memory 18, that is, the system cache can send the read data to the CPU 11.

[0071] Step 507, based on the replacement algorithm, select way(N+2); then further query whether the enable bit corresponding to way(N+2) is valid (for example, “1”). Assuming that the enable bit corresponding to way(N+2) is valid, the read data is stored in the cache block in the OCM4 corresponding to the tag address in way(N+2). In this way, when the subsequent IP component needs to access the data, it can directly hit in the OCM4 without accessing the external memory 18 again.

[0072] The above describes the process of releasing the OCM in the NPU 13 and the ISP 14 in the non-working state and accessing data based on the architecture of the system cache shown in FIG. 3 through the embodiments shown in FIGS. 2-5. In one possible implementation of the embodiments of the present application, when the NPU 13 or the ISP 14 is powered on or resumes work or needs to work, the released OCM can also be retrieved. The following describes the process of releasing the OCM by the system cache 17 by taking the power-on of the NPU 13 and the retrieval of the OCM3 as an example and combining the flow shown in FIG. 6. The flow shown in FIG. 6 can be performed by the system cache 17 based on the indication information received from the CPU 11, which is used to indicate that the OCM3 is retrieved from the system cache. The flow shown in FIG. 6 includes steps 601-605.

[0073] Step 601, when the NPU 13 starts working, the states of the search bits corresponding to the ways N and (N+1) are kept unchanged (i.e. valid), and the enable bits of the ways N and (N+1) are configured as invalid. The enable bits corresponding to the ways N and (N+1) are set as invalid, and the data read from the memory is not allowed to be stored in the OCM 3, and the data stored in the OCM 3 is not allowed to be replaced, but after receiving a read or write access request, the tag information of the ways N and (N+1) can still be searched to determine whether a hit occurs.

[0074] Step 602, the dirty data in the cache block corresponding to the way N is written back to the memory.

[0075] Step 603, after the dirty data in the cache block corresponding to the way N is completely written back to the memory 18, the search bit corresponding to the way N is configured as invalid. Thus, the cache block in the OCM 3 corresponding to the way N is released.

[0076] After the above steps 601 to 603, the enable bits and the search bits of the tag array T corresponding to each way are as shown in FIG. 7A.

[0077] Step 604, the dirty data in the cache block corresponding to the way (N+1) is written back to the memory.

[0078] Step 605, after the dirty data in the cache block corresponding to the way (N+1) is completely written back to the memory 18, the search bit corresponding to the way (N+1) is configured as invalid. Thus, the cache block in the OCM 3 corresponding to the way (N+1) is released.

[0079] After the search bits corresponding to the ways N and (N+1) are both set as invalid, after receiving a read or write access request, the tag information of the ways N and (N+1) is no longer searched.

[0080] Thus, after the steps 601 to 605, the OCM 3 is released. After the above step 605, the enable bits and the search bits of the tag array T corresponding to each way are as shown in FIG. 7B.

[0081] In an optional implementation of the embodiment of the application, after the above step 605, the system cache 17 can further include a step 606: the system cache 17 can also clear the tag information in the ways N and (N+1). Optionally, the system cache 17 can also clear the data in the OCM 3. Optionally, the system cache 17 can also power down the storage space corresponding to the tag array 02 shown in FIG. 4. Finally, the CPU 11 can also set the dedicated signal transmission channel 201 between the OCM 3 and the system cache 17 as unavailable, for example, power down the components related to the dedicated signal transmission channel 201.

[0082] Thus, after step 601 and step 606, the CPU 11 is configured for the OCM 3 to be recycled, and the NPU 13 can use the OCM 3 as an on-chip dedicated cache.

[0083] The electronic device 100 provided by the embodiments of the present application is shown by the above embodiments shown in FIG. 1 to FIG. 7. The embodiments of the present application further provide an electronic device, which can include the electronic device 100 shown in FIG. 1 and the memory 108. The memory 108 stores software programs or data of the electronic device 100. The specific implementation of the memory 108 is described in the above embodiments shown in FIG. 1, and is not described herein. The system cache 17 and the extended OCM of the present embodiment can be used to load the software programs or data in the memory 108, so that the software programs or data are used by one or more of the plurality of IP components as system data.

[0084] In addition, the embodiments of the present application further provide a method for accessing data. Referring to FIG. 8, FIG. 8 is a flow 800 of the method for accessing data provided by the embodiments of the present application. The method for accessing data can be performed by the system cache 17 shown in FIG. 1. The method for accessing data includes steps 801 and 802. Step 801 enables the IP component to access first system data stored in the on-chip memory through first tag information; and step 802 enables the IP component to access second system data stored in the data array through second tag information. The IP component can include a processor, which can include a plurality of different types or functions of processors, and the specific implementation is described in the above embodiments. The access can include a read or write operation.

[0085] In a possible implementation, the above-mentioned enabling the IP component to access the first system data stored in the on-chip memory through the first tag information includes: receiving an access request from the second processor, the access request including a tag address to be accessed; comparing the tag address with the first tag information to obtain a comparison result; and enabling the second processor to access the first system data based on the comparison result. When the comparison result is a hit, the second processor implements the access.

[0086] In a possible implementation, the method for accessing data further includes: receiving configuration information from the central processor; and based on the configuration information, configuring the first tag information in the first tag array to enable the on-chip memory as an extension of the system cache, and the specific implementation is described in the above embodiments.

[0087] In a possible implementation, the method for accessing data further comprises: receiving indication information from the central processor; and based on the indication information, clearing the first tag information in the first tag array to recycle the in-page memory from the system cache, as described in the previous embodiments.

[0088] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An electronic device, characterized by comprising: Comprising: a first processor comprising an on-chip memory; a system cache comprising a first tag array, a second tag array and a data array, the first tag array being configured to store first tag information of the on-chip memory, the second tag array being configured to store second tag information of the data array; the system cache being configured to enable access to first system data stored in the on-chip memory via the first tag information, and to enable access to second system data stored in the data array via the second tag information. The first processor comprises at least one of an image signal processor (ISP), a digital signal processor (DSP), a neural processing unit (NPU), a graphics processing unit (GPU), a video processor, an audio processor, a modem, or a display module. 2.The electronic device of claim 1, wherein, 3. The electronic device according to any one of claims 1 or 2, wherein: the first system data and the second system data are both allowed to be accessed by a plurality of processors. The plurality of processors comprises a second processor different from the first processor. 4.The electronic device of claim 3, wherein, The second processor comprises at least one of a central processing unit (CPU), an image signal processor (ISP), a digital signal processor (DSP), a neural processing unit (NPU), a graphics processing unit (GPU), a video processor, an audio processor, a modem, or a display module. 5.The electronic device of claim 4, wherein, The system cache is specifically configured to:

6. The electronic device of claim 4 or 5, wherein, receive an access request from the second processor, the access request comprising a tag address to be accessed; compare the tag address with the first tag information to obtain a comparison result; and enable the second processor to access the first system data based on the comparison result. The system cache is further configured to:

7. The electronic device of any one of claims 1 to 6, wherein, receive configuration information from a central processor; and configure the first tag information in the first tag array based on the configuration information, so as to enable the first on-chip memory to serve as an extension of the system cache. The system cache is further configured to:

8. The electronic device of any one of claims 1 to 7, wherein, receive indication information from a central processor; and empty the first tag information in the first tag array based on the indication information, so as to reclaim the on-chip memory from the system cache.

9. The electronic device according to any one of claims 1 to 8, wherein: the on-chip memory and the data array have the same or different power supply configurations; wherein the power supply configurations comprise at least one of a power domain and a clock domain. The electronic device further comprises a system bus and a dedicated signal transmission channel; 10.The electronic device of any one of claims 1 to 9, wherein, the system bus is configured to connect the system cache and the first processor; and the dedicated signal transmission channel is configured to connect the system cache and the on-chip memory. The first processor further comprises at least one processor core; and when the at least one processor core is in a non-working state, the system cache is configured to enable access to the first system data stored in the on-chip memory via the first tag information. 11.The electronic device of any one of claims 1 to 10, wherein, The electronic device comprises a memory and the electronic device according to any one of claims 1 to 11; and 12. An electronic device, comprising: the memory is configured to store software programs and data of the electronic device. ​ 13. A method for accessing data, applied to an electronic device, characterized in that, The electronic device includes a first processor including an on-chip memory therein and a system cache including a first tag array for storing first tag information of the on-chip memory, a second tag array for storing second tag information of a data array, and the data array; and the method includes: enabling access to first system data stored in the on-chip memory through the first tag information; enabling access to second system data stored in the data array through the second tag information.

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