Receiver front-end circuit

Abstract

The present disclosure provides a receiver front-end circuit, comprising: a first input unit and a second input unit, configured to operate alternately on the basis of a common-mode voltage of a differential input signal and to output a differential output signal; a variable resistor unit, configured to adjust, on the basis of a variable resistor control signal, a differential load resistance provided to the differential output signal; and a control unit, configured to generate the variable resistor control signal on the basis of the common-mode voltage of the differential input signal. According to the receiver front-end circuit of the present disclosure, a differential input signal having a wide common-mode voltage range can be received at a low power supply voltage, and the output amplitude of the generated differential output signal does not vary significantly with changes in the common-mode voltage of the differential input signal, thereby improving receiver compatibility and reducing power consumption.

Description

Receiver front-end circuit TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of electronic circuits, and in particular, the present disclosure relates to a receiver front-end circuit. BACKGROUND

[0002] With the continuous development of semiconductor technology, integrated circuits are developing towards low power consumption, high compatibility and high integration. In order to be compatible with differential input signals of various common-mode voltage ranges, a receiver for wired data communication usually includes a rail-to-rail front-end circuit. The receiver front-end circuit can include two parallel differential input stages for receiving differential input signals with different ranges of common-mode voltages, respectively.

[0003] However, the existing receiver front-end circuit has at least two defects. First, when the power supply voltage of the receiver front-end circuit is less than the common-mode voltage of the differential input signal, the receiver front-end circuit usually cannot work normally. Furthermore, when the common-mode voltage of the differential input signal changes greatly, the amplitude of the differential output signal of the receiver front-end circuit will also change greatly, so a variable gain amplifier needs to be incorporated to adjust the amplitude of the output of the receiver front-end circuit, resulting in an increase in chip power consumption and area.

[0004] In order to solve the above problems, a receiver front-end circuit is needed which at least overcomes the above defects, i.e. the receiver front-end circuit can work at a low power supply voltage and support a wide input common-mode voltage range, i.e. the amplitude of the output voltage does not change greatly with the change of the common-mode voltage of the input signal.

[0005] The above information disclosed in this BACKGROUND section is only for the purpose of understanding the background of the present disclosure, and therefore can contain information that does not constitute prior art. SUMMARY

[0006] In order to solve the above problems existing in the prior art, the present disclosure proposes a new type of receiver front-end circuit.

[0007] According to one aspect of the present disclosure, a receiver front-end circuit is provided, comprising: a first input unit and a second input unit, which alternately work according to the common-mode voltage of a differential input signal and output a differential output signal; a variable resistance unit, which adjusts the differential load resistance provided to the differential output signal according to a variable resistance control signal; and a control unit, which generates the variable resistance control signal according to the common-mode voltage of the differential input signal.

[0008] The receiver front-end circuit according to the present disclosure uses two input units connected in parallel and operating alternately, and a variable resistance unit capable of adjusting a differential load resistance according to a common-mode voltage of a differential input signal, and can realize reception of a differential input signal having a wide common-mode voltage range at a low power supply voltage, and the output amplitude of a differential output signal generated does not have a large change with a change in the common-mode voltage of the differential input signal, thereby improving the compatibility of the receiver and reducing power consumption.

[0009] However, the effects of the present disclosure are not limited to the above-mentioned effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that the foregoing General Description and the following Detailed Description are exemplary and explanatory, and are intended to provide further explanation of the claimed present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0010] The accompanying drawings are included to provide a further understanding of the present disclosure, and the drawings illustrate exemplary embodiments of the present disclosure, and together with the description, serve to explain the present disclosure concepts.

[0011] FIG. 1 is a schematic block diagram illustrating a receiver front-end circuit according to an embodiment of the present disclosure.

[0012] FIG. 2 is a schematic circuit diagram illustrating a first input unit according to an embodiment of the present disclosure.

[0013] FIG. 3 is a schematic circuit diagram illustrating a second input unit according to an embodiment of the present disclosure.

[0014] FIG. 4 is a schematic circuit diagram illustrating a variable resistance unit according to an embodiment of the present disclosure.

[0015] FIG. 5 is a schematic circuit diagram illustrating a control unit according to an embodiment of the present disclosure.

[0016] FIG. 6 is a schematic circuit diagram illustrating a receiver front-end circuit according to an embodiment of the present disclosure.

[0017] FIG. 7 is a schematic circuit diagram illustrating a receiver front-end circuit according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various example embodiments of the present disclosure. As used herein, an "embodiment" is a non-limiting example of an apparatus or method employing one or more inventive concepts disclosed herein. It will be evident, however, that the various example embodiments can be practiced without these specific details, or with one or more equivalent configurations. In other instances, well-known structures and functions have not been described in detail in order to not unnecessarily obscure the disclosure.

[0019] Unless otherwise indicated, the example embodiments described are to be understood as providing example features of variations of some ways in which the present inventive concepts can be implemented in practice. Thus, unless otherwise indicated, features, components, units, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the embodiments can be additionally combined, separated, interchanged, and / or reconfigured without departing from the present inventive concepts.

[0020] For purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to include only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] Although the terms "first," "second," etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0022] The terminology used herein for the purpose of describing particular embodiments is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including," "includes," "having," "has," "a," "an," "one," and / or "said" are used in the detailed description and / or claims, such terms are intended to be inclusive (i.e., in a manner that says that one), unless explicitly indicated to the contrary.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0024] Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Like reference numerals refer to like elements throughout.

[0025] Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Like reference numerals refer to like elements throughout.

[0026] FIG. 1 is a schematic block diagram illustrating a receiver front-end circuit 10 according to an embodiment of the present disclosure. As shown in FIG. 1, according to an embodiment of the present disclosure, the receiver front-end circuit 10 can include a first input unit 201, a second input unit 202, a variable resistance unit 300, and a control unit 400.

[0027] As shown in FIG. 1, according to an embodiment of the present disclosure, the receiver front-end circuit 10 can be configured to receive differential input signals 11, 12 including a positive input signal 11 and a negative input signal 12, and generate differential output signals 31, 32 including a positive output signal 31 and a negative output signal 32, and transmit the differential output signals 31, 32 to other circuits of the receiver.

[0028] As shown in FIG. 1, according to an embodiment of the present disclosure, the input terminals of the first input unit 201 and the second input unit 202 connected in parallel receive the differential input signals 11, 12 and output the differential output signals 31, 32 from the output terminals. Further, as shown in FIG. 1, according to an embodiment of the present disclosure, the differential input signals 11, 12 are also input to the control unit 400. Further, the output terminals of the first input unit 201 and the second input unit 202 connected in parallel are also connected to the input terminals of the variable resistance unit 300. According to an embodiment of the present disclosure, the variable resistance unit 300 can provide an adjustable differential load resistance for the differential output signals 31, 32. As shown in FIG. 1, according to an embodiment of the present disclosure, the control unit 400 can output a variable resistance control signal 41 to the variable resistance unit 300 for adjusting the resistance value of the differential load resistance.

[0029] The circuit implementation of the first input unit 201, the second input unit 202, the variable resistance unit 300, and the control unit 400 will be described below in conjunction with specific embodiments.

[0030] FIG. 2 is a schematic circuit diagram illustrating the first input unit 201 according to an embodiment of the present disclosure. As shown in FIG. 2, the first input unit 201 can include the first input transistor M21 and the second input transistor M22 as a differential input pair of transistors, and a current source IA. As shown in FIG. 2, according to an embodiment of the present disclosure, the first input transistor M21 and the second input transistor M22 can each be a P-type MOS (Metal Oxide Semiconductor) transistor.

[0031] As shown in FIG. 2, according to an embodiment of the present disclosure, one end of the current source IA can be connected to a power supply voltage VDD, and the other end can be connected to the source of the first input transistor M21 and the source of the second input transistor M22, thereby generating a bias current from the power supply flow IA to the first input transistor M21 and the second input transistor M22.

[0032] As shown in FIG. 2, according to an embodiment of the present disclosure, the gate of the first input transistor M21 can receive the positive input signal 11, and the drain can output the negative output signal 32. Similarly, as shown in FIG. 2, according to an embodiment of the present disclosure, the gate of the second input transistor M22 can receive the negative input signal 12, and the drain can output the positive output signal 31.

[0033] According to an embodiment of the present disclosure, the power supply voltage VDD of the receiver front-end circuit 10 can be lower than the highest common-mode voltage of the differential input signals 11, 12. For example, the power supply voltage can be 1.8V, and the common-mode voltage range of the differential input signals 11, 12 can be 0-2.4V. That is, the power supply voltage 1.8V is lower than the highest common-mode voltage 2.4V of the differential input signals 11, 12.

[0034] Therefore, when the common-mode voltage of the differential input signals 11, 12 is low, the first input transistor M21 and the second input transistor M22 are turned on, so that the first input unit 201 is in an operating state, i.e., the first input transistor M21 and the second input transistor M22 perform common-source stage amplification on the differential input signals 11, 12, thereby outputting the differential output signals 31, 32 at the drains of the first input transistor M21 and the second input transistor M22. On the contrary, when the common-mode voltage of the differential input signals 11, 12 is high, the first input transistor M21 and the second input transistor M22 are turned off, so that the first input unit 201 does not operate on the differential input signals 11, 12.

[0035] According to embodiments of the present disclosure, the first threshold voltage VTP can be preset for the common-mode voltage of the differential input signals 11, 12. According to embodiments of the present disclosure, the first input transistor M21 and the second input transistor M22 of the first input unit 201 can be formed by the same P-type MOS transistor and have the same threshold voltage. According to embodiments of the present disclosure, the threshold voltage of the first input transistor M21 and the second input transistor M22 can be set as the first threshold voltage VTP.

[0036] According to embodiments of the present disclosure, when the common-mode voltage of the differential input signals 11, 12 is less than the first threshold voltage VTP, the first input transistor M21 and the second input transistor M22 of the first input unit 201 can perform common-source amplification on the differential input signals 11, 12 and output the differential output signals 31, 32; and when the common-mode voltage of the differential input signals 11, 12 is greater than or equal to the first threshold voltage VTP, the first input unit 201 does not operate on the differential input signals 11, 12.

[0037] FIG. 3 is a schematic circuit diagram illustrating the second input unit 202 according to embodiments of the present disclosure. As shown in FIG. 3, according to embodiments of the present disclosure, the second input unit 202 can include a third input transistor M23 and a fourth input transistor M24. As shown in FIG. 3, according to embodiments of the present disclosure, the third input transistor M23 and the fourth input transistor M24 can each be an N-type MOS transistor.

[0038] As shown in FIG. 3, according to embodiments of the present disclosure, the gate of the third input transistor M23 can receive the positive input signal 11, the drain can be connected to the power supply voltage VDD, and the source can output the positive output signal 31. Similarly, as shown in FIG. 3, according to embodiments of the present disclosure, the gate of the fourth input transistor M24 can receive the negative input signal 12, the drain can be connected to the power supply voltage VDD, and the source can output the negative output signal 32.

[0039] Therefore, when the common-mode voltage of the differential input signals 11, 12 is high, the third input transistor M23 and the fourth input transistor M24 are turned on, so that the second input unit 202 is in an operating state, i.e., the third input transistor M23 and the fourth input transistor M24 perform source follower amplification on the differential input signals 11, 12, thereby outputting the differential output signals 31, 32 at the sources of the third input transistor M23 and the fourth input transistor M24. Conversely, when the common-mode voltage of the differential input signals 11, 12 is low, the third input transistor M23 and the fourth input transistor M24 are turned off, so that the second input unit 202 does not operate on the differential input signals 11, 12.

[0040] According to embodiments of the present disclosure, the second threshold voltage VTN can be preset for the common-mode voltage of the differential input signals 11, 12. According to embodiments of the present disclosure, the second threshold voltage VTN can be preset for the common-mode voltage of the differential input signals 11, 12. According to embodiments of the present disclosure, the third input transistor M23 and the fourth input transistor M24 of the second input unit 202 can be formed by the same N-type MOS transistor and have the same threshold voltage. According to embodiments of the present disclosure, the threshold voltage of the third input transistor M23 and the fourth input transistor M24 can be set to the second threshold voltage VTN.

[0041] According to embodiments of the present disclosure, when the common-mode voltage of the differential input signals 11, 12 is greater than the second threshold voltage VTN, the third input transistor M23 and the fourth input transistor M24 of the second input unit 202 can source-follower amplify the differential input signals 11, 12 and output the differential output signals 31, 32; and when the common-mode voltage of the differential input signals 11, 12 is less than or equal to the second threshold voltage VTN, the second input unit 202 does not operate on the differential input signals 11, 12.

[0042] Referring to FIGS. 2 and 3, according to embodiments of the present disclosure, by adjusting the parameters, such as the size, of the first input transistor M21, the second input transistor M22, the third input transistor M23, and the fourth input transistor M24, the first threshold voltage VTP can be equal to the second threshold voltage VTN, denoted as the threshold voltage VT.

[0043] Therefore, referring to FIGS. 2 and 3, according to embodiments of the present disclosure, when the common-mode voltage of the differential input signals 11, 12 is less than the threshold voltage VT, the first input transistor M21 and the second input transistor M22 are turned on, and the third input transistor M23 and the fourth input transistor M24 are turned off, so that the first input unit 201 works and the second input unit 202 does not work, i.e., the first input transistor M21 and the second input transistor M22 source-stage amplify the differential input signals 11, 12, thereby outputting the differential output signals 31, 32 at the drains of the first input transistor M21 and the second input transistor M22. In addition, due to the low common-mode voltage of the differential input signals 11, 12, according to the principle of source-stage amplification, the common-mode voltage of the differential output signals 31, 32 is also low.

[0044] Accordingly, with reference to FIGS. 2 and 3, according to the embodiments of the present disclosure, when the common-mode voltage of the differential input signals 11, 12 is greater than or equal to the threshold voltage VT, the first input transistor M21 and the second input transistor M22 are turned off, and the third input transistor M23 and the fourth input transistor M24 are turned on, so that the first input unit 201 does not work and the second input unit 202 works, i.e., the third input transistor M23 and the fourth input transistor M24 source-follower amplify the differential input signals 11, 12, thereby outputting the differential output signals 31, 32 at the sources of the third input transistor M23 and the fourth input transistor M24. In addition, due to the high common-mode voltage of the differential input signals 11, 12, according to the principle of source-follower amplification, the common-mode voltage of the differential output signals 31, 32 is low.

[0045] Therefore, according to the embodiments of the present disclosure, by setting the first threshold voltage VTP to be equal to the second threshold voltage VTN, the first input transistor M21 and the second input transistor M22 can be alternately turned on and turned off with respect to the third input transistor M23 and the fourth input transistor M24. That is, at any moment, only one of the first input unit 201 and the second input unit 202 amplifies the differential input signals 11, 12, and accordingly outputs the differential output signals 31, 32, and the common-mode voltage of the differential output signals 31, 32 is similar.

[0046] FIG. 4 is a schematic circuit diagram illustrating a variable resistance unit 300 according to an embodiment of the present disclosure. As shown in FIG. 4, according to the embodiments of the present disclosure, the variable resistance unit 300 can include a first load resistor R31, a second load resistor R32, a third load resistor R33, a fourth load resistor R34, and a load switch transistor M31.

[0047] As shown in FIG. 4, according to the embodiments of the present disclosure, the first load resistor R31 and the third load resistor R33 can be connected in series between the positive output signal 31 and the ground voltage GND in turn, and the second load resistor R32 and the fourth load resistor R34 can be connected in series between the negative output signal 32 and the ground voltage GND in turn. According to the embodiments of the present disclosure, in order to guarantee the symmetry of the differential circuit, the resistance of the first load resistor R31 and the resistance of the second load resistor R32 can be the same, i.e., R31 = R32, and the resistance of the third load resistor R33 and the resistance of the fourth load resistor R34 can be the same, i.e., R33 = R34.

[0048] As shown in FIG. 4, according to an embodiment of the present disclosure, the source of the load switch transistor M31 is connected at a node between the first load resistor R31 and the third load resistor R33, the drain is connected at a node between the second load resistor R32 and the fourth load resistor R34, and the gate receives the variable resistance control signal 41.

[0049] As shown in FIG. 4, according to an embodiment of the present disclosure, the load switch transistor M31 can be an N-type MOS transistor. Therefore, according to an embodiment of the present disclosure, when the variable resistance control signal 41 is at a low level, the load switch transistor M31 is turned off, the first load resistor R31 and the third load resistor R33 are connected in series and the second load resistor R32 and the fourth load resistor R34 are connected in series, so that the differential load resistances of the differential output signals 31, 32 are R31+R33 and R32+R34, respectively.

[0050] In addition, according to an embodiment of the present disclosure, when the variable resistance control signal 41 is at a high level, the load switch transistor M31 is turned on, the third load resistor R33 and the fourth load resistor R34 are connected in parallel, and therefore the third load resistor R33 and the fourth load resistor R34 no longer contribute to the differential output, so that the differential load resistances of the differential output signals 31, 32 are R31 and R32, respectively.

[0051] Therefore, according to an embodiment of the present disclosure, when the variable resistance control signal 41 is at a low level, the variable resistance unit 300 provides a larger differential load resistance, and when the variable resistance control signal 41 is at a high level, the variable resistance unit 300 provides a smaller differential load resistance. That is, according to an embodiment of the present disclosure, the variable resistance unit 300 can adjust the differential load resistance it provides to the differential output signals 31, 32 according to the variable resistance control signal 41.

[0052] FIG. 5 is a schematic circuit diagram showing the control unit 400 according to an embodiment of the present disclosure. As shown in FIG. 5, according to an embodiment of the present disclosure, the control unit 400 can include a first terminal resistor R41, a second terminal resistor R42, and an inverter 401.

[0053] As shown in FIG. 5, according to an embodiment of the present disclosure, the first terminal resistor R41 and the second terminal resistor R42 can be connected in series in turn between the positive input signal 11 and the negative input signal 12. According to an embodiment of the present disclosure, the resistance values of the first terminal resistor R41 and the second terminal resistor R42 can be the same, i.e. R41=R42. Therefore, according to an embodiment of the present disclosure, the voltage at the node between the first terminal resistor R41 and the second terminal resistor R42 can be the common-mode voltage of the differential input signals 11, 12.

[0054] As shown in FIG. 5, according to embodiments of the present disclosure, the input terminal of the inverter 401 can be connected to a node between the first terminal resistor R41 and the second terminal resistor R42, that is, the inverter 401 can receive the common-mode voltage of the differential input signal 11, 12. In addition, according to embodiments of the present disclosure, the inverter 401 can output the variable resistance control signal 41.

[0055] Specifically, according to embodiments of the present disclosure, when the common-mode voltage of the differential input signal 11, 12 is low, for example, less than the threshold voltage VT described above with reference to FIG. 2 and FIG. 3, the inverter 401 receives the common-mode voltage with a low level and thus outputs the variable resistance control signal 41 with a high level. Accordingly, according to embodiments of the present disclosure, when the common-mode voltage of the differential input signal 11, 12 is high, for example, greater than the threshold voltage VT, the inverter 401 receives the common-mode voltage with a high level and thus outputs the variable resistance control signal 41 with a low level.

[0056] FIG. 6 is a schematic circuit diagram illustrating the receiver front-end circuit 10 according to embodiments of the present disclosure.

[0057] Referring to FIG. 6, according to embodiments of the present disclosure, when the common-mode voltage of the differential input signal 11, 12 is less than the threshold voltage VT, the first input transistor M21 and the second input transistor M22 in the first input unit 201 are turned on, and the third input transistor M23 and the fourth input transistor M24 in the second input unit 202 are turned off, forming a common-source differential amplifier composed of the first input transistor M21 and the second input transistor M22 in the receiver front-end circuit 10, common-source amplifying the differential input signal 11, 12, and outputting the differential output signal 31, 32.

[0058] According to embodiments of the present disclosure, when the common-mode voltage of the differential input signal 11, 12 is less than the threshold voltage VT, the differential gain is jointly determined by the transconductance of the common-source amplifier composed of the first input transistor M21 and the second input transistor M22 and the resistance value of the differential load resistance of the variable resistance unit 300. According to the principle of common-source amplification, the transconductance of the common-source amplifier is large.

[0059] In addition, since the common-mode voltage of the differential input signals 11, 12 is less than the threshold voltage VT, so that the low-level voltage is input to the control unit 400 (the inverter 401), the variable resistance control signal 41 outputted thereby is high level, so that the load switch transistor M31 in the variable resistance unit 300 is turned on, and the differential load resistance provided by the variable resistance unit is small (R31 / R32). Therefore, when the common-mode voltage of the differential input signals 11, 12 is less than the threshold voltage VT, although the transconductance of the common-source amplifier is large, the differential load resistance of the variable resistance unit 300 is small, so that the overall differential gain changes relatively small.

[0060] On the other hand, with reference to FIG. 6, according to the embodiment of the present disclosure, when the common-mode voltage of the differential input signals 11, 12 is greater than or equal to the threshold voltage VT, the first input transistor M21 and the second input transistor M22 in the first input unit 201 are turned off, and the third input transistor M23 and the fourth input transistor M24 in the second input unit 202 are turned on, forming a differential source follower amplifier composed of the third input transistor M23 and the fourth input transistor M24 in the receiver front-end circuit 10, source follower amplifying the differential input signals 11, 12, and outputting the differential output signals 31, 32.

[0061] According to the embodiment of the present disclosure, when the common-mode voltage of the differential input signals 11, 12 is greater than or equal to the threshold voltage VT, the differential gain is determined by the transconductance of the source follower amplifier composed of the third input transistor M23 and the fourth input transistor M22 and the resistance value of the differential load resistance of the variable resistance unit 300. According to the principle of source follower amplification, the transconductance of the source follower amplifier is small.

[0062] In addition, since the common-mode voltage of the differential input signals 11, 12 is greater than or equal to the threshold voltage VT, so that the high-level voltage is input to the control unit 400 (the inverter 401), the variable resistance control signal 41 outputted thereby is low level, so that the load switch transistor M31 in the variable resistance unit 300 is turned off, and the differential load resistance provided by the variable resistance unit is large (R31+R33 / R32+R44). Therefore, when the common-mode voltage of the differential input signals 11, 12 is greater than or equal to the threshold voltage VT, although the transconductance of the source follower amplifier is small, the resistance value of the differential load resistance of the variable resistance unit 300 is large, so that the overall differential gain changes relatively small.

[0063] Therefore, with reference to FIG. 6, according to the embodiment of the present disclosure, the overall differential gain changes relatively little regardless of whether the common-mode voltage of the differential input signals 11, 12 is greater than or equal to the threshold voltage VT or less than the threshold voltage VT, that is, the amplitude of the differential output signals 31, 32 does not change greatly with the common-mode voltage of the differential input signals 11, 12.

[0064] Although the circuit implementation of the receiver front-end circuit 10 is described above in connection with specific examples, the present disclosure is not limited thereto. For example, although the first input unit 201 and the second input unit 202 are implemented using a P-type MOS transistor and an N-type MOS transistor, respectively, above, those skilled in the art will appreciate that, according to the teachings of the present disclosure, the first input unit 201 and the second input unit 202 having the same functions can also be implemented in other ways, for example, using an N-type MOS transistor and a P-type MOS transistor, respectively, to implement the first input unit 201 and the second input unit 202. At this time, the load switch transistor M31 included in the variable resistance unit 300 can be implemented using a P-type MOS transistor accordingly. All these variants should be covered within the scope of the present disclosure.

[0065] FIG. 7 is a schematic circuit diagram showing a receiver front-end circuit 10' according to another embodiment of the present disclosure.

[0066] Unlike FIG. 6, as shown in FIG. 7, according to an alternative embodiment of the present disclosure, the first input transistor M21 and the second input transistor M22 can both be N-type MOS transistors. At this time, one end of the current source IA can be connected to the ground voltage VSS, and the other end can be connected to the source of the first input transistor M21 and the source of the second input transistor M22, thereby generating a bias current of the current source IA from the first input transistor M21 and the second input transistor M22. As shown in FIG. 7, according to the alternative embodiment of the present disclosure, the gate of the first input transistor M21 can receive the positive input signal 11, and the drain can output the negative output signal 32; the gate of the second input transistor M22 can receive the negative input signal 12, and the drain can output the positive output signal 31.

[0067] In addition, unlike FIG. 6, as shown in FIG. 7, according to an alternative embodiment of the present disclosure, the third input transistor M23 and the fourth input transistor M24 can both be P-type MOS transistors. As shown in FIG. 7, according to the alternative embodiment of the present disclosure, the gate of the third input transistor M23 can receive the positive input signal 11, the drain can be connected to the ground voltage VSS, and the source can output the positive output signal 31. In addition, as shown in FIG. 7, according to the alternative embodiment of the present disclosure, the gate of the fourth input transistor M24 can receive the negative input signal 12, the drain can be connected to the ground voltage VSS, and the source outputs the negative output signal 32.

[0068] In addition, unlike FIG. 6, as shown in FIG. 7, according to an alternative embodiment of the present disclosure, the load switch transistor M31 of the variable resistance unit 300 can be a P-type MOS transistor, the source of which is connected to a node between the first load resistor R31 and the third load resistor R33, the drain of which is connected to a node between the second load resistor R32 and the fourth load resistor R34, and the gate of which receives the variable resistance control signal 41.

[0069] The working principle of the receiver front-end circuit 10' shown in FIG. 7 is basically the same as that of the receiver front-end circuit 10 shown in FIG. 6.

[0070] Specifically, in the receiver front-end circuit 10' shown in FIG. 7, when the common-mode voltage of the differential input signal 11, 12 is less than the threshold voltage VT, the first input transistor M21 and the second input transistor M22 in the first input unit 201 are turned off, and the third input transistor M23 and the fourth input transistor M24 in the second input unit 202 are turned on, forming a differential source follower amplifier composed of the third input transistor M23 and the fourth input transistor M24 in the receiver front-end circuit 10, source following and amplifying the differential input signal 11, 12, and outputting the differential output signal 31, 32.

[0071] According to an alternative embodiment of the present disclosure, when the common-mode voltage of the differential input signal 11, 12 is less than the threshold voltage VT, the differential gain is jointly determined by the transconductance of the source follower amplifier composed of the third input transistor M23 and the fourth input transistor M22 and the resistance value of the differential load resistance of the variable resistance unit 300. According to the principle of source following, the transconductance of the source follower amplifier is small.

[0072] In addition, since the common-mode voltage of the differential input signal 11, 12 is less than the threshold voltage VT, so that the low-level voltage is input to the control unit 400 (inverter 401), the variable resistance control signal 41 output by it is high, so that the load switch transistor M31 in the variable resistance unit 300 is turned off, and the differential load resistance provided by the variable resistance unit is large (R31+R33 / R32+R44). Therefore, when the common-mode voltage of the common-mode voltage of the differential input signal 11, 12 is less than the threshold voltage VT, although the transconductance of the source follower amplifier is small, the resistance value of the differential load resistance of the variable resistance unit 300 is large, so that the overall differential gain changes relatively small.

[0073] On the other hand, in the receiver front-end circuit 10' shown in FIG. 7, when the common-mode voltage of the differential input signal 11, 12 is greater than or equal to the threshold voltage VT, the first input transistor M21 and the second input transistor M22 in the first input unit 201 are turned on, and the third input transistor M23 and the fourth input transistor M24 in the second input unit 202 are turned off, forming a common-source differential amplifier composed of the first input transistor M21 and the second input transistor M22 in the receiver front-end circuit 10, which performs common-source amplification on the differential input signal 11, 12, and outputs the differential output signal 31, 32.

[0074] According to the alternative embodiment of the present disclosure, when the common-mode voltage of the differential input signal 11, 12 is greater than or equal to the threshold voltage VT, the differential gain is jointly determined by the transconductance of the common-source amplifier composed of the first input transistor M21 and the second input transistor M22 and the resistance value of the differential load resistance of the variable resistance unit 300. According to the principle of common-source amplification, the transconductance of the common-source amplifier is large.

[0075] In addition, since the common-mode voltage of the differential input signal 11, 12 is greater than or equal to the threshold voltage VT, a high level is input to the control unit 400 (the inverter 401), so that the variable resistance control signal 41 output by it is at a low level, so that the load switch transistor M31 in the variable resistance unit 300 is turned on, and the differential load resistance provided by the variable resistance unit is small (R31 / R32). Therefore, when the common-mode voltage of the differential input signal 11, 12 is greater than or equal to the threshold voltage VT, although the transconductance of the common-source amplifier is large, the differential load resistance of the variable resistance unit 300 is small, so that the overall differential gain changes relatively small.

[0076] Therefore, with reference to FIG. 7, according to the alternative embodiment of the present disclosure, whether the common-mode voltage of the differential input signal 11, 12 is greater than or equal to the threshold voltage VT or less than the threshold voltage VT, the overall differential gain changes relatively small, that is, the amplitude of the differential output signal 31, 32 will not change greatly with the change of the common-mode voltage of the differential input signal 11, 12.

[0077] The receiver front-end circuit according to the present disclosure uses two input units connected in parallel and working alternately, and a variable resistance unit capable of adjusting the differential load resistance according to the common-mode voltage of the differential input signal, which can realize the reception of the differential input signal with a wide common-mode voltage range at a low power supply voltage, and the output amplitude of the differential output signal generated does not change greatly with the change of the common-mode voltage of the differential input signal, thereby improving the compatibility of the receiver and reducing the power consumption.

[0078] For purposes of illustration, a limited number of possible implementations of the present disclosure have been set forth above. While the present disclosure has been described with reference to the implementations thereof, it is to be understood that the implementations can be varied and modified and elements added to, or deleted from, such implementations without departing from the spirit and scope of the present disclosure as disclosed in the appended claims.

[0079] Although numerous details have been described herein, these should not be construed as limiting the scope of the disclosure or the scope of protection that can be sought, but rather as a description of features that can be particular to certain implementations. Certain features described herein in the context of separate implementations can also be implemented in combination. Conversely, various features described in the context of a single implementation can also be implemented separately or in any suitable subcombination. Furthermore, although features can be described above as acting in certain combinations and even initially claimed as such, in some cases, one or more features from a claimed combination can be excised from the combination, and the claimed combination can be directed to a subcombination or variation of a subcombination.

Claims

1. A receiver front-end circuit comprising: a first input unit and a second input unit configured to operate alternately according to a common-mode voltage of a differential input signal and to output a differential output signal; a variable resistance unit configured to adjust a differential load resistance provided to the differential output signal according to a variable resistance control signal; and a control unit configured to generate the variable resistance control signal according to the common-mode voltage of the differential input signal.

2. The receiver front-end circuit of claim 1, wherein, The common-mode voltage of the differential input signal is greater than a power supply voltage of the receiver front-end circuit.

3. The receiver front-end circuit according to claim 1 or 2, wherein when the common-mode voltage of the differential input signal is less than a threshold voltage, one of the first input unit and the second input unit operates and the other does not operate, and wherein, when the common-mode voltage of the differential input signal is greater than or equal to the threshold voltage, the other of the first input unit and the second input unit operates and the one does not operate.

4. The receiver front-end circuit according to claim 3, wherein, when the common-mode voltage of the differential input signal is less than the threshold voltage, the one of the first input unit and the second input unit operates and has a small transconductance, and wherein, when the common-mode voltage of the differential input signal is greater than or equal to the threshold voltage, the other of the first input unit and the second input unit operates and has a large transconductance.

5. The receiver front-end circuit according to claim 4, wherein when the common-mode voltage of the differential input signal is less than the threshold voltage, the one of the first input unit and the second input unit forms a source follower amplifier, and wherein, when the common-mode voltage of the differential input signal is greater than or equal to the threshold voltage, the other of the first input unit and the second input unit forms a common source amplifier.

6. The receiver front-end circuit according to claim 4, wherein, when the common-mode voltage of the differential input signal is less than the threshold voltage, the control unit generates the variable resistance control signal having a first level, and wherein, when the common-mode voltage of the differential input signal is greater than or equal to the threshold voltage, the control unit generates the variable resistance control signal having a second level different from the first level.

7. The receiver front-end circuit according to claim 6, wherein the variable resistance unit causes a differential load resistance to be large according to the variable resistance control signal having the first level and to be small according to the variable resistance control signal having the second level.

8. The receiver front-end circuit according to claim 3, wherein, the first input unit and the second input unit respectively include P-type MOS transistors and N-type MOS transistors or respectively include N-type MOS transistors or P-type MOS transistors.

9. The receiver front-end circuit according to claim 8, wherein the threshold voltage is determined according to threshold voltages of the P-type MOS transistors and the N-type MOS transistors.

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