Single-ended drive circuit, transmitter, configuration method and related devices

Abstract

This invention relates to the field of power electronic device technology, and particularly to a single-ended drive circuit, transmitter, configuration method, and related apparatus. The circuit includes a bias branch, a bias node, and an adjustable bootstrap capacitor. The output signal terminal of the bias branch is connected to a power supply via a load resistor. The drive terminal of the bias branch is connected to the bias node, and one end of the adjustable bootstrap capacitor is connected between the bias node and the drive terminal. The other end of the adjustable bootstrap capacitor is connected to the power supply, achieving dynamic charge coupling compensation for power supply disturbances. This allows the potential of the bias node of the current source branch to float synchronously with power supply changes, thereby maintaining the stability of the voltage at the drive terminal of the bias branch. This achieves passive, high-bandwidth, and low-power power supply noise suppression, solving the problem that traditional single-ended CML drivers are susceptible to power supply noise and simultaneous switching noise interference, leading to a degradation in output signal quality under high channel density and high speed conditions.

Description

Technical Field

[0001] This invention relates to the field of power electronic device technology, and in particular to a single-ended drive circuit, transmitter, configuration method and related apparatus. Background Technology

[0002] In the current field of high-speed digital communication and data center interconnection, as signal rates continue to climb to 112Gbps and higher, the performance of serial high-speed transceivers (SerDes) has become a key bottleneck for system bandwidth and energy efficiency. Existing high-speed SerDes transmitter drivers (TX drivers), as the end circuit of the signal chain, directly determine the bit error rate (BER) and eye diagram aperture of the link through their output swing, linearity, and noise immunity. Currently, SerDes transmitters commonly use differential CML drivers based on Current Mode Logic (CML) drive structures. The core idea is to drive differential load resistors with a constant current source, achieve high-speed current switching output through the alternating conduction of switching transistors, and rely on complementary signals to achieve power supply disturbance cancellation and common-mode noise suppression, resulting in excellent signal integrity and noise immunity. However, as the number of SerDes channels increases, the cost of its two-wire symmetrical wiring structure in terms of area, power consumption, and packaging complexity becomes increasingly higher. Especially in applications such as multi-channel SerDes, on-chip optoelectronic interconnects (CPO), and chiplet-level I / O interconnects, differential CML drivers are no longer able to meet the needs of future high-density interconnects due to their large footprint, high power consumption, and low wiring density.

[0003] Current technologies are exploring single-ended high-speed CML drive structures to achieve higher channel integration and energy efficiency under the same area and power consumption conditions. However, single-ended structures inherently lack common-mode noise cancellation mechanisms and are extremely sensitive to power supply noise (PSN) and simultaneous switching noise (SSN). This can easily cause the output current to fluctuate with power supply disturbances, resulting in unstable output signal amplitude, increased phase jitter, and eye diagram closure, becoming a major obstacle restricting the performance of high-speed single-ended transmission. Summary of the Invention

[0004] This invention provides a single-ended driving circuit, transmitter, configuration method, and related devices to solve the problem that existing single-ended high-speed CML drivers are susceptible to power supply noise and simultaneous switching noise interference under high channel density and high speed conditions, resulting in a decrease in output signal quality.

[0005] The present invention provides a single-ended driving circuit, comprising: a bias branch, a bias node, and an adjustable bootstrap capacitor;

[0006] The output signal terminal of the bias branch is connected to the power supply through a load resistor;

[0007] The driving end of the bias branch is connected to the bias node, one end of the adjustable bootstrap capacitor is connected between the bias node and the driving end, and the other end of the adjustable bootstrap capacitor is connected to the power supply.

[0008] Optionally, the adjustable bootstrap capacitor includes at least one set of capacitor units; the capacitor unit includes a controlled switch and a capacitor connected together.

[0009] Optionally, when there are multiple groups of capacitor units, the capacitor units in each group are connected in parallel.

[0010] Optionally, the bias branch includes a first NMOS transistor and a second NMOS transistor;

[0011] The drain of the first NMOS transistor serves as the output signal terminal and is connected to the load resistor;

[0012] The gate of the first NMOS transistor serves as the driving terminal and is connected to the bias node;

[0013] The source of the first NMOS transistor is connected to the drain of the second NMOS transistor;

[0014] The source of the second NMOS transistor is grounded; the gate of the second NMOS transistor serves as the input signal terminal.

[0015] Optionally, the bias node includes a low-noise reference circuit; the low-noise reference circuit is connected to the bias branch and is used to provide a DC component to the bias branch.

[0016] Optionally, the capacitor is a MOS capacitor.

[0017] The present invention also provides a transmitter, including the circuit described above.

[0018] The present invention also provides a configuration method for a single-ended driving circuit, applied to the circuit described above, comprising:

[0019] The optimal compensation value of the adjustable bootstrap capacitor is calculated based on the driving input capacitor, transistor transconductance, and on-resistance of the single-ended driving circuit.

[0020] The capacitance value of the adjustable bootstrap capacitor is configured to the optimal compensation capacitance value.

[0021] The present invention also provides an electronic device, the device comprising a processor and a memory:

[0022] The memory is used to store program code and transmit the program code to the processor;

[0023] The processor is used to execute the method described above according to the instructions in the program code.

[0024] The present invention also provides a computer-readable storage medium for storing program code for performing the method described above.

[0025] As can be seen from the above technical solutions, the present invention has the following advantages:

[0026] The present invention provides a single-ended driving circuit, including a bias branch, a bias node, and an adjustable bootstrap capacitor; the output signal terminal of the bias branch is connected to a power supply through a load resistor; the driving terminal of the bias branch is connected to the bias node, one end of the adjustable bootstrap capacitor is connected between the bias node and the driving terminal, and the other end of the adjustable bootstrap capacitor is connected to the power supply.

[0027] In this invention, by setting adjustable bootstrap capacitors connected between the bias node and the drive terminal, and between the power supply and the drive terminal, dynamic charge coupling compensation for power supply disturbances is achieved. This allows the bias node potential of the current source branch to float synchronously with power supply changes, thereby maintaining the stability of the voltage at the drive terminal of the bias branch. This achieves passive, high-bandwidth, and low-power power supply noise suppression, solving the problem that traditional single-ended CML drivers are susceptible to power supply noise and simultaneous switching noise interference under high channel density and high speed conditions, resulting in a decrease in output signal quality. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of a single-ended driving circuit provided in an embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of the adjustable bootstrap capacitor provided in an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram illustrating an application scenario of a single-ended driving circuit provided in an embodiment of the present invention.

[0032] Figure 4A schematic diagram of the simulation results of a single-ended drive circuit is provided as a simulation application example of the present invention; wherein, Figure 4 (a) in the diagram is the simulated eye diagram of a traditional single-ended CML circuit. Figure 4 (b) in the figure is the simulated eye diagram of the single-ended drive circuit of the present invention;

[0033] Figure 5 This is a flowchart illustrating a configuration method for a single-ended driving circuit provided in an embodiment of the present invention. Detailed Implementation

[0034] Current-mode logic (CML) drivers inherently possess high bandwidth, small voltage swing, and fast rise and fall edges, making them ideal for ultra-high-speed, short-distance transmission applications. Furthermore, traditional CML architectures are mostly fully differential, relying on two complementary output signals to achieve common-mode noise self-cancellation and power supply disturbance suppression, which offers significant advantages in achieving high-speed, long-distance, and low-error-rate transmission. Therefore, current-mode logic (CML) drivers, due to their small swing, fast switching speed, and high output linearity, are widely used in the transmit (TX) output stage of current 112Gbps and higher-speed serial transceivers (SerDes).

[0035] Existing CML driver architectures mostly employ differential structures, suppressing power and ground noise by canceling out two complementary signals, achieving strong common-mode rejection and high signal integrity. While differential CMLs perform well in high-speed applications, with increasing system integration, SerDes systems are evolving towards higher density, more channels, and lower power consumption. In particular, the number of channels in SerDes is growing exponentially, with dozens or even hundreds of transmit channels often integrated into a single SoC or co-packaged optoelectronic (CPO) module. In this high-density integration context, the differential CML structure, due to its symmetrical wiring requirements for dual output signals, leads to congested wiring, excessive area footprint, and significantly increased power consumption, while also causing parasitic coupling and package noise issues. In contrast, single-ended high-speed drivers can achieve twice the channel density in the same area, reduce the number of power and ground return paths, and have higher scalability and energy efficiency potential in optoelectronic interconnects and on-chip interconnects. Therefore, single-ended high-speed drives will be a potential direction for improvement in future high-density SerDes architectures, especially in new application scenarios such as AI data centers, high-performance computing (HPC) and co-packaged optoelectronics. The continuous increase in the number of channels makes single-ended high-speed CML drives a future architectural trend.

[0036] Traditional single-ended high-speed CML drivers typically use a fixed bias voltage source to control the gate potential of cascaded transistors to achieve a constant output current. However, during high-speed switching, a non-ideal coupling relationship exists between the power supply terminal (VDD) and the bias terminal (VB). When the power supply is disturbed, the bias node potential cannot change synchronously due to the limitation of circuit parasitic capacitance, resulting in transient current mismatch, causing the output current to fluctuate with power supply noise. This coupling modulation effect is particularly prominent in single-ended architectures because they lack the common-mode cancellation mechanism of differential paths, causing power supply ripple to be directly reflected at the output signal terminal, resulting in a significant decrease in power supply rejection ratio (PSRR). Furthermore, as the number of channels increases and multiple driver units switch simultaneously, the parasitic inductance of the package and power network further amplifies SSN noise, thus forming cross-channel coupling within the driver stage, significantly increasing output jitter. Therefore, compared with differential CML, single-ended high-speed drivers are inherently at a disadvantage in terms of power supply noise (PSN) and simultaneous switching noise (SSN). Due to the lack of a differential cancellation channel, any power supply or ground fluctuations directly modulate the drive current, causing output signal amplitude jitter and phase drift, leading to eye diagram collapse and increased bit error rate. Therefore, existing single-ended CML drive structures generally face severe power supply noise sensitivity issues. Under the influence of power supply fluctuations, simultaneous switching noise (SSN), and ground bounce noise, the bias node voltage is disturbed, thereby modulating the output current, resulting in output eye diagram closure, decreased linearity, and increased jitter, making it difficult to meet signal integrity requirements at 112G and above.

[0037] To mitigate the aforementioned issues, current mainstream improvements to single-ended high-speed CML drivers primarily focus on two approaches: power supply regulation and bias servo, and bootstrap compensation. The first approach involves introducing an on-chip low-dropout regulator (LDO) or current mirror feedback to stabilize the bias. This is achieved by adding a high-speed servo loop to the bias branch to stabilize the current source bias and reduce the impact of power supply disturbances. While this method can improve bias stability to some extent, it requires additional amplifiers, current sensing, and feedback paths, resulting in high power consumption and complex structures that are difficult to implement. Furthermore, due to the limited bandwidth of the LDO loop, it cannot effectively suppress GHz-level high-frequency power supply noise and SSN. The second approach involves improving the bias current source by detecting changes in the output current and adjusting the bias voltage in real time to automatically follow power supply fluctuations. However, this approach is prone to introducing additional noise under high-speed conditions and is complex to implement. Moreover, current designs are typically based on differential architectures, making it difficult to maintain effective compensation symmetry in single-ended applications, and they lack adjustable mechanisms to address parasitic parameter differences between different channels.

[0038] Furthermore, simultaneous switching noise (SSN) is another major issue in multi-channel SerDes systems. When multiple single-ended channels switch simultaneously within the same power domain, parasitic inductances in the package and power networks cause transient current backflow, resulting in ground bounce noise and cross-channel crosstalk. Existing solutions mitigate SSN conduction by introducing decoupling capacitors, such as on-chip decoupling capacitors, or isolation inductors, such as supply isolation networks, in the power path. However, this physical isolation method is difficult to maintain effective high-frequency filtering capabilities in high-frequency applications due to the limitations of on-chip parasitic inductance and ESR of decoupling capacitors, and it also occupies a large area, making it unsuitable for multi-small-channel integration.

[0039] Therefore, the existing technologies that improve PSRR by adding power supply decoupling capacitors and introducing on-chip voltage regulators or current mirror compensation circuits have the following drawbacks: First, on-chip decoupling capacitors are limited by area and parasitic effects at high frequencies, making it difficult to provide effective high-frequency power supply stability; Second, although voltage regulators or servo compensation circuits can stabilize the bias, they add additional amplifier stages and feedback paths, leading to increased power consumption, noise introduction, and decreased bandwidth; Third, although differential alternatives can cancel common-mode noise, their area and power consumption are too high in multi-channel layouts, making them unsuitable for high-speed, high-density packaging. In summary, existing single-ended high-speed CML drivers have the following typical drawbacks: First, there is a lack of dynamic potential following mechanism between the power supply and bias nodes, causing power supply disturbances to directly modulate the drive current; Second, the cumulative effect of SSN and power supply noise during multi-channel parallel operation cannot be effectively isolated, leading to cross-channel interference; Third, existing voltage regulator and servo solutions have high power consumption and complex structures, making them unsuitable for high-speed, low-power designs.

[0040] Therefore, existing single-ended high-speed driver solutions are significantly inadequate in balancing the four aspects of "high speed", "single-ended", "noise immunity" and "low power consumption", making it difficult to achieve low power consumption, high density and high speed output.

[0041] To address the aforementioned technical problems, this invention proposes a high-speed single-ended CML drive circuit with bootstrap bias compensation. By introducing an adjustable capacitor CB between the power supply terminal and the bias node, a bootstrapped bias structure is formed, allowing the bias node to dynamically float (e.g., synchronously rise or fall) during power supply fluctuations. This dynamically cancels the modulation of the cascaded transistor's (M2) gate voltage by power supply disturbances, achieving charge-coupled compensation for power supply disturbances. This maintains a constant gate-source voltage and bias current in the cascaded transistor, ensuring the drive current is not modulated by power supply ripple. This structure is equivalent to building a capacitive coupling channel in the bias branch. When high-frequency power supply disturbances occur, the adjustable capacitor CB injects compensating charge into the VB node through charge coupling, stabilizing the transient potential difference between VB and VDD, significantly improving power supply noise suppression. Furthermore, the adjustable characteristics of the capacitor CB allow for dynamic adjustment of the compensation coefficient based on different process angles, temperatures, channel densities, or operating rates, ensuring stable performance even under multi-channel parallel driving conditions, achieving cross-channel consistency and high robustness.

[0042] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0043] The technical terms involved in this invention will be explained below.

[0044] CML (Current Mode Logic) circuits are current-mode logic circuits that operate by switching a constant bias current between differential or single-ended loads to output high-speed logic levels. Due to their small output node voltage swing and fast switching speed, CML structures are commonly used in high-speed SerDes transceivers, clock distribution, and analog front-end drivers.

[0045] A single-ended CML driver is a variant of the CML circuit that uses only a single output signal terminal (Vout) to transmit signals. Compared to the traditional differential CML structure, it has a smaller area, lower power consumption, and higher channel density, but it is more sensitive to power supply noise and ground bounce noise.

[0046] The bias voltage node (VB) is the DC reference point in the CML driver stage that controls the output current. It is typically used to define the operating range of cascaded transistors (such as M2). The stability of the bias voltage directly affects the linearity and noise suppression performance of the current source output.

[0047] Bootstrapped bias is a dynamic compensation technique that introduces a capacitor between the bias node and the power supply, causing the bias node to change synchronously with the power supply during high-speed switching. This technique reduces the transient potential change of the bias node relative to the power supply, thereby counteracting the modulation effect of power supply noise in the current path.

[0048] Adjustable bootstrap capacitor (C) B This is a capacitive element connected between the power supply and the bias node, and its capacitance value can be adjusted according to external control voltage, process angle, or temperature. This capacitor is used to dynamically compensate for transient fluctuations in the bias node, achieving adaptive suppression of supply noise and simultaneous switching noise (SSN).

[0049] SSN (Simultaneous Switching Noise) refers to the common-mode voltage fluctuations caused by the parasitic inductance of the power supply or ground leads when multiple channels switch simultaneously. This noise can lead to inconsistent output swings or delayed jitter among the channels, and in severe cases, crosstalk and eye diagram closure.

[0050] Supply noise refers to transient disturbances in VDD voltage caused by factors such as regulator ripple, package parasitics, and power sharing. In single-ended drivers, supply noise directly modulates the output current and level, affecting output linearity and signal integrity.

[0051] The cascaded transistor (M2) is used to isolate the output node from the bias current source, increase the circuit's output impedance, and improve bandwidth. Its gate voltage is controlled by the bias node, which is a key aspect of the compensation capacitor CB in this invention.

[0052] The output load resistor (RL), located between the power supply and the output node, is used to convert the drive current into an output voltage signal. Its resistance value affects the output swing and power consumption balance.

[0053] Eye diagram is an important indicator of high-speed signal integrity, comprehensively reflecting the effects of noise, jitter, distortion, etc. A larger opening indicates better signal quality. This invention improves the eye diagram opening of single-ended drives through bootstrapped bias compensation.

[0054] In one embodiment, see Figure 1 The present invention provides a single-ended driving circuit, comprising: a bias branch 1, a bias node, and an adjustable bootstrap capacitor C. B ;

[0055] The output signal terminal of bias branch 1 is connected to the load resistor R. L Connect to power supply VDD;

[0056] The driving end of bias branch 1 and the bias node V B Connection, bias node V B An adjustable bootstrap capacitor C is connected between the driver and the input terminal. B One end, adjustable bootstrap capacitor C B The other end is connected to the power supply VDD.

[0057] It should be noted that the output signal terminal is connected to the load resistor R. L Connected to the positive terminal of the power supply VDD, the level swing of the output signal at the output signal terminal is determined by the current flowing through the load resistor R. L The current is determined by the load resistor RL. The current path of this drive circuit is as follows: power supply VDD → through load resistor RL → bias branch 1 → ground. Bias branch 1 has an input signal terminal V. IN Among them, the input signal terminal V IN The bias branch 1 is used to receive input signals and to control the current on / off state, and to modulate the data of the input signal.

[0058] Bias node V B Used to provide DC bias voltage for bias branch 1 to drive bias branch 1.

[0059] In this embodiment, the capacitance of the adjustable bootstrap capacitor CB can be adjusted. In this embodiment, the power supply VDD and the bias node V... B An adjustable bootstrap capacitor C is connected between them. B This makes the adjustable bootstrap capacitor C B Voltage changes from the power supply can be transmitted to the bias node V via capacitive coupling. B Make the bias node V B The potential of the bias branch 1 fluctuates synchronously with the voltage fluctuation of the power supply VDD, thereby keeping the voltage at the drive end constant.

[0060] The working principle of this embodiment is as follows: Capacitive coupling is used to create a controlled compensation voltage at the bias node to compensate for power supply noise, thereby offsetting the changes in output current caused by power supply disturbances. Specifically, when the power supply VDD voltage rises, the adjustable bootstrap capacitor C... B The upper potential rises, and the adjustable bootstrap capacitor C B The coupling current flowing through it will momentarily increase the bias node V. B The potential of the variable capacitor C cancels out the voltage change at the drive terminal of bias branch 1; when the voltage of the power supply VDD drops, the adjustable bootstrap capacitor C... B As the potential at the upper end decreases, the adjustable bootstrap capacitor C... BDischarge causes the bias node V to... B The potential of the bias branch 1 decreases synchronously, thereby stabilizing the voltage at the drive terminal. Therefore, in this embodiment, the voltage at the bias node VDD decreases synchronously with the power supply VDD. B An adjustable bootstrap capacitor C is connected between them. B This forms a bootstrap compensation mechanism, enabling the single-ended drive circuit to maintain a constant bias current under power fluctuation conditions, achieving passive, high-bandwidth, and low-power power noise suppression, and possessing excellent power supply rejection performance (PSRR).

[0061] This embodiment introduces an adjustable bootstrap capacitor C between the driver stage and bias branch 1. B This achieves dynamic charge coupling compensation for power supply disturbances, enabling the bias node potential of the current source branch to float synchronously with power supply changes, thereby maintaining the gate-source voltage V of the cascaded transistor in bias branch 1. gs Constant power supply noise suppression is achieved, enabling passive, high bandwidth, and low power consumption. This solves the problem that traditional single-ended CML drivers are susceptible to power supply noise and simultaneous switching noise interference, which can lead to a decrease in output signal quality under high channel density and high speed (such as 112Gbps and above).

[0062] In one embodiment, the bias branch 1 includes a first NMOS transistor M1 and a second NMOS transistor M2;

[0063] The drain of the first NMOS transistor M1 is used as the output signal terminal and connected to the load resistor;

[0064] The gate of the first NMOS transistor M1 is used as the driving terminal and connected to the bias node;

[0065] The source of the first NMOS transistor M1 is connected to the drain of the second NMOS transistor M2;

[0066] The source of the second NMOS transistor M2 is grounded; the gate of the second NMOS transistor M2 is used as the input signal terminal.

[0067] It should be noted that, as Figure 1 As shown, the entire circuit uses NMOS transistors to construct a current-mode logic drive (CML) structure to provide high-speed, high-linearity single-ended voltage output. This structure includes an input signal terminal V. IN Output signal terminal V OUT Load resistance R L Adjustable bootstrap capacitor C B Pull-up bias node V B The transistor consists of a current-controlled transistor (i.e., the second NMOS transistor) M2 and an input switching transistor (i.e., the first NMOS transistor) M1. The gate of the first NMOS transistor M1 receives the input signal terminal V.IN The signal controls the current flow to achieve data modulation; the second NMOS transistor M2 serves as the current control stage, and its gate bias voltage is controlled by the bias node V. B Provided for setting the magnitude of a constant drive current.

[0068] In traditional CML single-ended drive structures, the second NMOS transistor M2 is typically controlled by a fixed DC bias voltage. Its gate bias node exhibits high impedance to power supply disturbances (ΔVDD), making it susceptible to power supply noise. When the power supply voltage fluctuates, the drain-source and gate-source voltages of M2 change accordingly, causing bias current fluctuations and resulting in problems such as output signal amplitude jitter, eye diagram closure, and unstable power consumption. Especially in high-speed, multi-channel SerDes transmitters, the simultaneous switching of numerous single-ended CMLs can cause severe simultaneous switching noise (SSN), further exacerbating the impact of power supply disturbances.

[0069] In this embodiment, an adjustable bootstrap capacitor C is provided. B The voltage change of the power supply VDD is transmitted to the bias node V via capacitive coupling. B Make the bias node V B The potential of M2 fluctuates synchronously with the fluctuations of the power supply VDD, thereby causing the gate-source voltage V of M2 to change. gs2 It remains essentially constant. Specifically, as the voltage of the power supply VDD rises, the adjustable bootstrap capacitor C... B As the upper potential rises, the adjustable bootstrap capacitor C... B The coupling current flowing through it will momentarily increase the bias node V. B The potential of M2 causes the gate-source voltage V to... gs2 The change is offset; when the voltage of the power supply VDD drops, the adjustable bootstrap capacitor C... B The potential at the upper end decreases, and the adjustable bootstrap capacitor C... B Discharge causes the bias node V to... B The potential decreases synchronously, thus maintaining the gate-source voltage V of M2. gs2 The drive circuit provided in this embodiment maintains a constant bias current under power fluctuation conditions, achieving excellent power supply rejection performance (PSRR). This bootstrap compensation mechanism ensures the drive circuit remains stable even under power fluctuation conditions.

[0070] Specifically, the working process of this embodiment is as follows:

[0071] The current path in this embodiment is: power supply VDD → load resistor R L →Second NMOS transistor M2→First NMOS transistor M1→Ground.

[0072] When the input signal terminal V IN When the input signal is high, the first NMOS transistor M1 is turned on, forming a current flowing from the power supply VDD through the load resistor R.L -The current path from the second NMOS transistor M2 to the first NMOS transistor M1 and ground, at this time the output terminal V OUT When the input signal goes low, the first NMOS transistor M1 is turned off, the current is interrupted, and the output V... OUT Through the load resistor R L The output level is pulled up to a high level. Throughout the process, the output level change is controlled by the conduction state of the first NMOS transistor M1, while the output swing and switching speed depend on the current stability of the second NMOS transistor M2. Due to the bootstrap compensation effect of this invention, the current of the second NMOS transistor M2 is almost unaffected by VDD fluctuations, thus significantly reducing output signal jitter and noise.

[0073] In one embodiment, the adjustable bootstrap capacitor includes at least one set of capacitor units; each capacitor unit includes a connected controlled switch and a capacitor.

[0074] It should be noted that the controlled switch has an on / off function. By changing its own on / off state, it alters the connection state of the capacitor (e.g., connecting or disconnecting), thereby changing the adjustable bootstrap capacitor C. B The overall capacitance value. In one example, such as... Figure 2 As shown, the controlled switch is connected in series with the capacitor. Figure 2 In this context, C represents a capacitor, and n represents the order of the capacitors.

[0075] Understandably, as a further improvement, the adjustable bootstrap capacitor C can be adjusted by controlling the controlled switch. B The capacitance value is adjusted to match different load capacitance and bias impedance conditions, thereby changing the response coefficient of the bias node to power supply fluctuations. This ensures that the compensation capacitor matches the power supply disturbance amplitude, achieving optimal noise suppression. In practical applications, the optimal C value can be found by monitoring the output eye diagram or noise power spectrum. B Configuration. In one example, this can be achieved via digital control signal D.<n:0> The controlled switch is controlled to select different equivalent capacitance values ​​to match different load capacitance and bias impedance conditions.<n:0> It refers to an n+1 bit digital control signal, which can be written into the control word via SPI controlled by the host computer.

[0076] In one embodiment, when there are multiple groups of capacitor cells, the groups of capacitor cells are connected in parallel.

[0077] It should be noted that, as Figure 2 As shown, each group of capacitor units is connected in parallel.

[0078] In one embodiment, the bias node includes a low-noise reference circuit; the low-noise reference circuit is connected to the bias branch 1 and is used to provide a DC component to the bias branch 1.

[0079] It should be noted that the bias node V in this embodiment B It can be generated by a low-noise reference circuit, such as a bandgap reference or a voltage divider network after RC filtering, to provide a stable DC component. Adjustable bootstrap capacitor C B The AC compensation signal is then superimposed on it to achieve the fusion of static bias and dynamic compensation. Based on this, the bias node V B It is fixed in steady state on DC and adapts to power fluctuations on AC, thus balancing steady-state accuracy and transient immunity.

[0080] In one embodiment, the capacitor is a MOS capacitor.

[0081] It should be noted that a MOS capacitor (Metal-Oxide-Semiconductor Capacitor) is a two-terminal capacitor structure made of metal-oxide-semiconductor bonding. One end is a metal gate and the other end is a semiconductor substrate. Its capacitance effect mainly relies on the depletion layer on the semiconductor surface and the dielectric effect of the oxide layer.

[0082] In one embodiment, the second NMOS transistor M2 serves as a constant current source, which can be replaced by a voltage-controlled current mirror, a segmented switching current array, or a charge pump-type dynamic bias unit to achieve programmable control of the output swing and common-mode level.

[0083] This invention provides a single-ended driving circuit that introduces an adjustable bootstrap capacitor CB into the single-ended CML driving structure. This allows for dynamic charge coupling to compensate for power fluctuations at the bias node, achieving a passive, high-bandwidth, and low-power power noise suppression mechanism. Furthermore, while maintaining the simplicity and high-speed characteristics of the single-ended architecture, it significantly improves its noise immunity and signal integrity, providing a scalable and practical core circuit foundation for future high-density multi-channel SerDes.

[0084] Compared to traditional fixed capacitor compensation or voltage-regulated servo methods, the high-speed single-ended CML driver provided by this invention features adjustable bootstrap bias. Without adding extra active loops or high-power modules, it achieves high-speed, low-power, and high PSRR single-ended output drive, significantly improving output eye diagram aperture and jitter performance. It balances signal integrity and energy efficiency requirements, providing an efficient, scalable, and noise-resistant core drive solution for future 112Gbps and higher-speed high-density single-ended SerDes transmitters. While ensuring the high-speed transmission characteristics and low power consumption of the CML circuit, it enhances the single-ended driver's ability to suppress power supply noise and simultaneous switching noise (SSN), achieving a balance between low power consumption, high density, and high-speed output. It solves the modulation problem of the bias node of traditional single-ended CML drivers due to power supply fluctuations, improves output current consistency and eye diagram aperture, significantly improves PSRR and signal integrity, and avoids the power consumption and complexity associated with using additional amplifiers or voltage regulator modules. This solution is particularly suitable for high-speed SerDes transmitters with speeds of 112Gbps and above, providing a scalable solution with both noise immunity and energy efficiency advantages for future single-ended multi-channel high-speed interconnects.

[0085] In one embodiment, the present invention also provides a transmitter including the circuitry of any of the above embodiments.

[0086] It should be noted that the transmitter in this embodiment can be a SerDes transmitter (TX).

[0087] like Figure 3 As shown, Figure 3 The block diagram shows the structure of the single-ended drive circuit provided by this invention applied to a SerDes transmitter (TX). Figure 3 In this circuit, the serializer is used to convert parallel data input to the SerDes transmitter (TX) into serial data and input the serial data to the driver CML Drv (i.e., the single-ended driver circuit provided by this invention). The CML Drv uses the serial data to drive the transmission line or the input terminal of the optoelectronic modulator based on its internal bootstrap compensation mechanism.

[0088] The SerDes transmitter is clocked by a phase-locked loop (PLL). In a multi-channel parallel system, the C of each channel... B It can be controlled independently. During the startup phase, the system can detect the output eye diagram or SSN index through the calibration circuit and adjust C. B To achieve the best noise reduction performance, the value should be set.

[0089] In a simulation application example, the single-ended driving circuit provided by the present invention is simulated, and the effect of the single-ended driving circuit provided by the present invention is explained in conjunction with the simulation result diagram.

[0090] In this application example, noise was added to the simulation of the traditional single-ended CML circuit and the single-ended drive circuit of the present invention. The simulation results are as follows: Figure 4 As shown. Among them, Figure 4 (a) in the diagram is the simulated eye diagram of a traditional single-ended CML circuit. Figure 4 (b) is the simulation eye diagram of the single-ended drive circuit of the present invention, according to Figure 4 As can be seen, compared with traditional single-ended CML circuits, this invention can truly reflect the actual operation of the circuit under real working conditions, providing a reliable basis for subsequent optimization. Furthermore, it demonstrates that the structure of the driving circuit of this invention achieves adaptive power supply noise suppression without adding additional active components, resulting in a simple circuit with small area and low power consumption. Compared with traditional solutions using negative feedback amplifiers or LDO voltage regulation, this invention achieves broadband noise compensation without the need for amplifiers, without introducing additional delay or bandwidth limitations. Moreover, this invention is applicable to single-ended CML drivers, current-controlled DAC (Digital-to-Analog Converter) output stages, on-chip optoelectronic modulator drivers, and multi-channel SerDes transmitters, providing a reliable driving solution for next-generation low-power, high-speed interconnects.

[0091] Please see Figure 5 The present invention provides a configuration method for a single-ended driving circuit, applicable to the circuit of any of the above embodiments, comprising:

[0092] 101. Obtain and calculate the optimal compensation value of the adjustable bootstrap capacitor based on the driving input capacitor, transistor transconductance, and on-resistance of the single-ended driving circuit.

[0093] It should be noted that the small-signal model of the bias node in a single-ended drive circuit can be represented as a circuit containing a bias resistor R. B Adjustable capacitor C B and the driver input capacitor C in The first-stage RC network. The drive input capacitor in this step is the driver input capacitor C. in Specifically, the transconductance of the transistor refers to the transconductance of the second NMOS transistor, and the on-resistance refers to the on-resistance of the second NMOS transistor.

[0094] 102. Configure the value of the adjustable bootstrap capacitor to the optimal compensation value.

[0095] It should be noted that the single-ended drive circuit achieves this by introducing an adjustable capacitor C into the bias network. B Its core principle lies in using capacitive coupling to create a controlled compensation voltage at the bias node to counteract power supply noise, thereby canceling out output current variations caused by power supply disturbances. BAdjustable capacitor C B and the driver input capacitor C in For a first-order RC network, the node voltage perturbations satisfy:

[0096]

[0097] in,

[0098]

[0099] k is the power supply noise coupling coefficient.

[0100] When the output current small signal changes as follows:

[0101]

[0102] in, For the transconductance of the second NMOS transistor, The on-resistance of the second NMOS transistor is... For the variable of power supply voltage, This represents the change in the bias node voltage.

[0103] To achieve optimal noise cancellation, the following conditions must be met:

[0104]

[0105] Therefore, the optimal coupling coefficient is obtained as follows:

[0106]

[0107] because,

[0108]

[0109] Therefore, the optimal compensation capacitance value can be derived as follows:

[0110]

[0111] Therefore, after obtaining the driving input capacitance, transistor transconductance, and transistor on-resistance, the optimal compensation capacitance value of the adjustable bootstrap capacitor can be calculated based on the above-mentioned formula for calculating the optimal compensation capacitance value. Then, the adjustable bootstrap capacitance value in the drive circuit is configured to the optimal compensation capacitance value. This is to achieve the best noise suppression effect. Furthermore, the calculation method provided in this embodiment not only lays the theoretical foundation for adjustable bias compensation, but also ensures that the compensation mechanism remains robust under different process, temperature, and load conditions.

[0112] In another implementation, in addition to using the above formula to calculate the optimal compensation capacitance... In addition, different discrete values ​​of CB[n] can be selected by digital control to approximate the above optimal result. Furthermore, the optimal configuration n can be searched in the adjustable bootstrap capacitor according to the principle of minimizing eye diagram opening, noise power spectral density, or output current fluctuation, so that the bias node generates a compensation voltage that matches the power supply disturbance amplitude, thereby achieving the best power supply noise and SSN (switching transient noise) suppression effect.

[0113] The present invention also provides an electronic device, the device including a processor and a memory:

[0114] The memory is used to store program code and transfer the program code to the processor;

[0115] The processor is used to execute the methods described in the above embodiments according to the instructions in the program code.

[0116] The present invention also provides a computer-readable storage medium for storing program code for performing the methods described in the above embodiments.

[0117] In summary, the single-ended driving circuit, transmitter, configuration method, and related devices provided by the present invention have the following beneficial effects.

[0118] Traditional current-mode CML drives achieve high-speed signal transmission through constant current sources and differential pair switching, but their power consumption is limited by the constant tail current, and in high-speed, large-swing transmission, they suffer from linearity degradation, increased common-mode jitter, and eye diagram shrinkage. Meanwhile, for voltage-mode drive structures, although static power consumption can be effectively reduced, they are prone to output distortion and inter-symbol interference under large-bandwidth signal transmission.

[0119] The unified, configurable, single-ended driver structure proposed in this invention achieves compatibility with both current-mode and voltage-mode signals at the architectural level. It can adjust to the optimal operating mode within the same driver core based on bandwidth, power consumption, and swing requirements. Through coordinated control of an adjustable dynamic current source and an adaptive voltage compensation network, it achieves optimal matching of output impedance, common-mode level, and transient response in different modes, thereby significantly improving signal integrity and power efficiency without adding extra complexity. Furthermore, this invention breaks away from the traditional single paradigm of CML's "constant current + differential load" in its cross-domain design concept, enabling the driver circuit to be flexibly applied in different system environments such as high-speed serial communication, ADC sampling buffers, and optoelectronic interface drivers, exhibiting good universality and scalability. Therefore, compared with existing technologies, this invention achieves quantitative improvements in bandwidth retention, output linearity, power consumption control, and mode reconfigurability, providing a unified, efficient, and reconfigurable driver solution for next-generation high-speed interconnects and mixed-signal interfaces.

[0120] Specifically, this invention achieves dynamic compensation of the bias node by introducing an adjustable bootstrap bias capacitor structure, and constructs a noise immunity mechanism that is universal in single-ended CML and voltage-mode drive circuits. It can adaptively cancel the bias current disturbance caused by power supply voltage fluctuation (ΔVDD), and overcome the inherent bottleneck of high impedance of the bias node and high sensitivity to power supply noise in traditional fixed bias circuits.

[0121] This invention centers on a synchronous coupling mechanism between power supply voltage fluctuations and the dynamic response of the bias node, achieved by introducing an adjustable bootstrap capacitor C between the bias node and the power supply terminal. B Make the bias node V B The voltage of the variable bootstrap capacitor CB can fluctuate in phase or proportionally during power supply transients, thereby maintaining a constant gate-source voltage of the current-controlled transistor M2 and effectively suppressing power supply noise, current jitter, and signal amplitude inconsistencies. The equivalent value of this variable bootstrap capacitor CB can be adjusted digitally or analogically to achieve optimal compensation under different loads, power supply noise spectra, and speed conditions. Compared with existing schemes using active feedback (such as operational amplifiers, LDOs, cascode feedback networks, etc.), this invention achieves broadband suppression with a purely passive compensation structure, avoiding additional power consumption, stability limitations, and noise amplification effects. Therefore, it has particular advantages in high-speed, low-power application scenarios.

[0122] Furthermore, the present invention also utilizes the bias node V B A low-noise reference circuit is incorporated to maintain a fixed reference potential in the DC domain for stable operation, while dynamic floating compensation is achieved in the AC domain using a bootstrap capacitor. This completes the construction of a dual-domain separated response mechanism. This biasing strategy combines DC accuracy with dynamic noise immunity, enabling the bias circuit to maintain steady-state and dynamic tracking in the DC and AC domains respectively. This allows the circuit to maintain constant output swing and extremely low jitter even at high data rates (e.g., >25Gbps). The bias node can be provided by a bandgap reference source or generated by an on-chip adaptive current mirror structure, in conjunction with C... B Adjustments are made to form a complete power supply noise tracking network.

[0123] At the structural level, this invention proposes a single-ended driver circuit for maintaining a constant bias current and achieving adaptive compensation for power supply fluctuations. This circuit is applicable not only to CML current-mode logic output stages but can also be extended to voltage-mode driver circuits, supporting unified implementation across multiple process nodes. Its function is equivalent to dynamic supply tracking compensation, thus enabling the output stage to possess excellent power supply rejection and signal linearization capabilities even in voltage modulation scenarios. Therefore, the principle of this invention has cross-domain universality and can be shared in various logic standards and physical layer interfaces, including single-ended SerDes transmitters, low-power MIPI PHY drivers, on-chip optical modulator interfaces, current-controlled DACs, and cross-power-domain I / O drivers.

[0124] Furthermore, in this invention, the adjustable bootstrap capacitor utilizes a MOS variable capacitor array or a digital control unit to adjust its equivalent capacitance value, achieving optimal adaptation to different noise frequency bands and load conditions. This allows for a balanced optimization of the output swing, power consumption, and noise performance of the single-ended drive circuit through bias current and adjustment of the adjustable bootstrap capacitor's capacitance value, resulting in low power consumption and low noise. Additionally, this invention achieves transient tracking through capacitive coupling, effectively improving PSRR and realizing broadband noise immunity compensation without the need for amplifiers or feedback amplification loops.

[0125] Therefore, this invention, through an adjustable bootstrap bias passive compensation mechanism, achieves adaptive tracking compensation for power supply disturbances without relying on complex active circuits. This significantly improves output signal integrity, reduces power consumption, and enhances power supply robustness in high-speed communication and analog mixed-signal applications. Its concept is not limited to a specific drive type but is based on the common principle of "dynamic coupling of bias potential," thus making it applicable to a wide range of circuit architectures. This invention represents a significant breakthrough in architectural concept and applicability. The structure is simple, highly integrable, and easy to implement in layouts. It can realize high-speed, low-power, noise-resistant drive units under standard CMOS processes, possessing significant engineering practical value and patent protection significance. For example, in terms of process implementation, the drive circuit provided by this invention can be applied to different process platforms such as all-CMOS, BiCMOS, or FinFET to achieve the same function.

[0126] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0127] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0128] Furthermore, in the various embodiments of the present invention, the functional units can be integrated into one processing unit, or each functional unit can be a separate physical entity, or two or more functional units can be integrated into one processing unit. The integrated unit described above can be implemented in hardware or as a software functional unit.

[0129] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0130] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0131] It should also be noted that in the description of this invention, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0132] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. For example, as long as configurable switching and linearized output control of current mode and voltage mode under a unified structure can be achieved, they can be regarded as reasonable variations and equivalent alternatives to the ideas of the present invention.

Claims

1. A single-ended drive circuit, characterized by comprising: include: Bias branch, bias node, and adjustable bootstrap capacitor; The output signal terminal of the bias branch is connected to the power supply through a load resistor; The driving end of the bias branch is connected to the bias node, one end of the adjustable bootstrap capacitor is connected between the bias node and the driving end, and the other end of the adjustable bootstrap capacitor is connected to the power supply.

2. The circuit of claim 1, wherein, The adjustable bootstrap capacitor includes at least one set of capacitor units; each capacitor unit includes a connected controlled switch and a capacitor.

3. The circuit of claim 2, wherein, When there are multiple groups of capacitor units, the capacitor units in each group are connected in parallel.

4. The circuit of claim 3, wherein, The bias branch includes a first NMOS transistor and a second NMOS transistor; The drain of the first NMOS transistor serves as the output signal terminal and is connected to the load resistor; The gate of the first NMOS transistor serves as the driving terminal and is connected to the bias node; The source of the first NMOS transistor is connected to the drain of the second NMOS transistor; The source of the second NMOS transistor is grounded; the gate of the second NMOS transistor serves as the input signal terminal.

5. The circuit of claim 4, wherein, The bias node includes a low-noise reference circuit; the low-noise reference circuit is connected to the bias branch and is used to provide a DC component to the bias branch.

6. The circuit of claim 5, wherein, The capacitor is a MOS capacitor.

7. A transmitter, characterized by Includes the circuit as described in any one of claims 1-6.

8. A configuration method of a single-ended drive circuit, characterized by comprising: Applied to the circuit as described in any one of claims 1-6, comprising: The optimal compensation value of the adjustable bootstrap capacitor is calculated based on the driving input capacitor, transistor transconductance, and on-resistance of the single-ended driving circuit. The capacitance value of the adjustable bootstrap capacitor is configured to the optimal compensation capacitance value.

9. An electronic device, comprising: The device includes a processor and a memory: The memory is used to store program code and transmit the program code to the processor; The processor is configured to execute the method as described in claim 8 according to instructions in the program code.

10. A computer readable storage medium characterized by, The computer-readable storage medium is used to store program code for performing the method as described in claim 8.

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