Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a driving circuit layer (102) disposed on a base (101); the driving circuit layer (102) at least comprises a plurality of circuit units; at least one circuit unit comprises a pixel driving circuit, and the pixel driving circuit comprises a driving transistor, a second switch transistor, and a capacitor; the driving transistor comprises a first active layer (13); the second switch transistor comprises a third active layer (19); the capacitor comprises a second electrode plate (15-1); the third active layer (19) is provided on the side of the first active layer (13) away from the base (101); the second electrode plate (15-1) is arranged between the first active layer (13) and the third active layer (19); the second electrode plate (15-1) is connected to a second end of the first active layer (13) by means of a first via hole (V1); the second electrode plate (15-1) forms a recessed region in the first via hole (V1); a dielectric layer (20) is provided on the side of the second electrode plate (15-1) away from the base (101); at least part of the dielectric layer (20) is provided in the recessed region; and the orthographic projection of the third active layer (19) on the base (101) overlaps the orthographic projection of the recessed region on the base (101).

Description

Display substrate, preparation method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202411376822.X, filed on September 29, 2024, and entitled "Display substrate, preparation method thereof and display device", the contents of which are hereby incorporated by reference into the present application. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a driving circuit layer disposed on a substrate, the driving circuit layer comprising at least a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising a driving transistor, a second switching transistor and a capacitor; the driving transistor comprising a first active layer, the second switching transistor comprising a third active layer, the capacitor comprising a second electrode plate, the third active layer being disposed on a side of the first active layer away from the substrate, the second electrode plate being disposed between the first active layer and the third active layer, the second electrode plate being connected to a second end of the first active layer through a first via, the second electrode plate forming a recessed area in the first via, the second electrode plate being provided with a dielectric layer on a side thereof away from the substrate, at least part of the dielectric layer being disposed in the recessed area, a projection of the third active layer on the substrate overlapping with a projection of the recessed area on the substrate.

[0006] In an example embodiment, a surface of the medium layer distal to the substrate forms a plane with a surface of the second plate distal to the substrate.

[0007] In an example embodiment, a footprint of the third active layer on the substrate includes a footprint of the recessed region on the substrate.

[0008] In an example embodiment, a footprint of the third active layer on the substrate overlaps with a footprint of the first active layer on the substrate.

[0009] In an example embodiment, the first via has a polygonal shape, at least one side of the first via has a length less than or equal to 1 micrometer; or, the first via has a circular shape, a diameter of the first via is less than or equal to 1 micrometer; or, the first via has an elliptical shape, a length of a minor axis of the first via is less than or equal to 1 micrometer.

[0010] In an example embodiment, the driving transistor further includes a second gate, the second gate is disposed between the first active layer and the second plate, a footprint of the second gate on the substrate overlaps with a footprint of the first active layer on the substrate, the capacitor includes a first plate, the second gate as the first plate, a footprint of the second gate on the substrate overlaps with a footprint of the second plate on the substrate.

[0011] In an example embodiment, the driving transistor further includes a first gate, the first gate is located on a side of the first active layer close to the substrate, a footprint of the first gate on the substrate overlaps with a footprint of the first active layer on the substrate.

[0012] In an example embodiment, the pixel driving circuit further includes a first power supply line, the first power supply line is disposed on a side of the third active layer distal to the substrate, the first power supply line is connected to the first end of the first active layer through a fifth via.

[0013] In an example embodiment, the second switch transistor further includes a third gate, the third gate is located between the third active layer and the second plate, a footprint of the third gate on the substrate overlaps with a footprint of the third active layer on the substrate.

[0014] In an example embodiment, the pixel driving circuit further comprises a light-emitting structure layer disposed away from the substrate side of the driving circuit layer, the light-emitting structure layer comprising a light-emitting device, the light-emitting device comprising a first electrode, a light-emitting functional layer and a second electrode disposed in sequence away from the substrate, the pixel driving circuit further comprising a second connection electrode, the second connection electrode being located between the third active layer and the first electrode, at least part of the second connection electrode being in contact with the surface of the second end of the third active layer away from the substrate side, the second connection electrode being connected with the second electrode plate through a sixth via, and the second connection electrode being connected with the first electrode.

[0015] In an example embodiment, the pixel driving circuit further comprises a sensing signal line, the sensing signal line being located away from the substrate side of the third active layer, and at least part of the sensing signal line being in contact with the surface of the first end of the third active layer away from the substrate side.

[0016] In an example embodiment, the pixel driving circuit further comprises a first switch transistor, the first switch transistor comprising a second active layer, the second active layer being located between the second electrode plate and the third active layer, the second active layer being provided with a first adapter electrode on the surface of the substrate side, the first adapter electrode being in contact with the second active layer, the first adapter electrode being provided with a second gate electrode on the substrate side, and the first adapter electrode being connected with the second gate electrode through a third via; and the second gate electrode serving as a gate electrode of the driving transistor.

[0017] In an example embodiment, the second active layer comprises a projection of the first adapter electrode on the substrate.

[0018] In an example embodiment, the first adapter electrode comprises a projection of the third via on the substrate.

[0019] In an example embodiment, the pixel driving circuit further comprises a first switch transistor, the first switch transistor comprising a second active layer, the second active layer being located between the second electrode plate and the third active layer, the second active layer being provided with a second adapter electrode on the surface of the substrate side, the second adapter electrode being in contact with the second active layer, the second adapter electrode being provided with a data signal line on the substrate side, and the second adapter electrode being connected with the data signal line through a fourth via.

[0020] In an example embodiment, the second active layer comprises a projection of the second adapter electrode on the substrate.

[0021] In an exemplary embodiment, a projection of the second transfer electrode on the substrate includes a projection of the fourth via on the substrate.

[0022] In an exemplary embodiment, the pixel driving circuit further includes a first connection electrode, the first connection electrode is located in the same film layer as the second plate, the first connection electrode is located between the data signal line and the second transfer electrode, the second transfer electrode is connected with the first connection electrode through the fourth via, and the first connection electrode is connected with the data signal line through a second via.

[0023] In another aspect, the present disclosure further provides a preparation method of a display substrate, including:

[0024] forming a driving circuit layer on a substrate, the driving circuit layer at least includes a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, the pixel driving circuit includes a second switch transistor, a driving transistor and a capacitor; the driving transistor includes a first active layer, the second switch transistor includes a third active layer, and the capacitor includes a second plate, the third active layer is arranged on a side of the first active layer away from the substrate, the second plate is arranged between the first active layer and the third active layer, the second plate is connected with a second end of the first active layer through a first via, the second plate forms a recessed area in the first via, a dielectric layer is arranged on a side of the second plate away from the substrate, at least part of the dielectric layer is arranged in the recessed area, and a projection of the third active layer on the substrate overlaps with a projection of the recessed area on the substrate.

[0025] In another aspect, the present disclosure further provides a display device including the aforementioned display substrate.

[0026] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or can be learned by practice of the present application. Other advantages of the present application will be realized and attained by those skilled in the art based on the description and drawings provided herein. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the technical scheme of the present application, and constitute a part of the specification, and are used to explain the technical scheme of the present application together with the embodiments of the present application, and do not constitute a limitation on the technical scheme of the present application.

[0028] Fig. 1 is a structural schematic diagram of a display device;

[0029] Fig. 2 is a planar structural schematic diagram of a display substrate;

[0030] Fig. 3 is a cross-sectional structural schematic diagram of a display substrate;

[0031] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to an example embodiment of the present disclosure;

[0032] FIG. 5a is a schematic diagram of a display substrate according to an example embodiment of the present disclosure, after forming a first hole in a process of preparing a first via hole;

[0033] FIG. 5b is a schematic diagram of a display substrate according to an example embodiment of the present disclosure, after forming an inorganic medium layer in a process of preparing a first via hole;

[0034] FIG. 5c is a schematic diagram of a display substrate according to an example embodiment of the present disclosure, after forming a first via hole in a process of preparing a first via hole.

[0035] FIG. 6 is a schematic diagram of a display substrate according to an example embodiment of the present disclosure, after forming a first conductive layer pattern in a process of preparing the display substrate;

[0036] FIGS. 7a and 7b are schematic diagrams of a display substrate according to an example embodiment of the present disclosure, after forming a second conductive layer pattern in a process of preparing the display substrate;

[0037] FIGS. 8a and 8b are schematic diagrams of a display substrate according to an example embodiment of the present disclosure, after forming a first semiconductor layer pattern in a process of preparing the display substrate;

[0038] FIGS. 9a and 9b are schematic diagrams of a display substrate according to an example embodiment of the present disclosure, after forming a third conductive layer pattern in a process of preparing the display substrate;

[0039] FIG. 10 is a schematic diagram of a display substrate according to an example embodiment of the present disclosure, after forming a fifth insulating layer pattern in a process of preparing the display substrate;

[0040] FIGS. 11a and 11b are schematic diagrams of a display substrate according to an example embodiment of the present disclosure, after forming a fourth conductive layer pattern in a process of preparing the display substrate;

[0041] FIGS. 12a and 12b are schematic diagrams of a display substrate according to an example embodiment of the present disclosure, after forming a medium layer in a process of preparing the display substrate;

[0042] FIG. 13 is a schematic diagram of a display substrate according to an example embodiment of the present disclosure, after forming a sixth insulating layer pattern in a process of preparing the display substrate;

[0043] FIGS. 14a and 14b are schematic diagrams of a display substrate according to an example embodiment of the present disclosure, after forming a fifth conductive layer pattern in a process of preparing the display substrate;

[0044] FIGS. 15a, 15b, and 15c are schematic diagrams of a display substrate according to an example embodiment of the present disclosure, after forming a second semiconductor layer pattern in a process of preparing the display substrate;

[0045] FIGS. 16a and 16b are schematic diagrams of a display substrate according to an example embodiment of the present disclosure, after forming a sixth conductive layer pattern in a process of preparing the display substrate;

[0046] FIGS. 17a, 17b and 17c are schematic views of a display substrate after forming a third semiconductor layer pattern in a manufacturing process of the display substrate according to an embodiment of the present disclosure;

[0047] FIG. 18 is a schematic view of a display substrate after forming an eighth insulating layer pattern in a manufacturing process of the display substrate according to an embodiment of the present disclosure;

[0048] FIGS. 19a and 19b are schematic views of a display substrate after forming a seventh conductive layer pattern in a manufacturing process of the display substrate according to an embodiment of the present disclosure;

[0049] FIG. 20 is a schematic view of a display substrate after forming a ninth insulating layer pattern in a manufacturing process of the display substrate according to an embodiment of the present disclosure;

[0050] FIGS. 21a and 21b are schematic views of a display substrate after forming an eighth conductive layer pattern in a manufacturing process of the display substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] The present application describes multiple embodiments, but the description is exemplary rather than limiting, and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described in the present application. Although many combinations of possible features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Unless specifically limited, any feature or element of any embodiment can be utilized with any other feature or element of any other embodiment, or can replace any other feature or element in any other embodiment.

[0052] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in the present application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in the present application can be implemented alone or in any appropriate combination. Accordingly, the embodiments are not to be restricted, except as by the appended claims and their equivalents. Additionally, various modifications and changes can be made within the scope of the attached claims.

[0053] Furthermore, in describing representative embodiments, the specification can have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process depends on the performance of certain steps, the method or process is not limited to the performance of the steps in the specific order described. One of ordinary skill in the art would realize that other step orders are possible. Therefore, the specific order of steps recited in the specification should not be construed as limitations on the claims. Moreover, the claims should not be limited to the performance of the steps in the order written, as one of ordinary skill would readily understand that the steps can be varied, and still remain within the spirit and scope of the present embodiments.

[0054] The inventor of the present disclosure found that in the related display backplane design, the active layer of the low-temperature polysilicon thin film transistor and the active layer of the oxide thin film transistor do not overlap with the deep hole below, preventing the semiconductor layer from climbing at the deep hole position and the uneven morphology leading to uneven characteristics. In the related display backplane, the active layer does not overlap with the deep hole, which cannot effectively utilize the space, making the length of the channel smaller, the storage capacitance smaller, leading to short channel effect, parasitic capacitance and other adverse effects, and further leading to display abnormalities.

[0055] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller is connected with the data driver, the scan driver, and the light emitting driver respectively, the data driver is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan driver is connected with a plurality of scan signal lines (S1 to Sm) respectively, and the light emitting driver is connected with a plurality of light emitting signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected with the scan signal line, the light emitting signal line, and the data signal line respectively, and the light emitting unit can include a light emitting device connected with the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data driver can sample the gray value using the clock signal, and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emitting driver can generate emission signals to be provided to the light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0056] FIG. 2 is a schematic diagram of a planar structure of a display substrate. In an example embodiment, the display substrate can include a display area and a frame area located at a periphery of the display area. As shown in FIG. 2, the display area of the display substrate can include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P can include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel can include a circuit unit and a light emitting unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected with a scan signal line, a data signal line and a light emitting signal line respectively, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light emitting signal line, and output a corresponding current to a light emitting device. The light emitting unit can include at least a light emitting device, the light emitting device is connected with the pixel driving circuit of the sub-pixel where the light emitting device is located respectively, and the light emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the light emitting device is located.

[0057] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 can be a green sub-pixel (G) emitting green light. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present disclosure.

[0058] In an example embodiment, the pixel unit can include four sub-pixels, and the four sub-pixels can be arranged in a horizontal parallel, vertical parallel or square manner, which is not limited in the present disclosure.

[0059] FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels in the display substrate. As shown in FIG. 3, in a plane perpendicular to the display substrate, the display area of the display substrate can include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate can include other film layers, such as a touch structure layer, which is not limited in the present disclosure.

[0060] In the example embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving circuit layer 102 can include a plurality of circuit units, which can at least include a pixel driving circuit, and the pixel driving circuit can include a plurality of transistors and a storage capacitor. The light emitting structure layer 103 can include a plurality of light emitting units, which can at least include a light emitting device, and the light emitting device can include an anode, an organic light emitting layer, and a cathode, the anode is connected with the pixel driving circuit, the organic light emitting layer is connected with the anode, and the cathode is connected with the organic light emitting layer, and the organic light emitting layer emits light of a corresponding color under the driving of the anode and the cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, the second encapsulation layer can be made of organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can prevent external water vapor from entering the light emitting structure layer 103.

[0061] In the example embodiment, the organic light emitting layer can include a light emitting layer (EML) and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0062] The display substrate of the present disclosure is illustrated below by some example embodiments.

[0063] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to an example embodiment of the present disclosure. In the example embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 9T2C structure. As shown in FIG. 4, the pixel driving circuit according to the example embodiment of the present disclosure can be a 3T1C structure, which can include 3 transistors (a first transistor T1 to a third transistor T3) and 1 storage capacitor C, and the pixel driving circuit is connected with a sensing signal line SL, a data signal line DATA, a first power supply line VDD, a second power supply line VSS, and a scan signal line SCAN, respectively.

[0064] In the example embodiment, the pixel driving circuit can include a first node N1, a second node N2, a fourth node N4, and a fifth node N5. The first node N1 is connected with a second electrode of the second transistor, a gate electrode of the first transistor T1, and a first terminal of the storage capacitor C, respectively. The second node N2 is connected with a second electrode of the third transistor, a second terminal of the storage capacitor C, a second electrode of the first transistor T1, and a first electrode of the light emitting device EL, respectively. The fourth node N4 is connected with the data signal line DATA and a first electrode of the second transistor, respectively. The fifth node N5 is connected with the sensing signal line SL and a first electrode of the third transistor, respectively.

[0065] In an example embodiment, a first end (a first plate) of the storage capacitor C is connected to the first node N1, and a second end (a second plate) of the storage capacitor C is connected to the second node N2.

[0066] In an example embodiment, the first transistor T1 is a driving transistor; the second transistor T2 is a first switch transistor for writing of a data signal; and the third transistor T3 is a second switch transistor for extracting of a threshold voltage or current.

[0067] In an example embodiment, a gate electrode of the first transistor T1 is connected to the first node N1, and the first node N1 is connected to a second electrode of the second transistor and a first end of the storage capacitor C; a first electrode of the first transistor T1 is connected to the first power supply line VDD; a second electrode of the first transistor T1 is connected to the second node N2, and the second node N2 is connected to a second electrode of the third transistor, a second end of the storage capacitor C, and a first electrode of the light emitting device EL; and a second electrode of the light emitting device EL is connected to the second power supply line VSS. The first transistor T1 is configured to generate a corresponding current at the second electrode of the first transistor T1 under control of a data signal received at the gate electrode of the first transistor T1, and control the light emitting device EL to emit light. A gate electrode of the second transistor T2 is connected to the scan signal line SCAN; a first electrode of the second transistor T2 is connected to the data signal line DATA through the fourth node N4; a second electrode of the second transistor T2 is connected to the first node N1, and the first node N1 is connected to the gate electrode of the first transistor T1 and the first end of the storage capacitor C; and the second transistor T2 is configured to receive a data signal transmitted by the data signal line DATA under control of the scan signal line SCAN. A gate electrode of the third transistor T3 is connected to the scan signal line SCAN; a first electrode of the third transistor T3 is connected to the sensing signal line SL through the fifth node N5; a second electrode of the third transistor T3 is connected to the second node N2, and the second node N2 is connected to the second end of the storage capacitor C, the second electrode of the first transistor T1, and the first electrode of the light emitting device EL; and the third transistor T3 is configured to extract a threshold voltage Vth and a mobility of the third transistor T3 in response to a compensation timing, and compensate the threshold voltage Vth.

[0068] In an example embodiment, the light emitting device EL can be an OLED including a first electrode (anode), a light emitting functional layer, and a second electrode (cathode) stacked in sequence; the light emitting device EL can be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked in sequence; or the light emitting device EL can be an LED.

[0069] In an example embodiment, a first electrode of the light emitting device EL is connected to the second node N2, a second electrode of the light emitting device EL is connected to the second power supply line VSS, and a signal of the second power supply line VSS is a low level signal continuously provided, and a signal of the first power supply line VDD is a high level signal continuously provided.

[0070] In an example embodiment, the second transistor T2 and the third transistor T3 can be oxide thin film transistors, and the first transistor T1 can be a low temperature poly-silicon thin film transistor. The active layer of the low temperature poly-silicon thin film transistor is made of low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate, i.e., an LTPO display substrate, can take advantage of both, can realize low frequency driving, can reduce power consumption, and can improve display quality.

[0071] The display substrate provided by the embodiment of the present disclosure comprises a driving circuit layer disposed on a substrate, wherein the driving circuit layer comprises at least a plurality of circuit units, and at least one circuit unit comprises a pixel driving circuit, and the pixel driving circuit comprises a driving transistor, a second switch transistor and a capacitor; the driving transistor comprises a first active layer, the second switch transistor comprises a third active layer, and the capacitor comprises a second electrode plate; the third active layer is disposed on a side of the first active layer away from the substrate, the second electrode plate is disposed between the first active layer and the third active layer, the second electrode plate is connected to a second end of the first active layer through a first via, the second electrode plate forms a recessed area in the first via, a dielectric layer is disposed on a side of the second electrode plate away from the substrate, at least part of the dielectric layer is disposed in the recessed area, and a projection of the third active layer on the substrate overlaps with a projection of the recessed area on the substrate.

[0072] In an example embodiment, a surface of the dielectric layer away from the substrate is planar with a surface of the second electrode plate away from the substrate.

[0073] In an example embodiment, a projection of the third active layer on the substrate contains a projection of the recessed area on the substrate.

[0074] In an example embodiment, a projection of the third active layer on the substrate overlaps with a projection of the first active layer on the substrate.

[0075] In an example embodiment, the first via has a polygonal shape, at least one side of the first via has a length less than or equal to 1 micrometer; or, the first via has a circular shape, a diameter of the first via is less than or equal to 1 micrometer; or, the first via has an elliptical shape, a length of a minor axis of the first via is less than or equal to 1 micrometer.

[0076] In an example embodiment, the driving transistor further includes a second gate electrode, the second gate electrode is disposed between the first active layer and the second plate, a projection of the second gate electrode on the substrate overlaps with a projection of the first active layer on the substrate, the capacitor includes a first plate, the second gate electrode as the first plate, a projection of the second gate electrode on the substrate overlaps with a projection of the second plate on the substrate.

[0077] In an example embodiment, the driving transistor further includes a first gate electrode, the first gate electrode is located on a side of the first active layer close to the substrate, a projection of the first gate electrode on the substrate overlaps with a projection of the first active layer on the substrate.

[0078] In an example embodiment, the pixel driving circuit further includes a first power signal line, the first power signal line is disposed on a side of the third active layer away from the substrate, the first power signal line is connected to the first end of the first active layer through a fifth via.

[0079] In an example embodiment, the second switch transistor further includes a third gate electrode, the third gate electrode is located between the third active layer and the second plate, a projection of the third gate electrode on the substrate overlaps with a projection of the third active layer on the substrate.

[0080] In an example embodiment, further including a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the light emitting structure layer includes a light emitting device, the light emitting device includes a first electrode, a light emitting functional layer and a second electrode disposed in sequence along a direction away from the substrate, the pixel driving circuit further includes a second connection electrode, the second connection electrode is located between the third active layer and the first electrode, at least part of the second connection electrode contacts a surface of the second end of the third active layer away from the substrate, the second connection electrode is connected to the second plate through a sixth via, and the second connection electrode is connected to the first electrode.

[0081] In an example embodiment, the pixel driving circuit further includes a sensing signal line, the sensing signal line is located on a side of the third active layer away from the substrate, and at least part of the sensing signal line contacts a surface of the first end of the third active layer away from the substrate.

[0082] In an example embodiment, the pixel driving circuit further comprises a first switch transistor, the first switch transistor comprises a second active layer, the second active layer is located between the second plate and the third active layer, the second active layer is provided with a first transfer electrode close to the surface of the substrate side, the first transfer electrode is in contact with the second active layer, the first transfer electrode is provided with a second gate electrode close to the substrate side, and the first transfer electrode is connected with the second gate electrode through a third via hole; the second gate electrode serves as a gate electrode of the driving transistor.

[0083] In an example embodiment, the orthographic projection of the second active layer on the substrate comprises the orthographic projection of the first transfer electrode on the substrate.

[0084] In an example embodiment, the orthographic projection of the first transfer electrode on the substrate comprises the orthographic projection of the third via hole on the substrate.

[0085] In an example embodiment, the pixel driving circuit further comprises a first switch transistor, the first switch transistor comprises a second active layer, the second active layer is located between the second plate and the third active layer, the second active layer is provided with a second transfer electrode close to the surface of the substrate side, the second transfer electrode is in contact with the second active layer, the second transfer electrode is provided with a data signal line close to the substrate side, and the second transfer electrode is connected with the data signal line through a fourth via hole.

[0086] In an example embodiment, the orthographic projection of the second active layer on the substrate comprises the orthographic projection of the second transfer electrode on the substrate.

[0087] In an example embodiment, the orthographic projection of the second transfer electrode on the substrate comprises the orthographic projection of the fourth via hole on the substrate.

[0088] In an example embodiment, the pixel driving circuit further comprises a first connection electrode, the first connection electrode is located in the same film layer as the second plate, the first connection electrode is located between the data signal line and the second transfer electrode, the second transfer electrode is connected with the first connection electrode through the fourth via hole, and the first connection electrode is connected with the data signal line through a second via hole.

[0089] The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development and the like for organic material. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not need a patterning process in the whole preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process in the whole preparation process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0090] In the exemplary embodiments, the circuit unit in the present disclosure refers to a region divided according to a pixel driving circuit, and the light emitting unit in the present disclosure refers to a region divided according to a light emitting device.

[0091] In the exemplary embodiments, the orthographic projection position of the light emitting unit on the substrate can correspond to the orthographic projection position of the circuit unit on the substrate, or the orthographic projection position of the light emitting unit on the substrate can not correspond to the orthographic projection position of the circuit unit on the substrate.

[0092] In the exemplary embodiments, the plurality of circuit units arranged in sequence along the first direction D1 can be referred to as a unit row, the plurality of circuit units arranged in sequence along the second direction D2 can be referred to as a unit column, the plurality of unit rows and the plurality of unit columns form an array of circuit units arranged in an array, the first direction D1 intersects the second direction D2, and for example, the first direction D1 is perpendicular to the second direction D2.

[0093] In the exemplary embodiments, taking three circuit units in the mth unit row and three circuit units in the m+1th unit row as an example, the preparation process of the display substrate can include the following operations.

[0094] (101) forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern can include sequentially depositing a first insulating thin film and a first conductive thin film on a substrate, patterning the first conductive thin film by a patterning process, forming the first insulating thin film into a first insulating layer covering the substrate, and forming the first conductive thin film into the first conductive layer pattern disposed on the first insulating layer, as shown in FIG. 6.

[0095] In an exemplary embodiment, the first conductive layer pattern can include data signal lines 11, which can have a strip shape and extend along the second direction D2. The data signal lines 11 of the circuit units adjacent in the second direction D2 in the mth unit row and the (m+1)th unit row can be connected into one body.

[0096] In an exemplary embodiment, the data signal lines 11 are provided with first connecting portions 11-1 on opposite sides in the first direction D1, which can have a rectangular block shape and extend out of the data signal lines 11 on opposite sides in the first direction D1. The first connecting portions 11-1 of the data signal lines 11 of the circuit units in the mth unit row are located at one end of the data signal lines 11 in the opposite direction of the second direction D2, and the first connecting portions 11-1 of the data signal lines 11 of the circuit units in the (m+1)th unit row are located at one end of the data signal lines 11 in the second direction D2, and the first connecting portions 11-1 of the circuit units adjacent in the second direction D2 in the mth unit row and the (m+1)th unit row are connected into one body.

[0097] In an exemplary embodiment, the data signal lines 11 can be a single-film layer structure, such as copper or molybdenum, or a multi-film layer structure, such as a titanium / aluminum / titanium laminated structure.

[0098] In an exemplary embodiment, the first insulating layer can be a silicon-nitrogen compound or a silicon-oxide compound.

[0099] (102) forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include sequentially depositing a second insulating thin film and a second conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the second conductive thin film by a patterning process, forming the second insulating thin film into a second insulating layer covering the first conductive layer pattern, and forming the second conductive thin film into the second conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 7a and 7b.

[0100] In an exemplary embodiment, the second conductive layer pattern can include a first gate 12, the first gate 12 including a first portion 12-1 extending along the first direction D1 and a second portion 12-2 extending along the second direction D2. The first portion 12-1 of the circuit unit in the mth unit row is located at one side of the circuit unit in the second direction D2, the first portions 12-1 of the adjacent circuit units in the mth unit row are connected integrally to form a strip structure extending along the first direction D1, and the second portion 12-2 of the circuit unit in the mth unit row is connected to the first portion 12-1 at the side opposite to the second direction D2. The first portion 12-1 of the circuit unit in the m+1th unit row is located at the side opposite to the circuit unit in the second direction D2, the first portions 12-1 of the adjacent circuit units in the m+1th unit row are connected integrally to form a strip structure extending along the first direction D1, and the second portion 12-2 of the circuit unit in the m+1th unit row is connected to the first portion 12-1 at the side of the second direction D2.

[0101] In an exemplary embodiment, the first gate 12 can be a single film layer structure, for example, copper or molybdenum, or a multi-film layer structure, for example, a titanium / aluminum / titanium laminated structure.

[0102] In an exemplary embodiment, the second insulating layer can be a silicon-nitrogen compound.

[0103] (103) forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern can include: sequentially depositing a third insulating thin film and a first semiconductor thin film on the substrate on which the aforementioned pattern is formed, patterning the first semiconductor thin film by a patterning process, causing the third insulating thin film to form a third insulating layer covering the second conductive layer pattern, and causing the first semiconductor thin film to form the first semiconductor layer pattern disposed on the third insulating layer, as shown in FIGS. 8a and 8b.

[0104] In an example embodiment, the first semiconductor layer pattern can include a first active layer 13, the first active layer 13 including a first main body portion 13-1 extending along the second direction D2, and a second connection portion 13-2 and a third connection portion 13-3 disposed at opposite ends of the first main body portion 13-1 in the second direction D2, the first main body portion 13-1 can have a strip shape, the second connection portion 13-2 and the third connection portion 13-3 can have a rectangular block shape, a projection of the first main body portion 13-1 on the substrate overlaps a projection of the first gate 12 on the substrate, and projections of the second connection portion 13-2 and the third connection portion 13-3 on the substrate do not overlap the projection of the first gate 12 on the substrate. The third connection portion 13-3 serves as a first terminal of the first transistor T1 and is connected to the first power signal line, and the second connection portion 13-2 serves as a second terminal of the first transistor T1 and is connected to the first electrode of the light emitting device, the first electrode plate of the capacitor C (the second gate 14), and the second terminal of the third transistor T3.

[0105] In an example embodiment, the first active layer 13 can be low-temperature polysilicon.

[0106] In an example embodiment, the third insulating layer can be a silicon nitride compound or a silicon oxide compound.

[0107] (104) forming a third conductive layer pattern. In an example embodiment, forming the third conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing a fourth insulating thin film and a third conductive layer, patterning the third conductive layer by a patterning process, causing the fourth insulating thin film to form a fourth insulating layer covering the first semiconductor layer pattern, and causing the third conductive thin film to form the third conductive layer pattern disposed on the fourth insulating layer, as shown in FIGS. 9a and 9b.

[0108] In an example embodiment, the third conductive layer pattern can include a second gate 14, the second gate 14 can have a rectangular block shape, a projection of the second gate 14 on the substrate overlaps a projection of the first main body portion 13-1 of the first active layer 13 on the substrate, and projections of the second gate 14 on the substrate do not overlap projections of the second connection portion 13-2 and the third connection portion 13-3 on the substrate. The first gate 12, the second gate 14, and the first active layer 13 form the first transistor T1, the first transistor T1 has a double-gate structure, and the first gate 12 and the second gate 14 are two gate electrodes of the first transistor T1, respectively.

[0109] In an example embodiment, the second gate 14 can be a single-film layer structure, for example, copper or molybdenum; or the second gate 14 can be a multi-film layer structure, for example, a titanium / aluminum / titanium laminated structure.

[0110] In an exemplary embodiment, the fourth insulating layer can be a silicon nitride compound or a silicon oxide compound.

[0111] (105) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a fifth insulating thin film, patterning the fifth insulating thin film by a patterning process, forming the fifth insulating layer covering the third conductive layer pattern, the fifth insulating layer in each circuit unit being provided with a plurality of vias, as shown in FIG. 10.

[0112] In an exemplary embodiment, the plurality of vias of the fifth insulating layer in each circuit unit includes a first via V1 and a second via V2, the orthographic projection of the first via V1 on the substrate is located within the orthographic projection of the third connecting part 13-3 of the first active layer 13 on the substrate, the fifth insulating layer and the fourth insulating layer within the first via V1 are etched away, exposing the surface of the second connecting part 13-2 of the first active layer 13, the first via V1 is configured to allow the second plate 15-1 formed subsequently to connect with the second connecting part 13-2 of the first active layer 13 through the via.

[0113] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the orthographic projection of the first connecting part 11-1 of the data signal line 11 on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the second via V2 are etched away, exposing the surface of the first connecting part 11-1 of the data signal line 11, the second via V2 is configured to allow the first connecting electrode 15-2 formed subsequently to connect with the first connecting part 11-1 of the data signal line 11 through the via.

[0114] In an exemplary embodiment, the second vias V2 of the circuit units adjacent in the second direction D2 in the mth unit row and the m+1th unit row are connected integrally.

[0115] (106) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth conductive layer, patterning the fourth conductive layer by a patterning process, so that the fourth conductive thin film forms the fourth conductive layer pattern provided on the fifth insulating layer, as shown in FIG. 11a and FIG. 11b.

[0116] In the example embodiment, the fourth conductive layer pattern includes the second plate 15-1 and the first connecting electrode 15-2, and the shapes of the second plate 15-1 and the first connecting electrode 15-2 each include a rectangular block. The second plate 15-1 of the circuit unit in the mth unit row is located on one side of the first connecting electrode 15-2 of the circuit unit in the mth unit row in the second direction D2, the second plate 15-1 of the circuit unit in the m+1th unit row is located on the opposite side of the first connecting electrode 15-2 of the circuit unit in the m+1th unit row in the second direction D2, and the first connecting electrodes 15-2 of the circuit units adjacent to each other in the second direction D2 in the mth unit row and the m+1th unit row are connected integrally.

[0117] In the example embodiment, the first part of the second plate 15-1 is overlapped with the orthogonal projection of the second gate 14 on the substrate to form a capacitor C. The second gate 14 serves as the first plate of the capacitor C.

[0118] In the example embodiment, the second part of the second plate 15-1 is connected with the second connecting part 13-2 of the first active layer 13 through the first via V1. The second part of the second plate 15-1 forms a recessed area in the first via V1.

[0119] In the example embodiment, the first connecting electrode 15-2 is connected with the first connecting part 11-1 of the data signal line 11 through the second via V2.

[0120] In the example embodiment, the second plate 15-1 and the first connecting electrode 15-2 can each be a single-film layer structure, such as copper or molybdenum, or the second plate 15-1 and the first connecting electrode 15-2 can each be a multi-film layer structure, such as a titanium / aluminum / titanium laminated structure.

[0121] In the example embodiment, the fifth insulating layer can be a silicon nitride compound or a silicon oxide compound.

[0122] (107) Forming a dielectric layer. In the example embodiment, forming the dielectric layer can include: on the substrate on which the aforementioned pattern is formed, depositing an organic insulating thin film, patterning the organic insulating thin film through an exposure and development process, so that the organic insulating thin film forms a dielectric pattern arranged on the fourth conductive layer pattern; and then, patterning the dielectric pattern through an ashing process to form the dielectric layer 20, as shown in FIGS. 12a and 12b. FIG. 12b can be a sectional view in the a-a’ direction of FIG. 12a.

[0123] In an example embodiment, the orthogonal projection of the dielectric layer 20 on the substrate is located within the orthogonal projection of the second plate 15-1 on the substrate, the orthogonal projection of the dielectric layer 20 on the substrate overlaps the orthogonal projection of the first via V1 on the substrate, the dielectric layer 20 fills the recessed area formed by the second plate 15-1 at the first via V1, and the dielectric layer 20 is in contact with the entire surface of the second plate 15-1 located in the first via V1.

[0124] In an example embodiment, the surface of the dielectric layer 20 away from the substrate is substantially flush with the surface of the second plate 15-1 away from the substrate, so that the surface of the dielectric layer 20 away from the substrate and the surface of the second plate 15-1 away from the substrate form a plane.

[0125] In an example embodiment, the material of the dielectric layer 20 can include an organic material, such as a resin.

[0126] (108) Forming a sixth insulating layer pattern. In an example embodiment, forming the sixth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a sixth insulating thin film, and patterning the sixth insulating thin film by a patterning process to form a sixth insulating layer covering the fourth conductive layer pattern and the dielectric layer, the sixth insulating layer in each circuit unit being provided with a plurality of vias, as shown in FIG. 13.

[0127] In an example embodiment, the plurality of vias of the sixth insulating layer in each circuit unit includes a third via V3 and a fourth via V4, the orthogonal projection of the third via V3 on the substrate is located within the orthogonal projection of the second gate 14 on the substrate, the sixth insulating layer and the fifth insulating layer in the third via V3 are etched away, exposing part of the surface of the second gate 14, and the third via V3 is configured to allow a first transfer electrode formed subsequently to connect with the second gate 14 through the via.

[0128] In an example embodiment, the orthogonal projection of the fourth via V4 on the substrate is located within the orthogonal projection of the first connecting electrode 15-2 on the substrate, the sixth insulating layer in the fourth via V4 is etched away, exposing part of the surface of the first connecting electrode 15-2, and the fourth via V4 is configured to allow a second transfer electrode formed subsequently to connect with the first connecting electrode 15-2 through the via.

[0129] In an example embodiment, the sixth insulating layer can be a silicon nitride compound or a silicon oxide compound.

[0130] (109) Forming a fifth conductive layer pattern. In an example embodiment, forming the fifth conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a fifth conductive thin film, and patterning the fifth conductive thin film by a patterning process to form a fifth conductive layer pattern disposed on the sixth insulating layer, as shown in FIGS. 14a and 14b.

[0131] In the example embodiment, the fifth conductive layer pattern includes the first transfer electrode 16-1 and the second transfer electrode 16-2, and the shape of each of the first transfer electrode 16-1 and the second transfer electrode 16-2 includes a rectangular block shape. The first transfer electrode 16-1 of the circuit unit in the mth unit row is located on one side of the second transfer electrode 16-2 of the circuit unit in the mth unit row in the second direction D2, the first transfer electrode 16-1 of the circuit unit in the (m+1)th unit row is located on the side opposite to the second transfer electrode 16-2 of the circuit unit in the (m+1)th unit row in the second direction D2, and the second transfer electrodes 16-2 of the circuit units adjacent to each other in the second direction D2 in the mth unit row and the (m+1)th unit row are connected into one body.

[0132] In the example embodiment, each of the first transfer electrode 16-1 and the second transfer electrode 16-2 can have a multi-film layer structure, for example, a titanium nitride / molybdenum laminated structure or a titanium / aluminum / titanium laminated structure.

[0133] (110) forming a second semiconductor layer pattern. In the example embodiment, forming the second semiconductor layer pattern can include: depositing a second semiconductor thin film on the substrate on which the aforementioned pattern is formed, and patterning the second semiconductor thin film by a patterning process, so that the second semiconductor thin film forms the second semiconductor layer pattern arranged on the fifth conductive layer pattern, as shown in FIGS. 15a, 15b and 15c. FIG. 15c is a sectional view in the b-b’ direction of FIG. 15a.

[0134] In the example embodiment, the second semiconductor layer pattern can include a second active layer 17, the second active layer 17 including a second main body part 17-1 extending along the second direction D2, and a fourth connecting part 17-2 and a fifth connecting part 17-3 arranged on the one side of the second main body part 17-1 in the first direction D1, the shape of the second main body part 17-1 can be a strip shape, the shape of each of the fourth connecting part 17-2 and the fifth connecting part 17-3 can be a rectangular block shape, the fourth connecting part 17-2 and the fifth connecting part 17-3 are located at opposite ends of the second main body part 17-1 in the second direction D2, the orthographic projection of the fourth connecting part 17-2 on the substrate contains the orthographic projection of the first transfer electrode 16-1 on the substrate, and the fourth connecting part 17-2 directly contacts the first transfer electrode 16-1; the orthographic projection of the fifth connecting part 17-3 on the substrate contains the orthographic projection of the second transfer electrode 16-2 on the substrate, and the fifth connecting part 17-3 directly contacts the second transfer electrode 16-2. The fifth connecting part 17-3 can serve as the first terminal of the second transistor T2 and be connected to the data signal line 11, and the fourth connecting part 17-2 can serve as the second terminal of the second transistor T2 and be connected to the second gate 14 of the first transistor T1.

[0135] In an example embodiment, the orthogonal projection of the first transfer electrode 16-1 on the substrate contains the orthogonal projection of the third via V3 on the substrate, and the first transfer electrode 16-1 is connected to the second gate 14 through the third via V3; the orthogonal projection of the second transfer electrode 16-2 on the substrate contains the orthogonal projection of the fourth via V4 on the substrate, and the second transfer electrode 16-2 is connected to the first connection electrode 15-2 through the fourth via V4, and the first connection electrode 15-2 is connected to the data signal line 11 through the second via V2.

[0136] In an example embodiment, the orthogonal projection of the second active layer 17 on the substrate does not overlap with the orthogonal projection of the second plate 15-1 on the substrate.

[0137] (111) Forming a sixth conductive layer pattern. In an example embodiment, forming the sixth conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing a seventh insulating thin film and a sixth conductive thin film, patterning the sixth conductive thin film through a patterning process, making the seventh insulating thin film form a seventh insulating layer, and making the sixth conductive thin film form a sixth conductive layer pattern disposed on the seventh insulating layer, as shown in FIGS. 16a and 16b.

[0138] In an example embodiment, the sixth conductive layer pattern includes third gates 18, the shapes of the third gates 18 each include a rectangular strip shape, the orthogonal projection of a first region of the third gate 18 on the substrate contains the orthogonal projection of the dielectric layer 20 on the substrate, and the first region of the third gate 18 is configured as a gate of a third transistor T3 to be formed later. The orthogonal projection of a second region of the third gate 18 on the substrate overlaps with the orthogonal projection of the second active layer 17 on the substrate, and the second region of the third gate 18 serves as a gate of the first transistor T1. Among them, the second active layer 17 and the second part of the third gate 18 form the second transistor T2.

[0139] In an example embodiment, the orthogonal projection of the third gate 18 on the substrate does not overlap with the orthogonal projection of the first transfer electrode 16-1 and the second transfer electrode 16-2 on the substrate.

[0140] In an example embodiment, the third gates 18 of the circuit units in the mth unit row are connected in one body to form a strip shape extending along the first direction, and the third gates 18 of the circuit units in the m+1th unit row are connected in one body to form a strip shape extending along the first direction.

[0141] In an example embodiment, the third gate 18 can be a multi-film layer structure, for example, a titanium nitride / molybdenum laminated structure, or a titanium / aluminum / titanium laminated structure.

[0142] In an example embodiment, the seventh insulating layer can be a silicon oxide compound.

[0143] (112) Forming a third semiconductor layer pattern. In an exemplary embodiment, forming the third semiconductor layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing an eighth insulating thin film and a third semiconductor thin film, patterning the third semiconductor thin film by a patterning process, making the eighth insulating thin film form an eighth insulating layer covering the sixth conductive layer pattern, and making the third semiconductor thin film form a third semiconductor layer pattern disposed on the eighth insulating layer, as shown in FIGS. 17a, 17b and 17c. FIG. 17c is a cross-sectional view in the direction of c-c’ in FIG. 17a.

[0144] In an exemplary embodiment, the third semiconductor layer pattern can include a third active layer 19, the third active layer 19 can have a rectangular block shape, a projection of the third active layer 19 on the substrate can overlap with a projection of the second region of the third gate 18 on the substrate, the projection of the third active layer 19 on the substrate can overlap with the projection of the first active layer 13 on the substrate, the projection of the third active layer 19 on the substrate can contain the projection of the dielectric layer 20 on the substrate, and the projection of the third active layer 19 on the substrate can contain the projection of the recessed region of the second plate 15-1 on the substrate. The projection of the third active layer 19 on the substrate does not overlap with the projection of the second active layer 17 on the substrate. The third active layer 19 and the third gate 18 form a third transistor T3.

[0145] (113) Forming an eighth insulating layer pattern. In an exemplary embodiment, forming the eighth insulating layer pattern can include: patterning the eighth insulating layer by a patterning process, making the eighth insulating layer in each circuit unit form a plurality of vias, as shown in FIG. 18.

[0146] In an exemplary embodiment, the plurality of vias of the eighth insulating layer in each circuit unit includes a fifth via V5 and a sixth via V6, a projection of the fifth via V5 on the substrate is located within a projection of the third connecting part 13-3 of the first active layer 13 on the substrate, the eighth insulating layer, the seventh insulating layer, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fifth via V5 are etched away, exposing part of the surface of the third connecting part 13-3 of the first active layer 13, and the fifth via V5 is configured to make the first power line (VDD) formed subsequently pass through the via and connect with the third connecting part 13-3 of the first active layer 13.

[0147] In the example embodiment, the orthogonal projection of the sixth via V6 on the substrate is located within the orthogonal projection of the second plate 15-1 on the substrate, the eighth insulating layer, the seventh insulating layer and the sixth insulating layer within the sixth via V6 are etched away, exposing part of the surface of the second plate 15-1, the sixth via V6 is configured to enable the second connecting electrode formed subsequently to connect with the second plate 15-1 through the via. The orthogonal projection of the sixth via V6 on the substrate does not overlap with the orthogonal projection of the dielectric layer 20 on the substrate.

[0148] (114) Forming a seventh conductive layer pattern. In the example embodiment, forming the seventh conductive layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing a seventh conductive thin film, patterning the seventh conductive thin film through a patterning process, so that the seventh conductive thin film forms the seventh conductive layer pattern disposed on the eighth insulating layer, as shown in FIGS. 19a and 19b.

[0149] In the example embodiment, the seventh conductive layer pattern includes the first power signal line 21, the second connecting electrode 22 and the sensing signal line 23. The first power signal line 21 of the circuit unit of the mth unit row is located on one side of the second connecting electrode 22 of the circuit unit of the mth unit row in the second direction D2, the first power signal line 21 of the circuit unit of the m+1th unit row is located on one side of the second connecting electrode 22 of the circuit unit of the m+1th unit row in the opposite direction of the second direction D2, the shape of the first power signal line 21 of each circuit unit includes a strip shape extending along the first direction D1, the first power signal lines 21 of adjacent circuit units of the mth unit row are connected in one body to form a line shape extending along the first direction D1, and the first power signal lines 21 of adjacent circuit units of the m+1th unit row are connected in one body to form a line shape extending along the first direction D1. The first power signal line 21 is connected with the third connecting part 13-3 of the first active layer 13 through the fifth via V5.

[0150] In the example embodiment, the second connecting electrode 22 is located between the first power signal line 21 and the sensing signal line 23, and the shape of the second connecting electrode 22 includes a rectangular block shape. The second connecting electrode 22 is connected with the second plate 15-1 through the sixth via V6. The orthogonal projection of the second connecting electrode 22 on the substrate overlaps with the orthogonal projection of the second end of the third active layer 19 on the substrate, and the second connecting electrode 22 is in contact with the surface of the second end of the third active layer 19 away from the substrate. The second end of the third active layer 19 is connected with the second end of the first transistor T1, the first pole of the light emitting device and the second plate 15-1 of the capacitor C as the second end of the third transistor T3.

[0151] In the example embodiment, the sensing signal line 23 of the circuit unit of the mth unit row is located on the side opposite to the second direction D2 of the second connection electrode 22 of the circuit unit of the mth unit row, and the sensing signal line 23 of the circuit unit of the (m+1)th unit row is located on the side of the second direction D2 of the second connection electrode 22 of the circuit unit of the (m+1)th unit row. The sensing signal line 23 includes a third main body part 23-1 and a sixth connection part 23-2. The third main body part 23-1 has a shape including a strip shape extending along the first direction D1, the third main body parts 23-1 of the plurality of circuit units of the mth unit row are connected to form a line shape extending along the first direction D1, and the third main body parts 23-1 of the plurality of circuit units of the (m+1)th unit row are connected to form a line shape extending along the first direction D1. The sixth connection part 23-2 has a shape including a rectangular block shape, the sixth connection part 23-2 of the circuit unit of the mth unit row is arranged on the side opposite to the second direction D2 of the third main body part 23-1, and the plurality of circuit units of the mth unit row can share one sixth connection part 23-2; the sixth connection part 23-2 of the circuit unit of the (m+1)th unit row is arranged on the side of the second direction D2 of the third main body part 23-1, and the plurality of circuit units of the (m+1)th unit row can share one sixth connection part 23-2; and the sixth connection part 23-2 shared by the plurality of circuit units of the mth unit row and the sixth connection part 23-2 shared by the plurality of circuit units of the (m+1)th unit row are connected to form one body.

[0152] In the example embodiment, the third main body part 23-1 has an orthographic projection on the substrate that overlaps the orthographic projection of the first end of the third active layer 19 on the substrate, and the second connection electrode 22 is in contact with the surface of the first end of the third active layer 19 away from the substrate. The first end of the third active layer 19 serves as the first end of the third transistor T3 and is connected to the sensing signal line SL.

[0153] In the example embodiment, the first power signal line 21, the second connection electrode 22, and the sensing signal line 23 can all have a single-film layer structure, such as copper or molybdenum; or the first power signal line 21, the second connection electrode 22, and the sensing signal line 23 can all have a multi-film layer structure, such as a titanium / aluminum / titanium laminated structure.

[0154] (115) Forming a ninth insulating layer pattern. In the example embodiment, forming the ninth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a ninth insulating thin film, and patterning the ninth insulating thin film by a patterning process, so that the ninth insulating thin film forms a ninth insulating layer covering the seventh conductive layer pattern, as shown in FIG. 20.

[0155] In an example embodiment, the ninth insulating layer is provided with a seventh via V7, a projection of the seventh via V7 on the substrate is located within a projection of the sixth connecting part 23-2 of the sensing signal line 23 on the substrate, the ninth insulating layer in the seventh via V7 is etched away, exposing part of the surface of the sixth connecting part 23-2, and the seventh via V7 is configured to allow the third connecting electrode formed subsequently to connect with the sixth connecting part 23-2 through the via.

[0156] In an example embodiment, the plurality of circuit units in the mth unit row can share one seventh via V7, the plurality of circuit units in the (m+1)th unit row can share one seventh via V7, and the seventh via V7 shared by the plurality of circuit units in the mth unit row and the seventh via V7 shared by the plurality of circuit units in the (m+1)th unit row are connected integrally.

[0157] In an example embodiment, the ninth insulating layer can be a silicon oxide compound or a silicon nitride compound.

[0158] (116) Forming an eighth conductive layer pattern. In an example embodiment, forming the eighth conductive layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing an eighth conductive thin film, and patterning the eighth conductive thin film through a patterning process, so that the eighth conductive thin film forms the eighth conductive layer pattern disposed on the ninth insulating layer, as shown in FIGS. 21a and 21b.

[0159] In an example embodiment, the eighth conductive layer pattern includes a third connecting electrode 24, the third connecting electrode 24 includes a fourth main body part 24-1 and a seventh connecting part 24-2, the fourth main body part 24-1 is in the shape of a line extending along the second direction D2, and the seventh connecting part 24-2 is in the shape of a rectangular block. The seventh connecting part 24-2 of the circuit unit in the mth unit row is disposed at one end of the fourth main body part 24-1 in the second direction D2, and the seventh connecting part 24-2 extends out of one side of the fourth main body part 24-1 in the first direction D1; the seventh connecting part 24-2 of the circuit unit in the (m+1)th unit row is disposed at one end of the fourth main body part 24-1 in the second direction D2, and the seventh connecting part 24-2 extends out of one side of the fourth main body part 24-1 in the first direction D1. The plurality of circuit units in the mth unit row share one third connecting electrode 24, the plurality of circuit units in the (m+1)th unit row share one third connecting electrode 24, and the third connecting electrode 24 shared by the mth unit row and the third connecting electrode 24 shared by the (m+1)th unit row are located in the same column of circuit units, and the seventh connecting part 24-2 of the third connecting electrode 24 shared by the mth unit row and the seventh connecting part 24-2 of the third connecting electrode 24 shared by the (m+1)th unit row are connected integrally.

[0160] In the example embodiment, the seventh connection part 24-2 of the third connection electrode 24 is connected to the sixth connection part 23-2 of the sensing signal line 23 through the seventh via V7.

[0161] In the example embodiment, the third connection electrode 24 can be a single film layer structure, for example, copper or molybdenum, or the third connection electrode 24 can be a multi-film layer structure, for example, a titanium / aluminum / titanium layer structure.

[0162] So far, the driving circuit layer of the present embodiment is prepared on the substrate. The subsequent preparation process can include forming a tenth insulating layer covering the eighth conductive layer pattern, a eleventh insulating layer disposed on the tenth insulating layer, an eighth via exposing the second connection electrode 22 in the tenth insulating layer and the eleventh insulating layer, a first electrode of the light emitting device formed on the eleventh insulating layer, and a pixel definition layer formed on the first electrode. The first electrode is connected to the second connection electrode 22 through the eighth via, and the pixel definition layer has a pixel opening formed therein, which exposes at least part of the surface of the first electrode. After the pixel definition layer is prepared, the subsequent preparation process can sequentially form a light emitting functional layer and a second electrode to complete the preparation of the light emitting structure layer, which will not be described here.

[0163] The preparation process of the substrate is shown in the example embodiment. The first via V1 connecting the second plate 15-1 of the capacitor and the first active layer 13 of the first transistor is filled with the dielectric layer 20, so that the surface of the second plate 15-1 is flat, and the orthogonal projection of the third active layer 19 on the substrate overlaps the orthogonal projection of the first active layer 13 on the substrate, and the flatness of the third active layer 19 is ensured, avoiding the influence of the via connecting the second plate 15-1 and the first active layer 13 on the flatness of the third active layer 19.

[0164] The preparation process of the substrate is shown in the example embodiment. By locating the data signal line 11 at the first conductive layer and the second plate 15-1 at the fourth conductive layer, the influence of the crosstalk of the data signal line 11 is reduced, and the influence of the parasitic capacitance of the first transistor during light emission is also reduced.

[0165] The preparation process of the substrate is shown in the example embodiment. By overlapping the orthogonal projection of the third active layer 19 on the substrate with the orthogonal projection of the first active layer 13 on the substrate, the space utilization can be improved, the orthogonal projection area of the second plate 15-1 on the substrate is increased, and thus the capacitance is increased.

[0166] The preparation process of the substrate is shown in the example embodiment. By overlapping the orthogonal projection of the third active layer 19 on the substrate with the orthogonal projection of the first active layer 13 on the substrate, the space utilization can be improved, the size of the first active layer 13 is increased, the short channel effect is reduced, the sub-threshold swing (SS) is increased, and the gray scale resolution is improved.

[0167] The preparation process of the substrate is shown in the embodiments of the present disclosure. The first transfer electrode 16-1 and the second transfer electrode 16-2 are formed on the surface of the second active layer 17 close to the substrate, so that the orthographic projection of the first transfer electrode 16-1 and the second transfer electrode 16-2 on the substrate can be located in the orthographic projection of the second active layer 17 on the substrate, and the space occupied by the first transfer electrode 16-1 and the second transfer electrode 16-2 is reduced.

[0168] The preparation process of the substrate is shown in the embodiments of the present disclosure. The first transfer electrode 16-1 and the second transfer electrode 16-2 are directly in contact with the second active layer 17, without the need for via connection, so as to avoid over-etching in the etching process of the via and damage to the second active layer 17.

[0169] The preparation process of the substrate is shown in the embodiments of the present disclosure. The orthographic projection of the first transfer electrode 16-1 and the second transfer electrode 16-2 on the substrate includes the orthographic projection of the via thereunder on the substrate, full-hole connection is achieved, the difficulty of deep-hole etching is reduced, and the connection stability is improved.

[0170] In an example embodiment, the preparation process of the substrate is shown in the embodiments of the present disclosure. The shape of the orthographic projection of at least one of the first via V1, the second via V2, the third via V3, the fourth via V4, the fifth via V5, the sixth via V6 and the seventh via V7 on the substrate can include a polygon, for example, a rectangle, a pentagon, a hexagon, etc. The length of at least one side of the polygon is less than or equal to 1 micrometer; or the shape of the orthographic projection of at least one of the first via V1, the second via V2, the third via V3, the fourth via V4, the fifth via V5, the sixth via V6 and the seventh via V7 on the substrate can include a circle, and the diameter of the circle is less than or equal to 1 micrometer; or the shape of the orthographic projection of at least one of the first via V1, the second via V2, the third via V3, the fourth via V4, the fifth via V5, the sixth via V6 and the seventh via V7 on the substrate can include an ellipse, and the length of the minor axis of the ellipse is less than or equal to 1 micrometer.

[0171] In an example embodiment, the preparation process of each via of the substrate is described by taking the first via V1 as an example. The formation of the first via V1 can include the following operations.

[0172] As shown in FIG. 5a, a first hole V1-1 is first formed in the fifth insulating layer 205, the first hole V1-1 extends to the surface of the first active layer 13, and exposes part of the surface of the first active layer 13;

[0173] As shown in FIG. 5b, subsequently, an inorganic medium layer 301 is deposited on the fifth insulating layer 205, and the inorganic medium layer 301 covers the inner wall of the first hole V1-1; wherein the inorganic medium layer 301 has a different etching ratio from the fifth insulating layer 205.

[0174] As shown in FIG. 5c, subsequently, the inorganic medium layer 301 is patterned by an exposure, development and etching process, so as to form a second hole V1-2 in the inorganic medium layer 301, and the second hole V1-2 exposes the sidewall of one side of the first hole V1-1 and part of the surface of the first active layer 13. The part of the surface of the first active layer 13 exposed by the first hole V1-1 is covered by the inorganic medium layer 301, and the other part of the surface of the first active layer 13 exposed by the first hole V1-1 is exposed by the second hole V1-2. Wherein, the area where the first active layer 13 exposed by the first hole V1-1 and the second hole V1-2 is located is as a first via V1, and the length a of the orthographic projection of the first via V1 on the second direction D2 on the substrate 101 is less than or equal to 1 micrometer.

[0175] The embodiments of the present disclosure show the preparation process of the display substrate, by controlling the size of each via of the display substrate to be less than or equal to 1 micrometer, the high pixel density of the display substrate is realized, for example, the pixel density of the display substrate can reach 1800PPI.

[0176] The embodiments of the present disclosure also provide a preparation method of a display substrate, comprising:

[0177] forming a driving circuit layer on a substrate, the driving circuit layer at least comprising a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising a third transistor, a first transistor and a capacitor; the first transistor comprising a first active layer, the third transistor comprising a third active layer, the capacitor comprising a second plate, the third active layer being disposed on the side of the first active layer away from the substrate, the second plate being disposed between the first active layer and the third active layer, the second plate being connected with the second end of the first active layer through a first via, the second plate forming a recessed area in the first via, the side of the second plate away from the substrate being provided with a dielectric layer, at least part of the dielectric layer being disposed in the recessed area, and the orthographic projection of the third active layer on the substrate and the orthographic projection of the recessed area on the substrate overlapping.

[0178] The embodiments of the present disclosure also provide a display device comprising any one of the display substrates described above. The display device can be a mobile phone, a wearable device, an AR or VR display device, a vehicle-mounted display device, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator or any product or component with a display function, and the embodiments of the present disclosure are not limited thereto.

[0179] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0180] In addition, the terms "first", "second", and the like are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" and the like can explicitly or implicitly include at least one of the features.

[0181] In the description of the present application, "a plurality of" means at least two, for example, two, three, etc., unless otherwise explicitly specified and limited.

[0182] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, "connecting" can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be directly connected, or indirectly connected through intermediate medium; can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0183] In the present application, unless otherwise explicitly specified and limited, the first feature is "on" or "under" the second feature, which can be direct contact between the first and second features, or indirect contact between the first and second features through intermediate medium. Moreover, the first feature "above", "above" and "above" the second feature can be directly above or obliquely above the first feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature can be directly below or obliquely below the first feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0184] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are contained in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples without contradiction.

[0185] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary and are not to be construed as limiting the present application, and the person skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.

Claims

1. A display substrate, comprising a driving circuit layer disposed on a base, the driving circuit layer comprising at least a plurality of circuit units, at least one of the circuit units comprising a pixel driving circuit, the pixel driving circuit comprising a driving transistor, a second switch transistor and a capacitor, the driving transistor comprising a first active layer, the second switch transistor comprising a third active layer, the capacitor comprising a second plate, the third active layer being disposed on a side of the first active layer away from the base, the second plate being disposed between the first active layer and the third active layer, the second plate being connected to a second end of the first active layer through a first via, the second plate forming a recessed region in the first via, a dielectric layer being disposed on a side of the second plate away from the base, at least part of the dielectric layer being disposed in the recessed region, a projection of the third active layer on the base overlapping a projection of the recessed region on the base. 2.The display substrate of claim 1, wherein, A surface of the dielectric layer away from the base is planar with a surface of the second plate away from the base. 3.The display substrate of claim 1, wherein, The projection of the third active layer on the base contains the projection of the recessed region on the base. 4.The display substrate of claim 1, wherein, The projection of the third active layer on the base overlaps the projection of the first active layer on the base. 5.The display substrate of claim 1, wherein, The first via has a polygonal shape, at least one side of the first via having a length less than or equal to 1 micrometer; or the first via has a circular shape, a diameter of the first via being less than or equal to 1 micrometer; or the first via has an elliptical shape, a length of a minor axis of the first via being less than or equal to 1 micrometer. 6.The display substrate according to any one of claims 1 to 5, wherein The driving transistor further comprises a second gate disposed between the first active layer and the second plate, a projection of the second gate on the base overlapping the projection of the first active layer on the base, the capacitor comprising a first plate, the second gate serving as the first plate, a projection of the second gate on the base overlapping a projection of the second plate on the base.

7. The display substrate according to any one of claims 1 to 5, wherein The driving transistor further comprises a first gate located on a side of the first active layer close to the base, a projection of the first gate on the base overlapping the projection of the first active layer on the base.

8. The display substrate according to any one of claims 1 to 5, wherein The pixel driving circuit further comprises a first power supply line, the first power supply line being disposed on a side of the third active layer away from the base, the first power supply line being connected to a first end of the first active layer through a fifth via.

9. The display substrate according to any one of claims 1 to 5, wherein The second switch transistor further comprises a third gate located between the third active layer and the second plate, a projection of the third gate on the base overlapping the projection of the third active layer on the base.

10. The display substrate according to any one of claims 1 to 5, wherein The display substrate further comprises a light-emitting structure layer disposed away from the substrate on the side of the driving circuit layer, the light-emitting structure layer comprising a light-emitting device, the light-emitting device comprising a first electrode, a light-emitting functional layer and a second electrode disposed in sequence away from the substrate, the pixel driving circuit further comprising a second connection electrode, the second connection electrode being located between the third active layer and the first electrode, at least part of the second connection electrode being in contact with the surface of the second end of the third active layer away from the substrate, the second connection electrode being connected to the second electrode plate through a sixth via, and the second connection electrode being connected to the first electrode.

11. The display substrate according to any one of claims 1 to 5, wherein The pixel driving circuit further comprises a sensing signal line, the sensing signal line being located on the side of the third active layer away from the substrate, and at least part of the sensing signal line being in contact with the surface of the first end of the third active layer away from the substrate.

12. The display substrate according to any one of claims 1 to 5, wherein The pixel driving circuit further comprises a first switch transistor, the first switch transistor comprising a second active layer, the second active layer being located between the second electrode plate and the third active layer, the second active layer being provided with a first adapter electrode on the surface of the side close to the substrate, the first adapter electrode being in contact with the second active layer, the first adapter electrode being provided with a second gate electrode on the side close to the substrate, and the first adapter electrode being connected to the second gate electrode through a third via; the second gate electrode serving as a gate electrode of the driving transistor. 13.The display substrate of claim 12, wherein, The second active layer comprises a projection of the first adapter electrode on the substrate. 14.The display substrate of claim 12, wherein, The first adapter electrode comprises a projection of the third via on the substrate.

15. The display substrate according to any one of claims 1 to 5, wherein The pixel driving circuit further comprises a first switch transistor, the first switch transistor comprising a second active layer, the second active layer being located between the second electrode plate and the third active layer, the second active layer being provided with a second adapter electrode on the surface of the side close to the substrate, the second adapter electrode being in contact with the second active layer, the second adapter electrode being provided with a data signal line on the side close to the substrate, and the second adapter electrode being connected to the data signal line through a fourth via. 16.The display substrate of claim 15, wherein, The second active layer comprises a projection of the second adapter electrode on the substrate. 17.The display substrate of claim 15, wherein, The second adapter electrode comprises a projection of the fourth via on the substrate. 18.The display substrate of claim 15, wherein, The pixel driving circuit further comprises a first connection electrode, the first connection electrode and the second electrode plate being located in the same film layer, the first connection electrode being located between the data signal line and the second adapter electrode, the second adapter electrode being connected to the first connection electrode through the fourth via, and the first connection electrode being connected to the data signal line through a second via.

19. A display substrate manufacturing method, comprising: Forming a driving circuit layer on a substrate, the driving circuit layer comprising at least a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising a second switch transistor, a driving transistor and a capacitor; the driving transistor comprising a first active layer, the second switch transistor comprising a third active layer, the capacitor comprising a second plate, the third active layer being disposed on a side of the first active layer away from the substrate, the second plate being disposed between the first active layer and the third active layer, the second plate being connected with a second end of the first active layer through a first via, the second plate forming a recessed region in the first via, a dielectric layer being disposed on a side of the second plate away from the substrate, at least part of the dielectric layer being disposed in the recessed region, a projection of the third active layer on the substrate overlapping with a projection of the recessed region on the substrate.

20. A display device comprising the display substrate according to any one of claims 1 to 18.

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