Pixel driving circuit and display panel

Abstract

A pixel driving circuit (PDC) and a display panel (PNL), which belong to the technical field of display. The pixel driving circuit (PDC) comprises a driving unit (IU), a shared light-emitting unit (GU), and a privacy light-emitting unit (FU), wherein an output end of the driving unit (IU) is electrically connected to an input end of the shared light-emitting unit (GU) and an input end of the privacy light-emitting unit (FU); the driving unit (IU) is configured to generate a driving signal; the privacy light-emitting unit (FU) has a privacy light-emitting element (FLD) and is configured to cause, at least in a privacy mode, the privacy light-emitting element (FLD) to be driven by the driving signal to emit light; and the shared light-emitting unit (GU) has a shared light-emitting element (GLD) and is configured to cause, in a shared mode, the shared light-emitting element (GLD) to be driven by the driving signal to emit light. A display panel (PNL) applying the pixel driving circuit (PDC) can achieve a privacy effect.

Description

Pixel driving circuit and display panel

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to Chinese Patent Application No. 202411389502.8, filed September 30, 2024, entitled “Pixel driving circuit and display panel,” the entire contents of which are incorporated herein by reference in its entirety TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a pixel driving circuit and a display panel. BACKGROUND

[0004] With the rapid development of display technology, display devices have gradually spread in people's lives. Among them, organic electroluminescent display devices have been widely used in mobile phones, televisions, notebook computers and other intelligent products due to their self-luminescence, low power consumption, wide viewing angle, fast response speed, high contrast and flexible display advantages. At the same time, in order to improve the use experience, a display device with a privacy function enters people's field of vision.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a pixel driving circuit and a display panel applying the pixel driving circuit.

[0007] According to one aspect of the present disclosure, a pixel driving circuit is provided, comprising a driving unit, a shared light-emitting unit and a privacy light-emitting unit.

[0008] The output end of the driving unit is electrically connected to the input end of the shared light-emitting unit and the input end of the privacy light-emitting unit.

[0009] The driving unit is configured to generate a driving signal.

[0010] The privacy light-emitting unit has a privacy light-emitting element and is configured to cause the privacy light-emitting element to emit light under the driving of the driving signal at least in a privacy mode.

[0011] The shared light-emitting unit has a shared light-emitting element and is configured to cause the shared light-emitting element to emit light under the driving of the driving signal in a shared mode.

[0012] According to an embodiment of the present disclosure, the first pole of the privacy light-emitting element is electrically connected with the output end of the driving unit, and the second pole of the privacy light-emitting element is used for loading a reference voltage.

[0013] According to an embodiment of the present disclosure, the shared light-emitting unit further comprises a first control unit and a first reset unit.

[0014] The second end of the first control unit is electrically connected with the second end of the first reset unit and the first pole of the shared light-emitting element, and the first end of the first control unit is electrically connected with the output end of the driving unit; the first reset unit is used for loading a second initialization voltage; and the second pole of the shared light-emitting element is used for loading a reference voltage.

[0015] The first control unit is used for making the output end of the driving unit and the first pole of the shared light-emitting element conductive in response to a second light-emitting signal; and the first reset unit is used for loading the second initialization voltage to the first pole of the shared light-emitting element in response to a second reset signal.

[0016] According to an embodiment of the present disclosure, the driving unit comprises a second reset unit, the first end of the second reset unit is used for loading a second initialization voltage, and the second end of the second reset unit is electrically connected with the output end of the driving unit; the second reset unit is used for loading the second initialization voltage to the output end of the driving unit in response to a second reset signal.

[0017] According to an embodiment of the present disclosure, the shared light-emitting unit further comprises a first control unit, the second end of the first control unit is electrically connected with the first pole of the shared light-emitting element; the first end of the first control unit is electrically connected with the output end of the driving unit; the first control unit is used for making the output end of the driving unit and the first pole of the shared light-emitting element conductive in response to a second light-emitting signal; and the second pole of the shared light-emitting element is used for loading a reference voltage.

[0018] The privacy light-emitting unit further comprises a second control unit, the second end of the second control unit is electrically connected with the output end of the driving unit, the first end of the second control unit is electrically connected with the first pole of the privacy light-emitting element, the second control unit is used for making the output end of the driving unit and the first pole of the privacy light-emitting element conductive in response to a third light-emitting signal, and the second pole of the privacy light-emitting element is used for loading a reference voltage.

[0019] According to an embodiment of the present disclosure, the shared light-emitting unit further comprises a first reset unit.

[0020] The first end of the first reset unit is configured to load a second initialization voltage, and the second end of the first reset unit is electrically connected to the second end of the first control unit; the first reset unit is configured to load the second initialization voltage to the second end of the first control unit in response to a second reset signal.

[0021] According to an embodiment of the present disclosure, the driving unit comprises a second reset unit, a first end of the second reset unit is configured to load a second initialization voltage, and a second end of the second reset unit is electrically connected to an output end of the driving unit; the second reset unit is configured to load the second initialization voltage to the output end of the driving unit in response to a second reset signal.

[0022] According to an embodiment of the present disclosure, the shared light emitting unit further comprises a first reset unit; a first end of the first reset unit is configured to load a second initialization voltage; a second end of the first reset unit is electrically connected to a second end of the first control unit; the first reset unit is configured to load the second initialization voltage to the second end of the first control unit in response to a second reset signal.

[0023] The anti-peep light emitting unit further comprises a third reset unit, a first end of the third reset unit is configured to load a second initialization voltage; a second end of the third reset unit is electrically connected to a second end of the second control unit; the third reset unit is configured to load the second initialization voltage to the second end of the second control unit in response to a second reset signal.

[0024] According to an embodiment of the present disclosure, the driving unit comprises a driving transistor; the driving transistor is configured to generate a driving current as the driving signal according to a voltage on a gate of the driving transistor; a second electrode of the driving transistor is electrically connected to an output end of the driving unit.

[0025] According to an embodiment of the present disclosure, the driving unit comprises a driving transistor and a switch unit; the driving transistor is configured to generate a driving current as the driving signal according to a voltage on a gate of the driving transistor; a first end of the switch unit is electrically connected to a second electrode of the driving transistor, and a second end of the switch unit is electrically connected to an output end of the driving unit; the switch unit is configured to electrically connect the second electrode of the driving transistor and the output end of the driving unit in response to a first light emitting signal.

[0026] According to another aspect of the present disclosure, a display panel is provided, comprising the pixel driving circuit.

[0027] According to an embodiment of the present disclosure, the display panel comprises a pixel layer and an angle limiting layer arranged in a stack; the anti-peep light emitting element and the shared light emitting element are arranged on the pixel layer.

[0028] The angle limiting layer is arranged on the light emitting side of the pixel layer, and the angle limiting layer has a first angle limiting structure corresponding to the shared light emitting element and a second angle limiting structure corresponding to the anti-peep light emitting element; the light emitted by the shared light emitting element is emitted to the outside of the display panel through the first angle limiting structure, and the light emitted by the anti-peep light emitting element is emitted to the outside of the display panel through the second angle limiting structure.

[0029] The first angle limiting structure makes the maximum light emitting angle of the shared light emitting element be a first light emitting angle; the second angle limiting structure makes the maximum light emitting angle of the anti-peep light emitting element be a second light emitting angle; and the first light emitting angle is greater than the second light emitting angle.

[0030] According to an embodiment of the present disclosure, the display panel is applied to a mobile intelligent terminal; and the display panel comprises the pixel driving circuit.

[0031] According to an embodiment of the present disclosure, the display panel is applied to a desktop display screen, a notebook display screen or a tablet computer; and the display panel comprises the pixel driving circuit.

[0032] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0033] The drawings herein are incorporated into the specification and form a part of the specification, show embodiments consistent with the present disclosure, and together with the specification serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0034] FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present disclosure.

[0035] FIG. 2 is a schematic diagram of a film layer structure of a display panel according to an embodiment of the present disclosure.

[0036] FIG. 3 is a schematic diagram of a pixel driving circuit according to a first embodiment of the present disclosure.

[0037] FIG. 4 is a timing diagram of a pixel driving circuit according to a first embodiment of the present disclosure.

[0038] FIG. 5 is a schematic diagram of a first reset stage of a pixel driving circuit in an anti-peep mode according to a first embodiment of the present disclosure.

[0039] FIG. 6 is a timing diagram of a second reset stage of the pixel driving circuit in the privacy mode according to the first embodiment of the present disclosure.

[0040] FIG. 7 is a timing diagram of a data write stage of the pixel driving circuit in the privacy mode according to the first embodiment of the present disclosure.

[0041] FIG. 8 is a timing diagram of a third reset stage of the pixel driving circuit in the privacy mode according to the first embodiment of the present disclosure.

[0042] FIG. 9 is a timing diagram of a light emitting stage of the pixel driving circuit in the privacy mode according to the first embodiment of the present disclosure.

[0043] FIG. 10 is a timing diagram of a first reset stage of the pixel driving circuit in the sharing mode according to the first embodiment of the present disclosure.

[0044] FIG. 11 is a timing diagram of a second reset stage of the pixel driving circuit in the sharing mode according to the first embodiment of the present disclosure.

[0045] FIG. 12 is a timing diagram of a data write stage of the pixel driving circuit in the sharing mode according to the first embodiment of the present disclosure.

[0046] FIG. 13 is a timing diagram of a third reset stage of the pixel driving circuit in the sharing mode according to the first embodiment of the present disclosure.

[0047] FIG. 14 is a timing diagram of a light emitting stage of the pixel driving circuit in the sharing mode according to the first embodiment of the present disclosure.

[0048] FIG. 15 is a timing diagram of a pixel driving circuit according to the second embodiment of the present disclosure.

[0049] FIG. 16 is a timing diagram of the pixel driving circuit according to the second embodiment of the present disclosure.

[0050] FIG. 17 is a timing diagram of a first reset stage of the pixel driving circuit in the privacy mode according to the second embodiment of the present disclosure.

[0051] FIG. 18 is a timing diagram of a second reset stage of the pixel driving circuit in the privacy mode according to the second embodiment of the present disclosure.

[0052] FIG. 19 is a timing diagram of a data write stage of the pixel driving circuit in the privacy mode according to the second embodiment of the present disclosure.

[0053] FIG. 20 is a timing diagram of a third reset stage of the pixel driving circuit in the privacy mode according to the second embodiment of the present disclosure.

[0054] FIG. 21 is a timing diagram of a light emitting stage of the pixel driving circuit in the privacy mode according to the second embodiment of the present disclosure.

[0055] FIG. 22 is a timing diagram of a first reset stage of a pixel driving circuit in a shared mode according to a second embodiment of the present disclosure.

[0056] FIG. 23 is a timing diagram of a second reset stage of a pixel driving circuit in a shared mode according to a second embodiment of the present disclosure.

[0057] FIG. 24 is a timing diagram of a data write stage of a pixel driving circuit in a shared mode according to a second embodiment of the present disclosure.

[0058] FIG. 25 is a timing diagram of a third reset stage of a pixel driving circuit in a shared mode according to a second embodiment of the present disclosure.

[0059] FIG. 26 is a timing diagram of a light emission stage of a pixel driving circuit in a shared mode according to a second embodiment of the present disclosure.

[0060] FIG. 27 is a timing diagram of a pixel driving circuit according to a third embodiment of the present disclosure.

[0061] FIG. 28 is a timing diagram of a pixel driving circuit according to a third embodiment of the present disclosure.

[0062] FIG. 29 is a timing diagram of a first reset stage of a pixel driving circuit in a privacy mode according to a third embodiment of the present disclosure.

[0063] FIG. 30 is a timing diagram of a second reset stage of a pixel driving circuit in a privacy mode according to a third embodiment of the present disclosure.

[0064] FIG. 31 is a timing diagram of a data write stage of a pixel driving circuit in a privacy mode according to a third embodiment of the present disclosure.

[0065] FIG. 32 is a timing diagram of a third reset stage of a pixel driving circuit in a privacy mode according to a third embodiment of the present disclosure.

[0066] FIG. 33 is a timing diagram of a light emission stage of a pixel driving circuit in a privacy mode according to a third embodiment of the present disclosure.

[0067] FIG. 34 is a timing diagram of a first reset stage of a pixel driving circuit in a shared mode according to a third embodiment of the present disclosure.

[0068] FIG. 35 is a timing diagram of a second reset stage of a pixel driving circuit in a shared mode according to a third embodiment of the present disclosure.

[0069] FIG. 36 is a timing diagram of a data write stage of a pixel driving circuit in a shared mode according to a third embodiment of the present disclosure.

[0070] FIG. 37 is a timing diagram of the third reset stage of the pixel driving circuit in the shared mode in the third embodiment of the present disclosure.

[0071] FIG. 38 is a timing diagram of the light emitting stage of the pixel driving circuit in the shared mode in the third embodiment of the present disclosure.

[0072] FIG. 39 is a timing diagram of the pixel driving circuit in the fourth embodiment of the present disclosure.

[0073] FIG. 40 is a timing diagram of the pixel driving circuit in the fourth embodiment of the present disclosure.

[0074] FIG. 41 is a timing diagram of the first reset stage of the pixel driving circuit in the privacy mode in the fourth embodiment of the present disclosure.

[0075] FIG. 42 is a timing diagram of the second reset stage of the pixel driving circuit in the privacy mode in the fourth embodiment of the present disclosure.

[0076] FIG. 43 is a timing diagram of the data writing stage of the pixel driving circuit in the privacy mode in the fourth embodiment of the present disclosure.

[0077] FIG. 44 is a timing diagram of the third reset stage of the pixel driving circuit in the privacy mode in the fourth embodiment of the present disclosure.

[0078] FIG. 45 is a timing diagram of the light emitting stage of the pixel driving circuit in the privacy mode in the fourth embodiment of the present disclosure.

[0079] FIG. 46 is a timing diagram of the first reset stage of the pixel driving circuit in the shared mode in the fourth embodiment of the present disclosure.

[0080] FIG. 47 is a timing diagram of the second reset stage of the pixel driving circuit in the shared mode in the fourth embodiment of the present disclosure.

[0081] FIG. 48 is a timing diagram of the data writing stage of the pixel driving circuit in the shared mode in the fourth embodiment of the present disclosure.

[0082] FIG. 49 is a timing diagram of the third reset stage of the pixel driving circuit in the shared mode in the fourth embodiment of the present disclosure.

[0083] FIG. 50 is a timing diagram of the light emitting stage of the pixel driving circuit in the shared mode in the fourth embodiment of the present disclosure.

[0084] FIG. 51 is a timing diagram of the pixel driving circuit in the fifth embodiment of the present disclosure.

[0085] FIG. 52 is a timing diagram of the pixel driving circuit in the fifth embodiment of the present disclosure.

[0086] FIG. 53 is a schematic diagram of a first reset stage of a pixel driving circuit in a privacy mode, according to a fifth embodiment of the present disclosure.

[0087] FIG. 54 is a schematic diagram of a second reset stage of a pixel driving circuit in a privacy mode, according to a fifth embodiment of the present disclosure.

[0088] FIG. 55 is a schematic diagram of a data write stage of a pixel driving circuit in a privacy mode, according to a fifth embodiment of the present disclosure.

[0089] FIG. 56 is a schematic diagram of a third reset stage of a pixel driving circuit in a privacy mode, according to a fifth embodiment of the present disclosure.

[0090] FIG. 57 is a schematic diagram of a light emitting stage of a pixel driving circuit in a privacy mode, according to a fifth embodiment of the present disclosure.

[0091] FIG. 58 is a schematic diagram of a first reset stage of a pixel driving circuit in a sharing mode, according to a fifth embodiment of the present disclosure.

[0092] FIG. 59 is a schematic diagram of a second reset stage of a pixel driving circuit in a sharing mode, according to a fifth embodiment of the present disclosure.

[0093] FIG. 60 is a schematic diagram of a data write stage of a pixel driving circuit in a sharing mode, according to a fifth embodiment of the present disclosure.

[0094] FIG. 61 is a schematic diagram of a third reset stage of a pixel driving circuit in a sharing mode, according to a fifth embodiment of the present disclosure.

[0095] FIG. 62 is a schematic diagram of a light emitting stage of a pixel driving circuit in a sharing mode, according to a fifth embodiment of the present disclosure. DETAILED DESCRIPTION

[0096] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided as non-limiting examples so that this disclosure will fully convey the scope thereof to those skilled in the art. Like reference numerals refer to like elements throughout the figures and description, which makes clear the disclosure without further elaboration.

[0097] Although relative terms are used in this specification, such as "upper", "lower", to describe one component's relative position to another component of the icon, these terms are used in this specification for convenience only, for example, according to the orientation of the examples shown in the drawings. It will be understood that if the device of the icon is turned upside down, the component described as being "upper" will become the component that is "lower". When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure, or that the structure is "directly" on the other structure, or that the structure is "indirectly" on the other structure via another structure.

[0098] In the embodiment of the present disclosure, the thin film transistor includes an active layer, a gate insulating layer and a gate electrode which are stacked. The active layer is located in a semiconductor layer, and the active layer includes a channel region and a source and a drain which are respectively located on both sides of the channel region. The channel region maintains a semiconductor property, and the source and the drain are both conductive. In the embodiment of the present disclosure, the functions of the "source" and the "drain" are sometimes exchanged with each other, i.e., the "source" and the "drain" can be exchanged with each other, in the case of using a transistor with opposite polarity or in the case of changing the current direction in the circuit operation. In the embodiment of the present disclosure, for any one transistor, one of the "source" and the "drain" is referred to as a first electrode of the transistor, and the other is referred to as a second electrode of the transistor.

[0099] The structure layer A is located on the side of the structure layer B away from the substrate, which can be understood as that the structure layer A is formed on the side of the structure layer B away from the substrate. When the structure layer B is a patterned structure, part of the structure of the structure layer A can also be located at the same physical height as the structure layer B or below the physical height of the structure layer B, wherein the substrate is the height reference.

[0100] It should be noted that the "same layer" of the embodiment of the present application can refer to the film layer on the same structure layer, for example, the film layer on the same layer can be a film layer formed with a specific pattern by the same film forming process, of course, the film layer with a specific pattern can also be at different heights or have different thicknesses.

[0101] In the embodiment of the present disclosure, the transistor refers to an element including at least a gate electrode, a drain electrode and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region or drain electrode) and the source electrode (source electrode terminal, source region or source electrode), and current can flow through the drain electrode, the channel region and the source electrode. The channel region refers to the region through which the current mainly flows.

[0102] In the embodiments of the present disclosure, the functions of the "source electrode" and the "drain electrode" are sometimes exchanged with each other in the case of using transistors with opposite polarities or in the case of changing the current direction in the operation of a circuit. Therefore, in the present specification, the "source electrode" and the "drain electrode" can be exchanged with each other. In the embodiments of the present disclosure, for any one transistor, one of the "source" and the "drain" is referred to as a first electrode of the transistor, and the other is referred to as a second electrode of the transistor, and the gate electrode is referred to as a control electrode of the transistor. The first electrode can be the drain electrode, and the second electrode can be the source electrode, or the first electrode can be the source electrode, and the second electrode can be the drain electrode. In the embodiments of the present disclosure, at least part of the signals has a high level and a low level; one of the high level and the low level can be a gate-on level of the signal, which can make the controlled transistor turn on; and the other of the high level and the low level can be a gate-off level of the signal, which can make the controlled transistor turn off. For example, for a signal for controlling a P-type transistor (which can be loaded to the control terminal of the P-type transistor), the gate-on level thereof is the low level, and the gate-off level thereof is the high level. For another example, for a signal for controlling an N-type transistor (which can be loaded to the control terminal of the N-type transistor), the gate-on level thereof is the high level, and the gate-off level thereof is the low level.

[0103] In the embodiments of the present disclosure, each signal has a signal terminal, so that the signal can be loaded to the signal terminal. For example, the first reset signal can be loaded to the first reset signal terminal. For another example, the data voltage can be loaded to the data voltage terminal.

[0104] In the related art, an organic electroluminescent device has been widely applied to smart products such as mobile phones, televisions, and notebook computers due to its advantages such as self-luminescence, low power consumption, wide viewing angle, fast response speed, high contrast, and flexible display. When the display device is used, the picture displayed by the display device can be seen by the surrounding people, which causes inconvenience to the user.

[0105] Therefore, the present application provides a pixel driving circuit PDC and a display panel applying the pixel driving circuit PDC (see FIG. 3, FIG. 15, FIG. 27, FIG. 39, and FIG. 51). The pixel driving circuit PDC comprises a driving unit IU, a shared light-emitting unit GU, and an anti-peep light-emitting unit FU; the output terminal of the driving unit IU is electrically connected with the input terminal of the shared light-emitting unit GU and the input terminal of the anti-peep light-emitting unit FU; the driving unit IU is configured to generate a driving signal; the anti-peep light-emitting unit FU has an anti-peep light-emitting element FLD and is configured to make the anti-peep light-emitting element FLD emit light under the driving of the driving signal at least in an anti-peep mode; and the shared light-emitting unit GU has a shared light-emitting element GLD and is configured to make the shared light-emitting element GLD emit light under the driving of the driving signal in a shared mode.

[0106] In an embodiment, the driving signal generated by the driving unit IU can be a driving current.

[0107] In an embodiment of the present disclosure, the driving unit IU generates a driving signal (e.g. a driving current) to open the privacy light emitting element FLD and close the sharing light emitting element GLD, so that the display panel is in a privacy mode, and the user can only see the image presented by the display panel at a specific angle (e.g. the user can only see the image presented by the display panel at the front of the display panel with the pixel driving circuit, or the user can see the image presented by the display panel at the front and any one side of the display panel). The driving unit IU generates a driving signal (e.g. a driving current) to open the privacy light emitting element FLD and also open the sharing light emitting element GLD, so that the display panel with the pixel driving circuit is in a sharing mode, and the user can see the image presented by the display panel at a larger viewing angle; or the driving unit IU generates a driving signal (e.g. a driving current) to open the sharing light emitting element GLD and close the privacy light emitting element FLD, so that the user can also see the image presented by the display panel at a larger viewing angle. In this way, the display panel with the pixel driving circuit can be switched between the privacy mode and the sharing mode.

[0108] FIG. 1 illustrates a schematic diagram of a display panel in an embodiment of the present disclosure. As shown in FIG. 1, the display panel PNL includes a display area AA and a peripheral area BB located at least one side of the display area AA. The display area AA of the display panel PNL includes an array of display units. Each display unit includes a sub-pixel PIX and a pixel driving circuit PDC for driving the sub-pixel PIX. The display panel PNL has a plurality of scan lines GL arranged along a row direction DH in the display area AA, each scan line GL is arranged in one-to-one correspondence with each display unit row, and each pixel driving circuit PDC of the corresponding display unit row is connected to the scan line GL. The display panel PNL has a plurality of data lines DL arranged along a column direction DV in the display area AA, each data line DL is arranged in one-to-one correspondence with each display unit column, and each pixel driving circuit PDC of the corresponding display unit column is connected to the data line DL. In this way, the pixel driving circuit PDC of each display unit is connected to one scan line GL and one data line DL. When a selection signal is loaded on the scan line GL, the data voltage Vdata loaded on the data line DL can be loaded to the pixel driving circuit PDC, so that the pixel driving circuit PDC can control the brightness of the sub-pixel PIX according to the written driving voltage.

[0109] Optionally, the sub-pixel PIX can be a current-driven self-luminous element, for example, can be any one of OLED, PLED, QLED, Micro LED, Mini LED and the like. In this embodiment, the sub-pixel PIX can include sub-pixels of multiple different colors, for example, including red sub-pixels for emitting red light, green sub-pixels for emitting green light, and blue sub-pixels for emitting blue light. It can be understood that in other embodiments of the present disclosure, the sub-pixels in the display area AA can also have sub-pixels of other colors (for example, yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, white sub-pixels for emitting white light, etc.).

[0110] FIG. 2 illustrates a schematic diagram of a film layer structure of a display panel. Referring to FIG. 2, the display panel includes a substrate SBT, a driving layer DRL, a pixel layer PIXL, and an angle limiting layer (not specifically labeled and shown in the drawings of the present application) which are sequentially stacked.

[0111] Optionally, the substrate SBT can be an inorganic material substrate SBT, an organic material substrate SBT, or a composite substrate formed by stacking an inorganic material substrate SBT and an organic material substrate SBT. For example, in some embodiments of the present disclosure, the material of the substrate SBT can be a glass material such as soda lime glass, quartz glass, sapphire glass, etc.

[0112] In some other embodiments of the present disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can also be a flexible substrate SBT, for example, the material of the substrate SBT can include polyimide.

[0113] Optionally, referring to FIG. 2, in the driving layer DRL, any one of the pixel driving circuits PDC can include a thin film transistor and a storage capacitor CST (not shown in the drawings of the present application). Further, the thin film transistor can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0114] It can be understood that in each of the pixel driving circuit PDC, the types of any two transistors can be the same or different. For example, in some embodiments, in one pixel driving circuit PDC, some transistors can be N-type transistors and some transistors can be P-type transistors. For another example, in some other embodiments, in one pixel driving circuit PDC, the materials of the active layers of some transistors can be low-temperature polysilicon semiconductor materials and the materials of the active layers of some transistors can be metal oxide semiconductor materials. In some embodiments of the present disclosure, the thin film transistors are low-temperature polysilicon transistors. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors and some thin film transistors are metal oxide transistors.

[0115] Optionally, referring to FIG. 2, the driving layer DRL can include a buffer layer (for example, the first buffer layer Buff1 and the second buffer layer Buff2 shown in FIG. 2) stacked on the substrate base plate SBT, a metal light shielding layer BSM arranged between the first buffer layer Buff1 and the substrate base plate SBT, a semiconductor layer (for example, the low-temperature polysilicon semiconductor layer PSCL and the metal oxide semiconductor layer OSCL shown in FIG. 2) in the pixel layer PIXL, a gate insulating layer (for example, the first gate insulating layer GI1, the second gate insulating layer GI2 and the third gate insulating layer GI3 shown in FIG. 2), a gate layer (for example, the first gate layer GT1, the second gate layer GT2 and the third gate layer GT3 shown in FIG. 2), an interlayer dielectric layer ILD, a source-drain metal layer (for example, the first source-drain metal layer SD1 and the second source-drain metal layer SD2 shown in FIG. 2), a planarization layer (for example, the first planarization layer PLN1 and the second planarization layer PLN2 shown in FIG. 2) and the like. Each thin film transistor and the storage capacitor CST (not specifically labeled in the drawings of the present disclosure) can be formed by the semiconductor layer, the gate insulating layer, the gate layer, the interlayer dielectric layer ILD, the source-drain metal layer and the like; of course, other film layers can also be used. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer can be used to form the active layer of the transistor (including the first electrode, the second electrode and the channel region of the transistor), and can also be used to form part of the wiring or the conductive structure by being conductive if necessary. The first source-drain metal layer SD1 can be used to form the scanning signal wiring; the gate layer can be used to form one or more of the reset control wiring, the light-emitting control wiring and the like, and can also be used to form the gate electrode of the transistor, and can also be used to form part or all of the electrode plate of the storage capacitor CST. The source-drain metal layer can be used to form the data wiring, the driving power voltage wiring and the like, and can also be used to form part of the electrode plate of the storage capacitor CST.

[0116] Of course, in other embodiments of the present disclosure, the drive layer DRL can also include other film layers as needed, for example, it can also include a metal light-blocking layer BSM between the semiconductor layer and the substrate SBT, etc. Any one of the above-mentioned semiconductor layer, gate layer, source-drain metal layer, etc. film layer can also be multi-layered as needed, for example, the drive layer DRL can include two different semiconductor layers, or include two or three source-drain metal layers, or include two or three gate layers; accordingly, the insulating film layer in the drive layer DRL (such as the gate insulating layer, the interlayer dielectric layer ILD, the planarization layer, etc.) can be adaptively increased or decreased, or new insulating film layers can be added as needed.

[0117] Optionally, the pixel layer PIXL can include a pixel electrode PEL, a light-emitting functional layer EL, and a common electrode layer COML which are sequentially stacked. The pixel electrode PEL has a plurality of pixel electrodes PE in the display area AA of the display panel. The pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of pixel electrodes PE, and any one pixel opening exposes at least a partial area of the corresponding pixel electrode PE. For example, the pixel definition layer PDL covers the edges of the pixel electrode PE and exposes at least a partial internal area of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of the pixel electrode PE (the area directly connected to the light-emitting functional layer EL), and further define the light-emitting area and light-emitting area of the sub-pixel PIX. The common electrode layer COML covers the light-emitting functional layer EL as a common electrode. The pixel electrode PEL and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EL, so that the light-emitting functional layer EL emits light. The part of the light-emitting functional layer EL between the pixel electrode PEL and the common electrode layer COML can serve as a light-emitting functional unit of the sub-pixel PIX. The pixel electrode PEL, the common electrode layer COML, and the light-emitting functional unit form a light-emitting element of the sub-pixel PIX. Among them, one of the pixel electrode PEL and the common electrode layer COML serves as an anode of the sub-pixel PIX, and the other serves as a cathode of the sub-pixel PIX.

[0118] In this example, the display panel is an OLED (Organic Light Emitting Diode) display panel. The light-emitting functional layer EL can include an organic light-emitting layer, and can include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Further, the organic light-emitting layer can include a light-emitting layer host material and a light-emitting layer guest material, which can be a fluorescent dopant or a phosphorescent dopant, and in particular can be a thermally activated delayed fluorescence material.

[0119] It can be understood that the display panel can also be other types of display panels, for example, can also be a QLED display panel, a QD-OLED display panel, or other types of display panels.

[0120] Referring to FIG. 2, the display panel can further include a thin film encapsulation layer TFE, which can be disposed on a surface of the pixel layer PIXL away from the substrate substrate SBT, and can include inorganic encapsulation layers and organic encapsulation layers alternately stacked. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PIXL and causing the materials in the pixel layer PIXL to age. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral region BB. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer can be located between the edge of the display region AA and the edge of the inorganic encapsulation layer.

[0121] Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer (not specifically shown in this figure) stacked in sequence on the side of the pixel layer PIXL away from the substrate substrate SBT. The first inorganic encapsulation layer covers the display region AA and extends to the outside of the barrier wall; the organic encapsulation layer covers the display region AA and extends to the inside of the barrier wall; and the second inorganic encapsulation layer covers the organic encapsulation layer and extends to the outside of the barrier wall. On the outside of the barrier wall, the second inorganic encapsulation layer is in contact with the first inorganic encapsulation layer. In this way, the organic encapsulation layer is enclosed by the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the stress on the first inorganic encapsulation layer and the second inorganic encapsulation layer is balanced. The first inorganic encapsulation layer and the second inorganic encapsulation layer enclose the organic encapsulation layer, isolating the organic encapsulation layer from water and oxygen. Of course, in other embodiments of the present disclosure, the display panel can also not be provided with a thin film encapsulation layer TFE, but other ways to encapsulate and protect the pixel layer PIXL.

[0122] In some embodiments of the present disclosure, the privacy light emitting element FLD and the shared light emitting element GLD are arranged on the pixel layer PIXL (not shown in the drawings); the angle limiting layer is arranged on the light emitting side of the pixel layer PIXL, and the angle limiting layer has a first angle limiting structure corresponding to the shared light emitting element GLD and a second angle limiting structure corresponding to the privacy light emitting element FLD; the light emitted by the shared light emitting element GLD is emitted to the outside of the display panel through the first angle limiting structure, and the light emitted by the privacy light emitting element FLD is emitted to the outside of the display panel through the second angle limiting structure; the first angle limiting structure makes the maximum light emitting angle of the shared light emitting element GLD be a first light emitting angle; the second angle limiting structure makes the maximum light emitting angle of the privacy light emitting element FLD be a second light emitting angle; and the first light emitting angle is greater than the second light emitting angle. In this way, when the privacy light emitting element FLD is turned on, the light emitted by the privacy light emitting element FLD passes through the second angle limiting structure, the second angle limiting structure changes the light path of the light emitted by the privacy light emitting element FLD, so that the light emitting viewing angle of the privacy light emitting element FLD is reduced; and when the shared light emitting element GLD is turned on, the light emitted by the shared light emitting element GLD passes through the first angle limiting structure, the first angle limiting structure changes the light path of the light emitted by the shared light emitting element GLD, so that the light emitting viewing angle of the shared light emitting element GLD is increased. In this way, the privacy mode or the sharing mode of the display panel can be realized.

[0123] As an example, the first angle limiting structure can be a black light shielding layer (which does not cause the light emitting viewing angle to be reduced) and a light collecting structure that collects light only in a specific direction, which can increase the light emitting viewing angle of the shared light emitting element GLD, so that the display effect of large viewing angle sharing of the shared light emitting element GLD can be realized; or the first angle limiting structure can not be provided with a black light shielding layer and a light collecting structure, so that the light emitting viewing angle of the shared light emitting element GLD can also be increased, and the display effect of large viewing angle sharing of the shared light emitting element GLD can be realized. The second angle limiting structure can be a black light shielding layer (which causes the light emitting viewing angle to be reduced) and a light collecting structure, which makes the light emitting viewing angle of the privacy light emitting element FLD be reduced, thereby realizing the effect of privacy.

[0124] In some embodiments of the present disclosure, the first pole of the privacy light emitting element FLD is electrically connected to the output end of the driving unit IU, and the second pole of the privacy light emitting element FLD is used to load a reference voltage VSS.

[0125] It should be noted that the display panel including the pixel driving circuit PDC in this embodiment can be applied to a mobile intelligent terminal, for example, the display panel can be a mobile phone display panel.

[0126] FIG. 3 illustrates an equivalent circuit diagram of the pixel driving circuit.

[0127] Referring to FIG. 3, in one example of the embodiment, the shared light emitting unit GU further comprises a first control unit M9 and a first reset unit M11; a second end of the first control unit M9 is electrically connected with a second end of the first reset unit M11 and a first pole of the shared light emitting element GLD, and a first end of the first control unit M9 is electrically connected with an output end of the driving unit IU; the first reset unit M11 is configured to load a second initialization voltage Vinit2; a second pole of the shared light emitting element GLD is configured to load a reference voltage VSS; the first control unit M9 is configured to make a conduction between the output end of the driving unit IU and the first pole of the shared light emitting element GLD in response to a second light emitting signal EM2; and the first reset unit M11 is configured to load the second initialization voltage Vinit2 to the first pole of the shared light emitting element GLD in response to a second reset signal PResetH. In this way, when the display panel is in the privacy display state, the driving unit IU generates a driving current as a driving signal, the driving current generated by the driving unit IU is loaded to the privacy light emitting element FLD, the privacy light emitting element FLD is turned on, and the shared light emitting element GLD is turned off; when the display panel is in the shared display state, the driving unit IU generates a driving current as a driving signal, the driving signal generated by the driving unit IU is loaded to the privacy light emitting element FLD, the privacy light emitting element FLD is turned on, the first control unit M9 loads the driving signal generated by the driving unit IU to the shared light emitting element GLD in response to the second light emitting signal EM2, and the shared light emitting element GLD is turned on.

[0128] The pixel driving circuit PDC is further described below by means of an equivalent circuit diagram (see FIG. 3) of the pixel driving circuit PDC (which can be applied to a mobile phone display panel):

[0129] A first pole of the gate reset transistor T1 is electrically connected with the first initialization voltage Vinit1, a second pole of the gate reset transistor T1 is electrically connected with a second pole of the driving transistor T3, a first pole of the second light emitting transistor T6, a first pole of the threshold compensation transistor T2, and the third node N3, a control pole of the gate reset transistor T1 is electrically connected with the first reset signal PReset, and the gate reset transistor T1 is configured to load the first initialization voltage Vinit1 to the third node N3 in response to a conduction level of the first reset signal PReset.

[0130] A second pole of the threshold compensation transistor T2 is electrically connected with the first node N1, a first electrode plate of the storage capacitor CST, and a control pole of the driving transistor T3, a control pole of the threshold compensation transistor T2 is electrically connected with the first scan signal NGate, and the threshold compensation transistor T2 is configured to load a signal of the third node N3 to the first node N1 in response to a conduction level of the first scan signal NGate.

[0131] The first electrode of the drive transistor T3 is electrically connected with the second node N2, the second electrode of the drive transistor T3 is electrically connected with the third node N3, the control electrode of the drive transistor T3 is electrically connected with the first node N1, and the drive transistor T3 is configured to load the signal of the second node N2 to the third node N3 in response to the on level of the first node N1.

[0132] The first electrode of the data write transistor T4 is electrically connected with the data voltage Vdata, the second electrode of the data write transistor T4 is electrically connected with the first electrode of the drive transistor T3 and the second node N2, the control electrode of the data write transistor T4 is electrically connected with the second scan signal PGate, and the data write transistor T4 is configured to write the data voltage Vdata to the second node N2 in response to the on level of the second scan signal PGate.

[0133] The first electrode of the first light emitting transistor T5 is electrically connected with the power supply voltage terminal, the first electrode of the first light emitting transistor T5 is electrically connected with the second node N2, the control electrode of the first light emitting transistor T5 is electrically connected with the first light emitting signal EM1, and the first light emitting transistor T5 is configured to load the power supply voltage to the second node N2 in response to the on signal of the first light emitting signal EM1.

[0134] The first electrode of the second light emitting transistor T6 is electrically connected with the third node N3, the second electrode of the second light emitting transistor T6 is electrically connected with the fourth node N4, the control electrode of the second light emitting transistor T6 is electrically connected with the first light emitting signal EM1, and the second light emitting transistor T6 is configured to load the signal of the third node N3 to the fourth node N4 in response to the on level of the first light emitting signal EM1.

[0135] In the pixel driving circuit PDC, the first reset unit M11 includes a first reset transistor T11, wherein the first electrode of the first reset transistor T11 is electrically connected with the second initialization voltage Vinit2, the second electrode of the first reset transistor T11 is electrically connected with the fifth node N5 and the shared light emitting element GLD, the control electrode of the first reset transistor T11 is electrically connected with the second reset signal PResetH, and the first reset transistor T11 is configured to load the second initialization voltage Vinit2 to the fifth node N5 in response to the on level.

[0136] The first electrode of the node control transistor T8 is electrically connected with the reset voltage Vref, the second electrode of the node control transistor T8 is electrically connected with the second node N2, the control electrode of the node control transistor T8 is electrically connected with the second reset signal PResetH, and the node control transistor T8 is configured to load the reset voltage Vref to the second node N2 in response to the on level of the second reset signal PResetH.

[0137] In the pixel driving circuit PDC, the first control unit M9 includes a shared control transistor T9. The first electrode of the shared control transistor T9 is electrically connected with the fifth node N5 and the shared light emitting element GLD, the second electrode of the shared control transistor T9 is electrically connected with the fourth node N4, the control electrode of the shared control transistor T9 is electrically connected with the second light emitting signal EM2, and the shared control transistor T9 is configured to load the signal of the fourth node N4 to the fifth node N5 in response to the on level of the second light emitting signal EM2, so as to make the shared light emitting element GLD open.

[0138] The first electrode of the anti-peep light emitting element FLD is electrically connected with the fourth node N4, the second electrode of the anti-peep light emitting element FLD is used to load the reference voltage VSS, and the anti-peep light emitting element FLD is configured to open under the driving current generated by the driving unit IU.

[0139] In this embodiment, the gate reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light emitting transistor T5, the second light emitting transistor T6, the first reset transistor T11, the node control transistor T8, and the shared control transistor T9 are P-type transistors, and the threshold compensation transistor T2 is an N-type transistor.

[0140] It can be understood that the on level refers to an output level capable of making the corresponding transistor achieve the on state. For example, when the transistor is a P-type transistor, the on level is a low level; and when the transistor is an N-type transistor, the on level is a high level.

[0141] The pixel driving circuit PDC is further described below through the timing of the pixel driving circuit PDC (see FIG. 4):

[0142] When the pixel driving circuit is in the anti-peep mode and the pixel driving circuit PDC is in the high-frequency refresh stage A1:

[0143] In the first reset stage P1: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first light-emitting signal EM1 is high level, and the second light-emitting signal EM2 (in the anti-peep mode) is low level. At this time, the first reset transistor T11, the node control transistor T8, and the shared control transistor T9 are turned on; the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first light-emitting transistor T5, and the second light-emitting transistor T6 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4 through the first reset transistor T11 and the shared control transistor T9, the reset of the anode of the anti-peep light-emitting element FLD is realized; and the reset voltage Vref is loaded to the second node N2 through the node control transistor T8, the reset of the first pole of the driving transistor T3 is realized (see FIG. 5).

[0144] In the second reset stage P2: the second reset signal PResetH is high level, the first reset signal PReset is low level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first light-emitting signal EM1 is high level, and the second light-emitting signal EM2 (in the anti-peep mode) is high level. At this time, the gate reset transistor T1 and the threshold compensation transistor T2 are turned on, and the data write transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, the first reset transistor T11, the node control transistor T8, and the shared control transistor T9 are turned off, so that the first initialization voltage Vinit1 is loaded to the first node N1 and the first electrode plate of the storage capacitor CST, and the charging of the storage capacitor CST can be realized (see FIG. 6).

[0145] In the data write stage P3: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is low level, the first light-emitting signal EM1 is high level, and the second light-emitting signal EM2 (in the anti-peep mode) is high level. At this time, the threshold compensation transistor T2, the driving transistor T3, and the data write transistor T4 are turned on; the gate reset transistor T1, the first light-emitting transistor T5, the second light-emitting transistor T6, the first reset transistor T11, the node control transistor T8, the shared control transistor T9, and the anti-peep control transistor T10 are turned off, so that the data voltage Vdata is loaded to the first node N1, the threshold compensation and the data write of the third node N3 are realized (see FIG. 7).

[0146] In the third reset stage P4: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, and the second emitting signal EM2 (in the anti-peep mode) is low level. At this time, the first reset transistor T11, the node control transistor T8, and the shared control transistor T9 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first emitting transistor T5, and the second emitting transistor T6 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4 through the first reset transistor T11 and the shared control transistor T9, and the reset of the anode of the anti-peep emitting element FLD is realized; and the reset voltage Vref is loaded to the second node N2 through the node control transistor T8, and the reset of the first pole of the driving transistor T3 is realized (see FIG. 8).

[0147] In the light emitting stage P5: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first emitting signal EM1 is low level, and the second emitting signal EM2 is high level. At this time, the first emitting transistor T5 and the second emitting transistor T6, and the driving transistor T3 are turned on; and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first reset transistor T11, the node control transistor T8, and the shared control transistor T9 are turned off, so that the anti-peep emitting element FLD is turned on (see FIG. 9).

[0148] When the pixel driving circuit PDC is in the anti-peep mode and is in the low-frequency refresh stage A2: in the first reset stage P1 to the light emitting stage P5, the first reset signal PReset always loads the first power voltage VGH, the first scan signal NGate always loads the second power voltage VGL, and the second scan signal PGate always loads the first power voltage VGH. In this stage, the pixel driving circuit PDC does not perform new data writing, so that the low-frequency refresh of the pixel driving circuit PDC can be realized.

[0149] When the pixel driving circuit PDC is in the shared mode and the pixel driving circuit PDC is in the high-frequency refresh stage:

[0150] In the first reset stage P1: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first light-emitting signal EM1 is high level, and the second light-emitting signal EM2 is low level. At this time, the first reset transistor T11, the node control transistor T8, and the shared control transistor T9 are turned on; the gate reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data write transistor T4, the first light-emitting transistor T5, and the second light-emitting transistor T6 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4, the reset of the anode of the privacy light-emitting element FLD is realized, and the reset voltage Vref is loaded to the second node N2 through the node control transistor T8, the reset of the first electrode of the driving transistor T3 is realized (see FIG. 10).

[0151] In the second reset stage P2: the second reset signal PResetH is high level, the first reset signal PReset is low level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first light-emitting signal EM1 is high level, and the second light-emitting signal EM2 is high level. At this time, the gate reset transistor T1 and the threshold compensation transistor T2 are turned on; the data write transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, the first reset transistor T11, the node control transistor T8, and the shared control transistor T9 are turned off, so that the first initialization voltage Vinit1 is loaded to the first node N1 and the first electrode plate of the storage capacitor CST, and the storage capacitor CST is charged (FIG. 11).

[0152] In the data write stage P3: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is low level, the first light-emitting signal EM1 is high level, and the second light-emitting signal EM2 is high level. At this time, the threshold compensation transistor T2, the driving transistor T3, and the data write transistor T4 are turned on; the gate reset transistor T1, the first light-emitting transistor T5, the second light-emitting transistor T6, the first reset transistor T11, the node control transistor T8, and the shared control transistor T9 are turned off, so that the data voltage Vdata is loaded to the first node N1, the threshold compensation and the data write of the third node N3 are realized (see FIG. 12).

[0153] In the third reset stage P4: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, and the second emitting signal EM2 is low level. At this time, the first reset transistor T11, the node control transistor T8, and the shared control transistor T9 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first emitting transistor T5, and the second emitting transistor T6 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4, and the reset of the anode of the privacy emitting element FLD is realized (see FIG. 13).

[0154] In the light emitting stage P5: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first emitting signal EM1 is low level, and the second emitting signal EM2 is low level. At this time, the first emitting transistor T5, the second emitting transistor T6, the driving transistor T3, and the shared control transistor T9 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first reset transistor T11, and the node control transistor T8 are turned off, so that the privacy emitting element FLD is turned on at the same time as the shared emitting element GLD (see FIG. 14).

[0155] When the pixel driving circuit PDC is in the shared mode and is in the low-frequency refresh stage A2 of the pixel driving circuit PDC. In the first reset stage P1 to the light emitting stage P5, the first reset signal PReset always loads the first power voltage VGH, the first scan signal NGate always loads the second power voltage VGL, and the second scan signal PGate always loads the first power voltage VGH. The pixel circuit does not perform new data writing, so that the low-frequency refresh of the pixel driving circuit PDC can be realized.

[0156] In another example of the embodiment, referring to FIG. 15, the driving unit IU includes a second reset unit M7, a first end of the second reset unit M7 is configured to load a second initialization voltage Vinit2, and a second end of the second reset unit M7 is electrically connected with an output end of the driving unit IU; the second reset unit M7 is configured to load the second initialization voltage Vinit2 to the output end of the driving unit IU in response to a second reset signal PResetH. In this way, when the display panel is in the privacy display state, the driving unit IU generates a driving current, the driving current generated by the driving unit IU is loaded on the privacy light emitting element FLD, the privacy light emitting element FLD is turned on, and the shared light emitting element GLD is turned off; when the display panel is in the sharing state, the driving unit IU generates a driving current, the driving current generated by the driving unit IU is loaded on the privacy light emitting element FLD, the privacy light emitting element FLD is turned on, and the first control unit M9 loads the driving current generated by the driving unit IU on the shared light emitting element GLD in response to the second light emitting signal EM2, and the shared light emitting element GLD is turned on. Moreover, the pixel driving circuit PDC can load the second initialization voltage Vinit2 to the output end of the driving unit IU by loading the second reset signal PResetH on the second reset unit M7, so as to reset the output end of the driving unit IU.

[0157] The pixel driving circuit PDC is further described below by means of an equivalent circuit diagram (see FIG. 15) of the pixel driving circuit PDC (for example, the pixel driving circuit PDC is applied to a mobile phone display panel, etc.):

[0158] A first pole of the gate reset transistor T1 is electrically connected with the first initialization voltage Vinit1, a second pole of the gate reset transistor T1 is electrically connected with a second pole of the driving transistor T3, a first pole of the second light emitting transistor T6, a first pole of the threshold compensation transistor T2, and the third node N3, a control pole of the gate reset transistor T1 is electrically connected with the first reset signal PReset, and the gate reset transistor T1 is configured to load the first initialization voltage Vinit1 to the third node N3 in response to a conduction level of the first reset signal PReset.

[0159] A second pole of the threshold compensation transistor T2 is electrically connected with the first node N1, a first electrode plate of the storage capacitor CST, and a control pole of the driving transistor T3, a control pole of the threshold compensation transistor T2 is electrically connected with the first scanning signal NGate, and the threshold compensation transistor T2 is configured to load a signal of the third node N3 to the first node N1 in response to a conduction level of the first scanning signal NGate.

[0160] A first electrode of the driving transistor T3 is electrically connected with the second node N2, a second electrode of the driving transistor T3 is electrically connected with the third node N3, a control electrode of the driving transistor T3 is electrically connected with the first node N1, and the driving transistor T3 is configured to load a signal of the second node N2 to the third node N3 in response to a turn-on level of the first node N1.

[0161] A first electrode of the data writing transistor T4 is electrically connected with the data voltage Vdata, a second electrode of the data writing transistor T4 is electrically connected with the first electrode of the driving transistor T3 and the second node N2, a control electrode of the data writing transistor T4 is electrically connected with the second scan signal PGate, and the data writing transistor T4 is configured to write the data voltage Vdata to the second node N2 in response to a turn-on level of the second scan signal PGate.

[0162] A first electrode of the first light emitting transistor T5 is electrically connected with the power supply voltage terminal, a first electrode of the first light emitting transistor T5 is electrically connected with the second node N2, a control electrode of the first light emitting transistor T5 is electrically connected with the first emission signal EM1, and the first light emitting transistor T5 is configured to load the power supply voltage to the second node N2 in response to a turn-on signal of the first emission signal EM1.

[0163] In the pixel driving circuit PDC, the driving unit IU further includes a switching unit M6, and the switching unit M6 includes a second light emitting transistor T6. A first electrode of the second light emitting transistor T6 is electrically connected with the third node N3, a second electrode of the second light emitting transistor T6 is electrically connected with the fourth node N4, a control electrode of the second light emitting transistor T6 is electrically connected with the first emission signal EM1, and the second light emitting transistor T6 is configured to load a signal of the third node N3 to the fourth node N4 in response to a turn-on level of the first emission signal EM1.

[0164] In the pixel driving circuit PDC, the driving unit IU further includes a second reset unit M7, and the second reset unit M7 includes a second reset transistor T7. A first electrode of the second reset transistor T7 is electrically connected with the second initialization voltage Vinit2, a second electrode of the second reset transistor T7 is electrically connected with the fourth node N4 and the anti-peep light emitting element FLD, a control electrode of the second reset transistor T7 is electrically connected with the second reset signal PResetH, and the second reset transistor T7 is configured to load the second initialization voltage Vinit2 to the fourth node N4 in response to a turn-on level.

[0165] The first electrode of the node control transistor T8 is electrically connected with the reset voltage Vref, the second electrode of the node control transistor T8 is electrically connected with the second node N2, and the control electrode of the node control transistor T8 is electrically connected with the second reset signal PResetH. The node control transistor T8 is configured to load the reset voltage Vref to the second node N2 in response to the on level of the second reset signal PResetH.

[0166] In the pixel driving circuit PDC, the first control unit M9 includes a shared control transistor. The first electrode of the shared control transistor T9 is electrically connected with the fourth node N4, the second electrode of the shared control transistor T9 is electrically connected with the fifth node N5, and the control electrode of the shared control transistor T9 is electrically connected with the second emission signal EM2. The shared control transistor T9 is configured to load the signal of the fourth node N4 to the fifth node N5 in response to the on level of the second emission signal EM2.

[0167] The first electrode of the anti-peep light emitting element FLD is electrically connected with the fourth node N4, the second electrode of the second light emitting transistor T6, and the first electrode of the shared control transistor T9.

[0168] In this embodiment, the gate reset transistor T1, the driving transistor T3, the data write transistor T4, the first light emitting transistor T5, the second light emitting transistor T6, the second reset transistor T7, the node control transistor T8, and the shared control transistor T9 are P-type transistors, and the threshold compensation transistor T2 is an N-type transistor.

[0169] It can be understood that the on level refers to an output level capable of making the corresponding transistor achieve the on state. For example, when the transistor is a P-type transistor, the on level is a low level; and when the transistor is an N-type transistor, the on level is a high level.

[0170] The pixel driving circuit PDC is further described below through the timing of the pixel driving circuit PDC (see FIG. 16):

[0171] When the pixel driving circuit PDC is in the anti-peep mode and the pixel driving circuit PDC is in the high-frequency refresh stage A1:

[0172] In the first reset stage P1: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first light-emitting signal EM1 is high level, and the second light-emitting signal EM2 is low level. At this time, the second reset transistor T7, the node control transistor T8, and the shared control transistor T9 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first light-emitting transistor T5, and the second light-emitting transistor T6 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4 through the second reset transistor T7 and the shared control transistor T9, the reset of the anode of the privacy light-emitting element FLD is realized; and the reset voltage Vref is loaded to the second node N2 through the node control transistor T8, the reset of the first electrode of the driving transistor T3 is realized (see FIG. 17).

[0173] In the second reset stage P2: the second reset signal PResetH is high level, the first reset signal PReset is low level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first light-emitting signal EM1 is high level, and the second light-emitting signal EM2 is high level. At this time, the gate reset transistor T1 and the threshold compensation transistor T2 are turned on; the data write transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, the second reset transistor T7, the node control transistor T8, and the shared control transistor T9 are turned off, so that the first initialization voltage Vinit1 is loaded to the first node N1 and the first electrode plate of the storage capacitor CST, and the charging of the storage capacitor CST is realized (see FIG. 18).

[0174] In the data write stage P3: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is low level, the first light-emitting signal EM1 is high level, and the second light-emitting signal EM2 is high level. At this time, the threshold compensation transistor T2 and the data write transistor T4 are turned on, and the gate reset transistor T1, the first light-emitting transistor T5, the second light-emitting transistor T6, the second reset transistor T7, the node control transistor T8, the shared control transistor T9, and the privacy control transistor T10 are turned off, so that the data voltage Vdata is loaded to the first node N1, the threshold compensation and data write of the third node N3 are realized (see FIG. 19).

[0175] In the third reset stage P4: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, and the second emitting signal EM2 is low level. At this time, the second reset transistor T7, the node control transistor T8, and the shared control transistor T9 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first emitting transistor T5, and the second emitting transistor T6 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4 through the second reset transistor T7 and the shared control transistor T9, and the reset of the anode of the privacy light emitting element FLD is realized; and the reset voltage Vref is loaded to the second node N2 through the node control transistor T8, and the reset of the first pole of the driving transistor T3 is realized (see FIG. 20).

[0176] In the light emitting stage P5: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first emitting signal EM1 is low level, and the second emitting signal EM2 is high level. At this time, the first emitting transistor T5 and the second emitting transistor T6 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data write transistor T4, the second reset transistor T7, the node control transistor T8, and the shared control transistor T9 are turned off, so that the privacy light emitting element FLD is turned on (see FIG. 21).

[0177] When the pixel driving circuit PDC is in the privacy mode and is in the low-frequency refresh stage A2: in the first reset stage P1 to the light emitting stage P5, the first reset signal PReset always loads the first power voltage VGH, the first scan signal NGate always loads the second power voltage VGL, and the second scan signal PGate always loads the first power voltage VGH. In this stage, the pixel driving circuit PDC does not perform new data writing, so that the low-frequency refresh of the pixel driving circuit PDC can be realized.

[0178] When the pixel driving circuit is in the shared mode and the pixel driving circuit PDC is in the high-frequency refresh stage A1:

[0179] In the first reset stage P1: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first light emitting signal EM1 is high level, and the second light emitting signal EM2 is low level. At this time, the second reset transistor T7, the node control transistor T8, and the shared control transistor T9 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first light emitting transistor T5, and the second light emitting transistor T6 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4, the reset of the anode of the privacy light emitting device FLD is realized; and the reset voltage Vref is loaded to the second node N2 through the node control transistor T8, the reset of the first electrode of the driving transistor T3 is realized (see FIG. 22).

[0180] In the second reset stage P2: the second reset signal PResetH is high level, the first reset signal PReset is low level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first light emitting signal EM1 is high level, and the second light emitting signal EM2 is high level. At this time, the gate reset transistor T1 and the threshold compensation transistor T2 are turned on, and the driving transistor T3, the data write transistor T4, the first light emitting transistor T5, the second light emitting transistor T6, the second reset transistor T7, the node control transistor T8, and the shared control transistor T9 are turned off, so that the first initialization voltage Vinit1 is loaded to the first node N1 and the first electrode plate of the storage capacitor CST, and the charging of the storage capacitor CST is realized (see FIG. 23).

[0181] In the data write stage P3: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is low level, the first light emitting signal EM1 is high level, and the second light emitting signal EM2 is high level. At this time, the threshold compensation transistor T2 and the data write transistor T4 are turned on, and the gate reset transistor T1, the first light emitting transistor T5, the second light emitting transistor T6, the second reset transistor T7, the node control transistor T8, and the shared control transistor T9 are turned off, so that the data voltage Vdata is loaded to the first node N1, the threshold compensation and the data write of the third node N3 are realized (see FIG. 24).

[0182] In the third reset stage P4: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, and the second emitting signal EM2 is low level. At this time, the second reset transistor T7, the node control transistor T8, and the shared control transistor T9 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first emitting transistor T5, and the second emitting transistor T6 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4, and the reset of the anode of the privacy emitting element FLD is realized (see FIG. 25).

[0183] In the light emitting stage P5: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first emitting signal EM1 is low level, and the second emitting signal EM2 is low level. At this time, the first emitting transistor T5, the second emitting transistor T6, the shared control transistor T9, and the driving transistor T3 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the second reset transistor T7, and the node control transistor T8 are turned off, so that the privacy emitting element FLD is turned on at the same time as the shared emitting element GLD (see FIG. 26).

[0184] When the pixel driving circuit PDC is in the sharing mode and is in the low-frequency refresh stage A2: in the first reset stage P1 to the light emitting stage P5, the first reset signal PReset always loads the first power voltage VGH, the first scan signal NGate always loads the second power voltage VGL, and the second scan signal PGate always loads the first power voltage VGH, and the pixel circuit does not perform new data writing, so that the low-frequency refresh of the pixel driving circuit PDC can be realized.

[0185] In some embodiments of the present disclosure, the shared light emitting unit GU further comprises a first control unit M9, a second end of the first control unit M9 is electrically connected with the first pole of the shared light emitting element GLD; a first end of the first control unit M9 is electrically connected with the output end of the driving unit IU; the first control unit M9 is configured to make the output end of the driving unit IU and the first pole of the shared light emitting element GLD conductive in response to the second light emitting signal EM2; the second pole of the shared light emitting element GLD is configured to load the reference voltage VSS; the anti-peep light emitting unit FU further comprises a second control unit M10; a second end of the second control unit M10 is electrically connected with the output end of the driving unit IU, and a first end of the second control unit M10 is electrically connected with the first pole of the anti-peep light emitting element FLD; the second control unit M10 is configured to make the output end of the driving unit IU and the first pole of the anti-peep light emitting element FLD conductive in response to the third light emitting signal EM3; and the second pole of the anti-peep light emitting element FLD is configured to load the reference voltage VSS. In this way, when the display panel is in the anti-peep mode, the third light emitting signal EM3 can be loaded to the second control unit M10, the second control unit M10 makes the driving current generated by the driving unit IU load to the anti-peep light emitting element FLD in response to the third light emitting signal EM3, the anti-peep light emitting element FLD is turned on, and the shared light emitting element GLD is turned off; when the display panel is in the shared mode, the second light emitting signal EM2 can be loaded to the first control unit M9, the first control unit M9 makes the driving current generated by the driving unit IU load to the shared light emitting element GLD in response to the second light emitting signal EM2, the shared light emitting element GLD is turned on, and the anti-peep light emitting element FLD is turned off. It should be noted that the display panel using the pixel driving circuit PDC of this embodiment can be a desktop display screen, a notebook display screen, or a tablet computer, etc.

[0186] In this embodiment, when the display panel is in the anti-peep mode, the driving current generated by the driving unit IU loads to the anti-peep light emitting element FLD, only the anti-peep light emitting element FLD in the pixel driving circuit PDC is turned on; when the display panel is in the shared mode, the driving current generated by the driving unit IU loads to the shared light emitting element GLD, only the shared light emitting element GLD in the pixel driving circuit PDC is turned on. In this way, the anti-peep light emitting element FLD and the shared light emitting element GLD can be turned on respectively in different modes (anti-peep mode and shared mode), which can reduce the difference in service life between the anti-peep light emitting element FLD and the shared light emitting element GLD to a certain extent.

[0187] In one example of this embodiment, the shared light emitting unit GU further comprises a first reset unit M11 (see FIG. 27); a first end of the first reset unit M11 is configured to load the second initialization voltage Vinit2, and a second end of the first reset unit M11 is electrically connected to the second end of the first control unit M9; the first reset unit M11 is configured to load the second initialization voltage Vinit2 to the second end of the first control unit M9 in response to the second reset signal PResetH. In this way, the second initialization voltage Vinit2 can be loaded to the first control end by loading the second reset signal PResetH to the first reset unit M11, so as to reset the anode of the shared light emitting element GLD.

[0188] The pixel driving circuit PDC is further described below by means of an equivalent circuit diagram (see FIG. 27) of the pixel driving circuit PDC:

[0189] The first pole of the gate reset transistor T1 is electrically connected to the first initialization voltage Vinit1, the second pole of the gate reset transistor T1 is electrically connected to the second pole of the driving transistor T3, the first pole of the second light emitting transistor T6, the first pole of the threshold compensation transistor T2 and the third node N3, the control pole of the gate reset transistor T1 is electrically connected to the first reset signal PReset, and the gate reset transistor T1 is configured to load the first initialization voltage Vinit1 to the third node N3 in response to the on level of the first reset signal PReset.

[0190] The second pole of the threshold compensation transistor T2 is electrically connected to the first node N1, the first electrode plate of the storage capacitor CST and the control pole of the driving transistor T3; the control pole of the threshold compensation transistor T2 is electrically connected to the first scan signal NGate, and the threshold compensation transistor T2 is configured to load the signal of the third node N3 to the first node N1 in response to the on level of the first scan signal NGate.

[0191] The first pole of the driving transistor T3 is electrically connected to the second node N2, the second pole of the driving transistor T3 is electrically connected to the third node N3, and the control pole of the driving transistor T3 is electrically connected to the first node N1; the driving transistor T3 is configured to load the signal of the second node N2 to the third node N3 in response to the on level of the first node N1.

[0192] A first electrode of the data writing transistor T4 is electrically connected with the data voltage Vdata, a second electrode of the data writing transistor T4 is electrically connected with the first electrode of the driving transistor T3 and the second node N2, a control electrode of the data writing transistor T4 is electrically connected with the second scanning signal PGate, and the data writing transistor T4 is configured to write the data voltage Vdata into the second node N2 in response to the on level of the second scanning signal PGate.

[0193] A first electrode of the first light emitting transistor T5 is electrically connected with the power supply voltage terminal, a second electrode of the first light emitting transistor T5 is electrically connected with the second node N2, a control electrode of the first light emitting transistor T5 is electrically connected with the first light emitting signal EM1, and the first light emitting transistor T5 is configured to load the power supply voltage into the second node N2 in response to the on signal of the first light emitting signal EM1.

[0194] In the pixel driving circuit PDC, the switch unit M6 includes a second light emitting transistor T6. A first electrode of the second light emitting transistor T6 is electrically connected with the third node N3, a second electrode of the second light emitting transistor T6 is electrically connected with the fourth node N4, a control electrode of the second light emitting transistor T6 is electrically connected with the first light emitting signal EM1, and the second light emitting transistor T6 is configured to load the signal of the third node N3 into the fourth node N4 in response to the on level of the first light emitting signal EM1.

[0195] In the pixel driving circuit, the first reset unit M11 includes a first reset transistor T11. A first electrode of the first reset transistor T11 is electrically connected with the second initialization voltage Vinit2, a second electrode of the first reset transistor T11 is electrically connected with the fifth node N5 and the shared light emitting element GLD, a control electrode of the first reset transistor T11 is electrically connected with the second reset signal PResetH, and the first reset transistor T11 is configured to load the second initialization voltage Vinit2 into the fifth node N5 in response to the on level of the second reset signal PResetH.

[0196] A first electrode of the node control transistor T8 is electrically connected with the reset voltage Vref, a second electrode of the node control transistor T8 is electrically connected with the second node N2, a control electrode of the node control transistor T8 is electrically connected with the second reset signal PResetH, and the node control transistor T8 is configured to load the reset voltage Vref into the second node N2 in response to the on level of the second reset signal PResetH.

[0197] In the pixel driving circuit, the first control unit M9 comprises a shared control transistor T9. The first electrode of the shared control transistor T9 is electrically connected with the fifth node N5, the second electrode of the shared control transistor T9 is electrically connected with the fourth node N4, the control electrode of the shared control transistor T9 is electrically connected with the second emission signal EM2, and the shared control transistor T9 is configured to load the signal of the fourth node N4 to the fifth node N5 in response to the on level of the second emission signal EM2.

[0198] In the pixel driving circuit, the second control unit M10 comprises an anti-peep control transistor T10. The first electrode of the anti-peep control transistor T10 is electrically connected with the fourth node N4 and the second electrode of the shared control transistor T9, the second electrode of the anti-peep control transistor T10 is electrically connected with the sixth node N6 and the anti-peep light emitting element FLD, the control electrode of the anti-peep control transistor T10 is electrically connected with the third emission signal EM3, and the anti-peep control transistor T10 is configured to load the signal of the fourth node N4 to the sixth node N6 in response to the on level of the third emission signal EM3.

[0199] The first electrode of the anti-peep light emitting element FLD is connected with the anti-peep control transistor T10 and the sixth node N6.

[0200] In this embodiment, the gate reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light emitting transistor T5, the second light emitting transistor T6, the first reset transistor T11, the node control transistor T8, the shared control transistor T9, and the anti-peep control transistor T10 are P-type transistors, and the threshold compensation transistor T2 is an N-type transistor.

[0201] It can be understood that the on level refers to an output level capable of making the corresponding transistor achieve the on state. For example, when the transistor is a P-type transistor, the on level is a low level; when the transistor is an N-type transistor, the on level is a high level.

[0202] The pixel driving circuit PDC is further introduced below through the timing diagram of the pixel driving circuit PDC (see FIG. 28):

[0203] When the pixel driving circuit PDC is in the anti-peep mode and the pixel driving circuit PDC is in the high-frequency refresh stage A1:

[0204] In the first reset stage P1: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first light emitting signal EM1 is high level, the second light emitting signal EM2 is low level, and the third light emitting signal EM3 is high level. At this time, the first reset transistor T11, the node control transistor T8, and the shared control transistor T9 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first light emitting transistor T5, the second light emitting transistor T6, and the anti-peep control transistor T10 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4 through the first reset transistor T11 and the shared control transistor T9, and the reset of the anode of the anti-peep light emitting element FLD is realized; and the reset voltage Vref is loaded to the second node N2 through the node control transistor T8, and the reset of the first pole of the driving transistor T3 is realized (see FIG. 29).

[0205] In the second reset stage P2: the second reset signal PResetH is high level, the first reset signal PReset is low level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first light emitting signal EM1 is high level, the second light emitting signal EM2 is high level, and the third light emitting signal EM3 is high level. At this time, the gate reset transistor T1 and the threshold compensation transistor T2 are turned on, and the data write transistor T4, the first light emitting transistor T5, the second light emitting transistor T6, the first reset transistor T11, the node control transistor T8, the shared control transistor T9, and the anti-peep control transistor T10 are turned off, so that the first initialization voltage Vinit1 is loaded to the first node N1 and the first electrode plate of the storage capacitor CST, and the charging of the storage capacitor CST is realized (see FIG. 30).

[0206] In the data write stage P3: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is low level, the first light emitting signal EM1 is high level, and the second light emitting signal EM2 is high level. At this time, the threshold compensation transistor T2 and the data write transistor T4 are turned on, and the gate reset transistor T1, the first light emitting transistor T5, the second light emitting transistor T6, the first reset transistor T11, the node control transistor T8, the shared control transistor T9, and the anti-peep control transistor T10 are turned off, so that the data voltage Vdata is loaded to the first node N1, and the threshold compensation and data write of the third node N3 are realized (see FIG. 31).

[0207] In the third reset stage P4: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, the second emitting signal EM2 is low level, and the third emitting signal EM3 is low level. At this time, the first reset transistor T11, the node control transistor T8, and the shared control transistor T9 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first emitting transistor T5, the second emitting transistor T6, and the anti-peep control transistor T10 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4, and the reset of the anode of the anti-peep light emitting element FLD is realized (see FIG. 32).

[0208] In the light emitting stage P5: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first emitting signal EM1 is low level, the second emitting signal EM2 is high level, and the third emitting signal EM3 is low level. At this time, the first emitting transistor T5, the second emitting transistor T6, the driving transistor T3, and the anti-peep control transistor T10 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first reset transistor T11, the node control transistor T8, and the shared control transistor T9 are turned off, so that the anti-peep light emitting element FLD is turned on (see FIG. 33).

[0209] When the display panel is in the anti-peep mode and is in the low-frequency refresh stage A2.

[0210] In the first reset stage P1 to the light emitting stage P5, the first reset signal PReset always loads the first power voltage VGH, the first scan signal NGate always loads the second power voltage VGL, and the second scan signal PGate always loads the first power voltage VGH. The pixel circuit does not perform new data writing, so that the low-frequency refresh of the pixel driving circuit PDC can be realized.

[0211] When the pixel driving circuit PDC is in the shared mode and the pixel driving circuit PDC is in the high-frequency refresh stage A1:

[0212] In the first reset stage P1: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, the second emitting signal EM2 is low level, and the third emitting signal EM3 is low level. At this time, the first reset transistor T11, the node control transistor T8, the shared control transistor T9 and the anti-peep control transistor T10 are turned on; the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first emitting transistor T5 and the second emitting transistor T6 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4 through the first reset transistor T11 and the shared control transistor T9, and the first electrode of the anti-peep control transistor T10 is reset; and the reset voltage Vref is loaded to the second node N2 through the node control transistor T8, and the first electrode of the driving transistor T3 is reset (see FIG. 34).

[0213] In the second reset stage P2: the second reset signal PResetH is high level, the first reset signal PReset is low level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, the second emitting signal EM2 is high level, and the third emitting signal EM3 is high level. At this time, the gate reset transistor T1 and the threshold compensation transistor T2 are turned on, and the data write transistor T4, the first emitting transistor T5, the second emitting transistor T6, the first reset transistor T11, the node control transistor T8, the shared control transistor T9 and the anti-peep control transistor T10 are turned off, so that the first initialization voltage Vinit1 is loaded to the first node N1 and the first electrode plate of the storage capacitor CST, and the storage capacitor CST is charged (see FIG. 35).

[0214] In the data write stage P3: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is low level, the first emitting signal EM1 is high level, the second emitting signal EM2 is low level, and the third emitting signal EM3 is high level. At this time, the threshold compensation transistor T2 and the data write transistor T4 are turned on, and the gate reset transistor T1, the first emitting transistor T5, the second emitting transistor T6, the first reset transistor T11, the node control transistor T8, the shared control transistor T9 and the anti-peep control transistor T10 are turned off, so that the data voltage Vdata is loaded to the first node N1, and the threshold compensation and data write of the third node N3 are realized (see FIG. 36).

[0215] In the third reset stage P4: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, the second emitting signal EM2 is low level, and the third emitting signal EM3 is low level. At this time, the first reset transistor T11, the node control transistor T8, the shared control transistor T9, and the privacy control transistor T10 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first emitting transistor T5, and the second emitting transistor T6 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4 through the first reset transistor T11 and the shared control transistor T9, and the first pole of the privacy control transistor T10 is reset; and the reset voltage Vref is loaded to the second node N2 through the node control transistor T8, and the first pole of the driving transistor T3 is reset (see FIG. 37).

[0216] In the light emitting stage P5: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first emitting signal EM1 is low level, the second emitting signal EM2 is low level, and the third emitting signal EM3 is high level. At this time, the first emitting transistor T5, the second emitting transistor T6, the shared control transistor T9, and the driving transistor T3 are turned on; the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first reset transistor T11, the node control transistor T8, the shared control transistor T9, and the privacy control transistor T10 are turned off, and the shared light emitting element GLD is turned on (see FIG. 38).

[0217] When the display panel is in the sharing mode and is in the low-frequency refresh stage A2:

[0218] In the first reset stage P1 to the light emitting stage P5, the first reset signal PReset always loads the first power voltage VGH, the first scan signal NGate always loads the second power voltage VGL, and the second scan signal PGate always loads the first power voltage VGH. The pixel circuit does not perform new data writing, so that the low-frequency refresh of the pixel driving circuit PDC can be realized.

[0219] In another example of the embodiment, referring to FIG. 39, the driving unit IU includes a second reset unit M7, a first end of the second reset unit M7 is configured to load a second initialization voltage Vinit2, and a second end of the second reset unit M7 is electrically connected with the output end of the driving unit IU; the second reset unit M7 is configured to load the second initialization voltage Vinit2 to the output end of the driving unit IU in response to a second reset signal PResetH. In this way, the second initialization voltage Vinit2 can be loaded to the output end of the driving unit IU by loading the second reset signal PResetH to the second reset unit M7.

[0220] The pixel driving circuit PDC is further described below by an equivalent circuit diagram (see FIG. 39) of the pixel driving circuit PDC:

[0221] The first pole of the gate reset transistor T1 is electrically connected with the first initialization voltage Vinit1, the second pole of the gate reset transistor T1 is electrically connected with the second pole of the driving transistor T3, the first pole of the second light-emitting transistor T6, the first pole of the threshold compensation transistor T2, and the third node N3, the control pole of the gate reset transistor T1 is electrically connected with the first reset signal PReset, and the gate reset transistor T1 is configured to load the first initialization voltage Vinit1 to the third node N3 in response to the on level of the first reset signal PReset.

[0222] The second pole of the threshold compensation transistor T2 is electrically connected with the first node N1, the first electrode plate of the storage capacitor CST, and the control pole of the driving transistor T3; the control pole of the threshold compensation transistor T2 is electrically connected with the first scanning signal NGate, and the threshold compensation transistor T2 is configured to load the signal of the third node N3 to the first node N1 in response to the on level of the first scanning signal NGate.

[0223] The first pole of the driving transistor T3 is electrically connected with the second node N2, the second pole of the driving transistor T3 is electrically connected with the third node N3, and the control pole of the driving transistor T3 is electrically connected with the first node N1; the driving transistor T3 is configured to load the signal of the second node N2 to the third node N3 in response to the on level of the first node N1.

[0224] The first pole of the data writing transistor T4 is electrically connected with the data voltage Vdata, the second pole of the data writing transistor T4 is electrically connected with the first pole of the driving transistor T3 and the second node N2, the control pole of the data writing transistor T4 is electrically connected with the second scanning signal PGate, and the data writing transistor T4 is configured to write the data voltage Vdata to the second node N2 in response to the on level of the second scanning signal PGate.

[0225] The first electrode of the first light-emitting transistor T5 is electrically connected to the power supply voltage terminal, the second electrode of the first light-emitting transistor T5 is electrically connected to the second node N2, and the control electrode of the first light-emitting transistor T5 is electrically connected to the first light-emitting signal EM1. The first light-emitting transistor T5 is configured to load the power supply voltage to the second node N2 in response to the on signal of the first light-emitting signal EM1.

[0226] In the pixel driving circuit PDC, the switch unit M6 includes a second light-emitting transistor T6. The first electrode of the second light-emitting transistor T6 is electrically connected to the third node N3, the second electrode of the second light-emitting transistor T6 is electrically connected to the fourth node N4, and the control electrode of the second light-emitting transistor T6 is electrically connected to the first light-emitting signal EM1. The second light-emitting transistor T6 is configured to load the signal of the third node N3 to the fourth node N4 in response to the on level of the first light-emitting signal EM1.

[0227] In the pixel driving circuit PDC, the second reset unit M7 can include a second reset transistor T7. The first electrode of the second reset transistor T7 is electrically connected to the second initialization voltage Vinit2, the second electrode of the second reset transistor T7 is electrically connected to the fourth node N4, and the control electrode of the second reset transistor T7 is electrically connected to the second reset signal PResetH. The second reset transistor T7 is configured to load the second initialization voltage Vinit2 to the fourth node N4 in response to the on level of the second reset signal PResetH.

[0228] The first electrode of the node control transistor T8 is electrically connected to the reset voltage Vref, the second electrode of the node control transistor T8 is electrically connected to the second node N2, and the control electrode of the node control transistor T8 is electrically connected to the second reset signal PResetH. The node control transistor T8 is configured to load the reset voltage Vref to the second node N2 in response to the on level of the second reset signal PResetH.

[0229] In the pixel driving circuit PDC, the first control unit M9 includes a shared control transistor T9. The first electrode of the shared control transistor T9 is electrically connected to the fourth node N4, the second electrode of the shared control transistor T9 is electrically connected to the fifth node N5, and the control electrode of the shared control transistor T9 is electrically connected to the second light-emitting signal EM2. The shared control transistor T9 is configured to load the signal of the fourth node N4 to the fifth node N5 in response to the on level of the second light-emitting signal EM2.

[0230] In the pixel driving circuit PDC, the second control unit M10 includes a privacy control transistor T10. The first electrode of the privacy control transistor T10 is electrically connected with the fourth node N4 and the second electrode of the shared control transistor T9, the second electrode of the privacy control transistor T10 is electrically connected with the sixth node N6 and the privacy light emitting element FLD, the control electrode of the privacy control transistor T10 is electrically connected with the third emission signal EM3, and the privacy control transistor T10 is configured to load the signal of the fourth node N4 to the sixth node N6 in response to the on level of the third emission signal EM3.

[0231] The first electrode of the privacy light emitting element FLD is electrically connected with the second electrode of the privacy control transistor T10, and the second electrode is electrically connected with a reference voltage.

[0232] It can be understood that, in the pixel driving circuit PDC, the privacy control transistor T10 is provided to control the privacy light emitting element FLD, and therefore the switching unit M6 can be provided in the pixel driving circuit PDC, or can not be provided.

[0233] In this embodiment, the gate reset transistor T1, the driving transistor T3, the data writing transistor T4, the first emission transistor T5, the second emission transistor T6, the second reset transistor T7, the node control transistor T8, the shared control transistor T9, and the privacy control transistor T10 are P-type transistors, and the threshold compensation transistor T2 is an N-type transistor.

[0234] It can be understood that the on level refers to an output level capable of turning on the corresponding transistor. For example, when the transistor is a P-type transistor, the on level is a low level; and when the transistor is an N-type transistor, the on level is a high level.

[0235] The pixel driving circuit PDC is further described below by means of a timing diagram (see FIG. 40) of the pixel driving circuit PDC:

[0236] When the pixel driving circuit PDC is in the privacy mode and the pixel driving circuit PDC is in the high-frequency refresh stage:

[0237] In the first reset stage P1: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first light emitting signal EM1 is high level, the second light emitting signal EM2 is low level, and the third light emitting signal EM3 is high level. At this time, the second reset transistor T7, the node control transistor T8, and the shared control transistor T9 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first light emitting transistor T5, the second light emitting transistor T6, and the anti-peep control transistor T10 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4 through the second reset transistor T7 and the shared control transistor T9, and the reset of the anode of the anti-peep light emitting element FLD is realized; and the reset voltage Vref is loaded to the second node N2 through the node control transistor T8, and the first electrode of the driving transistor T3 is reset (see FIG. 41).

[0238] In the second reset stage P2: the second reset signal PResetH is high level, the first reset signal PReset is low level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first light emitting signal EM1 is high level, the second light emitting signal EM2 is high level, and the third light emitting signal EM3 is high level. At this time, the gate reset transistor T1 and the threshold compensation transistor T2 are turned on, and the data write transistor T4, the first light emitting transistor T5, the second light emitting transistor T6, the second reset transistor T7, the node control transistor T8, the shared control transistor T9, and the anti-peep control transistor T10 are turned off, so that the first initialization voltage Vinit1 is loaded to the first node N1 and the first electrode plate of the storage capacitor CST, and the storage capacitor CST is charged (see FIG. 42).

[0239] In the data write stage P3: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is low level, the first light emitting signal EM1 is high level, and the second light emitting signal EM2 is high level. At this time, the threshold compensation transistor T2 and the data write transistor T4 are turned on, and the gate reset transistor T1, the first light emitting transistor T5, the second light emitting transistor T6, the second reset transistor T7, the node control transistor T8, the shared control transistor T9, and the anti-peep control transistor T10 are turned off, so that the data voltage Vdata is loaded to the first node N1, and the threshold compensation and data write of the third node N3 are realized (see FIG. 43).

[0240] In the third reset stage P4: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, the second emitting signal EM2 is low level, and the third emitting signal EM3 is low level. At this time, the second reset transistor T7 and the shared control transistor T9 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first emitting transistor T5, the second emitting transistor T6, and the anti-peep control transistor T10 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4, and the reset of the anode of the anti-peep light emitting element FLD is realized (see FIG. 44).

[0241] In the light emitting stage P5: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first emitting signal EM1 is low level, the second emitting signal EM2 is high level, and the third emitting signal EM3 is low level. At this time, the first emitting transistor T5, the second emitting transistor T6, the driving transistor T3, and the anti-peep control transistor T10 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the second reset transistor T7, the node control transistor T8, and the shared control transistor T9 are turned off, so that the anti-peep light emitting element FLD is turned on (see FIG. 45).

[0242] When the pixel driving circuit PDC is in the anti-peep mode and the pixel driving circuit PDC is in the low-frequency refresh stage A2.

[0243] In the first reset stage P1 to the light emitting stage P5, the first reset signal PReset always loads the first power voltage VGH, the first scan signal NGate always loads the second power voltage VGL, and the second scan signal PGate always loads the first power voltage VGH. The pixel circuit does not perform new data writing, so that the low-frequency refresh of the pixel driving circuit PDC can be realized.

[0244] When the pixel driving circuit PDC is in the shared mode and the pixel driving circuit PDC is in the high-frequency refresh stage A1:

[0245] In the first reset stage P1: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, the second emitting signal EM2 is low level, and the third emitting signal EM3 is low level. At this time, the second reset transistor T7, the node control transistor T8, the shared control transistor T9 and the anti-peep control transistor T10 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first emitting transistor T5 and the second emitting transistor T6 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4 through the second reset transistor T7 and the shared control transistor T9, and the first pole of the anti-peep control transistor T10 is reset; and the reset voltage Vref is loaded to the second node N2 through the node control transistor T8, and the first pole of the driving transistor T3 is reset (see FIG. 46).

[0246] In the second reset stage P2: the second reset signal PResetH is high level, the first reset signal PReset is low level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, the second emitting signal EM2 is high level, and the third emitting signal EM3 is high level. At this time, the gate reset transistor T1 and the threshold compensation transistor T2 are turned on, and the data write transistor T4, the first emitting transistor T5, the second emitting transistor T6, the second reset transistor T7, the node control transistor T8, the shared control transistor T9 and the anti-peep control transistor T10 are turned off, so that the first initialization voltage Vinit1 is loaded to the first node N1 and the first electrode plate of the storage capacitor CST, and the storage capacitor CST is charged (see FIG. 47).

[0247] In the data write stage P3: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is low level, the first emitting signal EM1 is high level, the second emitting signal EM2 is low level, and the third emitting signal EM3 is high level. At this time, the threshold compensation transistor T2 and the data write transistor T4 are turned on, and the gate reset transistor T1, the first emitting transistor T5, the second emitting transistor T6, the second reset transistor T7, the node control transistor T8, the shared control transistor T9 and the anti-peep control transistor T10 are turned off, so that the data voltage Vdata is loaded to the first node N1, and the threshold compensation and data write of the third node N3 are realized (see FIG. 48).

[0248] In the third reset stage P4: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, the second emitting signal EM2 is low level, and the third emitting signal EM3 is low level. At this time, the second reset transistor T7, the node control transistor T8, the shared control transistor T9, and the anti-peep control transistor T10 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first emitting transistor T5, and the second emitting transistor T6 are turned off, so that the second initialization voltage Vinit2 is loaded to the fourth node N4 through the second reset transistor T7 and the shared control transistor T9, and the first pole of the anti-peep control transistor T10 is reset; and the reset voltage Vref is loaded to the second node N2 through the node control transistor T8, and the first pole of the driving transistor T3 is reset (see FIG. 49).

[0249] In the light emitting stage P5: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first emitting signal EM1 is low level, the second emitting signal EM2 is low level, and the third emitting signal EM3 is high level. At this time, the first emitting transistor T5, the second emitting transistor T6, the driving transistor T3, and the shared control transistor T9 are turned on; the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the second reset transistor T7, the node control transistor T8, the shared control transistor T9, and the anti-peep control transistor T10 are turned off, and the shared light emitting element GLD is turned on (see FIG. 50).

[0250] When the pixel driving circuit PDC is in the shared mode and the pixel driving circuit PDC is in the low-frequency refresh stage A2:

[0251] In the first reset stage P1 to the light emitting stage P5, the first reset signal PReset always loads the first power voltage VGH, the first scan signal NGate always loads the second power voltage VGL, and the second scan signal PGate always loads the first power voltage VGH. The pixel circuit does not perform new data writing, so that the low-frequency refresh of the pixel driving circuit PDC can be realized.

[0252] In another example of the embodiment, referring to FIG. 51, the shared light emitting unit GU further comprises a first reset unit M11, a first end of the first reset unit M11 is configured to load the second initialization voltage Vinit2, a second end of the first reset unit M11 is electrically connected with the second end of the first control unit M9, the first reset unit M11 is configured to load the second initialization voltage Vinit2 to the second end of the first control unit M9 in response to the second reset signal PResetH. The privacy light emitting unit FU further comprises a third reset unit M12, a first end of the third reset unit M12 is configured to load the second initialization voltage Vinit2, a second end of the third reset unit M12 is electrically connected with the second end of the second control unit M10, the third reset unit M12 is configured to load the second initialization voltage Vinit2 to the second end of the second control unit M10 in response to the second reset signal PResetH. In this way, the reset of the anode of the shared light emitting element GLD can be achieved by loading the second reset signal PResetH to the first reset unit M11 to load the second initialization voltage Vinit2 to the anode of the shared light emitting element GLD, and the reset of the anode of the privacy light emitting element FLD can be achieved by loading the second reset signal PResetH to the third reset unit M12 to load the second initialization voltage Vinit2 to the anode of the privacy light emitting element FLD.

[0253] The pixel driving circuit PDC is further described below by an equivalent circuit diagram (see FIG. 51) of the pixel driving circuit PDC:

[0254] A first pole of the gate reset transistor T1 is electrically connected with the first initialization voltage Vinit1, a second pole of the gate reset transistor T1 is electrically connected with a second pole of the driving transistor T3, a first pole of the second light emitting transistor T6, a first pole of the threshold compensation transistor T2 and the third node N3, a control pole of the gate reset transistor T1 is electrically connected with the first reset signal PReset, the gate reset transistor T1 is configured to load the first initialization voltage Vinit1 to the third node N3 in response to a conduction level of the first reset signal PReset.

[0255] A second pole of the threshold compensation transistor T2 is electrically connected with the first node N1, a first electrode plate of the storage capacitor CST and a control pole of the driving transistor T3, a control pole of the threshold compensation transistor T2 is electrically connected with the first scan signal NGate, the threshold compensation transistor T2 is configured to load a signal of the third node N3 to the first node N1 in response to a conduction level of the first scan signal NGate.

[0256] A first electrode of the drive transistor T3 is electrically connected to the second node N2, a second electrode of the drive transistor T3 is electrically connected to the third node N3, a control electrode of the drive transistor T3 is electrically connected to the first node N1, and the drive transistor T3 is configured to load a signal of the second node N2 to the third node N3 in response to a turn-on level of the first node N1.

[0257] A first electrode of the data write transistor T4 is electrically connected to the data voltage Vdata, a second electrode of the data write transistor T4 is electrically connected to the first electrode of the drive transistor T3 and the second node N2, a control electrode of the data write transistor T4 is electrically connected to the second scan signal PGate, and the data write transistor T4 is configured to write the data voltage Vdata to the second node N2 in response to a turn-on level of the second scan signal PGate.

[0258] A first electrode of the first light emitting transistor T5 is electrically connected to the power supply voltage terminal, a first electrode of the first light emitting transistor T5 is electrically connected to the second node N2, a control electrode of the first light emitting transistor T5 is electrically connected to the first emission signal EM1, and the first light emitting transistor T5 is configured to load the power supply voltage to the second node N2 in response to a turn-on signal of the first emission signal EM1.

[0259] In the pixel driving circuit PDC, the switch unit M6 includes a second light emitting transistor; wherein a first electrode of the second light emitting transistor T6 is electrically connected to the third node N3, a second electrode of the second light emitting transistor T6 is electrically connected to the fourth node N4, a control electrode of the second light emitting transistor T6 is electrically connected to the second emission signal EM2, and the second light emitting transistor T6 is configured to load a signal of the third node N3 to the fourth node N4 in response to a turn-on level of the second emission signal EM2.

[0260] In the pixel driving circuit, the third reset unit M12 includes a third reset transistor T12, wherein a first electrode of the third reset transistor T12 is electrically connected to the second initialization voltage Vinit2, a second electrode of the third reset transistor T12 is electrically connected to the fifth node N5 and the shared light emitting element GLD, a control electrode of the third reset transistor T12 is electrically connected to the second reset signal PResetH, and the third reset transistor T12 is configured to load the second initialization voltage Vinit2 to the fifth node N5 in response to a turn-on level.

[0261] A first electrode of the node control transistor T8 is electrically connected to the reset voltage Vref, a second electrode of the node control transistor T8 is electrically connected to the second node N2, a control electrode of the node control transistor T8 is electrically connected to the second reset signal PResetH, and the node control transistor T8 is configured to load the reset voltage Vref to the second node N2 in response to a turn-on level of the second reset signal PResetH.

[0262] In the pixel driving circuit PDC, the first control unit M9 comprises a shared control transistor T9. Wherein, the first electrode of the shared control transistor T9 is electrically connected with the first electrode of the second light emitting transistor T6, the second electrode of the shared control transistor T9 is electrically connected with the fifth node N5, the control electrode of the shared control transistor T9 is electrically connected with the third light emitting signal EM3, and the shared control transistor T9 is configured to load the signal of the first electrode of the second light emitting transistor T6 to the fifth node N5 in response to the on level of the third light emitting signal EM3.

[0263] In the pixel driving circuit PDC, the second control unit M10 comprises an anti-peep control transistor T10. Wherein, the first electrode of the anti-peep control transistor T10 is electrically connected with the second initialization voltage Vinit2, the second electrode of the anti-peep control transistor T10 is electrically connected with the fifth node N5, the second electrode of the shared control transistor T9 and the shared light emitting element GLD, the control electrode of the anti-peep control transistor T10 is electrically connected with the second reset signal PResetH, and the anti-peep control transistor T10 is configured to load the signal of the second initialization voltage Vinit2 to the fifth node N5 in response to the on level of the second reset signal PResetH.

[0264] The first electrode of the anti-peep light emitting element FLD is electrically connected with the fourth node N4, and the second electrode is electrically connected with the reference voltage.

[0265] The pixel driving circuit PDC is further introduced by the timing diagram (see FIG. 52) of the pixel driving circuit PDC as follows:

[0266] When the pixel driving circuit PDC is in the anti-peep mode and the pixel driving circuit PDC is in the high frequency refresh stage A1:

[0267] In the first reset stage P1: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, the second emitting signal EM2 is high level, and the third emitting signal EM3 is high level. At this time, the third reset transistor T12, the node control transistor T8 and the first reset transistor T11 are turned on, the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first emitting transistor T5, the second emitting transistor T6, the shared control transistor T9 are turned off, so that the reset voltage Vref is loaded to the second node N2, the reset of the first electrode of the driving transistor T3 is realized, the second initialization voltage Vinit2 is loaded to the fourth node N4 through the third reset transistor T12, the reset of the fourth node N4 is realized, and the second initialization voltage Vinit2 is loaded to the fifth node N5 through the first reset transistor T11, and the reset of the fifth node N5 is realized (see FIG. 53).

[0268] In the second reset stage P2: the second reset signal PResetH is high level, the first reset signal PReset is low level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, the second emitting signal EM2 is high level, and the third emitting signal EM3 is loaded with the first power voltage VGH. At this time, the gate reset transistor T1 and the threshold compensation transistor T2 are turned on, the data write transistor T4, the first emitting transistor T5, the second emitting transistor T6, the third reset transistor T12, the node control transistor T8, the shared control transistor T9, the first reset transistor T11 are turned off, so that the first initialization voltage Vinit1 is loaded to the first node N1 and the first electrode plate of the storage capacitor CST, and the charging of the storage capacitor CST is realized (see FIG. 54).

[0269] In the data write stage P3: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is low level, the first emitting signal EM1 is high level, the second emitting signal EM2 is high level, and the third emitting signal EM3 is loaded with the first power voltage VGH. At this time, the threshold compensation transistor T2 and the data write transistor T4 are turned on, the gate reset transistor T1, the first emitting transistor T5, the second emitting transistor T6, the third reset transistor T12, the node control transistor T8, the shared control transistor T9, the first reset transistor T11 are turned off, so that the data voltage Vdata is loaded to the first node N1, the threshold compensation and the data write of the third node N3 are realized (see FIG. 55).

[0270] In the third reset stage P4: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first emitting signal EM1 is high level, the second emitting signal EM2 is high level, and the third emitting signal EM3 is high level. At this time, the third reset transistor T12, the node control transistor T8 and the first reset transistor T11 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data write transistor T4, the first emitting transistor T5, the second emitting transistor T6 and the shared control transistor T9 are turned off, so that the reset voltage Vref is loaded to the second node N2, the reset of the first pole of the driving transistor T3 is realized, the second initialization voltage Vinit2 is loaded to the fourth node N4 through the third reset transistor T12, the reset of the fourth node N4 is realized, and the second initialization voltage Vinit2 is loaded to the fifth node N5 through the first reset transistor T11, and the reset of the fifth node N5 is realized (see FIG. 56).

[0271] In the light emitting stage P5: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first emitting signal EM1 is low level, the second emitting signal EM2 is low level, and the third emitting signal EM3 is loaded with the first power voltage VGH. At this time, the first emitting transistor T5 and the second emitting transistor T6 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the third reset transistor T12, the node control transistor T8, the shared control transistor T9 and the first reset transistor T11 are turned off, so that the anti-peep light emitting element FLD is turned on (see FIG. 57).

[0272] When the display panel is in the anti-peep mode and is in the low-frequency refresh stage A2.

[0273] In the first reset stage P1 to the light emitting stage P5, the first reset signal PReset is always loaded with the first power voltage VGH, the first scan signal NGate is always loaded with the second power voltage VGL, and the second scan signal PGate is always loaded with the first power voltage VGH. The pixel circuit does not perform new data writing, so that the low-frequency refresh of the pixel driving circuit PDC can be realized.

[0274] When the pixel driving circuit PDC is in the shared mode and the pixel driving circuit PDC is in the high-frequency refresh stage:

[0275] In the first reset stage P1: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first light emitting signal EM1 is high level, the second light emitting signal EM2 is loaded with the first power voltage VGH, and the third light emitting signal EM3 is high level. At this time, the third reset transistor T12, the node control transistor T8, and the first reset transistor T11 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first light emitting transistor T5, the second light emitting transistor T6, and the shared control transistor T9 are turned off, so that the second initialization voltage Vinit2 is loaded to the fifth node N5 through the first reset transistor T11, the reset of the anode of the shared light emitting element GLD is realized; the reset voltage Vref is loaded to the second node N2 through the node control transistor T8, the reset of the first pole of the driving transistor T3 is realized; and the second initialization voltage Vinit2 is loaded to the fourth node N4 through the third reset transistor T12, the reset of the anti-peep light emitting element FLD is realized (see FIG. 58).

[0276] In the second reset stage P2: the second reset signal PResetH is high level, the first reset signal PReset is low level, the first scan signal NGate is high level, the second scan signal PGate is high level, the first light emitting signal EM1 is high level, the second light emitting signal EM2 is loaded with the first power voltage VGH, and the third light emitting signal EM3 is high level. At this time, the gate reset transistor T1 and the threshold compensation transistor T2 are turned on; the data write transistor T4, the first light emitting transistor T5, the second light emitting transistor T6, the third reset transistor T12, the node control transistor T8, the shared control transistor T9, and the first reset transistor T11 are turned off, so that the first initialization voltage Vinit1 is loaded to the first node N1 and the first electrode plate of the storage capacitor CST, and the charging of the storage capacitor CST is realized (see FIG. 59).

[0277] In the data write stage P3: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is high level, the second scan signal PGate is low level, the first light emitting signal EM1 is high level, the second light emitting signal EM2 is loaded with the first power voltage VGH, and the third light emitting signal EM3 is high level. At this time, the threshold compensation transistor T2 and the data write transistor T4 are turned on, and the gate reset transistor T1, the first light emitting transistor T5, the second light emitting transistor T6, the third reset transistor T12, the node control transistor T8, the shared control transistor T9, and the first reset transistor T11 are turned off, so that the data voltage Vdata is loaded to the first node N1, and the threshold compensation and data write of the third node N3 are realized (see FIG. 60).

[0278] In the third reset stage P4: the second reset signal PResetH is low level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first light emitting signal EM1 is high level, the second light emitting signal EM2 is loaded with the first power voltage VGH, and the third light emitting signal EM3 is high level. At this time, the third reset transistor T12, the node control transistor T8, and the first reset transistor T11 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the first light emitting transistor T5, the second light emitting transistor T6, and the shared control transistor T9 are turned off, so that the second initialization voltage Vinit2 is loaded to the fifth node N5 through the first reset transistor T11, the reset of the anode of the shared light emitting element GLD is realized; the reset voltage Vref is loaded to the second node N2 through the node control transistor T8, the reset of the first pole of the driving transistor T3 is realized; and the second initialization voltage Vinit2 is loaded to the fourth node N4 through the third reset transistor T12, the reset of the privacy light emitting element FLD is realized (see FIG. 61).

[0279] In the light emitting stage P5: the second reset signal PResetH is high level, the first reset signal PReset is high level, the first scan signal NGate is low level, the second scan signal PGate is high level, the first light emitting signal EM1 is low level, the second light emitting signal EM2 is loaded with the first power voltage VGH, and the third light emitting signal EM3 is loaded with low level. At this time, the first light emitting transistor T5, the second light emitting transistor T6, the driving transistor T3, and the shared control transistor T9 are turned on, and the gate reset transistor T1, the threshold compensation transistor T2, the data write transistor T4, the second light emitting transistor T6, the third reset transistor T12, the node control transistor T8, and the first reset transistor T11 are turned off. In this way, the privacy light emitting element FLD is turned off, and the shared light emitting element GLD is turned on (see FIG. 62).

[0280] When the display panel is in the shared mode and in the low-frequency refresh stage A2:

[0281] In the first reset stage P1 to the light emitting stage P5, the first reset signal PReset is always loaded with the first power voltage VGH, the first scan signal NGate is always loaded with the second power voltage VGL, and the second scan signal PGate is always loaded with the first power voltage VGH. The pixel circuit does not perform new data writing, so that the low-frequency refresh of the pixel driving circuit PDC can be realized.

[0282] In some embodiments of the present disclosure, the driving unit IU includes a driving transistor T3, the driving transistor T3 is configured to generate a driving current according to a voltage on a gate thereof, and a second pole of the driving transistor T3 is electrically connected with an output end of the driving unit IU.

[0283] In some embodiments of the present disclosure, the driving unit IU comprises a driving transistor T3 and a switch unit M6; the driving transistor T3 is configured to generate a driving current according to a voltage on its gate; a first end of the switch unit M6 is electrically connected to the second electrode of the driving transistor T3, and a second end of the switch unit M6 is electrically connected to the output end of the driving unit IU; the switch unit M6 is configured to electrically connect the second electrode of the driving transistor T3 and the output end of the driving unit IU in response to the first light-emitting signal EM1.

[0284] It can be understood that, in a pixel driving circuit PDC, for example, the pixel driving circuit PDC is used for a mobile phone display panel, since the second control unit M10 for controlling the opening and closing of the anti-peep light-emitting element FLD is not arranged in the pixel driving circuit PDC, the switch unit M6 must be arranged in the pixel driving circuit PDC, so that the switch unit M6 can electrically connect the second electrode of the driving transistor T3 and the output end of the driving unit IU in response to the light-emitting signal, thereby controlling the opening or closing of the anti-peep light-emitting element FLD. In another pixel driving circuit PDC, for example, the pixel driving circuit PDC is used for a notebook display panel, the second control unit M10 for controlling the anti-peep light-emitting element FLD is arranged in the anti-peep light-emitting unit FU, and the first control unit M9 for controlling the shared light-emitting element GLD is arranged in the shared light-emitting unit GU, so the switch unit M6 can not be arranged in the pixel driving circuit PDC, of course, the switch unit M6 can also be arranged.

[0285] Further, when only one of the driving unit IU, the anti-peep light-emitting unit FU, and the shared light-emitting unit GU is provided with a reset unit (for example, the third reset unit M12 for resetting the anode of the anti-peep light-emitting unit FU, the first reset unit M11 for resetting the anode of the shared light-emitting unit GU, or the second reset unit M7 for resetting the driving unit IU) for anode reset, the reset unit can be arranged in one of the driving unit IU, the anti-peep light-emitting unit FU, and the shared light-emitting unit GU.

[0286] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the aspects disclosed herein. It is intended that the present disclosure cover any and all variations of the present disclosure including combinations of the features of the present disclosure falling within the general scope of the disclosure. The specification and examples are illustrative only and not restrictive of the present disclosure. The true scope and spirit of the present disclosure is indicated by the appended claims.

Claims

1. A pixel driving circuit, wherein, The display device comprises a driving unit, a shared light-emitting unit and a privacy light-emitting unit; an output terminal of the driving unit is electrically connected with an input terminal of the shared light-emitting unit and an input terminal of the privacy light-emitting unit; the driving unit is configured to generate a driving signal; the privacy light-emitting unit comprises a privacy light-emitting element and is configured to make the privacy light-emitting element emit light under the driving of the driving signal at least in a privacy mode; the shared light-emitting unit comprises a shared light-emitting element and is configured to make the shared light-emitting element emit light under the driving of the driving signal in a shared mode.

2. The pixel driving circuit according to claim 1, wherein a first pole of the privacy light-emitting element is electrically connected with the output terminal of the driving unit, and a second pole of the privacy light-emitting element is configured to load a reference voltage.

3. The pixel driving circuit of claim 2, wherein, The shared light-emitting unit further comprises a first control unit and a first reset unit; a second terminal of the first control unit is electrically connected with a second terminal of the first reset unit and a first pole of the shared light-emitting element, and a first terminal of the first control unit is electrically connected with the output terminal of the driving unit; the first reset unit is configured to load a second initialization voltage; and a second pole of the shared light-emitting element is configured to load the reference voltage. The first control unit is configured to make the output terminal of the driving unit and the first pole of the shared light-emitting element conductive in response to a second light-emitting signal; and the first reset unit is configured to load the second initialization voltage to the first pole of the shared light-emitting element in response to a second reset signal.

4. The pixel driving circuit of claim 2, wherein, The driving unit comprises a second reset unit, a first terminal of the second reset unit is configured to load the second initialization voltage, and a second terminal of the second reset unit is electrically connected with the output terminal of the driving unit; the second reset unit is configured to load the second initialization voltage to the output terminal of the driving unit in response to a second reset signal.

5. The pixel driving circuit of claim 1, wherein, The shared light-emitting unit further comprises a first control unit, a second terminal of the first control unit is electrically connected with the first pole of the shared light-emitting element; a first terminal of the first control unit is electrically connected with the output terminal of the driving unit; the first control unit is configured to make the output terminal of the driving unit and the first pole of the shared light-emitting element conductive in response to a second light-emitting signal; and a second pole of the shared light-emitting element is configured to load the reference voltage. The privacy light-emitting unit further comprises a second control unit; a second terminal of the second control unit is electrically connected with the output terminal of the driving unit, a first terminal of the second control unit is electrically connected with the first pole of the privacy light-emitting element, the second control unit is configured to make the output terminal of the driving unit and the first pole of the privacy light-emitting element conductive in response to a third light-emitting signal, and a second pole of the privacy light-emitting element is configured to load the reference voltage.

6. The pixel driving circuit of claim 5, wherein, The shared light-emitting unit further comprises a first reset unit. a first terminal of the first reset unit is configured to load the second initialization voltage, and a second terminal of the first reset unit is electrically connected with the second terminal of the first control unit; the first reset unit is configured to load the second initialization voltage to the second terminal of the first control unit in response to a second reset signal.

7. The pixel driving circuit of claim 5, wherein, The driving unit comprises a second reset unit, a first end of the second reset unit is used for loading a second initialization voltage, and a second end of the second reset unit is electrically connected with an output end of the driving unit; the second reset unit is used for loading the second initialization voltage to the output end of the driving unit in response to a second reset signal.

8. The pixel driving circuit of claim 5, wherein, The shared light-emitting unit further comprises a first reset unit; a first end of the first reset unit is used for loading a second initialization voltage; a second end of the first reset unit is electrically connected with the second end of the first control unit; the first reset unit is used for loading the second initialization voltage to the second end of the first control unit in response to a second reset signal. The privacy light-emitting unit further comprises a third reset unit, a first end of the third reset unit is used for loading a second initialization voltage; a second end of the third reset unit is electrically connected with the second end of the second control unit, and the third reset unit is used for loading the second initialization voltage to the second end of the second control unit in response to a second reset signal.

9. The pixel driving circuit of claim 8, wherein, The driving unit comprises a driving transistor; the driving transistor is used for generating a driving current as the driving signal according to a voltage on a gate of the driving transistor; a second electrode of the driving transistor is electrically connected with an output end of the driving unit.

10. The pixel driving circuit according to any one of claims 2 to 4, 6 and 7, wherein The driving unit comprises a driving transistor and a switch unit; the driving transistor is used for generating a driving current as the driving signal according to a voltage on a gate of the driving transistor; a first end of the switch unit is electrically connected with a second electrode of the driving transistor, and a second end of the switch unit is electrically connected with an output end of the driving unit; the switch unit is used for electrically connecting the second electrode of the driving transistor with the output end of the driving unit in response to a first light-emitting signal.

11. A display panel comprising the pixel driving circuit according to any one of claims 1 to 10.

12. The display panel of claim 11, wherein, The display panel comprises a pixel layer and an angle limiting layer which are arranged in a stack; the privacy light-emitting element and the shared light-emitting element are arranged on the pixel layer; The angle limiting layer is arranged on a light-emitting side of the pixel layer, and the angle limiting layer has a first angle limiting structure corresponding to the shared light-emitting element and a second angle limiting structure corresponding to the privacy light-emitting element; light emitted by the shared light-emitting element is emitted to outside of the display panel through the first angle limiting structure, and light emitted by the privacy light-emitting element is emitted to outside of the display panel through the second angle limiting structure; The first angle limiting structure makes a maximum light-emitting angle of the shared light-emitting element be a first light-emitting angle; the second angle limiting structure makes a maximum light-emitting angle of the privacy light-emitting element be a second light-emitting angle; the first light-emitting angle is greater than the second light-emitting angle.

13. The display panel of claim 11, wherein, The display panel is applied to a mobile intelligent terminal; and the display panel comprises the pixel driving circuit according to any one of claims 2 to 4.

14. The display panel of claim 11, wherein, The display panel is applied to a desktop display screen, a notebook display screen or a tablet computer; and the display panel comprises the pixel driving circuit according to claims 5 to 9.

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