Display substrate and display apparatus

Abstract

Provided in the embodiments of the present disclosure are a display substrate and a display apparatus. The display substrate comprises: a plurality of sub-pixels, a plurality of data lines and a plurality of first signal lines, which are located in a display area; first signal provision line groups, which are electrically connected to the first signal lines, are located in first-type frame areas and extend to a binding area in a first frame area; and at least one first signal pin group and at least one integrated circuit pin group, which are located in the binding area, wherein in a first direction, the at least one first signal pin group is located on at least one side of the at least one integrated circuit pin group, each first signal pin group and a corresponding first signal provision line group are located on the same side of the at least one integrated circuit pin group, and first signal pins in the first signal pin group are configured to be electrically connected to first signal provision lines in the corresponding first signal provision line group.

Description

Display substrate and display device

[0001] The present application claims priority to the Chinese patent application No. 202411376292.9, filed on September 29, 2024, and entitled "Display substrate and display device", the contents of which are to be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of the present disclosure provide a display substrate, comprising:

[0006] a substrate comprising a display area, a first frame area and a first type of frame area; in a first direction, the first type of frame area is located on at least one side of the display area; in a second direction, the first frame area is located on one side of the display area, the first frame area is provided with a binding area, and the first direction intersects the second direction;

[0007] a plurality of sub-pixels located in the display area;

[0008] a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of data lines extend along the second direction and are arranged at intervals along the first direction;

[0009] a plurality of first signal lines located in the display area and extending along the first direction and arranged along the second direction, the plurality of first signal lines are electrically connected to the plurality of sub-pixels;

[0010] At least one first signal providing line group is located in the first type of border area and extends to the binding area in the first border area, wherein the first signal providing line in the first signal providing line group is configured to be electrically connected to at least one of the plurality of first signal lines;

[0011] A plurality of bonded pin groups and at least one integrated circuit pin group are located in the bonded area. The plurality of bonded pin groups include at least one first signal pin group. At least a portion of the integrated circuit pins in the integrated circuit pin group are configured to be electrically connected to the plurality of data lines. In the first direction, the at least one first signal pin group is located on at least one side of the at least one integrated circuit pin group. The at least one first signal pin group corresponds one-to-one with the at least one first signal providing line group. The at least one first signal pin group and the corresponding first signal providing line group are located on the same side of the at least one integrated circuit pin group. At least a portion of the first signal pins in the at least one first signal group are configured to be electrically connected to at least a portion of the first signal providing line in the corresponding first signal providing line group.

[0012] In an exemplary embodiment, in the second direction, the plurality of bonding pin groups are located on the side of the integrated circuit pin group away from the display area;

[0013] The plurality of bonded pin groups further includes at least one drive pin group and at least one power pin group, wherein the at least one drive pin group corresponds one-to-one with the at least one integrated circuit pin group and is electrically connected to the corresponding integrated circuit pin group; in the first direction, at least one power pin group is provided between the at least one first signal pin group and the at least one drive pin group.

[0014] In an exemplary embodiment, the first type of bezel area is further provided with a plurality of gate drive circuit signal lines, which extend to the first bezel area. In the same first type of bezel area, in the first direction, the first signal providing line group is located on the side of the plurality of gate drive circuit signal lines away from the display area.

[0015] In an exemplary embodiment, the first type of border region includes a third border region and a fourth border region, the third border region is located at one side of the display region in the first direction, and the fourth border region is located at the other side of the display region; the at least one first signal providing line group includes a first first signal providing line group and a second first signal providing line group, the first first signal providing line group is located in the third border region and extends to the first border region, and the second first signal providing line group is located in the fourth border region and extends to the first border region.

[0016] The at least one first signal pin group includes a first first signal pin group and a second first signal pin group, at least part of the first signal pins in the first first signal pin group are electrically connected with at least part of the first signal providing lines in the first first signal providing line group, and at least part of the first signal pins in the second first signal pin group are electrically connected with at least part of the first signal providing lines in the second first signal providing line group.

[0017] In the first direction, the first first signal pin group and the first first signal providing line group are located at the same side of the at least one driving pin group, and the second first signal pin group and the second first signal providing line group are located at the same side of the at least one driving pin group.

[0018] In an exemplary embodiment, the at least one power pin group includes a first power pin group and a second power pin group, the binding region further includes a first power signal providing line group and a second power signal providing line group, at least part of the power pins in the first power pin group are electrically connected with at least part of the power signal providing lines in the first power signal providing line group, and at least part of the power pins in the second power pin group are electrically connected with at least part of the power signal providing lines in the second power signal providing line group.

[0019] In the binding area, in the first direction, the first power pin group and the second power pin group are located on both sides of the at least one driving pin group, the first power signal supply line group and the second power signal supply line group are located on both sides of the at least one driving pin group, the first power signal supply line group is located on the same side of the at least one driving pin group as the first power pin group, and the second power signal supply line group is located on the same side of the at least one driving pin group as the second power pin group; the first first signal pin group is located on the side of the first power pin group away from the at least one driving pin group, and the second first signal pin group is located on the side of the second power pin group and the second power signal supply line group away from the at least one driving pin group.

[0020] In an exemplary embodiment, the plurality of gate drive circuit signal lines includes a plurality of first gate drive circuit signal lines and a plurality of second gate drive circuit signal lines, the plurality of first gate drive circuit signal lines are located in the third frame area and extend to the first frame area; the plurality of second gate drive circuit signal lines are located in the fourth frame area and extend to the first frame area;

[0021] In the binding area, in the first direction, the first power signal supply line group is located on the same side of the at least one driving pin group as the plurality of first gate drive circuit signal lines, and the second power signal supply line group is located on the same side of the at least one driving pin group as the plurality of second gate drive circuit signal lines; the first first signal supply line group is located on the side of the plurality of first gate drive circuit signal lines away from the at least one integrated circuit pin group, and the second first signal supply line group is located on the side of the plurality of second gate drive circuit signal lines away from the at least one integrated circuit pin group.

[0022] In an example embodiment, in a direction perpendicular to a plane where the substrate is located, the plurality of sub-pixels are arranged on one side of the base, at least one of the plurality of sub-pixels comprises a pixel driving circuit and a light emitting element, the pixel driving circuit comprises at least one thin film transistor, a planarization layer located on a side of the thin film transistor away from the base to cover the thin film transistor, the light emitting element is located on a side of the planarization layer away from the base, the planarization layer comprises a first planarization layer via, the thin film transistor comprises an active layer located on the base, a gate located on a side of the active layer away from the substrate, a source and a drain located on a side of the gate away from the substrate, a transfer electrode located on a side of the source and the drain away from the substrate, in the same sub-pixel, one of the source and the drain in one of the thin film transistors is electrically connected to the transfer electrode through the via, and the transfer electrode is electrically connected to the light emitting element through the first planarization layer via;

[0023] In the display area, the data line is arranged in the same layer as the transfer electrode, and the first signal line is arranged in the same layer as at least one of the active layer, the source and the drain, and the gate;

[0024] In the binding area, the first signal providing line and the power signal providing line in the power signal providing line group are arranged in the same layer as at least one of the source and the drain and the transfer electrode.

[0025] In an example embodiment, the sub-pixel further comprises at least one capacitor, a first plate of the capacitor is arranged in the same layer as the gate of the at least one thin film transistor, and in a direction perpendicular to a plane where the substrate is located, a second plate of the capacitor is located between the gate of the at least one thin film transistor and the source and the drain;

[0026] In the binding area, the first signal providing line is a multi-layer structure arranged in the same layer as the source and the drain, the transfer electrode, the gate, and the second plate of the capacitor, and the multi-layer structure is electrically connected.

[0027] In an example embodiment, in the binding area, the plurality of first gate driving circuit signal lines are bent in a direction pointing to the display area along the third frame area, and are electrically connected to the integrated circuit pin group closest to the first power signal providing line group; the plurality of second gate driving circuit signal lines are bent in a direction pointing to the display area along the fourth frame area, and are electrically connected to the integrated circuit pin group closest to the second power signal providing line group;

[0028] In the binding area, at least part of the structure of the first gate drive circuit signal line at least partially overlaps the orthogonal projection of the power signal supply line in the substrate, and the first gate drive circuit signal line and the power signal supply line in the overlapping area are located in different conductive layers; at least part of the structure of the second gate drive circuit signal line at least partially overlaps the orthogonal projection of the power signal supply line in the substrate, and the plurality of second gate drive circuit signal lines and the power signal supply line in the overlapping area are located in different conductive layers.

[0029] In an exemplary embodiment, the plurality of binding pin groups further comprises a first gate drive circuit pin group and a second gate drive circuit pin group;

[0030] In the first direction, the first first signal pin group is located on the side of the first gate drive circuit pin group away from the first power pin group, and the second first signal pin group is located on the side of the second gate drive circuit pin group away from the second power pin group;

[0031] The first gate drive circuit signal line is arranged to be electrically connected with the corresponding first gate drive circuit pin in the first gate drive circuit pin group, and the second gate drive circuit signal line is arranged to be electrically connected with the corresponding second gate drive circuit pin in the second gate drive circuit pin group;

[0032] In the binding area, at least part of the structure of at least part of the gate drive circuit signal line and the power signal supply line have an unoverlapping area.

[0033] In an exemplary embodiment, in the binding area, in the area where the gate drive circuit signal line and the power signal supply line overlap, the gate drive circuit signal line is a multi-layer structure arranged in the same layer as the gate, the second plate of the capacitor; in at least part of the area where the gate drive circuit signal line and the power signal supply line do not overlap, the gate drive circuit signal line is a multi-layer structure arranged in the same layer as the source and the drain, the transfer electrode, the gate, and the second plate of the capacitor, and the multi-layer structure is electrically connected.

[0034] In an exemplary embodiment, in the direction of the display area pointing to the first frame area, the first frame area comprises a first fan-out area, a bending area, a second fan-out area and the binding area arranged in sequence;

[0035] In the first fan-out area, the first signal supply line, the plurality of first gate drive circuit signal lines, and the plurality of second gate drive circuit signal lines are a multi-layer structure arranged in the same layer as the gate and the second plate of the capacitor, and are electrically connected;

[0036] In the second fan-out area, the first signal supply line, the plurality of first gate drive circuit signal lines, and the plurality of second gate drive circuit signal lines are arranged in the same layer as at least one of the gate, the second plate of the capacitor, the source and the drain, the transfer electrode, and are located on the side of the power supply signal supply line group away from the plurality of drive pin groups in the first direction.

[0037] In an exemplary embodiment, the same power supply signal supply line group includes a first power supply signal supply line and a second power supply signal supply line, the first fan-out area is further provided with at least one first power supply connection line, at least one second power supply connection line, and a plurality of first data connection lines, the bending area is further provided with at least one first power supply connection structure, at least one second power supply connection structure, and a plurality of second data connection lines, and the second fan-out area is further provided with a plurality of third data connection lines, the first power supply signal supply line and the second power supply signal supply line are extended to the second fan-out area by the binding area;

[0038] The first power supply connection structure is arranged to electrically connect the first power supply connection line with the corresponding first power supply signal supply line, and the second power supply connection structure is arranged to electrically connect the second power supply connection line with the corresponding second power supply signal supply line;

[0039] The plurality of data lines, the plurality of first data connection lines, the plurality of second data connection lines, and the plurality of third data connection lines correspond one-to-one, and the data line is electrically connected with the corresponding integrated circuit pin in the corresponding integrated circuit binding pin group through the corresponding first data connection line, the corresponding second data connection line, and the corresponding third data connection line.

[0040] In an exemplary embodiment, in the first fan-out area, the plurality of first data connection lines are a multi-layer structure arranged in the same layer as the gate and the second plate of the capacitor, and the first power supply connection line and the second power supply connection line are a multi-layer structure arranged in the same layer as the source and the drain, and the transfer electrode, and are electrically connected;

[0041] In the bending area, the third data connection line, the first power supply connection structure, the second power supply connection structure, the first signal supply line, and the gate drive circuit signal line are arranged in the same layer as the source and the drain, and are arranged with intervals between different signal lines.

[0042] In the second fan-out area, the third data connection line is arranged in the same layer as at least one of the gate electrode and the second plate of the capacitor.

[0043] In an exemplary embodiment, in the second fan-out area, the third data connection line is a multi-layer structure arranged in the same layer as the gate electrode and the second plate of the capacitor, the first signal supply line, the plurality of first gate drive circuit signal lines, and the plurality of second gate drive circuit signal lines are multi-layer structures arranged in the same layer as the gate electrode, the second plate of the capacitor, the source electrode, the drain electrode, and the transfer electrode, and the multi-layer structures are electrically connected.

[0044] In an exemplary embodiment, the first fan-out area further comprises at least one first signal connection structure, at least one first signal pin is included in the same first signal pin group, the types of the first signal supply line and the plurality of first signal lines include at least one type, the type of the first signal supply line, the type of the first signal line, and the type of the first signal pin correspond one-to-one, and the first signal supply line is electrically connected to the first signal line of the corresponding type and the first signal pin of the corresponding type.

[0045] In the first bezel area, the number of first signal supply lines of the same type in at least one first signal supply line is at least two, at least two first signal supply lines of the same type in the first fan-out area are electrically connected through the corresponding first signal connection structure, in the area where the first signal connection structure is connected to the corresponding first signal supply line, the first signal supply line is arranged in the same layer as one of the gate electrode and the second plate of the capacitor, the first signal connection structure is arranged in the same layer as the other of the gate electrode and the second plate of the capacitor, and the corresponding first signal connection structures of the first signal supply lines of different types are arranged at intervals.

[0046] In an exemplary embodiment, the types of the first signal pins in the two first signal pin groups are the same, the types of the first signal supply lines in the first first signal supply line group and the second first signal supply line group are the same, and the same first signal line is electrically connected to the first signal supply lines of the corresponding type in the first first signal supply line group and the second first signal supply line group.

[0047] In an example embodiment, the display region is further provided with a plurality of first signal connection lines, the first signal connection lines are arranged in the same layer as the transition electrodes, the plurality of first signal connection lines are arranged at intervals along the first direction and extend along the second direction, the types of the plurality of first signal connection lines correspond to the types of the plurality of first signal lines one by one, the first signal connection lines are electrically connected to the plurality of first signal lines of the corresponding types through vias, and a same first signal line is electrically connected to the plurality of first signal connection lines of the corresponding types through vias.

[0048] In an example embodiment, the integrated circuit pins in the integrated circuit pin group and the binding pins in the binding pin group are a multi-layer structure arranged in the same layer as the source and the drain, the transition electrodes, and the multi-layer structure is electrically connected.

[0049] In an example embodiment, the third frame region further includes a plurality of first gate drive circuits, and the fourth frame region further includes a plurality of second gate drive circuits.

[0050] The plurality of first gate drive circuits are arranged along the direction in which the third frame region extends, the plurality of second gate drive circuits are arranged along the direction in which the fourth frame region extends, the first gate drive circuit signal line is further electrically connected to the plurality of first gate drive circuits, and the second gate drive circuit signal line is further electrically connected to the plurality of second gate drive circuits.

[0051] In the first direction, in the third frame region, the at least one first signal supply line is located on the side of the plurality of first gate drive circuits away from the display region, and in the fourth frame region, the at least one first signal supply line is located on the side of the plurality of second gate drive circuits away from the display region.

[0052] In an example embodiment, the display region further includes a plurality of scan signal lines, the plurality of scan signal lines extend along the first direction and are arranged along the second direction.

[0053] The first gate drive circuit and the second gate drive circuit are arranged to be electrically connected to the corresponding scan signal line, and the scan signal line is arranged in the same layer as at least one of the gate and the second plate of the capacitor.

[0054] In an example embodiment, the plurality of first signal lines include a plurality of initial signal lines, the at least one first signal supply line group includes at least one initial signal supply line group, the at least first signal pin group includes at least one initial signal pin group, and the initial signal pin group includes at least one initial signal pin.

[0055] The at least one initial signal pin is included in the same initial signal pin group, a kind of initial signal providing line in the at least one initial signal providing line group and a kind of the plurality of initial signal lines include at least one, the kind of the initial signal providing line, the kind of the initial signal line, the kind of the initial signal pin one-to-one correspondence, the initial signal providing line is electrically connected with the initial signal line of the corresponding kind and the initial signal pin of the corresponding kind.

[0056] In a second aspect, the embodiments of the present disclosure provide a display substrate, comprising:

[0057] A substrate comprises a display area, a first frame area, and a first type of frame area; in a first direction, the first type of frame area is located on at least one side of the display area; in a second direction, the first frame area is located on one side of the display area, and the first frame area is provided with a binding area, and the first direction intersects the second direction;

[0058] A plurality of sub-pixels are located in the display area.

[0059] A plurality of data lines are located in the display area and electrically connected to the plurality of sub-pixels, and the plurality of data lines extend along the second direction and are arranged at intervals along the first direction.

[0060] A plurality of first signal lines are located in the display area, extend along the first direction, and are arranged along the second direction, and the plurality of first signal lines are electrically connected to the plurality of sub-pixels.

[0061] At least one first signal providing line group is located in the first type of frame area and extends to the binding area in the first frame area, and a first signal providing line in the first signal providing line group is arranged to be electrically connected to at least one first signal line in the plurality of first signal lines.

[0062] At least one integrated circuit pin group is located in the binding area, and at least part of the integrated circuit pins in the integrated circuit pin group are arranged to be electrically connected to the plurality of data lines.

[0063] In the binding area, in the first direction, a main part of the at least one first signal providing line group is located on at least one side of the at least one integrated circuit pin group, at least part of the structure of at least part of the first signal providing line is a multi-layer structure, and the multi-layer structure is electrically connected.

[0064] In an exemplary embodiment, the first type of frame area is further provided with a plurality of gate drive circuit signal lines, and the plurality of gate drive circuit signal lines extend to the binding area in the first frame area.

[0065] In the binding area, in the first direction, the main body part of the gate drive circuit signal line is located at least one side of the at least one integrated circuit pin group, and is located at the same side of the first middle line, the first signal supply line in the first signal supply line group, the gate drive circuit signal line and the integrated circuit pin group farthest from the first middle line are electrically connected, and the first middle line is a middle line of the first frame area extending in the second direction;

[0066] In the binding area, at least part of the structure of at least part of the gate drive circuit signal line is a multilayer structure, and the multilayer structure is electrically connected.

[0067] In an exemplary embodiment, the binding area further comprises at least one power signal supply line group, and in the first direction, the at least one power signal supply line group is located at least one side of the at least one integrated circuit pin group.

[0068] In the binding area, in the first direction, the same side of the first middle line, the gate drive circuit signal line and the first signal supply line are bent in the direction of the display area pointing to the first frame area, and are electrically connected with the integrated circuit pin group farthest from the first middle line. At least part of the structure of the gate drive circuit signal line and the first signal supply line at least partially overlaps the orthogonal projection of the power signal supply line group on the substrate, and the gate drive circuit signal line and the first signal supply line are located in different conductive layers with the power signal supply line in the overlapping area.

[0069] In an exemplary embodiment, in the direction perpendicular to the plane where the substrate is located, the display substrate at least comprises a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer arranged in sequence on one side of the substrate.

[0070] In the display area, the data line is located in the second source-drain metal layer, and the first signal line is located in at least one conductive layer of the first gate metal layer, the second gate metal layer and the first source-drain metal layer.

[0071] In the binding area, the first signal line and the gate drive circuit signal line are located in at least one conductive layer of the first gate metal layer, the second gate metal layer and the first source-drain metal layer.

[0072] In an exemplary embodiment, in the direction of the display area pointing to the first frame area, the first frame area comprises a first fan-out area, a bending area, a second fan-out area and the binding area arranged in sequence.

[0073] In at least part of the first fan-out area, the binding area, the first signal supply line and the gate drive circuit signal line overlap with the power supply signal supply line, the first signal supply line and the gate drive circuit signal line are a multi-layer structure located in the first gate metal layer and the second gate metal layer, and the multi-layer structure is electrically connected.

[0074] In at least part of the second fan-out area, the binding area, the first signal supply line and the gate drive circuit signal line do not overlap with the power supply signal supply line, the first signal supply line and the gate drive circuit signal line are a multi-layer structure located in the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer, and the multi-layer structure is electrically connected.

[0075] In an exemplary embodiment, the power supply signal supply lines in the power supply signal supply line group are extended to the second fan-out area by the binding area.

[0076] In at least part of the second fan-out area and the binding area, the power supply signal supply lines in the power supply signal supply line group are a multi-layer structure located in the first source-drain metal layer and the second source-drain metal layer, and the multi-layer structure is electrically connected.

[0077] In a third aspect, the present disclosure also provides a display device comprising the display substrate as described in any of the above embodiments.

[0078] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0079] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0080] FIG. 1 shows a structural schematic diagram of a display device;

[0081] FIG. 2 shows a structural schematic diagram of a display substrate;

[0082] FIG. 3 shows an enlarged structural schematic diagram of a first bezel area;

[0083] FIG. 4 shows a structural schematic diagram of a display substrate;

[0084] FIG. 5 shows a structural schematic diagram of a display substrate;

[0085] FIG. 6a shows an equivalent circuit schematic diagram of a pixel drive circuit;

[0086] Fig. 6b shows an equivalent circuit schematic diagram of a pixel driving circuit;

[0087] Fig. 6c shows an equivalent circuit schematic diagram of a pixel driving circuit;

[0088] Fig. 7a shows a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0089] Fig. 7b shows a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0090] Fig. 7c shows a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0091] Fig. 7d shows a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0092] Fig. 8a shows an enlarged structural schematic diagram of M1 position in Figs. 7a-7d;

[0093] Fig. 8b shows an enlarged structural schematic diagram of M1 position in Figs. 7a-7d;

[0094] Fig. 8c shows an enlarged structural schematic diagram of M1 position in Figs. 7a-7d;

[0095] Fig. 8d shows an enlarged structural schematic diagram of M1 position in Figs. 7a-7d;

[0096] Fig. 8e shows a cross-sectional structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0097] Fig. 9a shows a cross-sectional structural schematic diagram of C1-C1 position in Figs. 8a-8d;

[0098] Fig. 9b shows a cross-sectional structural schematic diagram of C1-C1 position in Figs. 8a-8d;

[0099] Fig. 9c shows a cross-sectional structural schematic diagram of C1-C1 position in Figs. 8a-8d;

[0100] Fig. 9d shows a cross-sectional structural schematic diagram of C2-C2 position in Figs. 8a-8c, 8d;

[0101] Fig. 9e shows a cross-sectional structural schematic diagram of C2-C2 position in Figs. 8a-8c, 8d;

[0102] Fig. 9f shows a cross-sectional structural schematic diagram of C2-C2 position in Figs. 8a-8c, 8d;

[0103] FIG. 9g is a schematic view of a cross-sectional structure of a C3-C3 position in FIGS. 8a-8d;

[0104] FIG. 9h is a schematic view of a cross-sectional structure of a C3-C3 position in FIGS. 8a-8d;

[0105] FIG. 9i is a schematic view of a cross-sectional structure of a C4-C4 position in FIG. 8a;

[0106] FIG. 9j is a schematic view of a cross-sectional structure of a C5-C5 position in FIG. 8a;

[0107] FIG. 9k is a schematic view of a cross-sectional structure of a C4-C4 position in FIGS. 8b-8d;

[0108] FIG. 9L is a schematic view of a cross-sectional structure of a C5-C5 position in FIGS. 8b-8d;

[0109] FIG. 9m is a schematic view of a cross-sectional structure of a C4-C4 position in FIGS. 8b-8d;

[0110] FIG. 9n is a schematic view of a cross-sectional structure of a C5-C5 position in FIGS. 8b-8d;

[0111] FIG. 10a is a schematic view of an enlarged M2 position in FIG. 8c;

[0112] FIG. 10b is a schematic view of an enlarged M2 position in FIG. 8c;

[0113] FIG. 10c is a schematic view of a cross-sectional structure of an E1-E1 position in FIG. 10a;

[0114] FIG. 10d is a schematic view of a cross-sectional structure of an E1-E1 position in FIG. 10b;

[0115] FIG. 11 is a schematic view of a structure of a display substrate according to an example embodiment of the present disclosure;

[0116] FIG. 12 is a schematic view of an enlarged M1 position in FIG. 11;

[0117] FIG. 13 is a schematic view of a display device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0118] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. The embodiments of the present disclosure can be implemented in various forms. It will be readily apparent to those skilled in the art that the embodiments and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. Embodiments in the present disclosure and features in the embodiments can be arbitrarily combined with each other in so far as there is no contradiction in combination.

[0119] In the drawings, the size, the thickness, or the region of each constituent element shown in each drawing can be exaggerated for clarity. Therefore, the present disclosure should not be construed as being limited to the size as shown in the drawings. The shape, the size, and the like of a part shown in the drawings are intended to illustrate the principle of the present disclosure and should not be construed as limiting the present disclosure thereto.

[0120] In the present disclosure, ordinal numbers such as "first", "second", and "third" are used to avoid confusion among constituents, and are not intended to indicate or imply a particular order among the constituents.

[0121] In the present disclosure, words of a positional relation or a positional direction such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relation of constituents with reference to the drawings, and are used only for convenience of description and simplification of the description, and are not intended to indicate or imply that the device or the element indicated thereby must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present disclosure. The positional relation of the constituents can be appropriately changed according to the direction of the constituents described. Therefore, the words described in the present disclosure are not limited to the words described herein, and can be appropriately changed according to the situation.

[0122] In the present disclosure, unless explicitly defined and limited otherwise, the terms "mount", "connected", and "connection" are to be construed broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate member, or communication between two elements inside. The above terms can be understood in the present disclosure according to the situation by those skilled in the art.

[0123] In the present disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (or drain terminal, drain connection region, or drain electrode) and the source electrode (or source terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0124] In the present disclosure, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In a case where a transistor having opposite polarity is used or a case where the direction of current flowing in a circuit is changed, the functions of the "source electrode" and the "drain electrode" can be sometimes interchanged with each other. Thus, in the present disclosure, the "source electrode" and the "drain electrode" can be interchanged with each other. In the present disclosure, the control electrode can be a gate electrode.

[0125] In the present disclosure, "electrically connected" includes a case where components are connected together through an element having some kind of electrical action. An element having some kind of electrical action is not particularly limited as long as it can perform transmission and reception of an electrical signal between components to be connected. An element having some kind of electrical action can be, for example, an electrode or a wiring, or a switching element such as a transistor, or another functional element such as a resistor, an inductor, or a capacitor.

[0126] FIG. 1 shows a structural schematic diagram of a display device, a display substrate can include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array, the timing controller is connected with the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit respectively, the data signal driving circuit is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan signal driving circuit is connected with a plurality of scan signal lines (G1 to Gm) respectively, and the light emission signal driving circuit is connected with a plurality of light emission signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting device connected with the circuit unit, the circuit unit can include a pixel driving circuit, and the pixel driving circuit can be connected with a scan signal line, a light emission signal line, and a data signal line (which can be referred to as a data line) respectively. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data signal driving circuit to the data signal driving circuit, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driving circuit to the scan signal driving circuit, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can generate a data voltage to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data signal driving circuit can sample the gray value using the clock signal, and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan signal driving circuit can generate a scan signal to be provided to the scan signal lines G1, G2, G3, …, and Gm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driving circuit can sequentially provide the scan signal having an on-level pulse to the scan signal lines G1 to Gm. For example, the scan signal driving circuit can be configured in the form of a shift register, and can generate the scan signal in a manner of sequentially transferring the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emission signal driving circuit can generate an emission signal to be provided to the light emission signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emission signal driving circuit can sequentially provide the emission signal having an off-level pulse to the light emission signal lines E1 to Eo. For example, the light emission driver can be configured in the form of a shift register, and can generate the emission signal in a manner of sequentially transferring the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number.

[0127] FIG. 2 shows a structural schematic diagram of a display panel. As shown in FIG. 2, the display panel can include a display area AA and a frame area BB located around the display area AA. In some examples, the frame area BB can include a first frame area (lower frame) B1 and a second frame area (upper frame) B2 oppositely arranged in the second direction Y, and a third frame area (left frame) B3 and a fourth frame area (right frame) B4 oppositely arranged in the first direction X. The first frame area B1 is in communication with the third frame area B3 and the fourth frame area B4, and the second frame area B2 is in communication with the third frame area B3 and the fourth frame area B4. In some examples, the display area AA can include a first edge (lower edge) and a second edge (upper edge) oppositely arranged in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) oppositely arranged in the first direction X. The display area AA can include a plurality of sub-pixels Pxij arranged regularly, the sub-pixels can include a pixel driving circuit and a light emitting device, the first frame area B1 can include a bonding circuit connecting a signal line to an external driving device, and the third frame area B3 and the fourth frame area B4 can include a gate driving circuit and a second power supply line VSS transmitting a voltage signal to the plurality of sub-pixels.

[0128] FIG. 3 shows a schematic diagram of a planar structure of the first bezel area B1, which can include, in a plane parallel to the display substrate, a first fan-out area 11, a bending area 12, a second fan-out area 13, and a binding area 14 arranged in sequence in a direction away from the display area AA. The binding area 14 can include, in a direction away from the bending area 12 of the second fan-out area 13, a driving chip area 141, a third fan-out area 142, and a binding electrode area 143 arranged in sequence. The first fan-out area 11 can include data connection lines, a first power connection line, and a second power line. The data connection lines are configured to connect data lines of the display area AA in a fan-out manner. The first power line is configured to connect a high-voltage power line (VDD) of the display area AA. The second power line is a low-voltage power line (VSS) located in the third bezel area B3 and the fourth bezel area B4. The bending area 12 can include a composite insulating layer provided with a groove, and is configured to bend the binding area 14 to the back of the display area AA (as shown in FIG. 4). The second fan-out area 13 includes a plurality of data connection lines in a fan-out manner. The driving chip area 141 can be provided with an integrated circuit (IC) 20 configured to be connected to the plurality of data connection lines. The binding electrode area 143 includes a plurality of bonding pads configured to be connected to a flexible printed circuit (FPC) 30. In an exemplary embodiment, the integrated circuit (IC) 20 can be connected to the driving chip area 141, and the flexible printed circuit (FPC) 30 can be connected to the binding electrode area 143. In an exemplary embodiment, the integrated circuit 20 (which can be referred to as a data driving circuit or a driving circuit) can generate a driving signal required for driving a sub-pixel, and can provide the driving signal to the sub-pixel Pxij located in the display area AA. For example, the driving signal can be a data signal for controlling the luminance of the sub-pixel. In an exemplary embodiment, the binding electrode area 143 can be provided with a pad (PAD) including a plurality of pins (PIN), and the flexible printed circuit 30 can be connected to the pad.

[0129] In an exemplary embodiment, as shown in FIG. 4, the bending area 12 can invert the surface of the binding area 14, i.e., the surface of the binding area 14 facing upward can be converted to face downward through the bending of the bending area 12. In an exemplary embodiment, when the bending area 12 is bent, the binding area 14 can overlap the display area AA in the thickness direction of the display panel.

[0130] In an example embodiment, for a large-size display substrate, a plurality of data driving ICs (may be referred to as driving ICs, i.e., driving integrated circuits) and a plurality of FPCs can be provided, the plurality of FPCs are respectively bound to the plurality of data driving ICs, for example, n data driving ICs can be provided to be respectively bound to n FPCs, n is a positive integer greater than or equal to 1, for example, n is 4, the embodiments of the present disclosure are not limited to four ICs and four FPCs, for example, two data driving ICs and two FPCs can be provided; for a small-size display substrate, one data driving IC or two data driving ICs can be provided. In the embodiments of the present disclosure, the number of data driving ICs and FPCs can be set according to the size of the display substrate and the need for function, which is not limited herein.

[0131] In an example embodiment, as shown in FIG. 5, it is a structural schematic diagram of a display substrate, the display area AA can be provided with a plurality of scan signal lines SL, a plurality of initial signal lines Vinit and a plurality of data lines DL0 in the data signal lines D (the same data signal line D can include the data line DL0 located in the display area AA and the data connection line DL located in the first frame area B1), the plurality of scan signal lines SL and the plurality of initial signal lines Vinit can extend along the first direction X and be arranged at intervals along the second direction Y, the plurality of data lines DL0 can extend along the second direction Y and be arranged at intervals along the first direction X, each scan signal line SL can be electrically connected with a plurality of sub-pixels Pxij in a row of sub-pixels, each data line DL0 can be electrically connected with a plurality of sub-pixels in a column of sub-pixels, the third frame area B3 and the fourth frame area B4 can be provided with a plurality of gate driving circuits GOA (GOA is a short for array substrate row driving, the full name in English is Gate Driver on Array), a plurality of initial signal providing lines Vinit0 and gate driving circuit signal lines (GOA signal lines), the GOA signal lines can include clock signal lines (for example, can include CK signal lines, CB signal lines), start signal lines (for example, can include STV signal lines) and the like, the gate driving circuit GOA is arranged to be electrically connected with the corresponding scan signal line SL and provide a scan signal to the corresponding scan signal line SL, the start signal line is arranged to provide a start signal to the corresponding gate driving circuit GOA, the clock signal line is arranged to provide a clock signal to the corresponding gate driving circuit GOA, and the initial signal line Vinit is arranged to provide an initial signal to the corresponding sub-pixel. The data connection line DL in the data signal line D can include a first data connection line DL1 located in the first fan-out area 11, a second data connection line DL2 located in the bending area 12 and a third data connection line DL3 located in the second fan-out area 13.

[0132] In the example embodiment, as shown in FIG. 5, the first fan-out area 11 can include a plurality of first data connection lines DL1, a first power connection line PL11, and a second power connection line PL21. The plurality of first data connection lines DL1 can be arranged at intervals along the first direction X. The first power connection line PL11 and the second power connection line PL21 are located at different conductive layers from the plurality of first data connection lines DL1. The first power connection line PL11 and the second power connection line PL21 can be located on a side of the plurality of first data connection lines DL1 away from the substrate. The bending area 12 can include a plurality of second data connection lines DL2, a first power connection structure PL12, and a second power connection structure PL22. The plurality of second data connection lines DL2, the first power connection structure PL12, and the second power connection structure PL22 are arranged at intervals along the first direction X. The second data connection lines DL2, the first power connection structure PL12, and the second power connection structure PL22 in the bending area 12 are generally located at the same conductive layer. Different signal lines need to be arranged at intervals to avoid signal short circuit. The second fan-out area 13 can include a plurality of third data connection lines DL3, a first power signal providing line VDD0, and a second power signal providing line VSS0. The first power signal providing line VDD0 and the second power signal providing line VSS0 can be located at the same conductive layer. The third data connection lines DL3 and the first power signal providing line VDD0 can be located at different conductive layers. The driving chip area 141 can be provided with an integrated circuit pin group 61. The driving circuit 20 (e.g., a driving IC) can be connected to the integrated circuit pin group 61 in a binding manner. An end of the third data connection line DL3 away from the second data connection line DL2 can be electrically connected to an integrated circuit binding pin in the integrated circuit pin group 61. The third fan-out area 142 can be provided with a plurality of pin connection lines 201. The binding electrode area 143 can be provided with a plurality of pads. The plurality of pads can include a first power pad 51, a second power pad 52, and a driving pad 53. The integrated circuit pin group 61 can be electrically connected to the driving pad 53 in the binding electrode area 143 through the pin connection line 201. The plurality of driving pads 53 can be connected to the flexible circuit board 30 (shown in FIG. 4) in a binding manner. The first power signal providing line VDD0 can be connected to the first power pad 51. The second power signal providing line VSS0 can be connected to the second power pad 52.

[0133] In an example embodiment, as shown in FIG. 5, the data lines DL0, the first data connection line DL1, the second data connection line DL2, and the third data connection line DL3 can be connected one by one, the first power signal supply line VDD0 can be electrically connected with the first power connection line PL11 through the first power connection structure PL12, and the second power signal supply line VSS0 can be electrically connected with the second power connection line PL21 through the second power connection structure PL22. The first power connection line PL11 can be connected with the first power line VDD located in the display area, and the second power connection line PL21 can be connected with the second power line VSS located in the third and fourth frame areas. The first power line VDD is electrically connected with a plurality of sub-pixels, and the second power line VSS is electrically connected with the cathode of the light emitting element EL.

[0134] In an example embodiment, as shown in FIG. 5, the gate drive circuit signal line can include a first gate drive circuit signal line 41 and a second gate drive circuit signal line 42. The first gate drive circuit signal line 41 extends from the third frame area B3 to the first frame area B1, and is connected with the first gate drive pad 541 and the gate drive circuit GOA located in the third frame area B3. The second gate drive circuit signal line 42 extends from the fourth frame area B4 to the first frame area B1, and is connected with the second gate drive pad 542 and the gate drive circuit GOA located in the fourth frame area B4. Alternatively, the gate drive circuit GOA can include a first gate drive circuit GOA1 arranged in the third frame area B3 and a second gate drive circuit GOA2 arranged in the fourth frame area B4. The first gate drive circuit GOA1 is configured to be electrically connected with the integrated circuit pin group 61 through the first gate drive circuit signal line 41, and the second gate drive circuit GOA2 is configured to be electrically connected with the integrated circuit pin group 61 through the second gate drive circuit signal line 42. The initial signal supply line Vinit0 located in the third and fourth frame areas B3 and B4 extends to the first frame area B1 and is configured to be electrically connected with the integrated circuit pin group 61. The initial signal line Vinit located in the display area AA is connected with the initial signal supply line Vinit0 located in the third and fourth frame areas B3 and B4, and is configured to provide the initial signal from the initial signal supply line Vinit0 to the corresponding sub-pixel Pxij.

[0135] In an example embodiment, at least one sub-pixel Pxij can include a pixel drive circuit and a light emitting element. In the same sub-pixel Pxij, the light emitting element is electrically connected with the pixel drive circuit and is configured to emit light under the drive of the pixel drive circuit. The pixel drive circuit can include, but is not limited to, a 7T1C circuit structure as shown in FIG. 6a, an 8T1C circuit structure as shown in FIGS. 6b and 6c. The pixel drive circuit is described in detail below in conjunction with FIGS. 6a to 6c:

[0136] As shown in FIG. 6a, it is an equivalent circuit diagram of a pixel driving circuit. In some examples, as shown in FIG. 6a, the pixel driving circuit of the present example can include seven transistors (i.e., first transistor T1 to seventh transistor T7) and one storage capacitor Cst. Among them, the gate of the third transistor T3 is electrically connected with the first node N1, the first pole of the third transistor T3 is electrically connected with the second node N2, and the second pole of the third transistor T3 is electrically connected with the third node N3. The third transistor T3 can also be referred to as a driving transistor. The gate of the fourth transistor T4 is electrically connected with the first scan line GL, the first pole of the fourth transistor T4 is electrically connected with the data signal line D, and the second pole of the fourth transistor T4 is electrically connected with the first pole of the third transistor T3. The fourth transistor T4 can also be referred to as a data writing transistor. The gate of the second transistor T2 is electrically connected with the first scan line GL, the first pole of the second transistor T2 is electrically connected with the gate of the third transistor T3, and the second pole of the second transistor T2 is electrically connected with the second pole of the third transistor T3. The second transistor T2 can also be referred to as a threshold compensation transistor. The gate of the fifth transistor T5 is electrically connected with the light-emitting control line EML, the first pole of the fifth transistor T5 is electrically connected with the first power supply line VDD, and the second pole of the fifth transistor T5 is electrically connected with the first pole of the third transistor T3. The gate of the sixth transistor T6 is electrically connected with the light-emitting control line EML, the first pole of the sixth transistor T6 is electrically connected with the second pole of the third transistor T3, and the second pole of the sixth transistor T6 is electrically connected with the anode of the light-emitting element EL. The fifth transistor T5 and the sixth transistor T6 can also be referred to as light-emitting control transistors. The first transistor T1 is electrically connected with the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3, and the seventh transistor T7 is electrically connected with the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first transistor T1 is electrically connected with the first reset control line RST1, the first pole of the first transistor T1 is electrically connected with the first initial signal line Vinit1, and the second pole of the first transistor T1 is electrically connected with the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected with the second reset control line RST2, the first pole of the seventh transistor T7 is electrically connected with the second initial signal line Vinit2, and the second pole of the seventh transistor T7 is electrically connected with the anode of the light-emitting element EL. The first transistor T1 and the seventh transistor T7 can also be referred to as reset control transistors. The first capacitor plate of the storage capacitor Cst is electrically connected with the gate of the third transistor T3, and the second capacitor plate of the storage capacitor Cst is electrically connected with the first power supply line VDD.

[0137] In the present example, the first node N1 is a connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3, and the second transistor T2, the second node N2 is a connection point of the fifth transistor T5, the fourth transistor T4, and the third transistor T3, the third node N3 is a connection point of the third transistor T3, the second transistor T2, and the sixth transistor T6, and the fourth node N4 is a connection point of the sixth transistor T6, the seventh transistor T7, and the light emitting element EL.

[0138] In some examples, the first transistor T1 to the seventh transistor T7 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0139] In some examples, the first power supply line VDD can be configured to provide a constant first voltage signal to the pixel circuit, the second power supply line VSS can be configured to provide a constant second voltage signal to the pixel circuit, and the first voltage signal can be greater than the second voltage signal. The first scan line GL can be configured to provide a scan signal SCAN to the pixel circuit, the data signal line D can be configured to provide a data signal DATA to the pixel circuit, the light emitting control line EML can be configured to provide a light emitting control signal EM to the pixel circuit, the first reset control line RST1 can be configured to provide a first reset control signal to the pixel circuit, and the second reset control line RST2 can be configured to provide a second reset control signal to the pixel circuit.

[0140] In some examples, the first initial signal line Vinit1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line Vinit2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, and the magnitudes of the first initial signal and the second initial signal can be, for example, between the first voltage signal and the second voltage signal, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same.

[0141] In the example embodiment, the pixel driving circuit can also be as shown in FIGS. 6b and 6c; the difference between FIG. 6b and FIG. 6a is that an eighth transistor T8 is added, the gate of the eighth transistor T8 is connected with the second node N2, the first pole of the eighth transistor T8 is connected with the third initial signal line Vinit3, and the gate of the eighth transistor T8 is connected with the third reset control line RST3. The difference between FIG. 6c and FIG. 6b is that the second pole of the first transistor T1 is connected with the third node N3. In the pixel driving circuit structure shown in FIG. 6a, the scan signal line SL in FIG. 5 can include the first scan line GL, the first reset control line RST1, the second reset control line RST2 and the light-emitting control line EML in FIG. 6a, and the initial signal line Vinit shown in FIG. 5 can include the first initial signal line Vinit1 and the second initial signal line Vinit2; in the pixel driving circuit structure shown in FIGS. 6b and 6c, the scan signal line SL in FIG. 5 can include the first scan line GL, the first reset control line RST1, the second reset control line RST2, the third reset control line RST3 and the light-emitting control line EML in FIGS. 6b and 6c, and the initial signal line Vinit shown in FIG. 5 can include the first initial signal line Vinit1, the second initial signal line Vinit2 and the third initial signal line Vinit3.

[0142] In the example embodiment, different frequencies are used under different pictures, which can improve power consumption to a certain extent. In high-precision frequency conversion technology, there are cases where multiple resets are required under one frame of picture. The load (resistance) of the initial signal supply line Vinit0 at the multiple reset positions is different, which causes one or more horizontal lines to appear on the screen. Therefore, it is very important to reduce the load of the initial signal supply line Vinit0.

[0143] The display substrate provided by the example embodiment of the present disclosure can include:

[0144] A substrate includes a display area, a first frame area and a first type of frame area; in a first direction, the first type of frame area is located on at least one side of the display area; in a second direction, the first frame area is located on one side of the display area, and the first frame area is provided with a binding area, and the first direction intersects the second direction;

[0145] A plurality of sub-pixels are located in the display area;

[0146] A plurality of data lines are located in the display area and electrically connected with the plurality of sub-pixels, and the plurality of data lines extend along the second direction and are arranged at intervals along the first direction;

[0147] A plurality of first signal lines are located in the display region and extend along the first direction and are arranged along the second direction, and the plurality of first signal lines are electrically connected to the plurality of sub-pixels.

[0148] At least one first signal supply line group is located in the first type of frame region and extends to the binding region in the first frame region, and a first signal supply line in the first signal supply line group is configured to be electrically connected to at least one first signal line in the plurality of first signal lines.

[0149] A plurality of binding pin groups and at least one integrated circuit pin group are located in the binding region, the plurality of binding pin groups include at least one first signal pin group, at least part of the integrated circuit pins in the integrated circuit pin group are configured to be electrically connected to the plurality of data lines, in the first direction, the at least one first signal pin group is located at least one side of the at least one integrated circuit pin group, the at least one first signal pin group corresponds to the at least one first signal supply line group one-to-one, the at least one first signal pin group and the corresponding first signal supply line group are located on the same side of the at least one integrated circuit pin group, and at least part of the first signal pins in the at least one first signal pin group are configured to be electrically connected to at least part of the first signal supply lines in the corresponding first signal supply line group.

[0150] In the display substrate provided by the embodiments of the present disclosure, a plurality of binding pin groups and at least one integrated circuit pin group are arranged in the binding region, at least one first signal supply line group is arranged in the first type of frame region, a first signal supply line in the first signal supply line group extends to the binding region, in the first direction, at least one first signal pin group is located at least one side of the at least one integrated circuit pin group, the at least one first signal pin group corresponds to the at least one first signal supply line group one-to-one, the first signal pin group and the corresponding first signal supply line group are located on the same side of the at least one integrated circuit pin group, and at least part of the first signal pins in the at least one first signal pin group are configured to be electrically connected to at least part of the first signal supply lines in the corresponding first signal supply line group. The display substrate provided by the embodiments of the present disclosure can reduce the resistance of the first signal supply line in the binding region, and to a certain extent, solve the technical problem that the display region has horizontal lines due to the large resistance of the first signal supply line.

[0151] In the example embodiment, the first signal line and the data line are located in different conductive layers.

[0152] As shown in FIGS. 7a-8d, FIGS. 7a-7d are structural schematic diagrams of a display substrate provided by an embodiment of the present disclosure, FIGS. 8a, 8b and 8c are enlarged structural schematic diagrams of the M1 position in FIGS. 7a-7c, and FIG. 8d is an enlarged structural schematic diagram of the M1 position in FIG. 7d. The display substrate can include:

[0153] a substrate including a display area AA, a first frame area B1 and a first type frame area B01; in a first direction X, the first type frame area B01 is located on at least one side of the display area AA; in a second direction Y, the first frame area B1 is located on a side of the display area AA, and the first frame area B1 is provided with a binding area 14, and the first direction X intersects the second direction Y;

[0154] a plurality of sub-pixels Pxij located in the display area AA;

[0155] a plurality of data lines DL0 located in the display area AA and electrically connected to the plurality of sub-pixels Pxij, the plurality of data lines DL0 extending along the second direction Y and being arranged at intervals along the first direction X;

[0156] a plurality of first signal lines VL1 located in the display area AA and extending along the first direction X and arranged along the second direction Y, the plurality of first signal lines VL1 being electrically connected to the plurality of sub-pixels Pxij, and the first signal lines VL1 and the data lines DL0 being located in different conductive layers;

[0157] at least one first signal providing line group VL10 located in the first type frame area B01 and extending to the binding area 14 in the first frame area B1, and a first signal providing line VL11 in the first signal providing line group VL10 being arranged to be electrically connected to at least one first signal line VL1 in the plurality of first signal lines VL1;

[0158] a plurality of binding pin groups and at least one integrated circuit pin group 61 located in the binding area 14, the plurality of binding pin groups including at least one first signal pin group 54; at least part of the integrated circuit pins in the integrated circuit pin group 61 are arranged to be electrically connected to the plurality of data lines DL0; in the first direction X, the at least one first signal pin group 54 is located on at least one side of the at least one integrated circuit pin group 61, the at least one first signal pin group 54 corresponds to the at least one first signal providing line group VL10 in one-to-one correspondence, Z the at least one first signal pin group 54 and the corresponding first signal providing line group VL10 are located on the same side of the at least one integrated circuit pin group 61, and at least part of the first signal pins in the at least one first signal pin group 54 are arranged to be electrically connected to at least part of the first signal providing lines VL11 in the corresponding first signal providing line group VL10.

[0159] In the exemplary embodiments, in the first direction X, the at least one first signal pin group 54 can be located on at least one side of the at least one integrated circuit pin group 61, i.e., the first signal pin group 54 is located at the outermost side of the first bezel area B1, which can minimize the length of the first signal supply line group VL10 in the bonding area 14 and reduce the resistance of the first signal supply line VL11.

[0160] In the exemplary embodiments, in the second direction Y, the plurality of bonding pin groups are located on the side of the integrated circuit pin group 61 away from the display area AA.

[0161] The plurality of bonding pin groups can further include at least one driving pin group 53 and at least one power pin group 50, the at least one driving pin group 53 corresponds to the at least one integrated circuit pin group 61 one-to-one, and the at least one driving pin group 53 is electrically connected to the corresponding integrated circuit pin group 61; in the first direction X, at least one power pin group 50 is provided between the at least one first signal pin group 54 and the at least one driving pin group 53, i.e., the first signal pin group 54 is located at the outermost side of the first bezel area B1, which can minimize the length of the first signal supply line group VL10 in the bonding area 14 and reduce the resistance of the first signal supply line VL11.

[0162] In the exemplary embodiments, the first type of bezel area B01 is further provided with a plurality of gate drive circuit signal lines 40, the plurality of gate drive circuit signal lines 40 extend to the first bezel area B1, in the same first type of bezel area B01, in the first direction X, the first signal supply line group VL10 is located on the side of the plurality of gate drive circuit signal lines 40 away from the display area AA, i.e., the first signal supply line group VL10 is located at the outermost side of the first type of bezel area B01, and the first signal pin group 54 is located at the outermost side of the first bezel area B1, which to some extent reduces the distance between the first signal supply line group VL10 and the first signal pin group 54, can reduce the length of the first signal supply line VL11 in the first signal supply line group VL10 in the bonding area 14, reduce the resistance of the first signal supply line VL11, and to some extent overcome the technical problem that the display area produces horizontal lines due to the large resistance of the first signal supply line VL11.

[0163] In the exemplary embodiments, as shown in FIGS. 7a-7d, the first type of bezel region B01 can include a third bezel region B3 and a fourth bezel region B4, the third bezel region B3 is located at one side of the display region AA in the first direction X, and the fourth bezel region B4 is located at the other side of the display region AA; the at least one first signal providing line group VL10 can include at least a first first signal providing line group VL101 and a second first signal providing line group VL102, the first first signal providing line group VL101 is located in the third bezel region B3 and extends to the first bezel region B1; the second first signal providing line group VL102 is located in the fourth bezel region B4 and extends to the first bezel region B1.

[0164] The at least one first signal pin group 54 can include a first first signal pin group 541 and a second first signal pin group 542, at least part of the first signal pins in the first first signal pin group 541 are arranged to be electrically connected with at least part of the first signal providing lines VL11 in the first first signal providing line group VL101, and at least part of the first signal pins in the second first signal pin group 542 are arranged to be electrically connected with at least part of the first signal providing lines VL11 in the second first signal providing line group VL102.

[0165] In the first direction X, the first first signal pin group 541 and the first first signal providing line group VL101 are located on the same side of the at least one driving pin group 53, and the second first signal pin group 542 and the second first signal providing line group VL102 are located on the same side of the at least one driving pin group 53.

[0166] In the exemplary embodiments, the at least one power pin group 50 includes at least a first power pin group 501 and a second power pin group 502, and the binding region 14 can further include a plurality of voltage signal providing line groups VD, the plurality of voltage signal providing line groups VD can include a first power signal providing line group VD1 and a second power signal providing line group VD2, at least part of the power pins in the first power pin group 501 are electrically connected with at least part of the power signal providing lines in the first power signal providing line group VD1, and at least part of the power pins in the second power pin group 502 are electrically connected with at least part of the power signal providing lines in the second power signal providing line group VD2.

[0167] In the binding area 14, in the first direction X, the first power pin group 501 and the second power pin group 502 are located on both sides of the at least one driving pin group 53, the first power signal supply line group VD1 and the second power signal supply line group VD2 are located on both sides of the at least one driving pin group 53, the first power signal supply line group VD1 is located on the same side of the at least one driving pin group 53 as the first power pin group 501, and the second power signal supply line group VD2 is located on the same side of the at least one driving pin group 53 as the second power pin group 502; the first first signal pin group 54 is located on the side of the first power pin group 501 away from the at least one driving pin group 53, and the second first signal pin group 54 is located on the side of the second power pin group 502 away from the at least one driving pin group 53.

[0168] In the exemplary embodiment, the plurality of gate drive circuit signal lines 40 can include a plurality of first gate drive circuit signal lines 41 and a plurality of second gate drive circuit signal lines 42, the plurality of first gate drive circuit signal lines 41 are located in the third frame area B3 and extend to the first frame area B1; the plurality of second gate drive circuit signal lines 42 are located in the fourth frame area B4 and extend to the first frame area B1;

[0169] In the binding area 14, in the first direction X, the first power signal supply line group VD1 is located on the same side of the at least one driving pin group 53 as the plurality of first gate drive circuit signal lines 41, and the second power signal supply line group VD2 is located on the same side of the at least one driving pin group 53 as the plurality of second gate drive circuit signal lines 42; the first first signal supply line group VL101 is located on the side of the plurality of first gate drive circuit signal lines 41 away from the at least one integrated circuit pin group 61, and the second first signal supply line group VL10 is located on the side of the plurality of second gate drive circuit signal lines 42 away from the at least one integrated circuit pin group 61, which can reduce the distance between the first signal supply line group VL10 and the corresponding first signal pin group 54 and reduce the resistance of the first signal supply line VL11 in the binding area.

[0170] In an exemplary embodiment, in a direction perpendicular to a plane where the substrate is located, a plurality of sub-pixels Pxij are arranged on one side of the base, at least one of the plurality of sub-pixels Pxij comprises a pixel driving circuit and a light emitting element, the pixel driving circuit comprises at least one thin film transistor, a planarization layer located on a side of the thin film transistor away from the base to cover the thin film transistor, the light emitting element is located on a side of the planarization layer away from the base, the planarization layer comprises a first planarization layer via, the thin film transistor comprises an active layer located on the base, a gate located on a side of the active layer away from the substrate, a source and a drain located on a side of the gate away from the substrate, a transfer electrode located on a side of the source and the drain away from the substrate, in the same sub-pixel Pxij, one of the source and the drain in one of the thin film transistors is electrically connected to the transfer electrode through the via, and the transfer electrode is electrically connected to the light emitting element through the first planarization layer via.

[0171] In the display area AA, the data line DL0 is arranged in the same layer as the transfer electrode, and the first signal line VL1 is arranged in the same layer as at least one of the active layer, the source and the drain, and the gate.

[0172] In the binding area 14, the first signal supply line VL11 and the power supply signal supply line in the power supply signal supply line group VD are arranged in the same layer as at least one of the source and the drain and the transfer electrode.

[0173] In an exemplary embodiment, the sub-pixel Pxij can further comprise at least one capacitor, a first plate of the capacitor is arranged in the same layer as the gate of the at least one thin film transistor, and in a direction perpendicular to a plane where the substrate is located, a second plate of the capacitor is located between the gate and the source and the drain of the at least one thin film transistor.

[0174] In the binding area 14, the first signal supply line VL11 is a multi-layer structure arranged in the same layer as the source and the drain, the transfer electrode, the gate, and the second plate of the capacitor, and the multi-layer structure is electrically connected.

[0175] In an exemplary embodiment, FIG. 8e shows a cross-sectional structure schematic diagram of a sub-pixel in the pixel area AA, which shows a transistor 21 and a capacitor 22 in the pixel driving circuit of the sub-pixel, and a light emitting element connected to the pixel driving circuit, wherein the transistor 21 can be a low-temperature polysilicon thin film transistor.

[0176] In some examples, as shown in FIG. 8e, in the direction Z perpendicular to the display substrate, the display area AA of the display substrate can at least include: the base 100, and the circuit structure layer 120, the light-emitting structure layer 130 and the encapsulation structure layer 140 arranged on the base 100 in sequence. The circuit structure layer 120 can at least include: pixel circuits of a plurality of sub-pixels, each pixel circuit of a sub-pixel can include a plurality of transistors and at least one capacitor. The light-emitting structure layer 130 can at least include: light-emitting elements of a plurality of sub-pixels. In other examples, a touch structure layer can be arranged on the side of the encapsulation structure layer 140 away from the base 100 to integrate a touch function.

[0177] In some examples, the circuit structure layer 120 of the display area can include: the shielding layer 200, the semiconductor layer, the first conductive layer (also referred to as the first gate metal layer), the second conductive layer (also referred to as the second gate metal layer), the third conductive layer (also referred to as the first source-drain metal layer) and the fourth conductive layer (also referred to as the second source-drain metal layer) arranged on the base 100. The first insulating layer (also referred to as the buffer layer) 101 can be arranged between the shielding layer 200 and the semiconductor layer; the second insulating layer (also referred to as the first gate insulating layer) 102 can be arranged between the semiconductor layer and the first conductive layer; the third insulating layer (also referred to as the second gate insulating layer) 103 can be arranged between the first conductive layer and the second conductive layer; the fourth insulating layer (also referred to as the interlayer insulating layer) 104 can be arranged between the second conductive layer and the third conductive layer; the fifth insulating layer (also referred to as the passivation layer) 105 and the sixth insulating layer (also referred to as the first planarization layer) 106 can be arranged between the third conductive layer and the fourth conductive layer, and the sixth insulating layer 106 can be located on the side of the fifth insulating layer 105 away from the base 100; the seventh insulating layer (also referred to as the second planarization layer) 107 can be arranged on the side of the fourth conductive layer away from the base 100. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104 and the fifth insulating layer 105 can be inorganic insulating layers, and the sixth insulating layer 106 and the seventh insulating layer 107 can be organic insulating layers. However, the present embodiment is not limited thereto. In other examples, the fifth insulating layer between the third conductive layer and the fourth conductive layer can be omitted, and only the sixth insulating layer can be arranged between the third conductive layer and the fourth conductive layer. In an exemplary embodiment, the active layer can be located in the semiconductor layer, the gate and the first plate of the capacitor can be located in the first conductive layer, the second plate of the capacitor can be located in the second conductive layer, the source and the drain can be located in the third conductive layer, and the transfer electrode can be located in the fourth conductive layer.

[0178] In some examples, as shown in FIG. 8e, the semiconductor layer of the display area can include: an active layer 210 of a transistor 21 in the pixel driving circuit. The active layer 210 of the transistor 21 can include: a first region 2101, a second region 2102, and a channel region 2100 between the first region 2101 and the second region 2102. The first conductive layer can include: a first gate 213 of the transistor 21, and a first electrode 221 of a capacitor 22. The first gate 213 of the transistor 21 can cover the channel region 2100 of the active layer 210 in the orthographic projection of the substrate 100. The second conductive layer can include: a second electrode 222 of the capacitor 22. The second electrode 222 and the first electrode 221 of the capacitor 22 can at least partially overlap in the orthographic projection of the substrate 100, for example, the two can coincide.

[0179] In some examples, as shown in FIG. 8e, the third conductive layer of the display area can include: a source 211 and a drain 212 of the transistor 21. The source 211 of the transistor 21 can be electrically connected with the first region 2101 of the active layer 210, and the drain 212 can be electrically connected with the second region 2102 of the first active layer 210. The fourth conductive layer can at least include: a transfer electrode 241. The transfer electrode 241 can be electrically connected with the drain 212 of the transistor 21 in the pixel driving circuit through the via hole of the fifth insulating layer 105 and the sixth insulating layer 106. The present example can realize the electrical connection between the pixel driving circuit and the light emitting element through the transfer electrode 241.

[0180] In some examples, as shown in FIG. 8e, the light emitting structure layer 130 can include: a pixel definition layer 134 and a plurality of light emitting elements. For example, each light emitting element can include: a first electrode 131 (which can be referred to as an anode) and a second electrode 133 (which can be referred to as a cathode) stacked with an organic light emitting layer 132. The first electrode 131 of the light emitting element can be an anode, and the first electrode 131 can be disposed on the seventh insulating layer 107 and electrically connected with the transfer electrode 241 through the via hole of the seventh insulating layer 107. The pixel definition layer 134 is disposed on the first electrode 131 and the seventh insulating layer 107, and the pixel definition layer 134 can be provided with a plurality of pixel openings, and each pixel opening can expose at least part of the surface of the corresponding first electrode 131. At least part of the organic light emitting layer 132 can be disposed in one pixel opening and connected with the corresponding first electrode 131. The second electrode 133 can be disposed on the organic light emitting layer 132 and connected with the organic light emitting layer 132. The organic light emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0181] In some examples, the organic light emitting layer 132 of the light emitting element can include at least one emitting layer (EML) and at least one of a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage driving of the first electrode 131 and the second electrode 133, the organic material can emit light according to the required gray scale by utilizing the light emitting characteristics of the organic material.

[0182] In some examples, the light emitting layers of light emitting elements of different colors can be different. For example, the red light emitting element includes a red light emitting layer, the green light emitting element includes a green light emitting layer, and the blue light emitting element includes a blue light emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light emitting layer can adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light emitting layer can adopt a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by one process (one evaporation process or one inkjet printing process), and the isolation can be realized by the surface step of the formed film layer or by surface treatment and the like. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light emitting layer can be prepared and formed by using a fine metal mask (FMM) or an open mask evaporation, or by using an inkjet process.

[0183] In some examples, as shown in FIG. 8e, the encapsulation structure layer 140 can include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked. Among them, the first encapsulation layer 141 and the third encapsulation layer 143 can be made of inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic material has high compactness and can prevent the invasion of water, oxygen, etc. The second encapsulation layer 142 can be arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to prevent external water vapor from entering the light emitting element. The second encapsulation layer 142 can be made of organic materials, such as high molecular materials containing desiccant or high molecular materials that can block water vapor, etc., or high molecular resins, etc. to perform planarization treatment on the surface of the display substrate, and can relieve the stress of the first encapsulation layer 141 and the third encapsulation layer 143, and can also include water-absorbing materials such as desiccant to absorb water, oxygen, etc. substances invading the inside. However, the present embodiment is not limited thereto. For example, the encapsulation structure layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0184] In the example embodiment, the difference between FIG. 8a and FIG. 8b is that in FIG. 8a, the first power signal supply line VDD0 and the second power signal supply line VSS0 are arranged in the same layer as the source and the drain, and in FIG. 8b, the first power signal supply line VDD0 and the second power signal supply line VSS0 are arranged in the same layer as the source and the drain and the transfer electrode.

[0185] In the example embodiment, in FIGS. 8a to 8d:

[0186] In the first area A1: the first signal supply line VL11 can be a multi-layer structure arranged in the same layer as the gate and the second plate of the second capacitor, the multi-layer structure can be electrically connected through a via, or the multi-layer structure is electrically connected in a lap joint manner; the second power connection line PL21 can be arranged in the same layer as at least one of the source and the drain and the transfer electrode, as shown in FIG. 9a, which is a schematic diagram of one kind of cross-sectional structure at C1-C1 position, the second power connection line PL21 can be arranged in the same layer as the source and the drain; FIG. 9b shows another schematic diagram of a cross-sectional structure at C1-C1 position, the second power connection line PL21 can be a multi-layer structure arranged in the same layer as the source and the drain and the transfer electrode, and the multi-layer structure can be electrically connected through a via; FIG. 9c shows another schematic diagram of a cross-sectional structure at C1-C1 position, the second power connection line PL21 can be a multi-layer structure arranged in the same layer as the source and the drain and the transfer electrode, and the multi-layer structure is electrically connected in a lap joint manner;

[0187] In the second region A2 and the third region A3 (regions where the gate driving circuit signal line 40 and the power signal supply line in the power signal supply line group 50 do not overlap): the gate driving circuit signal line 40 and the first signal supply line VL11 can be a single-layer or multi-layer structure arranged in the same layer as at least one of the gate, the second plate of the capacitor, the source and the drain, the transfer electrode, the multi-layer structure can be electrically connected through a via hole or in a lap joint manner, wherein FIGS. 9d-9f show several cross-sectional structure schematic diagrams of the C2-C2 position in FIGS. 8a-8b, 8d, and FIGS. 9g and 9h show several cross-sectional structure schematic diagrams of the C3-C3 position in FIGS. 8a-8d; as shown in FIGS. 9d and 9g, the gate driving circuit signal line 40 can be a multi-layer structure arranged in the same layer as the gate and the second plate of the capacitor; as shown in FIGS. 9e and 9h, the gate driving circuit signal line 40 can be a multi-layer structure arranged in the same layer as the gate, the second plate of the capacitor, the source and the drain; as shown in FIG. 9f, the gate driving circuit signal line 40 can be a multi-layer structure arranged in the same layer as the gate, the second plate of the capacitor, the source and the drain, the transfer electrode; as shown in FIG. 9d, the first signal supply line VL11 can be a single-layer structure arranged in the same layer as the source and the drain; as shown in FIG. 9e, the first signal supply line VL11 can be a multi-layer structure arranged in the same layer as the gate, the second plate of the capacitor, the source and the drain; as shown in FIG. 9f, the first signal supply line VL11 can be a multi-layer structure arranged in the same layer as the gate, the second plate of the capacitor, the source and the drain, the transfer electrode;

[0188] In the area where the gate driving circuit signal line 40 and the power signal supply lines in the power signal supply line group 50 overlap: FIG. 9i shows a cross-sectional structure schematic diagram of the C4-C4 position in FIG. 8a, FIG. 9j shows a cross-sectional structure schematic diagram of the C5-C5 position in FIG. 8a, the gate driving circuit signal line 40 can be a multi-layer structure (the multi-layer structure can be connected through a via) arranged in the same layer as the gate and the second plate of the capacitor, and the first power signal supply line VDD0 and the second power signal supply line VSS0 in the power signal supply line group 50 can be a single-layer structure arranged in the same layer as the source and the drain; FIG. 9k shows a cross-sectional structure schematic diagram of the C4-C4 position in FIG. 8b-8d, FIG. 9L shows a cross-sectional structure schematic diagram of the C5-C5 position in FIG. 8b-8d, the gate driving circuit signal line 40 can be a multi-layer structure (the multi-layer structure can be connected through a via) arranged in the same layer as the gate and the second plate of the capacitor, and the first power signal supply line VDD0 and the second power signal supply line VSS0 in the power signal supply line group 50 can be a multi-layer structure (the multi-layer structure can be electrically connected through a lap joint) arranged in the same layer as the source and the drain and the transfer electrode; FIG. 9m shows another cross-sectional structure schematic diagram of the C4-C4 position in FIG. 8b-8d, FIG. 9n shows another cross-sectional structure schematic diagram of the C5-C5 position in FIG. 8b-8d, the gate driving circuit signal line 40 can be a multi-layer structure (the multi-layer structure can be connected through a via) arranged in the same layer as the gate and the second plate of the capacitor, and the first power signal supply line VDD0 and the second power signal supply line VSS0 in the power signal supply line group 50 can be a multi-layer structure (the multi-layer structure can be electrically connected through a via) arranged in the same layer as the source and the drain and the transfer electrode.

[0189] In an example embodiment, the binding area 14 can include a driving chip area 141, a third fan-out area 142 and a binding electrode area 143 arranged in sequence along the first frame area B1 pointing to the display area AA, wherein the integrated circuit pin group 61 is located in the driving chip area 141, the binding pin group is located in the binding electrode area 143, and the third fan-out area 142 is provided with a plurality of pin connection lines 201, and the integrated circuit pins in the integrated circuit pin group 61 are electrically connected to the driving pins in the driving pin group 53 through the pin connection lines 201.

[0190] In an example embodiment, in the structures shown in FIGS. 7a-7c and 8a-8c, in the binding area 14, a plurality of first gate driving circuit signal lines 41 are bent in the direction pointing to the display area AA along the third frame area B3, and are electrically connected to the integrated circuit pin group 61 closest to the first power signal supply line group VD1; a plurality of second gate driving circuit signal lines 42 are bent in the direction pointing to the display area AA along the fourth frame area B4, and are electrically connected to the integrated circuit pin group 61 closest to the second power signal supply line group VD2;

[0191] In the binding area 14, at least part of the structure of the first gate drive circuit signal line 41 at least partially overlaps the orthogonal projection of the power signal supply line in the first power signal supply line group VD1 on the substrate, the first gate drive circuit signal line 41 and the power signal supply line in the first power signal supply line group VD1 are located in different conductive layers at the overlapping area; at least part of the structure of the second gate drive circuit signal line 42 at least partially overlaps the orthogonal projection of the power signal supply line in the second power signal supply line group VD2 on the substrate, the plurality of second gate drive circuit signal lines 42 and the power signal supply line in the second power signal supply line group VD2 are located in different conductive layers at the overlapping area.

[0192] In the exemplary embodiment, as shown in FIG. 8c, at least part of the structure of the first gate drive circuit signal line 41 between the bending position M3 and the integrated circuit pin group 61 connected thereto at least partially overlaps the orthogonal projection of the power signal supply line in the first power signal supply line group VD1 on the substrate, the first gate drive circuit signal line 41 and the power signal supply line in the first power signal supply line group VD1 are located in different conductive layers at the overlapping area; at least part of the structure of the second gate drive circuit signal line 42 between the bending position M3 and the corresponding integrated circuit pin group 61 at least partially overlaps the orthogonal projection of the power signal supply line in the second power signal supply line group VD2 on the substrate, the plurality of second gate drive circuit signal lines 42 and the power signal supply line in the second power signal supply line group VD2 are located in different conductive layers at the overlapping area.

[0193] In the structure shown in FIG. 7d and FIG. 8d, the plurality of binding pin groups can further include at least one gate drive circuit pin group 56, the at least one gate drive circuit pin group 56 can include a first gate drive circuit pin group 561 and a second gate drive circuit pin group 562;

[0194] In the first direction X, the first first signal pin group 541 is located on the side of the first gate drive circuit pin group 561 away from the first power pin group 501, and the second first signal pin group 542 is located on the side of the second gate drive circuit pin group 562 away from the second power pin group 502;

[0195] The first gate drive circuit signal line 41 is arranged to be electrically connected with the corresponding first gate drive circuit pin in the first gate drive circuit pin group 561, and the second gate drive circuit signal line 42 is arranged to be electrically connected with the corresponding second gate drive circuit pin in the second gate drive circuit pin group 562, which can reduce the wiring distance between the gate drive circuit signal line 40 and the gate drive circuit pin group 56, and reduce the resistance of the gate drive circuit signal line 40.

[0196] In the binding area 14, at least part of the structure in the gate drive circuit signal line 40 and the power signal supply line in the power signal supply line group AD have a non-overlapping area.

[0197] In an example embodiment, in the binding area 14, in the area where the gate drive circuit signal line 40 overlaps with the power signal supply line, the gate drive circuit signal line 40 can be a multi-layer structure arranged in the same layer as the gate, the second plate of the capacitor, as shown in FIGS. 9i-9n; in at least part of the area where the gate drive circuit signal line 40 does not overlap with the power signal supply line, the gate drive circuit signal line 40 can be a multi-layer structure arranged in the same layer as the source and drain, the switching electrode, the gate, and the second plate of the capacitor (the structure of the gate drive circuit signal line 40 can be as shown in FIG. 9f), and the multi-layer structure can be electrically connected. The gate drive circuit signal line 40 arranged as a multi-layer structure can reduce resistance and provide display effects of the display substrate.

[0198] In an example embodiment, in the direction from the display area AA to the first frame area B1, the first frame area B1 includes the first fan-out area 11, the bending area 12, the second fan-out area 13, and the binding area 14 arranged in sequence.

[0199] In the first fan-out area 11, the first signal supply line VL11, the plurality of first gate drive circuit signal lines 41, and the plurality of second gate drive circuit signal lines 42 are multi-layer structures arranged in the same layer as the gate and the second plate of the capacitor, and the multi-layer structures are electrically connected; as shown in FIGS. 9a-9c;

[0200] In the second fan-out area 13, the first signal supply line, the plurality of first gate drive circuit signal lines 41, and the plurality of second gate drive circuit signal lines 42 are arranged in the same layer as at least one of the gate, the second plate of the capacitor, the source and drain, and the switching electrode (as shown in FIGS. 9d-9f), and in the first direction X, on the same side of the plurality of drive pin groups 53, the first signal supply line VL11 and the gate drive circuit signal line 40 are located on the side of the power signal supply line group 50 away from the plurality of drive pin groups 53.

[0201] In the example embodiment, the same power signal providing line group 50 can include a first power signal providing line VDD0 and a second power signal providing line VSS0, the first fan-out area 11 is further provided with at least one first power connection line PL11, at least one second power connection line PL21, and a plurality of first data connection lines DL1, the bending area 12 is further provided with at least one first power connection structure PL12, at least one second power connection structure PL22, and a plurality of second data connection lines DL2, the second fan-out area 13 is further provided with a plurality of third data connection lines DL3, and the first power signal providing line VDD0 and the second power signal providing line VSS0 are extended to the second fan-out area 13 by the binding area 14;

[0202] The first power connection structure PL12 is configured to electrically connect the first power connection line PL11 with the corresponding first power signal providing line VDD0, and the second power connection structure PL22 is configured to electrically connect the second power connection line PL21 with the corresponding second power signal providing line VSS0.

[0203] The plurality of data lines DL0, the plurality of first data connection lines DL1, the plurality of second data connection lines DL2, and the plurality of third data connection lines DL3 are one-to-one corresponding, and the data line DL0 is electrically connected with the corresponding integrated circuit pin in the corresponding integrated circuit binding pin group 61 through the corresponding first data connection line DL1, the corresponding second data connection line DL2, and the corresponding third data connection line DL3.

[0204] In the example embodiment, in the first fan-out area 11, the plurality of first data connection lines DL1 are a multi-layer structure arranged in the same layer as the gate and the second plate of the capacitor, the first power connection line PL11 and the second power connection line PL21 are a multi-layer structure arranged in the same layer as the source and the drain, and the switching electrode, and the multi-layer structures are electrically connected, as shown in FIGS. 9b and 9c.

[0205] In the bending area 12, the third data connection line DL3, the first power connection structure PL12, the second power connection structure PL22, the first signal providing line VL11, and the gate drive circuit signal line 40 are arranged in the same layer as the source and the drain, and are arranged with intervals between different signal lines.

[0206] In the second fan-out area 13, the third data connection line DL3 is arranged in the same layer as at least one of the gate and the second plate of the capacitor.

[0207] In the structure shown in FIG. 7a, FIG. 7c and FIG. 7d, in the bending area 12, the size of the first power supply connection structure PL12 along the first direction X is consistent with the size of the third data connection line DL3 along the first direction X, and the first power supply connection structure PL12 and the third data connection line DL3 can be arranged alternately; in the structure shown in FIG. 7b, in the bending area 12, the size of the plurality of first power supply connection structures PL12 along the first direction X is greater than the size of the third data connection line DL3 along the first direction X.

[0208] In the structure shown in FIG. 7c, two power supply signal providing line groups 50 are arranged on both sides of each driving pin group 53, in the first fan-out area 11, one first power supply connection line PL11 corresponds to one driving pin group 53 and the first power supply signal providing line VDD0 on both sides of the driving pin group 53, and is electrically connected with the corresponding first power supply signal providing line VDD0, without being connected with the first power supply signal providing line VDD0 on both sides of other driving pin groups 53; in the structure shown in FIG. 7d, only two power supply signal providing line groups 50 (a first power supply signal providing line group 501 and a second power supply signal providing line group 502) are arranged in the first frame area B1, in the first fan-out area 11, the first power supply connection line PL11 is electrically connected with the first power supply signal providing line VDD0 in the first power supply signal providing line group 501 and the second power supply signal providing line group.

[0209] In the second fan-out area 13, the third data connection line DL3 can be a multi-layer structure arranged in the same layer as the gate electrode, the second plate of the capacitor, the source electrode and the drain electrode, and the switching electrode (as shown in FIG. 9f), and the multi-layer structure is electrically connected.

[0210] In the example embodiment, the types of the first signal pins in the two first signal pin groups 54 are the same, the types of the first signal providing lines VL11 in the first and second first signal providing line groups VL101 and VL102 are the same, and the same first signal line VL1 is electrically connected with the first signal providing lines VL11 of the corresponding types in the first and second first signal providing line groups VL101 and VL102.

[0211] In the example embodiment, the plurality of first signal lines VL1 can include a plurality of initial signal lines Vinit, at least one first signal providing line group VL10 includes at least one initial signal providing line group Vinit0, at least one initial signal pin group is included in at least one first signal pin group 54, and at least one initial signal pin is included in the initial signal pin group.

[0212] The initial signal providing lines in the initial signal providing line group Vinit0 and the categories of the initial signal lines Vinit include at least one, and the categories of the initial signal providing lines, the categories of the initial signal lines, and the categories of the initial signal pins correspond one-to-one, and the initial signal providing lines are electrically connected to the initial signal lines of the corresponding categories and the initial signal pins of the corresponding categories.

[0213] In the exemplary embodiments, the categories of the initial signal providing lines in the initial signal providing line group Vinit0 and the initial signal lines Vinit can include n, n being a positive integer greater than or equal to 1, as shown in FIG. 10a, the categories of the initial signal providing lines in the initial signal providing line group Vinit0 can include a first initial signal providing line Vinit01, a second initial signal providing line Vinit02, and a third initial signal providing line Vinit03.

[0214] In the exemplary embodiments, as shown in FIGS. 10a to 10c, the first fan-out area 11 can further include at least one first signal connection structure L1; at least one first signal pin is included in the same first signal pin group 54, the categories of the first signal providing lines VL11 and the first signal lines VL1 include at least one, the categories of the first signal providing lines VL11, the categories of the first signal lines VL1, and the categories of the first signal pins correspond one-to-one, and the first signal providing lines VL11 are electrically connected to the first signal lines VL1 of the corresponding categories and the first signal pins of the corresponding categories;

[0215] In the first border area B1, among the at least one first signal providing line VL11, the number of the first signal providing lines VL11 of the same category is at least two, and in the first fan-out area 11, the at least two first signal providing lines VL11 of the same category are electrically connected through the corresponding first signal connection structure L1, in the area where the first signal connection structure L1 is connected to the corresponding first signal providing line VL11, the first signal providing line is arranged in the same layer as one of the gate and the second plate of the capacitor, the first signal connection structure L1 is arranged in the same layer as the other of the gate and the second plate of the capacitor, and the first signal connection structures L1 corresponding to the first signal providing lines VL11 of different categories are arranged at intervals.

[0216] As shown in FIG. 10a and FIG. 10b, which are schematic diagrams of an enlarged structure of the M2 position in FIG. 8c, the first signal supply line VL11 can include a first initial signal supply line Vinit01, a second initial signal supply line Vinit02, and a third initial signal supply line Vinit03. In the first bezel area B1, the number of the first initial signal supply line Vinit01, the second initial signal supply line Vinit02, and the third initial signal supply line Vinit03 is two, respectively. Correspondingly, the first signal connection structure L1 can include a first initial signal connection structure Vinit01L, a second initial signal connection structure Vinit02L, and a third initial signal connection structure Vinit03L. Two first initial signal supply lines Vinit01 are connected in parallel through the first initial signal connection structure Vinit01L, two second initial signal supply lines Vinit02 are connected in parallel through the second initial signal connection structure Vinit02L, and two third initial signal supply lines Vinit03 are connected in parallel through the third initial signal connection structure Vinit03L. The first initial signal connection structure Vinit01L can be electrically connected to the two first initial signal supply lines Vinit01 through the via hole VM. The second initial signal connection structure Vinit02L can be electrically connected to the two second initial signal supply lines Vinit02 through the via hole VM. The third initial signal connection structure Vinit03L can be electrically connected to the two third initial signal supply lines Vinit03 through the via hole VM. FIG. 10c is a schematic diagram of a cross-sectional structure of the E1-E1 position in FIG. 10a. FIG. 10d is a schematic diagram of a cross-sectional structure of the E1-E1 position in FIG. 10b.

[0217] In the exemplary embodiments, the first signal supply line VL11 of the same type in the bezel area is arranged in a structure of at least two parallel lines, which can reduce the resistance of the first signal supply line VL11.

[0218] In the structure shown in FIG. 10a, the number of the first signal supply line VL11 of the same type in the first type of bezel area B01 (which can include the third bezel area B3 and the fourth bezel area B4) and the first bezel area B1 is two. In the structure shown in FIG. 10b, the number of the first signal supply line VL11 of the same type in the first type of bezel area B01 (which can include the third bezel area B3 and the fourth bezel area B4) is one, and the number of the first signal supply line VL11 of the same type in the first bezel area B1 is two, which can save the space of the first type of bezel area B01.

[0219] The first signal supply lines VL11 shown in FIGS. 10b-10d are a first initial signal supply line Vinit01, a second initial signal supply line Vinit02, and a third initial signal supply line Vinit03. Correspondingly, the first signal lines VL1 in the display area AA can include a first initial signal line Vinit1, a second initial signal line Vinit2, and a third initial signal line Vinit3 (i.e., the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 shown in FIGS. 6b and 6c). The first initial signal supply line Vinit01 can be electrically connected to a plurality of first initial signal lines Vinit1, the second initial signal supply line Vinit02 can be electrically connected to a plurality of second initial signal lines Vinit2, and the third initial signal supply line Vinit03 can be electrically connected to a plurality of third initial signal lines Vinit3.

[0220] In an example embodiment, the pixel driving circuits of the plurality of sub-pixels can form a plurality of rows and a plurality of columns. Each first signal line VL1 can be electrically connected to at least part of the pixel driving circuits in at least one row of pixel driving circuits. Each data line DL0 can be electrically connected to at least part of the pixel driving circuits in at least one column of pixel driving circuits.

[0221] In an example embodiment, as shown in FIG. 7a, the display area AA further includes a plurality of first signal connection lines SVL1. The first signal connection lines SVL1 are disposed in the same layer as the relay electrodes. The plurality of first signal connection lines SVL1 are arranged at intervals along the first direction X and extend along the second direction Y. The types of the plurality of first signal connection lines SVL1 correspond one-to-one to the types of the plurality of first signal lines VL1. The first signal connection lines SVL1 are electrically connected to the plurality of first signal lines VL1 of the corresponding types through vias. The same first signal line VL1 is electrically connected to the plurality of first signal connection lines SVL1 of the corresponding types through vias. The plurality of first signal connection lines SVL1 of the same type and the plurality of first signal lines VL1 of the same type in the display area AA are connected to each other to form a grid-like structure, thereby reducing the voltage drop of the first signal lines VL1 and improving display uniformity.

[0222] In an example embodiment, the integrated circuit pins in the integrated circuit pin group 61 and the bonding pins in the bonding pin group can be a multi-layer structure disposed in the same layer as the source and drain electrodes and the relay electrodes. The multi-layer structure is electrically connected, which can reduce the resistance of the integrated circuit pins and the bonding pins.

[0223] In an example embodiment, the third bezel area B3 can further include a plurality of first gate driving circuits GOA1, and the fourth bezel area B4 can further include a plurality of second gate driving circuits GOA2.

[0224] The plurality of first gate driving circuits GOA1 can be arranged along a direction in which the third bezel area B3 extends, and the plurality of second gate driving circuits GOA2 can be arranged along a direction in which the fourth bezel area B4 extends. The first gate driving circuit signal line 41 is further electrically connected to the plurality of first gate driving circuits GOA1, and the second gate driving circuit signal line 42 is further electrically connected to the plurality of second gate driving circuits GOA2.

[0225] In the first direction X, in the third bezel area B3, the at least one first signal supply line VL11 is located on a side of the plurality of first gate driving circuits GOA1 away from the display area AA, and in the fourth bezel area B4, the at least one first signal supply line VL11 is located on a side of the plurality of second gate driving circuits GOA2 away from the display area AA.

[0226] In an example embodiment, the display area AA further includes a plurality of scan signal lines SL, the plurality of scan signal lines SL extend along the first direction X and are arranged along the second direction Y.

[0227] The first gate driving circuit GOA1 and the second gate driving circuit GOA2 are configured to be electrically connected to the corresponding scan signal line SL, and the scan signal line SL can be disposed in the same layer as at least one of the gate and the second plate of the capacitor.

[0228] In an example embodiment, the plurality of scan signal lines SL can include a first reset control line RST1, a second reset control line RST2, an emission control line EML, a first scan line GL, and a third reset control line RST3 as shown in FIGS. 6a to 6c, and in the first type of bezel area B01, each gate driving circuit GOA can be configured to supply a signal to one of the first reset control line RST1, the second reset control line RST2, the emission control line EML, the first scan line GL, and the third reset control line RST3.

[0229] In an example embodiment, the gate driving circuit signal line 40 can include a clock signal line (for example, which can include a CK signal line and a CB signal line) and a start signal line (for example, which can include an STV signal line), and the gate driving circuit signal line 40 is configured to supply a signal to the gate driving circuit GOA.

[0230] The display substrate can include a plurality of gate driving circuits GOA, a plurality of first gate driving circuit signal lines 41, a plurality of second gate driving circuit signal lines 42, a plurality of first signal supply lines VL11, and a plurality of second signal supply lines VL12.

[0231] The substrate comprises a display area AA, a first frame area B1 and a first type frame area B01; in the first direction X, the first type frame area B01 is located on at least one side of the display area AA; in the second direction Y, the first frame area B1 is located on one side of the display area AA, and the first frame area B1 is provided with a binding area 14, and the first direction X intersects the second direction Y;

[0232] A plurality of sub-pixels Pxij are located in the display area AA;

[0233] A plurality of data lines DL0 are located in the display area AA and electrically connected to the plurality of sub-pixels Pxij, and the plurality of data lines DL0 extend along the second direction Y and are arranged at intervals along the first direction X;

[0234] A plurality of first signal lines VL1 are located in the display area AA and extend along the first direction X and are arranged along the second direction Y, and the plurality of first signal lines VL1 are electrically connected to the plurality of sub-pixels Pxij; in an exemplary embodiment, the first signal line VL1 and the data line DL0 can be located in different conductive layers;

[0235] At least one first signal providing line group VL10 is located in the first type frame area B01 and extends to the binding area 14 in the first frame area B1, and the first signal providing line VL11 in the first signal providing line group VL10 is arranged to be electrically connected to at least one first signal line VL1 in the plurality of first signal lines VL1;

[0236] At least one integrated circuit pin group 61 is located in the binding area 14, and at least part of the integrated circuit pins in the integrated circuit pin group 61 are arranged to be electrically connected to the plurality of data lines DL0;

[0237] In the binding area 14, in the first direction X, the main part of the at least one first signal providing line group VL10 is located on at least one side of the at least one integrated circuit pin group 61, and at least part of the first signal providing line VL11 has a multi-layer structure, and the multi-layer structure can be electrically connected.

[0238] In an exemplary embodiment, at least part of the first signal providing line VL11 has a multi-layer structure electrically connected, which can reduce the resistance of the first signal providing line VL11 and avoid the phenomenon of horizontal lines in the display area due to the large resistance of the first signal providing line VL11.

[0239] In an exemplary embodiment, the first type frame area B01 is further provided with a plurality of gate drive circuit signal lines 40, and the plurality of gate drive circuit signal lines 40 extend to the binding area 14 in the first frame area B1;

[0240] In the binding area 14, in the first direction X, the main body part of the gate drive circuit signal line 40 is located at least on one side of the at least one integrated circuit pin group 61, on the same side of the first center line O1-O1, the first signal supply line VL11 in the first signal supply line group VL10, the gate drive circuit signal line is electrically connected to the integrated circuit pin group 61 farthest from the first center line, and the first center line O1-O1 is the center line of the first frame area B1 extending along the second direction Y.

[0241] In the binding area 14, at least part of the structure of at least part of the gate drive circuit signal line 40 is a multilayer structure, and the multilayer structure can be electrically connected.

[0242] In the example embodiment, in the binding area 14, at least part of the structure of at least part of the gate drive circuit signal line 40 is a multilayer structure located between the source-drain metal layer and the gate metal layer, which can reduce the resistance of the gate drive circuit signal line 40.

[0243] In the example embodiment, the binding area 14 further comprises at least one power supply signal supply line group 50, and in the first direction X, the at least one power supply signal supply line group 50 is located at least on one side of the at least one integrated circuit pin group 61.

[0244] In the binding area 14, on the same side of the first center line O1-O1 in the first direction X, the gate drive circuit signal line 40 and the first signal supply line VL11 are bent in the direction of the display area AA along the first type of frame area B01, and are electrically connected to the integrated circuit pin group 61 farthest from the first center line O1-O1. At least part of the structure of the gate drive circuit signal line 40 and the first signal supply line VL11 (for example, it can be at least part of the structure between the bending position M3 of the gate drive circuit signal line 40 and the first signal supply line VL11 in FIG. 12 and the integrated circuit pin group 61 connected thereto), and the orthographic projection of the power supply signal supply line group 50 on the substrate at least partially overlaps, and the gate drive circuit signal line 40 and the first signal supply line VL11 and the power supply signal supply line in the power supply signal supply line group 50 are located in different conductive layers in the overlapping area.

[0245] In the example embodiment, in the direction perpendicular to the plane where the substrate is located, the display substrate at least comprises a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer arranged in sequence on one side of the substrate.

[0246] In the display area AA, the data line DL0 is located in the second source-drain metal layer, and the first signal line VL1 can be located in at least one conductive layer of the first gate metal layer, the second gate metal layer, and the first source-drain metal layer.

[0247] In the binding area 14, the first signal line VL1 and the gate drive circuit signal line 40 can be located in at least one of the first gate metal layer, the second gate metal layer, and the first source-drain metal layer.

[0248] In an example embodiment, at least part of the gate of the above-mentioned transistor can be located in the first gate metal layer, the second plate of the capacitor can be located in the second gate metal layer, the source and the drain can be located in the first source-drain metal layer, and the transfer electrode can be located in the second source-drain metal layer. In an example embodiment, the display substrate can further include a third gate metal layer and a third source-drain metal layer, the third gate metal layer can be located between the second gate metal layer and the first source-drain metal layer in a direction perpendicular to the plane in which the substrate is located, and the third source-drain metal layer can be located on a side of the second source-drain metal layer away from the substrate, and the third source-drain metal layer can be provided with at least part of the gate of the transistor.

[0249] In an example embodiment, in 12, the cross-sectional structure schematic diagram of the C1-C1 position can be as shown in FIGS. 9a and 9c, the cross-sectional structure schematic diagram of the C2-C2 position can be as shown in FIGS. 9d-9f, the cross-sectional structure schematic diagram of the C3-C3 position can be as shown in FIGS. 9g-9h, the cross-sectional structure schematic diagram of the C4-C4 position can be as shown in FIGS. 9k and 9m, and the cross-sectional structure schematic diagram of the C5-C5 position can be as shown in FIGS. 9L and 9n.

[0250] In an example embodiment, in the direction from the display area AA to the first frame area B1, the first frame area B1 can include the first fan-out area 11, the bending area 12, the second fan-out area 13, and the binding area 14 arranged in sequence.

[0251] In the first fan-out area 11 and the binding area 14, at least part of the region where the first signal supply line VL11 and the gate drive circuit signal line 40 overlap the power supply signal supply line, the first signal supply line VL11 and the gate drive circuit signal line 40 are in a multi-layer structure located in the first gate metal layer and the second gate metal layer, and the multi-layer structure can be electrically connected, as shown in FIGS. 9a-9c, 9k-9n.

[0252] In the second fan-out area 13 and the binding area 14, at least part of the region where the first signal supply line VL11 and the gate drive circuit signal line 40 do not overlap the power supply signal supply line, the first signal supply line VL11 and the gate drive circuit signal line 40 are in a multi-layer structure located in the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer, and the multi-layer structure can be electrically connected, as shown in FIG. 9f.

[0253] In an example embodiment, the power supply signal supply lines in the power supply signal supply line group 50 are extended from the binding area 14 to the second fan-out area 13.

[0254] In the second fan-out area 13 and at least part of the binding area 14, the power signal supply lines in the power signal supply line group 50 can be a multi-layer structure located in the first source-drain metal layer and the second source-drain metal layer, and the multi-layer structure can be electrically connected, as shown in FIGS. 9k-9n.

[0255] In an example embodiment, the power signal supply lines in the power signal supply line group 50 can be a three-layer structure located in the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer.

[0256] In an example embodiment, in the first fan-out area 11, at least part of the area where the first signal supply line VL11 and the gate drive circuit signal line 40 overlap with the power signal supply line, the first signal supply line VL11 and the gate drive circuit signal line 40 can be a multi-layer structure located in the first gate metal layer, the second gate metal layer, and the third gate metal layer, and the multi-layer structure can be electrically connected.

[0257] In an example embodiment, in the second fan-out area 13, at least part of the area where the first signal supply line VL11 and the gate drive circuit signal line 40 do not overlap with the power signal supply line, the first signal supply line VL11 and the gate drive circuit signal line 40 can be a multi-layer structure located in the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the third gate metal layer, and the multi-layer structure can be electrically connected.

[0258] In an example embodiment, the electrical connection between the above-mentioned multi-layer structures can be that the multi-layer structures are electrically connected through vias, or the multi-layer structures are electrically connected through a lapping method.

[0259] In an example embodiment, the first area A1, the second area A2, and the third area A3 in FIG. 12 are consistent with the structures of the first area A1, the second area A2, and the third area A3 shown in FIGS. 8a-8d, and will not be described again here.

[0260] In an example embodiment, the first signal supply line VL11 can be an initial signal supply line Vinit0, or other constant voltage signal lines, for example, can be a second power supply line VSS.

[0261] In an example embodiment, the power pin group 50 can include a first power pin 51 and a second power pin 52, the first power pin 51 is configured to be connected to the first power signal supply line VDD0, and the second power pin 52 is configured to be connected to the second power signal supply line VSS0.

[0262] In the example embodiments as shown in FIGS. 8a-8d and 12, the binding pin group can further include a test pin group 55, the driving chip area 141 can further be provided with a test circuit 71, the test circuit 71 can be electrically connected to the corresponding test pin in the test pin group 55 through a test lead 81, and the at least partial gate driving circuit signal line 40 can be electrically connected to the corresponding test pin in the test pin group 55 through the test lead 81.

[0263] In the example embodiments, the display substrate can be an O1-O1 symmetric structure (can be substantially symmetric).

[0264] The display device provided by the embodiments of the present disclosure can be as shown in FIG. 13, and can include a display substrate.

[0265] The display substrate is the display substrate provided by any one of the preceding embodiments, and has similar principles and effects, which will not be described here again.

[0266] In an example embodiment, the display device can be a liquid crystal display (LCD) or an organic light emitting diode (OLED) or a light emitting diode (LED) display device. The display device can be a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function.

[0267] The display substrate and the display device provided by the embodiments of the present disclosure are provided with a plurality of binding pin groups and at least one integrated circuit pin group in the binding area, at least one first signal providing line group in the first type of frame area, the first signal providing line in the first type of signal providing line group extending to the binding area, at least one first signal pin group being located on at least one side of the at least one integrated circuit pin group in the first direction, the at least one first signal pin group corresponding to the at least one first signal providing line group one by one, the first signal pin group and the corresponding first signal providing line group being located on the same side of the at least one integrated circuit pin group, and at least part of the first signal pins in the at least one first signal pin group being arranged to be electrically connected with at least part of the first signal providing lines in the corresponding first signal providing line group. The display substrate provided by the embodiments of the present disclosure can directly electrically connect the first signal providing line with the first signal pin group, so as to reduce the resistance of the first signal providing line in the binding area, and to solve the technical problem that the display area has horizontal lines due to the large resistance of the first signal providing line to a certain extent.

[0268] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0269] In the case of no conflict, the features in the embodiments of the present disclosure, i.e., the embodiments, can be combined with each other to obtain new embodiments.

[0270] Although the embodiments disclosed by the embodiments of the present disclosure are as above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the embodiments of the present disclosure, and is not used to limit the embodiments of the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the implementation form and details without departing from the spirit and scope of the embodiments of the present disclosure, but the patent protection scope of the embodiments of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, comprising: a substrate comprising a display area, a first frame area and a first type frame area; in a first direction, the first type frame area is located at least one side of the display area; in a second direction, the first frame area is located at one side of the display area, the first frame area is provided with a binding area, the first direction intersects the second direction; a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area and electrically connected with the plurality of sub-pixels, the plurality of data lines extend along the second direction and are arranged at intervals along the first direction; a plurality of first signal lines located in the display area and extending along the first direction and arranged along the second direction, the plurality of first signal lines are electrically connected with the plurality of sub-pixels; at least one first signal providing line group located in the first type frame area and extending to the binding area in the first frame area, the first signal providing lines in the first signal providing line group are arranged to be electrically connected with at least one first signal line in the plurality of first signal lines; a plurality of binding pin groups and at least one integrated circuit pin group located in the binding area, the plurality of binding pin groups comprise at least one first signal pin group; at least part of the integrated circuit pins in the integrated circuit pin group are arranged to be electrically connected with the plurality of data lines; in the first direction, the at least one first signal pin group is located at least one side of the at least one integrated circuit pin group, the at least one first signal pin group corresponds to the at least one first signal providing line group one by one, the at least one first signal pin group and the corresponding first signal providing line group are located on the same side of the at least one integrated circuit pin group, and at least part of the first signal pins in the at least one first signal pin group are arranged to be electrically connected with at least part of the first signal providing lines in the corresponding first signal providing line group.

2. The display substrate according to claim 1, in the second direction, the plurality of binding pin groups are located on the side of the integrated circuit pin group away from the display area; the plurality of binding pin groups further comprise at least one driving pin group and at least one power pin group, the at least one driving pin group corresponds to the at least one integrated circuit pin group one by one, and the at least one driving pin group is electrically connected with the corresponding integrated circuit pin group; in the first direction, at least one power pin group is arranged between the at least one first signal pin group and the at least one driving pin group.

3. The display substrate according to claim 2, the first type frame area is further provided with a plurality of gate drive circuit signal lines, the plurality of gate drive circuit signal lines extend to the first frame area, in the same first type frame area, in the first direction, the first signal providing line group is located on the side of the plurality of gate drive circuit signal lines away from the display area. 4.The display substrate of claim 3, wherein the first type of the bezel region comprises a third bezel region and a fourth bezel region, the third bezel region is located at one side of the display region in the first direction, and the fourth bezel region is located at the other side of the display region; the at least one first signal supply line group comprises a first first signal supply line group and a second first signal supply line group, the first first signal supply line group is located in the third bezel region and extends to the first bezel region, and the second first signal supply line group is located in the fourth bezel region and extends to the first bezel region. The at least one first signal pin group comprises a first first signal pin group and a second first signal pin group, at least part of the first signal pins in the first first signal pin group are electrically connected with at least part of the first signal supply lines in the first first signal supply line group, and at least part of the first signal pins in the second first signal pin group are electrically connected with at least part of the first signal supply lines in the second first signal supply line group. In the first direction, the first first signal pin group and the first first signal supply line group are located at the same side of the at least one driving pin group, and the second first signal pin group and the second first signal supply line group are located at the same side of the at least one driving pin group. 5.The display substrate of claim 4, wherein the at least one power pin group comprises a first power pin group and a second power pin group, the binding region further comprises a first power signal supply line group and a second power signal supply line group, at least part of the power pins in the first power pin group are electrically connected with at least part of the power signal supply lines in the first power signal supply line group, and at least part of the power pins in the second power pin group are electrically connected with at least part of the power signal supply lines in the second power signal supply line group. In the binding region, in the first direction, the first power pin group and the second power pin group are located at two sides of the at least one driving pin group, the first power signal supply line group and the second power signal supply line group are located at two sides of the at least one driving pin group, the first power signal supply line group is located at the same side of the first power pin group as the at least one driving pin group, and the second power signal supply line group is located at the same side of the second power pin group as the at least one driving pin group; the first first signal pin group is located at the side of the first power pin group away from the at least one driving pin group, and the second first signal pin group is located at the side of the second power pin group and the second power signal supply line group away from the at least one driving pin group.

6. The display substrate according to claim 5, wherein the plurality of gate driving circuit signal lines comprise a plurality of first gate driving circuit signal lines and a plurality of second gate driving circuit signal lines, the plurality of first gate driving circuit signal lines are located in the third frame region and extend to the first frame region, and the plurality of second gate driving circuit signal lines are located in the fourth frame region and extend to the first frame region. In the binding region, in the first direction, the first group of power supply signal lines and the plurality of first gate driving circuit signal lines are located on the same side of the at least one driving pin group, the second group of power supply signal lines and the plurality of second gate driving circuit signal lines are located on the same side of the at least one driving pin group, the first group of first signal lines is located on the side of the plurality of first gate driving circuit signal lines away from the at least one integrated circuit pin group, and the second group of first signal lines is located on the side of the plurality of second gate driving circuit signal lines away from the at least one integrated circuit pin group.

7. The display substrate according to claim 6, wherein in a direction perpendicular to a plane on which the substrate lies, the plurality of sub-pixels are arranged on one side of the substrate, at least one of the plurality of sub-pixels comprises a pixel driving circuit and a light emitting element, the pixel driving circuit comprises at least one thin film transistor, a planarization layer located on a side of the thin film transistor away from the substrate to cover the thin film transistor, and the light emitting element is located on a side of the planarization layer away from the substrate, the planarization layer comprises a first planarization layer via, the thin film transistor comprises an active layer located on the substrate, a gate located on a side of the active layer away from the substrate, a source and a drain located on a side of the gate away from the substrate, and a transfer electrode located on a side of the source and the drain away from the substrate, in the same sub-pixel, one of the source and the drain in one of the thin film transistors is electrically connected to the transfer electrode through a via, and the transfer electrode is electrically connected to the light emitting element through the first planarization layer via. In the display region, the data lines are arranged in the same layer as the transfer electrodes, and the first signal lines are arranged in the same layer as at least one of the active layer, the source and the drain, and the gate. In the binding region, the first signal lines and the power supply signal lines in the group of power supply signal lines are arranged in the same layer as at least one of the source and the drain and the transfer electrode.

8. The display substrate according to claim 7, wherein the sub-pixel further comprises at least one capacitor, a first plate of the capacitor is arranged in the same layer as the gate of the at least one thin film transistor, and in a direction perpendicular to a plane on which the substrate lies, a second plate of the capacitor is located between the gate of the at least one thin film transistor and the source and the drain. In the binding area, the first signal providing line is a multi-layer structure arranged in the same layer with the source and the drain, the transfer electrode, the gate, and the second plate of the capacitor, and the multi-layer structure is electrically connected. 9.The display substrate of claim 8, in the binding area, the plurality of first gate driving circuit signal lines are bent in the direction of the display area along the third frame area, and are electrically connected to the integrated circuit pin group closest to the first power signal providing line group; the plurality of second gate driving circuit signal lines are bent in the direction of the display area along the fourth frame area, and are electrically connected to the integrated circuit pin group closest to the second power signal providing line group. In the binding area, at least part of the structure of the first gate driving circuit signal line at least partially overlaps the orthogonal projection of the power signal providing line in the substrate, and the first gate driving circuit signal line and the power signal providing line in the overlapping area are located in different conductive layers; at least part of the structure of the second gate driving circuit signal line at least partially overlaps the orthogonal projection of the power signal providing line in the substrate, and the plurality of second gate driving circuit signal lines and the power signal providing line in the overlapping area are located in different conductive layers. 10.The display substrate of claim 8, the plurality of binding pin groups further comprising a first gate driving circuit pin group and a second gate driving circuit pin group. In the first direction, the first first signal pin group is located on the side of the first gate driving circuit pin group away from the first power pin group, and the second first signal pin group is located on the side of the second gate driving circuit pin group away from the second power pin group. The first gate driving circuit signal line is arranged to be electrically connected to the corresponding first gate driving circuit pin in the first gate driving circuit pin group, and the second gate driving circuit signal line is arranged to be electrically connected to the corresponding second gate driving circuit pin in the second gate driving circuit pin group. In the binding area, at least part of the structure of at least part of the gate driving circuit signal line has an un-overlapping area with the power signal providing line. 11.The display substrate of claim 9 or 10, in the binding area, in the area where the gate driving circuit signal line overlaps the power signal providing line, the gate driving circuit signal line is a multi-layer structure arranged in the same layer with the gate and the second plate of the capacitor; in at least part of the area where the gate driving circuit signal line does not overlap the power signal providing line, the gate driving circuit signal line is a multi-layer structure arranged in the same layer with the source and the drain, the transfer electrode, the gate, and the second plate of the capacitor, and the multi-layer structure is electrically connected. 12.The display substrate of any one of claims 8 to 10, wherein, along a direction pointing from the display area to the first frame area, the first frame area comprises a first fan-out area, a bending area, a second fan-out area, and the binding area arranged in sequence. In the first fan-out area, the first signal supply line, the plurality of first gate driving circuit signal lines, and the plurality of second gate driving circuit signal lines are a multi-layer structure arranged in the same layer as the gate and the second plate of the capacitor, and the multi-layer structure is electrically connected; In the second fan-out area, the first signal supply line, the plurality of first gate driving circuit signal lines, and the plurality of second gate driving circuit signal lines are arranged in the same layer as at least one of the gate, the second plate of the capacitor, the source, the drain, and the transfer electrode, and the first signal supply line and the gate driving circuit signal line are located on a side of the power supply signal supply line group away from the plurality of driving pin groups in the first direction. 13.The display substrate of claim 12, wherein the same power supply signal supply line group comprises a first power supply signal supply line and a second power supply signal supply line, the first fan-out area further comprises at least one first power supply connection line, at least one second power supply connection line, and a plurality of first data connection lines, the bending area further comprises at least one first power supply connection structure, at least one second power supply connection structure, and a plurality of second data connection lines, the second fan-out area further comprises a plurality of third data connection lines, and the first power supply signal supply line and the second power supply signal supply line extend to the second fan-out area through the binding area. The first power supply connection structure is configured to electrically connect the first power supply connection line and the corresponding first power supply signal supply line, and the second power supply connection structure is configured to electrically connect the second power supply connection line and the corresponding second power supply signal supply line. The plurality of data lines, the plurality of first data connection lines, the plurality of second data connection lines, and the plurality of third data connection lines correspond one-to-one, and the data line is electrically connected to the corresponding integrated circuit pin in the corresponding integrated circuit binding pin group through the corresponding first data connection line, the corresponding second data connection line, and the corresponding third data connection line. 14.The display substrate of claim 13, wherein, in the first fan-out area, the plurality of first data connection lines are a multi-layer structure arranged in the same layer as the gate and the second plate of the capacitor, the first power supply connection line and the second power supply connection line are a multi-layer structure arranged in the same layer as the source, the drain, and the transfer electrode, and the multi-layer structures are electrically connected; In the bending area, the third data connection line, the first power supply connection structure, the second power supply connection structure, the first signal supply line, and the gate driving circuit signal line are arranged in the same layer as the source and the drain, and different signal lines are arranged with intervals therebetween; In the second fan-out area, the third data connection line is arranged in the same layer as at least one of the gate and the second plate of the capacitor.

15. The display substrate according to claim 12, in the second fan-out area, the third data connection line is a multi-layer structure arranged in the same layer as the gate electrode and the second plate of the capacitor, the first signal supply line, the plurality of first gate driving circuit signal lines, the plurality of second gate driving circuit signal lines are multi-layer structures arranged in the same layer as the gate electrode, the second plate of the capacitor, the source electrode, the drain electrode and the transfer electrode, and the multi-layer structures are electrically connected.

16. The display substrate according to claim 12, the first fan-out area further comprises at least one first signal connection structure, at least one kind of first signal pin is included in the same first signal pin group, the kind of the first signal supply line and the plurality of first signal lines includes at least one kind, the kind of the first signal supply line, the kind of the first signal line and the kind of the first signal pin are one-to-one corresponding, the first signal supply line is electrically connected with the first signal line of the corresponding kind and the first signal pin of the corresponding kind; in the first bezel area, in at least one kind of first signal supply line, the number of the same kind of first signal supply line is at least two, in the first fan-out area, at least two first signal supply lines of the same kind are electrically connected through the corresponding first signal connection structure, in the area where the first signal connection structure is connected with the corresponding first signal supply line, the first signal supply line is arranged in the same layer as one of the gate electrode and the second plate of the capacitor, the first signal connection structure is arranged in the same layer as the other of the gate electrode and the second plate of the capacitor, and the first signal connection structures corresponding to the first signal supply lines of different kinds are arranged at intervals.

17. The display substrate according to claim 16, the kinds of the first signal pins in the two first signal pin groups are the same, the kinds of the first signal supply lines in the first first signal supply line group and the second first signal supply line group are the same, and the same first signal line is electrically connected with the first signal supply lines of the corresponding kind in the first first signal supply line group and the second first signal supply line group.

18. The display substrate according to claim 16, the display area further comprises a plurality of first signal connection lines, the first signal connection lines are arranged in the same layer as the transfer electrode, the plurality of first signal connection lines are arranged at intervals along the first direction and extend along the second direction, the kinds of the plurality of first signal connection lines correspond to the kinds of the plurality of first signal lines one-to-one, the first signal connection lines are electrically connected with the plurality of first signal lines of the corresponding kind through vias, and the same first signal line is electrically connected with the plurality of first signal connection lines of the corresponding kind through vias.

19. The display substrate according to claim 7 or 8, the integrated circuit pins in the integrated circuit pin group and the binding pins in the binding pin group are multi-layer structures arranged in the same layer as the source electrode, the drain electrode and the transfer electrode, and the multi-layer structures are electrically connected. 20.The display substrate of claim 8, wherein the third bezel area further comprises a plurality of first gate driving circuits, and the fourth bezel area further comprises a plurality of second gate driving circuits. The plurality of first gate driving circuits are arranged along a direction in which the third bezel area extends, the plurality of second gate driving circuits are arranged along a direction in which the fourth bezel area extends, the first gate driving circuit signal line is further electrically connected with the plurality of first gate driving circuits, and the second gate driving circuit signal line is further electrically connected with the plurality of second gate driving circuits. In the first direction, in the third bezel area, the at least one first signal supply line is located on a side of the plurality of first gate driving circuits away from the display area, and in the fourth bezel area, the at least one first signal supply line is located on a side of the plurality of second gate driving circuits away from the display area. 21.The display substrate of claim 20, wherein the display area further comprises a plurality of scan signal lines, the plurality of scan signal lines extend along the first direction and are arranged along the second direction. The first gate driving circuit and the second gate driving circuit are configured to be electrically connected with a corresponding scan signal line, and the scan signal line is configured to be arranged in the same layer as at least one of the gate and the second plate of the capacitor. 22.The display substrate of any one of claims 1 to 10, wherein the plurality of first signal lines comprise a plurality of initial signal lines, the at least one first signal supply line group comprises at least one initial signal supply line group, the at least first signal pin group comprises at least one initial signal pin group, and the initial signal pin group comprises at least one initial signal pin. In the same initial signal pin group, at least one initial signal pin is included, the initial signal supply line in the at least one initial signal supply line group and the plurality of initial signal lines comprise at least one type, the type of the initial signal supply line, the type of the initial signal line, and the type of the initial signal pin correspond to each other, and the initial signal supply line is electrically connected with the initial signal line of the corresponding type and the initial signal pin of the corresponding type. 23.A display substrate, comprising: a substrate comprising a display area, a first bezel area, and a first type of bezel area; in a first direction, the first type of bezel area is located on at least one side of the display area; in a second direction, the first bezel area is located on a side of the display area, the first bezel area is provided with a binding area, and the first direction intersects the second direction; a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area and electrically connected with the plurality of sub-pixels, the plurality of data lines extend along the second direction and are arranged at intervals along the first direction; a plurality of first signal lines located in the display area and extending along the first direction and arranged along the second direction, the plurality of first signal lines being electrically connected with the plurality of sub-pixels; and at least one first signal supply line group, at least one first signal pin group, and at least one first signal pin. at least one first signal providing line group is located in the first type of frame area and extends to the binding area in the first frame area, a first signal providing line in the first signal providing line group is arranged to be electrically connected with at least one first signal line in the plurality of first signal lines; at least one integrated circuit pin group is located in the binding area, at least part of integrated circuit pins in the integrated circuit pin group are arranged to be electrically connected with the plurality of data lines; in the binding area, in the first direction, a main part of the at least one first signal providing line group is located at least on one side of the at least one integrated circuit pin group, at least part of the first signal providing line has a multi-layer structure, and the multi-layer structure is electrically connected.

24. The display substrate according to claim 23, wherein the first type of frame area is further provided with a plurality of gate drive circuit signal lines, and the plurality of gate drive circuit signal lines extend to the binding area in the first frame area; in the binding area, in the first direction, a main part of the gate drive circuit signal lines is located at least on one side of the at least one integrated circuit pin group and on the same side of the first middle line, a first signal providing line in the first signal providing line group, the gate drive circuit signal lines and the integrated circuit pin group farthest from the first middle line are electrically connected, and the first middle line is a middle line of the first frame area extending in the second direction; in the binding area, at least part of the gate drive circuit signal lines has a multi-layer structure, and the multi-layer structure is electrically connected.

25. The display substrate according to claim 24, wherein the binding area further comprises at least one power signal providing line group, and in the first direction, the at least one power signal providing line group is located at least on one side of the at least one integrated circuit pin group; in the binding area, in the first direction on the same side of the first middle line, the gate drive circuit signal lines and the first signal providing line are bent in a direction of the first type of frame area pointing to the display area, and are electrically connected with the integrated circuit pin group farthest from the first middle line, at least part of structures of the gate drive circuit signal lines and the first signal providing line at least partially overlap with a normal projection of the power signal providing line group on the substrate, and the gate drive circuit signal lines and the first signal providing line are located in different conductive layers from the power signal providing line in the overlapping area.

26. The display substrate according to claim 25, wherein in a direction perpendicular to a plane in which the substrate is located, the display substrate comprises, in sequence, a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer located on one side of the substrate; in the display area, the data lines are located in the second source-drain metal layer, and the first signal lines are located in at least one conductive layer of the first gate metal layer, the second gate metal layer and the first source-drain metal layer; In the binding area, the first signal line and the gate drive circuit signal line are located in at least one of the first gate metal layer, the second gate metal layer, and the first source-drain metal layer.

27. The display substrate of claim 26, in a direction pointing from the display area to the first bezel area, the first bezel area comprises a first fan-out area, a bending area, a second fan-out area, and the binding area arranged in sequence. In at least a part of the first fan-out area and the binding area where the first signal line and the gate drive circuit signal line overlap with the power signal line, the first signal line and the gate drive circuit signal line are a multi-layer structure located in the first gate metal layer and the second gate metal layer, and the multi-layer structure is electrically connected. In at least a part of the second fan-out area and the binding area where the first signal line and the gate drive circuit signal line do not overlap with the power signal line, the first signal line and the gate drive circuit signal line are a multi-layer structure located in the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer, and the multi-layer structure is electrically connected.

28. The display substrate of claim 26 or 27, the power signal lines in the power signal line group are extended from the binding area to the second fan-out area. In at least a part of the second fan-out area and the binding area, the power signal lines in the power signal line group are a multi-layer structure located in the first source-drain metal layer and the second source-drain metal layer, and the multi-layer structure is electrically connected.

29. A display device comprising the display substrate of any one of claims 1 to 22, or comprising the display substrate of any one of claims 23 to 28.

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