MEMS device and packaging method therefor

Abstract

A MEMS device and a packaging method therefor. The MEMS device comprises a main wafer and a substrate wafer. The main wafer comprises an MEMS sensitive structure and a first conductive layer. The MEMS sensitive structure comprises a plurality of separated portions, each separated portion having a bottom surface. The plurality of bottom surfaces are flush with each other to form a bottom plane of the MEMS sensitive structure. The first conductive layer abuts against the bottom plane and is electrically connected to the substrate wafer.

Description

MEMS device and packaging method thereof

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to the Chinese patent application No. 202411357723.7, filed on September 26, 2024, and entitled “MEMS device and packaging method thereof”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of MEMS (Micro-Electro-Mechanical System) devices, in particular, to a MEMS device and a packaging method thereof. BACKGROUND

[0004] In the related art, a MEMS device mainly includes a main wafer (for example, a MEMS chip) and a substrate wafer (for example, an ASIC chip), and at present, the packaging of the main wafer and the substrate wafer is difficult. SUMMARY

[0005] The purpose of the present disclosure is to provide a MEMS device, in which the packaging of the main wafer and the substrate wafer is less difficult, and the two are more easily integrated together.

[0006] In order to achieve the above purpose, the present disclosure provides a MEMS device, comprising a main wafer and a substrate wafer, the main wafer comprising a MEMS sensitive structure and a first conductive layer, the MEMS sensitive structure comprising a plurality of sub-body parts, the sub-body parts having a bottom surface, a plurality of the bottom surfaces being arranged flush to form a bottom plane of the MEMS sensitive structure, the first conductive layer being in abutment with the bottom plane, and the first conductive layer being electrically connected with the substrate wafer.

[0007] Optionally, the main wafer comprises a second conductive layer, the second conductive layer being arranged on a side of the first conductive layer close to the substrate wafer, and the second conductive layer electrically connecting the first conductive layer and the substrate wafer.

[0008] Optionally, the substrate wafer comprises a third conductive layer, the first conductive layer, the second conductive layer and the third conductive layer being stacked in a first direction in sequence, and the second conductive layer electrically connecting the first conductive layer and the third conductive layer.

[0009] Optionally, the second conductive layer and the third conductive layer are both configured as metal layers, and the second conductive layer is bonded to the third conductive layer.

[0010] Optionally, the first conductive layer is configured as a polysilicon layer or a metal layer, and the first conductive layer is in abutment with the second conductive layer.

[0011] Optionally, the first conductive layer comprises a plurality of conductive bodies, the conductive bodies have a first part and a second part connected with each other, the first part abuts against the body part, the second part abuts against the second conductive layer, the first part and the second part each have a width in a second direction perpendicular to the first direction, and the width of the second part is greater than the width of the first part.

[0012] Optionally, the first part and the second part are perpendicular to each other.

[0013] Optionally, at least one of the conductive bodies is configured as an L-shaped conductive body.

[0014] Optionally, at least one of the conductive bodies is configured as an inverted T-shaped conductive body.

[0015] Optionally, the plurality of body parts comprises a plurality of movable parts, the main body wafer comprises a first insulating layer arranged on the MEMS sensitive structure, and the first insulating layer is formed with a first cavity for movement of the movable parts.

[0016] Optionally, the plurality of body parts comprises a plurality of fixed parts, the first conductive layer comprises a plurality of conductive bodies, at least one of the conductive bodies extends into the first cavity and abuts against a corresponding fixed part.

[0017] Optionally, the first insulating layer is further formed with a first notch, and the plurality of conductive bodies comprises a conductive body arranged in the first notch.

[0018] Optionally, the main body wafer comprises a barrier layer and a second insulating layer, the first insulating layer, the barrier layer and the second insulating layer are sequentially stacked in the first direction, the barrier layer is formed with a second notch, the second insulating layer is provided with a third notch arranged in pairs with the second notch, and the conductive body is arranged in the pair of second notch and third notch.

[0019] Optionally, the first insulating layer is configured as a silicon dioxide layer, and the barrier layer is configured as a silicon nitride layer.

[0020] Optionally, the second insulating layer is configured as a silicon dioxide layer.

[0021] Optionally, the second insulating layer is further formed with a fourth notch arranged in pairs with the third notch, and the second conductive layer is arranged in the fourth notch.

[0022] Optionally, the MEMS device comprises a cover wafer, the cover wafer, the main body wafer and the substrate wafer are sequentially stacked in the first direction, and the cover wafer is formed with a second cavity for movement of the movable parts.

[0023] Optionally, the main wafer comprises a fourth conductive layer arranged on a top surface of the MEMS sensitive structure, and the cover wafer comprises a fifth conductive layer, wherein the fourth conductive layer and the fifth conductive layer are both configured as metal layers, and the fourth conductive layer is bonded with the fifth conductive layer.

[0024] On the basis of the above technical solution, the disclosure further provides a packaging method of a MEMS device, the packaging method being used for packaging the above-mentioned MEMS device, and the packaging method comprising the following steps: arranging a first conductive layer on a wafer substrate; etching the wafer substrate to form a MEMS sensitive structure; shaping a substrate wafer; and electrically connecting the first conductive layer with the substrate wafer.

[0025] Optionally, the substrate wafer comprises a third conductive layer, and the packaging method comprises: arranging a second conductive layer abutting against the first conductive layer on the wafer substrate; and bonding the second conductive layer and the third conductive layer together.

[0026] Optionally, the packaging method comprises: arranging a first insulating layer on the wafer substrate; arranging a first gap on the first insulating layer; making the first conductive layer abut against the MEMS sensitive structure through the first gap; and arranging a first cavity on the first insulating layer.

[0027] Optionally, the packaging method comprises: arranging a barrier layer on the first insulating layer; forming a second gap on the barrier layer; arranging the first conductive layer in the second gap; and arranging a second insulating layer on the barrier layer.

[0028] Optionally, the packaging method comprises: after the step of etching the wafer substrate to form a MEMS sensitive structure, etching the first insulating layer to make the first insulating layer form the first cavity.

[0029] Optionally, the packaging method comprises: before the step of etching the first insulating layer to make the first insulating layer form the first cavity, arranging a barrier layer on the second insulating layer.

[0030] Optionally, the packaging method comprises: forming a fourth gap on the second insulating layer; and arranging a third conductive layer in the fourth gap.

[0031] Optionally, the wafer substrate comprises a buried oxygen layer, and the packaging method comprises: after the step of bonding the second conductive layer and the third conductive layer together, removing a substrate layer of the wafer substrate outside the buried oxygen layer, and removing the buried oxygen layer.

[0032] Optionally, the packaging method comprises: forming a cover wafer, the cover wafer comprising a fifth conductive layer; disposing a fourth conductive layer on the MEMS sensitive structure; and bonding the fourth conductive layer and the fifth conductive layer together.

[0033] By the above technical solution, in the MEMS device provided by the present disclosure, the main body wafer comprises the MEMS sensitive structure and the first conductive layer, the MEMS sensitive structure comprises a plurality of split parts arranged flush on the bottom surface, and the first conductive layer is in abutment with the bottom surface of the split part and is electrically connected with the substrate wafer, that is, the first conductive layer is arranged separately from the MEMS sensitive structure, and the first conductive layer and the MEMS sensitive structure are two independent components. In this way, by arranging the bottom plane of the MEMS sensitive structure as a plane, the present disclosure can reduce the difficulty of etching the MEMS sensitive structure, and the first conductive layer can be processed separately to reduce the processing limitation of the etching process on the main body wafer. Therefore, while ensuring that the MEMS sensitive structure is electrically connected with the substrate wafer through the first conductive layer, the packaging difficulty of the main body wafer and the substrate wafer can be reduced, so that the main body wafer and the substrate wafer can be more easily integrated together. Moreover, by arranging the bottom plane of the MEMS sensitive structure as a plane, the height of the first conductive layer and the height of the MEMS sensitive structure can be ensured, so that the MEMS sensitive structure has a larger movement space.

[0034] Other features and advantages of the present disclosure will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0035] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, and are used together with the following specific embodiments to explain the present disclosure but do not constitute a limitation on the present disclosure. In the drawings:

[0036] FIG. 1 is a structural schematic diagram of a MEMS device in the related art;

[0037] FIG. 2 is a structural schematic diagram of a MEMS device provided by an exemplary embodiment of the present disclosure;

[0038] FIG. 3 is a structural schematic diagram of a main body wafer provided by an exemplary embodiment of the present disclosure;

[0039] FIG. 4 is a structural schematic diagram of a substrate wafer provided by an exemplary embodiment of the present disclosure;

[0040] FIG. 5 is a structural schematic diagram of a cover wafer provided by an exemplary embodiment of the present disclosure;

[0041] FIGS. 6-25 are structural schematic diagrams of a MEMS device corresponding to steps of a packaging method of the MEMS device provided by an exemplary embodiment of the present disclosure;

[0042] FIG. 26 is a flow chart of a packaging method of a MEMS device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] The specific embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to illustrate and explain the present disclosure, and are not intended to limit the present disclosure.

[0044] In the present disclosure, unless otherwise specified, the orientation words such as "upper" and "lower" generally refer to the "upper" and "lower" in the direction of gravity when the corresponding components are in a use state, "top" and "bottom" generally refer to the "top" and "bottom" in the height direction with respect to the corresponding components in the use state, and "first direction" and "second direction" are defined based on the drawing surface direction of FIG. 2, in which "first direction" is indicated by "L1" in the drawing, and "second direction" is indicated by "L2" in the drawing. The terms "first", "second", and the like used in the present disclosure are used to distinguish one element from another element, and do not have sequential or important meanings. In addition, in the following description, when referring to the drawings, the same reference numerals in different drawings represent the same or similar elements unless otherwise explained. The above definitions are only used to explain and illustrate the present disclosure, and should not be understood as limiting the present disclosure.

[0045] In the present disclosure, the MEMS (Micro-Electro-Mechanical System) device is an industrial technology that combines microelectronics technology and mechanical engineering together, the internal structure is generally in the micron or even nanometer level, is an independent intelligent system, focuses on ultra-precision machining, and involves microelectronics, materials, mechanics, chemistry, and mechanical science. SOI (Silicon On Insulator) means that the silicon transistor structure is on the insulator, the principle is to add an insulator between the Silicon transistors, which can reduce the parasitic capacitance between the two by one time. CVD (Chemical Vapor Deposition) is a thin film process defined as the deposition of solid thin films on the surface of the substrate due to gas phase chemical reaction, and the deposition material is usually atoms, molecules or a combination of the two. PVD (Physical Vapor Deposition) is a thin film process that uses physical methods to vaporize the surface of solid or liquid materials into gaseous atoms, molecules or partially ionized ions, and through the process of low-pressure gas (or plasma) to deposit a thin film with certain special function on the substrate surface. DIRE (Deep Reactive Ion Etching) is a microelectronic dry etching process that can produce directional etching, which is the most basic process, and is a silicon etching technology with a certain high aspect ratio based on fluorine-based gas.

[0046] In the related art, referring to FIG. 1, the main wafer 1' includes a MEMS sensitive structure 11', the MEMS sensitive structure 11' is formed with a protrusion 12' close to one side of the substrate wafer 2', and the main wafer 1' is electrically connected with the substrate wafer 2' through the protrusion 12'. In this way, the protrusion 12' is designed integrally with the MEMS sensitive structure 11', and in the actual production process, the main wafer 1' is usually first etched to form the protrusion 12', and then etched to form the MEMS sensitive structure 11'. Due to the limitation of the high aspect ratio in the etching process, the height of the protrusion 12' is limited, which affects the mechanical movement of the MEMS sensitive structure 11'. In addition, due to the setting of the protrusion 12', the etching depth needs to be large in the second etching process, and the processing difficulty of the MEMS sensitive structure 11' at the protrusion 12' is large. Therefore, it is difficult to etch and form the MEMS sensitive structure 11'. In addition, since the protrusion 12' usually needs to be bonded with the substrate wafer, the protrusion 12' needs to be designed with sufficient size to ensure the bonding reliability between the substrate wafer, thereby limiting the design space and flexibility of the MEMS sensitive structure 11'.

[0047] To solve the above problems, according to the specific embodiments provided by the present disclosure, referring to FIGS. 2-5, the present disclosure provides a MEMS device, comprising a main wafer 1 and a substrate wafer 2, the main wafer 1 comprising a MEMS sensitive structure 11 and a first conductive layer 12, the MEMS sensitive structure 11 comprising a plurality of split parts 111, the split parts 111 having bottom surfaces 1111, the plurality of bottom surfaces 1111 being arranged flush to form a bottom plane 112 of the MEMS sensitive structure 11, the first conductive layer 12 abutting against the bottom plane 112, and the first conductive layer 12 being electrically connected with the substrate wafer 2.

[0048] Through the above technical solution, in the MEMS device provided by the present disclosure, the main wafer 1 comprises the MEMS sensitive structure 11 and the first conductive layer 12, the MEMS sensitive structure 11 comprises the plurality of split parts 111 with the flush arranged bottom surfaces 1111, and the first conductive layer 12 abuts against the bottom surfaces 1111 of the split parts 111 while being electrically connected with the substrate wafer 2, that is, the first conductive layer 12 is arranged separately from the MEMS sensitive structure 11, and the first conductive layer 12 and the MEMS sensitive structure 11 are two independent components. In this way, by arranging the bottom plane 112 of the MEMS sensitive structure 11 as a plane, the present disclosure can reduce the difficulty of etching the MEMS sensitive structure 11, and the first conductive layer 12 can be processed separately to reduce the processing limitation of the etching process on the main wafer 1. Therefore, while ensuring that the MEMS sensitive structure 11 is electrically connected with the substrate wafer 2 through the first conductive layer 12, the present disclosure can reduce the packaging difficulty of the main wafer 1 and the substrate wafer 2, so that the main wafer 1 and the substrate wafer 2 can be more easily integrated together. Moreover, by arranging the bottom plane 112 of the MEMS sensitive structure 11 as a plane, the height of the first conductive layer 12 can also be ensured, so that the MEMS sensitive structure 11 has a larger movement space. In addition, the first conductive layer 12 can also be designed as any suitable shape and size according to actual needs, so as to reduce the area of the bottom surfaces 1111 of the split parts 111 occupied by the first conductive layer 12 as much as possible, while ensuring sufficient contact between the first conductive layer 12 and the substrate wafer 2, reducing the packaging difficulty of the main wafer 1 and the substrate wafer 2, and making the main wafer 1 and the substrate wafer 2 more easily integrated together.

[0049] In the MEMS device provided in the present disclosure, the main body wafer 1 can be electrically connected to the substrate wafer 2 in any suitable manner, which is not specifically limited in the present disclosure. As an exemplary embodiment, referring to FIG. 2, the main body wafer 1 can include a second conductive layer 13, which can be arranged on the side of the first conductive layer 12 close to the substrate wafer 2, and the second conductive layer 13 is electrically connected to the first conductive layer 12 and the substrate wafer 2. Among them, the size of the second conductive layer 13 in the second direction can be greater than that of the first conductive layer 12, which can improve the electrical connection reliability of the second conductive layer 13 and the first conductive layer 12 on the one hand, and the first conductive layer 12 can be electrically connected to the substrate wafer 2 through the second conductive layer 13, thereby improving the electrical connection reliability of the first conductive layer 12 and the substrate wafer 2.

[0050] On the basis of the above-mentioned embodiments, as an exemplary embodiment, referring to FIG. 2, the substrate wafer 2 can include a third conductive layer 21, and the first conductive layer 12, the second conductive layer 13 and the third conductive layer 21 can be stacked in the first direction in sequence, and the second conductive layer 13 is electrically connected to the first conductive layer 12 and the third conductive layer 21. In this way, the arrangement of the first conductive layer 12 and the second conductive layer 13 can facilitate the electrical connection between the main body wafer 1 and the substrate wafer 2, and the arrangement of the second conductive layer 13 can improve the electrical connection reliability of the first conductive layer 12 and the third conductive layer 21. Specifically, one end of the first conductive layer 12 can be connected to the bottom surface 1111 of the body part 111 of the main body wafer 1, and the other end protrudes towards the substrate wafer 2 to facilitate connection with the second conductive layer 13. The second conductive layer 13 can increase its contact area with the third conductive layer 21 relative to the second conductive layer 13 while ensuring electrical connection with the first conductive layer 12, so as to improve the electrical connection reliability between the first conductive layer 12 and the third conductive layer 21, and further improve the electrical connection reliability between the main body wafer 1 and the substrate wafer 2.

[0051] In other embodiments, the second conductive layer 13 can not be arranged, and the first conductive layer 12 can be directly electrically connected to the third conductive layer 21, for example, the first conductive layer 12 and the third conductive layer 21 are directly abutted together, which can also achieve the electrical connection between the main body wafer 1 and the substrate wafer 2, which is not specifically limited in the present disclosure.

[0052] In the MEMS device provided by the present disclosure, the first conductive layer 12 and the second conductive layer 13 can realize the conductive connection between them in any suitable manner, and the present disclosure does not make specific limitations in this regard. As an exemplary embodiment, referring to FIG. 2 and FIG. 4, the second conductive layer 13 and the third conductive layer 21 can be both configured as metal layers, and the second conductive layer 13 is bonded with the third conductive layer 21. The second conductive layer 13 and the third conductive layer 21 are both configured as metal layers, which on the one hand can realize the conductive connection between the second conductive layer 13 and the third conductive layer 21 in the case of contact between them, and on the other hand, based on the second conductive layer 13 and the third conductive layer 21 being both configured as metal layers, the bonding connection mode can realize the electrical signal intercommunication between the main wafer 1 and the substrate wafer 2 while realizing the electrical connection between the first conductive layer 12 and the second conductive layer 13, wherein the bonding generally includes direct bonding, anode bonding, eutectic bonding and the like, and the present disclosure does not make specific limitations in this regard.

[0053] In the MEMS device provided by the present disclosure, as an exemplary embodiment, the first conductive layer 12 can be configured as a polysilicon layer or a metal layer, and the first conductive layer 12 abuts against the second conductive layer 13. Among them, the polysilicon has the properties of both metal and semiconductor, has good electrical and optical properties, and the polysilicon layer can be deposited on the bottom surface 1111 of the body part 111 by CVD process, so as to realize the electrical connection between the first conductive layer 12 and the MEMS sensitive structure 11, and then facilitate the abutment between the first conductive layer 12 and the second conductive layer 13. In addition, the first conductive layer 12 can also be configured as a metal layer, such as Au, Al, W, Mo, Cu and the like, which can also play a conductive role, or the first conductive layer 12 can also be configured as a polysilicon doped conductive metal, so as to further improve the electrical performance of the first conductive layer 12.

[0054] In the MEMS device provided by the present disclosure, the first conductive layer 12 can be configured in any suitable form, and the present disclosure does not make specific limitations thereon. As an exemplary embodiment, referring to FIGS. 2 and 3, the first conductive layer 12 can include a plurality of conductive bodies 121, which can have a first part 1211 connected to a second part 1212, the first part 1211 abutting against the body part 111, and the second part 1212 abutting against the second conductive layer 13, the first part 1211 and the second part 1212 can each have a width in a second direction perpendicular to the first direction, and the width of the second part 1212 is greater than the width of the first part 1211. That is, the first part 1211 and the second part 1212 can be configured to have different sizes, in which the size of the first part 1211 in the second direction is smaller than that of the second part 1212, so as to reduce the area of contact between the conductive body 121 and the body part 111, i.e., to reduce the area occupied by the conductive body 121 on the bottom surface 1111 of the body part 111, so as to increase the proportion of the part in the MEMS sensitive structure 11 that can be mechanically moved, and to improve the effective design space of the main wafer 1. The width of the second part 1212 in the second direction is greater than that of the first part 1211, so as to increase the contact area between the conductive body 121 and the second conductive layer 13, i.e., to improve the reliability of the conductive connection between the first conductive layer 12 and the second conductive layer 13.

[0055] In the present disclosure, the first part 1211 and the second part 1212 can be perpendicular to each other. That is, the second part 1212 can protrude toward the substrate wafer 2 relative to the first part 1211 in the first direction, further facilitating the connection between the conductive body 121 and the second conductive layer 13, i.e., facilitating the conductive connection between the first conductive layer 12 and the second conductive layer 13, and the perpendicular arrangement of the first part 1211 and the second part 1212 can also improve the stability of the conductive body 121 arranged between the main wafer 1 and the substrate wafer 2.

[0056] In the MEMS device provided by the present disclosure, as an exemplary embodiment, referring to FIG. 3, at least one conductive body 121 can be configured as an L-shaped conductive body 121. In the present disclosure, the bottom surface 1111 of the L-shaped conductive body 121 abuts against the second conductive layer 13, and the top surface of the L-shaped conductive body 121 abuts against the body part 111, so as to meet the requirements of reducing the area occupied by the conductive body 121 on the bottom surface 1111 of the body part 111 and increasing the contact area between the conductive body 121 and the second conductive layer 13.

[0057] In some other embodiments, the at least one electrically conductive body 121 can also be configured as an inverted T-shaped electrically conductive body 121. In this case, the bottom surface 1111 of the inverted T-shaped electrically conductive body 121 is in abutment with the second electrically conductive layer 13, and the top surface of the inverted T-shaped electrically conductive body 121 is in abutment with the split body part 111, which can also meet the requirement of reducing the area occupied by the electrically conductive body 121 on the bottom surface 1111 of the split body part 111 while increasing the contact area between the electrically conductive body 121 and the second electrically conductive layer 13, and the present disclosure does not make specific limitations in this regard.

[0058] In yet some other embodiments, the at least one electrically conductive body 121 can also be configured as a "several" shaped electrically conductive body 121, in which case the electrically conductive body 121 has a second split part 1212 in abutment with the second electrically conductive layer 13, and two first split parts 1211 in abutment with the split body part 111, both of which are perpendicular to the second split part 1212, and the end portions of the two first split parts 1211 can be bent and extended away from each other to further increase the contact area between the first split parts 1211 and the split body part 111, and thus improve the reliability of the electrical connection between the electrically conductive body 121 and the split body part 111.

[0059] In the MEMS device provided by the present disclosure, as an exemplary embodiment, referring to FIG. 3, the plurality of split body parts 111 can include a plurality of movable parts 113, and the main body wafer 1 can include a first insulating layer 14 arranged on the MEMS sensitive structure 11, and the first insulating layer 14 is formed with a first cavity 141 for movement of the movable part 113. In this way, the first insulating layer 14 is formed with the first cavity 141, and the split body part 111 is matched with the first insulating layer 14, which can realize the sealing connection of the substrate wafer 2 in the direction of the bottom of the MEMS sensitive structure 11, and the setting of the first cavity 141 can provide movement space for the movable part 113.

[0060] In the MEMS device provided by the present disclosure, as an exemplary embodiment, referring to FIG. 3, the plurality of split body parts 111 can include a plurality of fixed parts 114, and the first electrically conductive layer 12 can include a plurality of electrically conductive bodies 121, at least one of which extends into the first cavity 141 and is in abutment with the corresponding fixed part 114. In this way, the MEMS sensitive structure 11 is realized to be in conductive connection with the first electrically conductive layer 12 through the setting of the fixed part 114, and thus the MEMS sensitive structure 11 can be fixed to the substrate wafer 2 and in conductive connection with the substrate wafer 2 through the cooperation of the second electrically conductive layer 13 and the third electrically conductive layer 21.

[0061] As an exemplary embodiment, referring to FIG. 3, the first insulating layer 14 can further be formed with a first gap 142, and the plurality of conductive bodies 121 can include conductive bodies 121 arranged in the first gap 142. In this way, the MEMS sensitive structure 11 can pass through the first insulating layer 14 through the conductive bodies 121 to realize conductive connection with the second conductive layer 13, and further realize conductive connection with the substrate wafer 2.

[0062] As an exemplary embodiment, referring to FIG. 2, the main body wafer 1 can further include a barrier layer 15 and a second insulating layer 16, the first insulating layer 14, the barrier layer 15 and the second insulating layer 16 can be sequentially stacked in the first direction, the barrier layer 15 is formed with a second gap 151, the second insulating layer 16 is provided with a third gap 161 arranged in pairs with the second gap 151, and the conductive bodies 121 are arranged in the pair of second gap 151 and third gap 161. Among them, the arrangement of the first insulating layer 14, the barrier layer 15 and the third insulating layer can improve the reliability of the connection between the main body wafer 1 and the substrate wafer 2, and further improve the reliability of the sealing of the MEMS sensitive structure 11, and the arrangement of the second gap 151 and the third gap 161 can facilitate the conductive bodies 121 to realize the conductive connection between the MEMS sensitive structure 11 and the second conductive layer 13.

[0063] Among them, the first insulating layer 14 can be configured as a silicon dioxide layer, and the barrier layer 15 can be configured as a silicon nitride layer. Among them, silicon dioxide has certain stability and can be used as a temporary support structure to facilitate the formation of the MEMS device, and then removed as the substrate layer 120, silicon nitride has excellent insulation and stability, and is difficult to etch easily, the silicon dioxide layer and the silicon nitride layer can be deposited on the bottom surface 1111 of the MEMS sensitive structure 11 in sequence by CVD process, and since the first insulating layer 14 needs to be etched by hydrogen fluoride vapor etching process to form the first cavity 141 in the actual production process, the arrangement of the barrier layer 15 can avoid damage to the second insulating layer 16 caused by hydrogen fluoride vapor in the process.

[0064] Among them, the second insulating layer 16 can be configured as a silicon dioxide layer, in the present disclosure, the first conductive layer 12 protrudes the barrier layer 15, and the arrangement of the second insulating layer 16 can realize sealing around the first conductive layer 12, while making the conductive bodies 121 insulated from each other. At the same time, the arrangement of the barrier layer 15 can avoid damaging the second insulating layer 16 when forming the first cavity 141.

[0065] In the MEMS device provided in the present disclosure, as an exemplary embodiment, referring to FIG. 3, the second insulating layer 16 can further be formed with a fourth notch 162 arranged in pairs with the third notch 161, and the second conductive layer 13 is arranged in the fourth notch 162. That is, the fourth notch 162 provides a mounting space for the second conductive layer 13, and the second conductive layer 13 can be arranged in the fourth notch 162 and flush with the second insulating layer 16 at the bottom surface 1111, so that the second insulating layer 16 can abut against the surface of the substrate wafer 2 to further improve the sealing performance of the MEMS sensitive structure 11.

[0066] In the MEMS device provided in the present disclosure, as an exemplary embodiment, referring to FIG. 5, the MEMS device includes a cover wafer 3, the cover wafer 3, the main body wafer 1 and the substrate wafer 2 are sequentially stacked in the first direction, and the cover wafer 3 is formed with a second cavity 31 for movement of the movable part 113. That is, the cover wafer 3 and the substrate wafer 2 are respectively arranged on the opposite sides of the main body wafer 1 in the first direction, so as to seal the top and bottom of the main body wafer 1. Among them, the second cavity 31 can provide a movement space for the movable part 113, and the second cavity 31 cooperates with the first cavity 141 to facilitate the movement of the movable part 113 in the first direction.

[0067] In the MEMS device provided in the present disclosure, the main body wafer 1 can be electrically connected to the cover wafer 3 by any suitable means, which is not limited in the present disclosure. As an exemplary embodiment, referring to FIG. 2 and FIG. 5, the main body wafer 1 can include a fourth conductive layer 17 arranged on the top surface of the MEMS sensitive structure 11, and the cover wafer 3 includes a fifth conductive layer 32, wherein the fourth conductive layer 17 and the fifth conductive layer 32 are both configured as metal layers, and the fourth conductive layer 17 is bonded to the fifth conductive layer 32. The fourth conductive layer 17 and the fifth conductive layer 32 are both configured as metal layers, which on the one hand can realize the conductive connection of the fourth conductive layer 17 and the fifth conductive layer 32 when they are in contact, and on the other hand, based on the fourth conductive layer 17 and the fifth conductive layer 32 being both configured as metal layers, the bonding connection mode can realize the electrical connection of the fourth conductive layer 17 and the fifth conductive layer 32 and the intercommunication of electrical signals between the main body wafer 1 and the cover wafer 3, wherein the bonding generally includes direct bonding, anode bonding, eutectic bonding and the like, which is not limited in the present disclosure.

[0068] On the basis of the above technical solutions, referring to FIG. 26, the packaging method of the MEMS device is also provided, which is used for packaging the MEMS device described above, and the packaging method comprises the following steps: disposing the first conductive layer 12 on the wafer substrate 100; etching the wafer substrate 100 to form the MEMS sensitive structure 11; forming the substrate wafer 2; and electrically connecting the first conductive layer 12 and the substrate wafer 2. Through the above method, referring to FIG. 6, the wafer substrate 100 can be provided first, referring to FIG. 11, the first conductive layer 12 is disposed on the wafer substrate 100, then the substrate wafer 2 is formed, referring to FIG. 15, the first conductive layer 12 is electrically connected with the substrate wafer 2, referring to FIG. 19, the wafer substrate 100 is etched to form the MEMS sensitive structure 11, wherein the first conductive layer 12 can be processed separately to reduce the processing limitation of the etching process on the MEMS sensitive structure 11, by setting the bottom plane 112 of the MEMS sensitive structure 11 as a plane, the difficulty of etching and forming the MEMS sensitive structure 11 can be reduced, and the first conductive layer 12 can be processed separately to reduce the processing limitation of the etching process on the main wafer 1, thereby, while ensuring that the MEMS sensitive structure 11 is electrically connected with the substrate wafer 2 through the first conductive layer 12, the packaging difficulty of the main wafer 1 and the substrate wafer 2 can be reduced, and the main wafer 1 and the substrate wafer 2 can be more easily integrated together.

[0069] In the packaging method of the MEMS device provided by the present disclosure, the wafer substrate 100 can be an SOI wafer, and the SOI wafer has a buried oxygen layer 110 (as shown in FIG. 6) to facilitate the thinning of the SOI wafer in subsequent processing. In other embodiments, the wafer substrate 100 can also be a common silicon wafer, and the present disclosure does not make specific limitations in this regard.

[0070] It should be noted that the packaging method of the MEMS device provided by the present disclosure can change the order of the above method steps in any suitable order on the basis of the above embodiments, and the present disclosure does not make specific limitations in this regard.

[0071] In the packaging method of the MEMS device provided by the present disclosure, the substrate wafer 2 can comprise a third conductive layer 21, and the packaging method comprises: disposing a second conductive layer 13 abutting against the first conductive layer 12 on the wafer substrate 100; and bonding the second conductive layer 13 and the third conductive layer 21 together. Through the above method, referring to FIG. 14, the second conductive layer 13 can be deposited on the first conductive layer 12 through a PVD process, and referring to FIG. 15, the first conductive layer 12 and the second conductive layer 13 are bonded.

[0072] In the packaging method of the MEMS device provided in the present disclosure, the method comprises: disposing a first insulating layer 14 on a wafer substrate 100; disposing a first gap 142 on the first insulating layer 14; making the first conductive layer 12 abut against the MEMS sensitive structure 11 through the first gap 142; and disposing a first cavity 141 on the first insulating layer 14. Through the above method, as shown in FIG. 7, the first insulating layer 14 is deposited on the top of the wafer substrate 100 by a CVD process, as shown in FIG. 9, the first insulating layer 14 can be etched by a DRIE process to form the first gap 142 on the first insulating layer 14; as shown in FIG. 10, the first conductive layer 12 is deposited by a CVD process, and the first conductive layer 12 abuts against the MEMS sensitive structure 11 through the first gap 142, as shown in FIG. 20, the first cavity 141 can be formed on the first insulating layer 14 by a hydrogen fluoride vapor etching process. The first insulating layer 14 is a silicon dioxide layer.

[0073] In the packaging method of the MEMS device provided in the present disclosure, the method comprises: disposing a first insulating layer 14 on a wafer substrate 100; disposing a first gap 142 on the first insulating layer 14; making the first conductive layer 12 abut against the MEMS sensitive structure 11 through the first gap 142; and disposing a first cavity 141 on the first insulating layer 14. Through the above method, as shown in FIG. 7, the first insulating layer 14 is deposited on the top of the wafer substrate 100 by a CVD process, as shown in FIG. 9, the first insulating layer 14 can be etched by a DRIE process to form the first gap 142 on the first insulating layer 14; as shown in FIG. 10, the first conductive layer 12 is deposited by a CVD process, and the first conductive layer 12 abuts against the MEMS sensitive structure 11 through the first gap 142, as shown in FIG. 20, the first cavity 141 can be formed on the first insulating layer 14 by a hydrogen fluoride vapor etching process. The first insulating layer 14 is a silicon dioxide layer.

[0074] In the packaging method of the MEMS device provided in the present disclosure, the method comprises: after "etching the wafer substrate 100 to form the MEMS sensitive structure 11", etching the first insulating layer 14 to make the first insulating layer 14 form the first cavity 141. Through the above method, as shown in FIG. 20, the first cavity 141 can be formed on the first insulating layer 14 by a hydrogen fluoride vapor etching process.

[0075] In the packaging method of the MEMS device provided in the present disclosure, the method comprises: before "etching the first insulating layer 14 to make the first insulating layer 14 form the first cavity 141", disposing a barrier layer 15 on the second insulating layer 16. Through the above method, as shown in FIG. 8, the barrier layer 15 is deposited on the first insulating layer 14 by a CVD process, as shown in FIG. 12, the second insulating layer 16 is deposited on the barrier layer 15 by a CVD process, as shown in FIG. 17, the MEMS device is flipped, as shown in FIG. 20, the first insulating layer 14 is etched by a hydrogen fluoride vapor etching process, so that the barrier layer 15 can be used to avoid damage to the second insulating layer 16 caused by hydrogen fluoride vapor.

[0076] In the packaging method of the MEMS device provided in the present disclosure, the method comprises: forming a fourth gap 162 on the second insulating layer 16; and disposing the second conductive layer 13 in the fourth gap 162. Through the technical method, as shown in FIG. 13, the second insulating layer 16 is etched by the RIE process to form the fourth gap 162 on the second insulating layer 16, as shown in FIG. 14, the second conductive layer 13 is deposited on the second insulating layer 16 by the PVD process, and the second conductive layer 13 fills the fourth gap 162.

[0077] In the packaging method of the MEMS device provided in the present disclosure, the wafer substrate 100 can comprise a buried oxygen layer 110, and the packaging method comprises: after the second conductive layer 13 and the third conductive layer 21 are bonded together, removing the substrate layer 120 of the wafer substrate 100 located outside the buried oxygen layer 110, and removing the buried oxygen layer 110. Through the technical method, as shown in FIG. 16, the side of the wafer substrate 100 away from the substrate wafer 2 is thinned by the grinding and polishing process until the substrate layer 120 and the buried oxygen layer 110 are removed.

[0078] In the packaging method of the MEMS device provided in the present disclosure, the wafer substrate 100 can comprise a buried oxygen layer 110, and the packaging method comprises: after the second conductive layer 13 and the third conductive layer 21 are bonded together, removing the substrate layer 120 of the wafer substrate 100 located outside the buried oxygen layer 110, and removing the buried oxygen layer 110. Through the technical method, as shown in FIG. 16, the side of the wafer substrate 100 away from the substrate wafer 2 is thinned by the grinding and polishing process until the substrate layer 120 and the buried oxygen layer 110 are removed.

[0079] In the packaging method of the MEMS device provided in the present disclosure, the method comprises: forming a cover wafer 3, the cover wafer 3 comprising a fifth conductive layer 32; disposing a fourth conductive layer 17 on the MEMS sensitive structure 11; and bonding the fourth conductive layer 17 and the fifth conductive layer 32 together. As shown in FIG. 25, the cover wafer 3 is provided, the cover wafer 3 comprising the fifth conductive layer 32, as shown in FIG. 18, the fourth conductive layer 17 and the pin plate 18 are deposited on the MEMS sensitive structure 11 by the PVD process, as shown in FIG. 21, the fourth conductive layer 17 and the fifth conductive layer 32 are bonded to realize the conductive connection between the cover wafer 3 and the MEMS sensitive structure 11, and as shown in FIG. 22, the part of the cover wafer 3 corresponding to the pin plate 18 is cut to expose the pin plate 18.

[0080] In the packaging method of the MEMS device provided in the present disclosure, the method comprises: forming a cover wafer 3, the cover wafer 3 comprising a fifth conductive layer 32; disposing a fourth conductive layer 17 on the MEMS sensitive structure 11; and bonding the fourth conductive layer 17 and the fifth conductive layer 32 together. As shown in FIG. 25, the cover wafer 3 is provided, the cover wafer 3 comprising the fifth conductive layer 32, as shown in FIG. 18, the fourth conductive layer 17 and the pin plate 18 are deposited on the MEMS sensitive structure 11 by the PVD process, as shown in FIG. 21, the fourth conductive layer 17 and the fifth conductive layer 32 are bonded to realize the conductive connection between the cover wafer 3 and the MEMS sensitive structure 11, and as shown in FIG. 22, the part of the cover wafer 3 corresponding to the pin plate 18 is cut to expose the pin plate 18.

[0081] In summary, in the packaging method provided by the present disclosure, as an exemplary embodiment, the process flow of the MEMS device packaging is as follows: first, referring to FIG. 6, a wafer substrate 100 is provided, and the wafer substrate 100 includes a buried oxide layer 110; second, referring to FIG. 7, a first insulating layer 14 is formed on the top of the wafer substrate 100 by a thermal oxidation process; third, referring to FIG. 8, a barrier layer 15 is deposited on the surface of the first insulating layer 14 by a CVD process; fourth, referring to FIG. 9, the first insulating layer 14 and the barrier layer 15 are etched by a DRIE process to form a first gap 142 and a second gap 151, respectively; fifth, referring to FIG. 10, a conductive layer is deposited on the surface of the barrier layer 15 by a CVD process, and the conductive layer fills the first gap 142 and the second gap 151; sixth, referring to FIG. 11, the conductive layer is etched by a RIE process to form a plurality of mutually isolated conductive bodies 121; seventh, referring to FIG. 12, a second insulating layer 16 is deposited on the surface of the barrier layer 15 by a CVD process, and the second insulating layer 16 covers the surface of the conductive bodies 121; eighth, referring to FIG. 13, the second insulating layer 16 is etched by a RIE process to form a fourth gap 162, and at this time the conductive bodies 121 are exposed through a third gap 161; ninth, referring to FIG. 14, a second conductive layer 13 is deposited in the third gap 161 by a PVD process, and the second conductive layer 13 is electrically connected with the conductive bodies 121; tenth, referring to FIG. 15, a substrate wafer 2 is provided, and the substrate wafer 2 is provided with a third conductive layer 21, and the second conductive layer 13 and the third conductive layer 21 are bonded; eleventh, referring to FIG. 16, the wafer substrate 100 is ground and polished to remove the buried oxide layer 110, so as to thin the wafer substrate 100; twelfth, referring to FIG. 17, the whole piece of MEMS device is flipped up and down; thirteenth, referring to FIG. 18, a fourth conductive layer 17 and a pin plate 18 are deposited on the wafer substrate 100 by a PVD process; fourteenth, referring to FIG. 19, the wafer substrate 100 is etched by a DRIE process to form a MEMS sensitive structure 11; fifteenth, referring to FIG. 20, the first insulating layer 14 is etched by a hydrogen fluoride vapor etching process to form a first cavity 141; sixteenth, referring to FIG. 21, a cover wafer 3 is provided, and the cover wafer 3 is provided with a fifth conductive layer 32, and the fourth conductive layer 17 and the fifth conductive layer 32 are bonded; seventeenth, referring to FIG. 22, the cover wafer 3 is cut to expose the pin plate 18, and the MEMS device is packaged by the above packaging method.

[0082] It should be noted that the processes used in the above packaging method, such as the PVD process, the CVD process, the DRIE process, etc., can be replaced by any suitable process known in the related art, for example, the DRIE process can be replaced by the RIE process, and the present disclosure does not make specific limitations in this regard.

[0083] The preferred embodiments of the present disclosure are described in detail above with reference to the drawings, but the present disclosure is not limited to the specific details of the above-described embodiments. Various simple modifications can be made to the technical solutions of the present disclosure within the technical concept of the present disclosure, and all of these simple modifications shall fall within the protection scope of the present disclosure.

[0084] In addition, it should be noted that each specific technical feature described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, various possible combinations are not described again by the present disclosure.

[0085] In addition, various different embodiments of the present disclosure can also be combined in any appropriate manner, as long as they do not deviate from the idea of the present disclosure, and they should also be considered as disclosed by the present disclosure.

Claims

1. A MEMS device, characterized by, The MEMS device comprises a main wafer (1) and a substrate wafer (2), The main wafer (1) comprises: a MEMS sensitive structure (11) comprising a plurality of sub-body portions (111) having bottom surfaces (1111) arranged flush to form a bottom plane (112) of the MEMS sensitive structure (11); and a first conductive layer (12) abutting against the bottom plane (112) and electrically connected to the substrate wafer (2).

2. The MEMS device of claim 1, wherein, The main wafer (1) comprises a second conductive layer (13) disposed on a side of the first conductive layer (12) close to the substrate wafer (2), and the second conductive layer (13) electrically connects the first conductive layer (12) and the substrate wafer (2).

3. The MEMS device of claim 2, wherein, The substrate wafer (2) comprises a third conductive layer (21), and the first conductive layer (12), the second conductive layer (13) and the third conductive layer (21) are stacked in sequence along a first direction, and the second conductive layer (13) electrically connects the first conductive layer (12) and the third conductive layer (21).

4. The MEMS device of claim 3, wherein, The second conductive layer (13) and the third conductive layer (21) are both configured as metal layers, and the second conductive layer (13) is bonded to the third conductive layer (21).

5. The MEMS device of claim 4, wherein, The first conductive layer (12) is configured as a polysilicon layer or a metal layer, and the first conductive layer (12) abuts against the second conductive layer (13).

6. The MEMS device of any of claims 2-5, wherein, The first conductive layer (12) comprises a plurality of conductive bodies (121) having first sub-portions (1211) and second sub-portions (1212) connected to each other, the first sub-portions (1211) abut against the sub-body portions (111), the second sub-portions (1212) abut against the second conductive layer (13), the first sub-portions (1211) and the second sub-portions (1212) both have widths in a second direction perpendicular to the first direction, and the width of the second sub-portions (1212) is greater than the width of the first sub-portions (1211).

7. The MEMS device of claim 6, wherein, The first sub-portions (1211) and the second sub-portions (1212) are perpendicular to each other.

8. The MEMS device of claim 7, wherein, At least one of the conductive bodies (121) is configured as an L-shaped conductive body (121).

9. The MEMS device of claim 7 or 8, wherein, At least one of the conductive bodies (121) is configured as an inverted T-shaped conductive body (121).

10. The MEMS device of any of claims 1-9, wherein, The plurality of sub-body portions (111) comprises a plurality of movable portions (113), and the main wafer (1) comprises a first insulating layer (14) disposed on the MEMS sensitive structure (11) and forming a first cavity (141) for movement of the movable portions (113).

11. The MEMS device of claim 10, wherein, The plurality of sub-body portions (111) comprises a plurality of fixed portions (114), and the first conductive layer (12) comprises a plurality of conductive bodies (121), at least one of the conductive bodies (121) extends into the first cavity (141) and abuts against a corresponding fixed portion (114).

12. The MEMS device of claim 11, wherein, The first insulating layer (14) is further formed with a first gap (142), and the plurality of conductive bodies (121) include a conductive body (121) arranged in the first gap (142).

13. The MEMS device of claim 11, wherein, The main body wafer (1) includes a barrier layer (15) and a second insulating layer (16), the first insulating layer (14), the barrier layer (15) and the second insulating layer (16) are sequentially stacked in a first direction, the barrier layer (15) is formed with a second gap (151), and the second insulating layer (16) is provided with a third gap (161) arranged in pairs with the second gap (151), and the conductive body (121) is arranged in the second gap (151) and the third gap (161) arranged in pairs.

14. The MEMS device of claim 13, wherein, The first insulating layer (14) is configured as a silicon dioxide layer, and the barrier layer (15) is configured as a silicon nitride layer.

15. The MEMS device of claim 13, wherein, The second insulating layer (16) is configured as a silicon dioxide layer.

16. The MEMS device of claim 13, wherein, The second insulating layer (16) is further formed with a fourth gap (162) arranged in pairs with the third gap (161), and a second conductive layer (13) is arranged in the fourth gap (162).

17. The MEMS device of any of claims 10-16, wherein, The MEMS device includes a cover wafer (3), the cover wafer (3), the main body wafer (1) and the substrate wafer (2) are sequentially stacked in a first direction, and the cover wafer (3) is formed with a second cavity (31) for movement of the movable part (113).

18. The MEMS device of claim 17, wherein, The main body wafer (1) includes a fourth conductive layer (17) arranged on a top surface of the MEMS sensitive structure (11), and the cover wafer (3) includes a fifth conductive layer (32), wherein the fourth conductive layer (17) and the fifth conductive layer (32) are both configured as metal layers, and the fourth conductive layer (17) is bonded with the fifth conductive layer (32).

19. A method of packaging a MEMS device, the method comprising: The packaging method is used for packaging the MEMS device of any one of claims 1-18, and the packaging method includes the following steps: arranging a first conductive layer (12) on a wafer substrate (100); etching the wafer substrate (100) to form a MEMS sensitive structure (11); forming a substrate wafer (2); electrically connecting the first conductive layer (12) with the substrate wafer (2).

20. The method of packaging a MEMS device of claim 19, wherein, The substrate wafer (2) includes a third conductive layer (21), and the packaging method includes: arranging a second conductive layer (13) abutting against the first conductive layer (12) on the wafer substrate (100); bonding the second conductive layer (13) and the third conductive layer (21) together.

21. The packaging method of a MEMS device according to claim 19 or 20, wherein, The packaging method includes: arranging a first insulating layer (14) on the wafer substrate (100); arranging a first gap (142) on the first insulating layer (14); and arranging a first cavity (141) on the first insulating layer (14).

22. The packaging method of a MEMS device according to claim 21, wherein, The packaging method includes: arranging a barrier layer (15) on the first insulating layer (14); forming a second gap (151) on the barrier layer (15); and disposing the first conductive layer (12) in the second gap (151); disposing a second insulating layer (16) on the barrier layer (15).

23. The method of packaging a MEMS device of claim 22, wherein, The packaging method comprises, after "etching the wafer substrate (100) to form the MEMS sensitive structure (11)", etching a first insulating layer (14) to form the first cavity (141) in the first insulating layer (14).

24. The method of packaging a MEMS device of claim 23, wherein, The packaging method comprises, before "etching a first insulating layer (14) to form the first cavity (141) in the first insulating layer (14)", disposing a barrier layer (15) on the second insulating layer (16).

25. The method of packaging a MEMS device of claim 22, wherein, The packaging method comprises: forming a fourth gap (162) on the second insulating layer (16); disposing a second conductive layer (13) in the fourth gap (162).

26. The method of packaging a MEMS device of any of claims 20-25, wherein, The wafer substrate (100) comprises a buried oxygen layer (110), and the packaging method comprises: after "bonding the second conductive layer (13) and the third conductive layer (21) together", removing a substrate layer (120) of the wafer substrate (100) outside the buried oxygen layer (110), and removing the buried oxygen layer (110).

27. The method of packaging a MEMS device of any of claims 20-25, wherein, The packaging method comprises: forming a cover wafer (3), the cover wafer (3) comprising a fifth conductive layer (32); disposing a fourth conductive layer (17) on the MEMS sensitive structure (11); bonding the fourth conductive layer (17) and the fifth conductive layer (32) together.

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