Planar split-gate vdmosfet and manufacturing method therefor

Abstract

The present invention relates to a planar split-gate VDMOSFET and a manufacturing method therefor. The planar split-gate VDMOSFET comprises: a drain region; a drift region, which is located on the drain region; a drain electrode, which is located on the side of the drain region that faces away from the drift region; a JFET region, which is located on the drift region; a body region, which is located on the drift region and on both sides of the JFET region; a source region, which is located on the body region and on both sides of the JFET region; a contact region, which is of a second conductivity type and is located outside the body region, wherein the bottom of the contact region is deeper than the bottom of the body region; a split gate electrode, which is split from the middle, wherein a separation region is located directly above the JFET region; and a source electrode, which is located on the source region and the contact region and is in direct contact with the source region and the contact region. The present invention reduces the gate-drain capacitance, reduces the switch power consumption of a device, and improves the performance of the device at a high frequency. Without affecting the specific on-resistance, the breakdown voltage of the device is increased, and the long-term reliability of the device is improved.

Description

Planar split-gate VDMOSFET and manufacturing method thereof Cross-reference to Related Applications

[0001] This patent application claims priority to the Chinese patent application with the application number 202411341958.7, the title of which is “Planar split-gate VDMOSFET and manufacturing method thereof”, filed on September 25, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of semiconductor manufacturing, in particular to a planar split-gate VDMOSFET, and a manufacturing method thereof. BACKGROUND

[0003] The planar gate VDMOSFET using the third-generation semiconductor material as the substrate has stronger voltage resistance, faster switching speed, and more applications in high-temperature, high-voltage, high-frequency, and high-power scenarios compared to the traditional Si-based planar gate VDMOSFET due to the advantages of the third-generation semiconductor material in having a larger band gap, thermal conductivity, critical breakdown field, and electron saturation drift speed. However, the larger gate-drain capacitance and specific on-resistance of the planar gate VDMOSFET still result in high power consumption during its high-power operation, limiting its high-frequency application. The planar split-gate VDMOSFET has better high-frequency characteristics due to the split gate, which reduces the gate-drain overlap area and the gate-drain capacitance. However, its long-term reliability is low under the working environment of high voltage applied to the drain. SUMMARY

[0004] Therefore, it is necessary to provide a planar split-gate VDMOSFET with good long-term reliability under the working environment of high voltage applied to the drain and a manufacturing method thereof.

[0005] A planar split-gate VDMOSFET, comprising: a drain region having a first conductivity type; a drift region having the first conductivity type on the drain region; a drain electrode on a side of the drain region facing away from the drift region; a JFET region having the first conductivity type on the drift region; a body region having a second conductivity type on the drift region on both sides of the JFET region; the first conductivity type and the second conductivity type being opposite conductivity types; a source region having the first conductivity type on the body region on both sides of the JFET region; a contact region having the second conductivity type on an outer side of the body region, and a bottom of the contact region being deeper than a bottom of the body region, the outer side of the body region being a side of the body region facing away from the JFET region; split-gate electrodes separated from each other by a separation region directly above the JFET region; and a source electrode on and in direct contact with the source region and the contact region.

[0006] The planar split-gate VDMOSFET has the contact region configured to have a deeper bottom than the body region, so that the contact region forms a PN junction with the drift region that is deeper than a PN junction between the body region and the drift region. When a high voltage is applied to the drain electrode, the peak electric field is shifted to the bottom of the contact region, away from a corner of the split-gate electrodes directly above the JFET region, i.e. away from the corner of the split-gate electrodes directly above the JFET region, which is a weak point of electric field breakdown. This makes the device have a higher voltage withstand capability, and improves the breakdown voltage of the device, so that the device has good long-term reliability in a working environment where a high voltage is applied to the drain electrode.

[0007] In one embodiment, the bottom of the contact region is 0.5 to 2 microns deeper than the bottom of the body region.

[0008] In one embodiment, the contact region is formed by etching a trench on the outer side of the body region, and implanting ions of the second conductivity type on the side and bottom of the trench.

[0009] In one embodiment, the contact region is formed by high-energy ion implantation.

[0010] In one embodiment, the drift region is formed by multiple epitaxial processes, and the contact region is formed by implanting ions of the second conductivity type after each epitaxial process and then performing a heat treatment to diffuse the implanted ions of the second conductivity type.

[0011] In one embodiment, the device further comprises a channel region between the source region and the JFET region, the channel region having the second conductivity type.

[0012] In one embodiment, the contact region has a doping concentration greater than a doping concentration of the channel region.

[0013] In one of the embodiments, a dielectric layer covering the split gate electrode is further included, and the source electrode covers the dielectric layer.

[0014] In one of the embodiments, the bottom and part of the side of the contact region is in direct contact with the drift region, part of the side of the contact region is in direct contact with the body region, and part of the side of the contact region is in direct contact with the source region.

[0015] In one of the embodiments, the first conductivity type is N type, and the second conductivity type is P type; or, the first conductivity type is P type, and the second conductivity type is N type.

[0016] In one of the embodiments, the material of the drain region and the drift region is silicon carbide or gallium nitride.

[0017] In one of the embodiments, the doping concentration of the JFET region is greater than the doping concentration of the drift region.

[0018] In one of the embodiments, the doping concentration of the drain region is greater than the doping concentration of the JFET region.

[0019] In one of the embodiments, the doping concentration of the source region is greater than the doping concentration of the JFET region.

[0020] In one of the embodiments, the doping concentration of the contact region is greater than the doping concentration of the body region.

[0021] A manufacturing method of a planar split gate VDMOSFET, comprising: obtaining a wafer with a first conductivity type layer formed on a substrate of a first conductivity type; the doping concentration of the substrate is greater than the doping concentration of the first conductivity type layer; forming a JFET region, a body region, a source region and a contact region in the first conductivity type layer; the JFET region and the source region have a first conductivity type, the body region and the contact region have a second conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types; the body region is formed on both sides of the JFET region, the source region is formed on the body region and on both sides of the JFET region, the contact region is located outside the body region, and the bottom of the contact region is deeper than the bottom of the body region; the outside of the body region is the side of the body region away from the JFET region; forming a split gate electrode on the first conductivity type layer; the split gate electrode is divided from the middle, and the division area is located directly above the JFET region; forming a source electrode in direct contact with the source region and the contact region on the source region and the contact region; and forming a drain electrode on the side of the substrate away from the first conductivity type layer.

[0022] The manufacturing method of the planar split-gate VDMOSFET sets the contact region deeper than the body region, and thus forms a PN junction deeper than the body region-drift region. When a high voltage is applied to the drain, the electric field intensity peak is transferred to the bottom of the contact region, away from the corner of the split-gate electrode above the JFET region, i.e. away from the corner of the split-gate electrode above the JFET region, which is a weak point of electric field breakdown, so that the device has higher voltage resistance, improves the breakdown voltage of the device, and thus has better long-term reliability of the device in the working environment of high voltage applied to the drain.

[0023] In one embodiment, the step of forming the JFET region, the body region, the source region and the contact region in the first conductive type layer comprises etching the first conductive type layer to form a trench, and implanting ions of the second conductive type on the side and bottom of the trench to form the contact region.

[0024] In one embodiment, the step of forming the JFET region, the body region, the source region and the contact region in the first conductive type layer comprises: step one, implanting ions of the second conductive type into the first conductive type layer to form a second conductive type region; step two, forming an epitaxial layer on the wafer; step three, implanting ions of the second conductive type into the epitaxial layer to form a second conductive type region; repeating the step two and the step three to form multiple layers of the second conductive type region, and then diffusing and connecting the second conductive type regions by heat treatment to form the contact region.

[0025] In one embodiment, the step of forming the JFET region, the body region, the source region and the contact region in the first conductive type layer comprises forming the contact region by high-energy ion implantation. BRIEF DESCRIPTION OF DRAWINGS

[0026] For a better description and illustration of the embodiments and / or examples of the inventions disclosed herein, reference can be made to one or more drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the best mode presently understood of these inventions.

[0027] FIG. 1 is a schematic diagram of a cross-sectional structure of an exemplary planar split-gate VDMOSFET based on a third-generation semiconductor material.

[0028] FIG. 2 is a schematic diagram of a cross-sectional structure of a planar split-gate VDMOSFET according to an embodiment of the present application.

[0029] FIG. 3 is a schematic diagram of a region where the electric field intensity peak occurs for the structure shown in FIG. 2.

[0030] FIG. 4 is a drift region resistance model of the VDMOSFET shown in FIG. 2 when it is turned on in the forward direction.

[0031] Figure 5 is a schematic diagram of a cross-sectional structure of a planar split gate VDMOSFET according to another embodiment of the present application.

[0032] Figure 6 is a schematic diagram of forming the contact region 8 according to an embodiment of the present application.

[0033] Figure 7 is a flow chart of a method of fabricating a planar split gate VDMOSFET according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] For the purposes of the present application, the following terms shall have the meanings indicated below:

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0037] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, then a dependent element or feature it is said to "beneath" or "under" another element or feature could be oriented "above" or "over" the other element or feature. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptions used herein interpreted accordingly.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, an implanted region formed by implantation can result in some implant in a region between the implanted region and a surface over which implantation occurs. Thus, the regions illustrated in the figures are schematic and are not intended to illustrate actual dimensions but are intended to be exemplary of the regions used in the devices described herein.

[0040] As used herein, semiconductor field terms are used by those skilled in the art, for example, P-type and N-type impurities, for distinguishing doping concentrations, simply P+ type represents P-type of heavy doping concentration, P type represents P-type of medium doping concentration, P- type represents P-type of light doping concentration, N+ type represents N-type of heavy doping concentration, N type represents N-type of medium doping concentration, N- type represents N-type of light doping concentration.

[0041] Figure 1 is a schematic diagram of a cross-sectional structure of an exemplary planar split-gate VDMOSFET with a third-generation semiconductor material as a substrate, including a drain region 1, a drift region 2, a body region 3, a JFET region 4, a source region 5, a channel region 6, a contact region 8, a gate dielectric layer 9, a split-gate electrode 10, an interlayer isolation medium 11, a source electrode 12, and a drain electrode 13. When a high voltage is applied to the drain electrode 13, the peak electric field strength appears at the corner of the split-gate electrode above the JFET region 4, i.e., the position indicated by the arrow in Figure 1. The body region 3 forms a PN junction with the drift region 2, and when a high voltage is applied to the drain electrode 13, the depletion layer formed by the PN junction pinches off the JFET region 4. The curvature of the corner of the split-gate electrode above the JFET region 4 is large, which causes the electric field to concentrate at the corner and the electric field strength to increase at the corner. The large electric field strength at the corner, if maintained for a long time, can cause electrons to tunnel into the gate dielectric layer 9 and cause damage, reducing the breakdown voltage and long-term reliability of the device.

[0042] The present application proposes a planar split-gate VDMOSFET with low loss (switching power consumption). Figure 2 is a schematic diagram of a cross-sectional structure of a planar split-gate VDMOSFET in an embodiment of the present application, including a drain region 1, a drift region 2, a body region 3, a JFET region 4, a source region 5, a contact region 8, a split-gate electrode 10, a source electrode 12, and a drain electrode 13.

[0043] The drain region 1 has a first conductivity type. In the embodiment shown in Figure 2, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type. The drift region 2 has the first conductivity type and is located on the drain region 1. The drain electrode 13 is located on the bottom surface of the drain region 1, i.e., the surface of the drain region 1 facing away from the drift region 2. The JFET region 4 has the first conductivity type and is located on the drift region 2. The body region 3 has the second conductivity type and is located on the drift region 2, on both sides of the JFET region 4. The source region 5 has the first conductivity type and is located on the body region 3, on both sides of the JFET region 4. The contact region 8 has the second conductivity type and is located on the outside of the body region 3, i.e., the side of the body region 3 facing away from the JFET region 4. The bottom of the contact region 8 is deeper than the bottom of the body region 3, i.e., the bottom of the contact region 8 extends to a position deeper than the bottom of the body region 3 towards the drift region 2. In an embodiment of the present application, the doping concentration of the contact region 8 is greater than the doping concentration of the body region 3. The split-gate electrode 10 is located on the source region 5, and the split-gate electrode 10 is divided in the middle, with the division region located directly above the JFET region 4. The source electrode 12 is located on and in direct contact with the source region 5 and the contact region 8. In an embodiment of the present application, the doping concentrations have the following relationship: source region 5 > JFET region 4 > drift region 2, drain region 1 > JFET region 4 > drift region 2.

[0044] The above-mentioned planar split-gate VDMOSFET sets the contact region 8 as deeper than the body region 3, and thus the contact region 8 forms a PN junction with the drift region 2 deeper than the PN junction between the body region 3 and the drift region 2. When a high voltage is applied to the drain electrode 13, the peak of the electric field intensity is transferred to the bottom of the contact region 8, i.e. the position indicated by the arrow in FIG. 3, away from the corner of the split-gate electrode above the JFET region 4, i.e. away from the corner of the split-gate electrode above the JFET region 4, which is the weak point of the electric field breakdown, so that the device has a higher voltage withstand capability, and the breakdown voltage of the device is improved, thereby having a better long-term reliability in the working environment of a high voltage applied to the drain electrode. The PN junction formed between the contact region 8 and the drift region 2 forms a depletion layer clamping the JFET region 4, which is deeper than the depletion layer of the device shown in FIG. 1, and thus can further enhance the clamping effect of the depletion layer, reduce the electric field concentration at the corner of the split-gate electrode, reduce the electric field intensity at the corner, and improve the breakdown voltage and long-term reliability of the device. FIG. 4 is a drift region resistance model of the VDMOSFET shown in FIG. 2 when the device is in forward conduction, and the oblique bar filled part in the figure is the transmission path of the current from the bottom of the JFET region 4 to the bottom of the drift region 2 when the device is in forward conduction. Based on the resistance distribution characteristics of the drift region of the VDMOSFET, when the device is in forward conduction, the depth of the contact region 8 and the depletion layer formed thereby do not affect the original current path and the specific on-resistance of the device before the depth reaches a certain value. Therefore, the planar split-gate VDMOSFET of the embodiment of the present application can improve the breakdown voltage and long-term reliability of the device while keeping the specific on-resistance unchanged.

[0045] The difference between the bottom depth of the contact region 8 and the bottom depth of the body region 3 is denoted as d, and the value of d needs to be reasonably controlled in order to obtain a better effect. If d is too small, when a high voltage is applied to the drain electrode 13, the peak of the electric field intensity cannot be transferred to the bottom of the contact region 8, but still at the corner of the split-gate electrode above the JFET region 4, i.e. close to the weak point of the electric field breakdown. Moreover, when a high voltage is applied to the drain electrode 13, the depletion layer formed by the contact region 8 cannot sufficiently reduce the electric field concentration at the corner of the split-gate electrode, and the electric field intensity at the corner is also large, which cannot improve the breakdown voltage and long-term reliability of the device. If d is too large, when the device is in forward conduction, the P+ contact region and the depletion layer formed thereby will affect the original current path and the specific on-resistance of the device. In an embodiment of the present application, the bottom of the contact region 8 is 0.5 to 2 microns deeper than the bottom of the body region 3.

[0046] In an embodiment of the present application, the contact region 8 shown in FIG. 2 is formed by etching (etching the epitaxial layer where the drift region 2 is located) a trench 7 on the outside of the body region 3, and then implanting ions of the second conductivity type on the side and bottom of the trench 7. By using the method of etching the trench 7 first and then implanting to form the contact region 8, the contact region 8 with a bottom depth deeper than the body region 3 can be formed without using high implantation energy.

[0047] In the embodiment shown in FIG. 2, the planar split-gate VDMOSFET further includes a channel region 6 of the second conductivity type between the source region 5 and the JFET region 4, the channel region 6 being on the body region 3. In one embodiment of the present application, the contact region 8 has a higher doping concentration than the channel region 6.

[0048] In one embodiment of the present application, the planar split-gate VDMOSFET further includes a dielectric layer covering the split-gate electrode 10, the source electrode 12 being on the dielectric layer. In the embodiment shown in FIG. 2, the dielectric layer includes a gate dielectric layer 9 under the split-gate electrode 10, and an interlayer dielectric 11 covering the split-gate electrode 10. In one embodiment of the present application, the gate dielectric layer 9 can include conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having dielectric constants from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 9 can include higher dielectric constant dielectric materials having dielectric constants from about 20 to at least about 100. Such higher dielectric constant dielectric materials can include, but are not limited to, hafnium oxide, hafnium silicates, titanium oxide, barium strontium titanates (BSTs) and lead zirconium titanates (PZTs). In one embodiment of the present application, the interlayer dielectric 11 can be a dielectric material such as silicon dioxide, silicon nitride, etc.

[0049] In one embodiment of the present application, the split-gate electrode 10, the source electrode 12 and the drain electrode 13 can be made of polysilicon, metal or alloy.

[0050] In one embodiment of the present application, the drain region 1 and the drift region 2 can be made of third generation semiconductor materials such as silicon carbide, gallium nitride, etc.

[0051] In the embodiment shown in FIG. 2, the inner edges of the split-gate electrode 10 extend above the JFET region 4, i.e. the orthogonal projection of the split-gate electrode 10 on the plane of the upper surface of the JFET region 4 overlaps a portion of the JFET region 4. The outer edges of the split-gate electrode 10 extend above the source region 5, i.e. the orthogonal projection of the split-gate electrode 10 on the plane of the upper surface of the source region 5 overlaps a portion of the source region 5.

[0052] In one embodiment of the present application, the bottom and part of the side of the contact region 8 is in direct contact with the drift region 2, part of the side of the contact region 8 is in direct contact with the body region 3, and part of the side of the contact region 8 is in direct contact with the source region 5.

[0053] In one embodiment of the present application, the contact region 8 is heavily doped to form an ohmic contact with the source electrode 12 to reduce the contact resistance. The heavily doped contact region 8 can also reduce the resistance of the second conductivity region and suppress the abnormal turn-on of the parasitic bipolar transistor when a high voltage is applied to the drain electrode 13.

[0054] In one embodiment of the present application, the contact region 8 is configured such that the surface in contact with the source electrode 12 is heavily doped, and the lower part of the contact region 8 is configured with a medium doping concentration, i.e. there is a change in the doping concentration of the upper surface of the contact region 8 and the remaining part.

[0055] In one embodiment of the present application, the drain region 1 is an N+ substrate, the drift region 2 is an N- region, the body region 3 is a P-type region, the JFET region 4 is an N-type region, the source region 5 is an N+ region, the channel region 6 is a P-type region, and the contact region 8 is a P+ region.

[0056] Figure 5 is a schematic diagram of the cross-sectional structure of a planar split-gate VDMOSFET in another embodiment of the present application, comprising a drain region 1, a drift region 2, a body region 3, a JFET region 4, a source region 5, a channel region 6, a contact region 8, a dielectric layer, a split-gate electrode 10, a source electrode 12, and a drain electrode 13. The main difference between the embodiment shown in Figure 5 and the embodiment shown in Figure 2 is that the contact region 8 is not formed by etching a trench 7 and then implanting ions of the second conductive type, i.e. no trench 7 is formed, and correspondingly, the source electrode 12 filled in the position of the trench 7 in Figure 2 is replaced by the whole contact region 8.

[0057] In one embodiment of the present application, the contact region 8 shown in Figure 5 is formed by high-energy ion implantation.

[0058] In another embodiment of the present application, the contact region 8 shown in Figure 5 is formed by multiple times of epitaxy of the drift region 2 and multiple times of implantation of ions of the second conductive type as shown in Figure 6. Specifically, the formation of the drift region 2 comprises multiple times of epitaxy of N-type semiconductor material, and after each epitaxy, implantation of ions of the second conductive type is performed in the film layer formed by the epitaxy, so as to form a second conductive type region in each film layer formed by the epitaxy, and then through heat treatment (annealing), the second conductive type regions are diffused and connected into one piece as the contact region 8.

[0059] Based on all the above embodiments, the planar split-gate VDMOSFET of the present application makes the electric field breakdown point away from the corner of the split-gate electrode without affecting the specific on-resistance of the device, and can further enhance the pinch-off effect of the depletion layer of the body region 3, reduce the electric field strength at the corner of the split-gate electrode, and achieve low switching loss, small leakage at the corner of the split-gate electrode, high breakdown voltage, and other effects.

[0060] The present application correspondingly provides a manufacturing method of a planar split-gate VDMOSFET. Figure 7 is a flowchart of the manufacturing method of a planar split-gate VDMOSFET in one embodiment of the present application, comprising the following steps:

[0061] S710, obtaining a wafer in which a first conductive type layer is formed on a substrate.

[0062] In one embodiment of this application, the substrate is a third-generation semiconductor material having a first conductivity type, such as silicon carbide, gallium nitride, etc. The first conductivity type layer can be formed epitaxially. The substrate subsequently serves as the drain region 1 of the device, and the first conductivity type layer subsequently serves as the drift region 2 of the device.

[0063] S720 forms a JFET region, a body region, a source region, and a contact region in the first conductivity type layer.

[0064] JFET region 4 and source region 5 have a first conductivity type, while body region 3 and contact region 8 have a second conductivity type, both of which can be formed by ion implantation. Body region 3 is formed on both sides of JFET region 4, source region 5 is formed on body region 3 and on both sides of JFET region 4, and contact region 8 is located outside body region 3 (i.e., the side of body region 3 away from JFET region 4), and the bottom of contact region 8 is deeper than the bottom of body region 3.

[0065] S730, a split gate electrode is formed on the first conductivity type layer.

[0066] In one embodiment of this application, a gate dielectric layer 9 is first formed on a first conductivity type layer, and then a split gate electrode 10 is formed on the gate dielectric layer 9. The split gate electrode 10 is separated in the middle, and the separation region is located directly above the JFET region 4.

[0067] S740 forms the source electrode on the source region and the contact region.

[0068] The source electrode 12 is in direct contact with the source region 5 and the contact region 8.

[0069] S750 forms a drain electrode on the back side of the substrate.

[0070] In the aforementioned method for manufacturing a planar split-gate VDMOSFET, the contact region 8 is set to be deeper at the bottom than the body region 3. Therefore, the contact region 8 and the drift region 2 form a PN junction that is deeper than the sum of the body region 3 and the drift region 2. When a high voltage is applied to the drain, the peak electric field intensity shifts to the bottom of the contact region 8, i.e., the position indicated by the arrow in Figure 3, away from the split gate electrode corner above the JFET region 4. This distances the device from the electric field breakdown weak point at the split gate electrode corner above the JFET region 4, resulting in higher breakdown voltage capability and improved device breakdown voltage. Consequently, the device exhibits better long-term reliability under high-voltage operating conditions.

[0071] In one embodiment of this application, step S720, forming the contact area 8, involves first etching a first conductivity type layer to form a trench 7, and then implanting second conductivity type ions into the sides and bottom of the trench 7 to form the contact area 8.

[0072] In one embodiment of this application, step S720, forming the contact area 8, specifically includes:

[0073] Step one, implanting ions of the second conductivity type into the first conductivity type layer to form a second conductivity type region.

[0074] Step two, forming an epitaxial layer on the wafer.

[0075] Step three, implanting ions of the second conductivity type into the epitaxial layer to form a second conductivity type region.

[0076] Repeating step two and step three to form multiple layers of the second conductivity type region, and then diffusing and connecting the multiple layers of the second conductivity type region into one piece through heat treatment to form the contact region 8.

[0077] In one embodiment of the present application, the contact region 8 can also be formed by high-energy ion implantation.

[0078] It should be understood that, although each step in the flowchart of the present application is shown in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowchart of the present application can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least some of the other steps or the steps or stages in the other steps.

[0079] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0080] Each technical feature of the above-described embodiments can be combined arbitrarily, and in order to make the description brief, all possible combinations of the technical features of the above-described embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present specification.

[0081] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A planar split-gate VDMOSFET characterized in that, comprising: a drain region having a first conductivity type; a drift region having the first conductivity type on the drain region; a drain electrode on a side of the drain region facing away from the drift region; a JFET region having the first conductivity type on the drift region; a body region having a second conductivity type on the drift region on both sides of the JFET region; the first conductivity type and the second conductivity type being opposite conductivity types; a source region having the first conductivity type on the body region on both sides of the JFET region; a contact region having the second conductivity type on an outer side of the body region, and a bottom of the contact region being deeper than a bottom of the body region, the outer side of the body region being a side of the body region facing away from the JFET region; a split gate electrode being split from a middle, the split region being directly above the JFET region; a source electrode on and in direct contact with the source region and the contact region.

2. The planar split-gate VDMOSFET of claim 1, wherein, The bottom of the contact region is 0.5 to 2 microns deeper than the bottom of the body region.

3. The planar split-gate VDMOSFET according to claim 1 or 2, characterized by, The contact region is formed by etching a trench on the outer side of the body region, and implanting ions of the second conductivity type on the side and the bottom of the trench.

4. The planar split-gate VDMOSFET according to claim 1 or 2, wherein The contact region is formed by high-energy ion implantation.

5. The planar split-gate VDMOSFET according to claim 1 or 2, wherein The drift region is formed by multiple epitaxial growths, and the contact region is formed by implanting ions of the second conductivity type after each epitaxial growth and then heat treatment to diffuse the implanted ions of the second conductivity type.

6. The planar split-gate VDMOSFET according to claim 1 or 2, wherein Further comprising a channel region between the source region and the JFET region, the channel region having the second conductivity type.

7. The planar split-gate VDMOSFET of claim 6, wherein, The doping concentration of the contact region is greater than the doping concentration of the channel region.

8. The planar split-gate VDMOSFET according to claim 1 or 2, wherein Further comprising a dielectric layer covering the split gate electrode, and the source electrode covers the dielectric layer.

9. The planar split-gate VDMOSFET according to claim 1 or 2, wherein The bottom and part of the side of the contact region are in direct contact with the drift region, part of the side of the contact region is in direct contact with the body region, and part of the side of the contact region is in direct contact with the source region.

10. The planar split-gate VDMOSFET according to claim 1 or 2, wherein The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

11. The planar split-gate VDMOSFET according to claim 1 or 2, wherein The material of the drain region and the drift region is silicon carbide or gallium nitride.

12. The planar split-gate VDMOSFET according to claim 1 or 2, wherein The doping concentration of the JFET region is greater than the doping concentration of the drift region.

13. The planar split-gate VDMOSFET according to claim 1 or 2, wherein The doping concentration of the drain region is greater than the doping concentration of the JFET region.

14. The planar split-gate VDMOSFET of claim 1 or 2, wherein, The doping concentration of the source region is greater than the doping concentration of the JFET region.

15. The planar split-gate VDMOSFET of claim 1 or 2, wherein, The doping concentration of the contact region is greater than the doping concentration of the body region.

16. A manufacturing method of a planar split gate VDMOSFET, comprising: obtaining a wafer having a first conductivity type layer formed on a substrate of a first conductivity type; the doping concentration of the substrate is greater than the doping concentration of the first conductivity type layer; forming a JFET region, a body region, a source region and a contact region in the first conductivity type layer; the JFET region and the source region have the first conductivity type, the body region and the contact region have the second conductivity type, the first conductivity type and the second conductivity type are opposite conductivity types; the body region is formed on both sides of the JFET region, the source region is formed on the body region, on both sides of the JFET region, the contact region is located outside the body region, and the bottom of the contact region is deeper than the bottom of the body region, the outside of the body region is the side of the body region away from the JFET region; forming a split gate electrode on the first conductivity type layer; the split gate electrode is divided from the middle, and the split area is located directly above the JFET region; forming a source electrode in direct contact with the source region and the contact region on the source region and the contact region; forming a drain electrode on the side of the substrate away from the first conductivity type layer.

17. The method of manufacturing a planar split gate VDMOSFET according to claim 16, wherein The step of forming a JFET region, a body region, a source region and a contact region in the first conductivity type layer comprises: etching the first conductivity type layer to form a trench; injecting second conductivity type ions into the side and bottom of the trench to form the contact region.

18. The method of manufacturing a planar split gate VDMOSFET according to claim 16, wherein The step of forming a JFET region, a body region, a source region and a contact region in the first conductivity type layer comprises: Step one, injecting second conductivity type ions into the first conductivity type layer to form a second conductivity type region; Step two, forming an epitaxial layer on the wafer again; Step three, injecting second conductivity type ions into the epitaxial layer to form a second conductivity type region; Repeating the step two and step three, forming multiple layers of second conductivity type regions, and then through heat treatment to diffuse and connect each second conductivity type region into a piece to form the contact region.

19. The method of manufacturing a planar split gate VDMOSFET according to claim 16, wherein The step of forming a JFET region, a body region, a source region and a contact region in the first conductivity type layer comprises: forming the contact region by high-energy ion implantation.

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